1 /******************************************************************************
2 * Copyright (c) 2022 Telink Semiconductor (Shanghai) Co., Ltd. ("TELINK")
3 * All rights reserved.
4 *
5 * Licensed under the Apache License, Version 2.0 (the "License");
6 * you may not use this file except in compliance with the License.
7 * You may obtain a copy of the License at
8 *
9 * http://www.apache.org/licenses/LICENSE-2.0
10 *
11 * Unless required by applicable law or agreed to in writing, software
12 * distributed under the License is distributed on an "AS IS" BASIS,
13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14 * See the License for the specific language governing permissions and
15 * limitations under the License.
16 *
17 *****************************************************************************/
18 /** @page SYS
19 *
20 * Introduction
21 * ===============
22 * Clock init and system timer delay.
23 *
24 * API Reference
25 * ===============
26 * Header File: sys.h
27 */
28
29 #ifndef SYS_H_
30 #define SYS_H_
31 #include "bit.h"
32 #include "reg_include/stimer_reg.h"
33
34 /**********************************************************************************************************************
35 * global constants *
36 *********************************************************************************************************************/
37
38 /**********************************************************************************************************************
39 * global macro *
40 *********************************************************************************************************************/
41 /*
42 * brief instruction delay
43 */
44
45 #define _ASM_NOP_ __asm__("nop")
46
47 #define CLOCK_DLY_1_CYC _ASM_NOP_
48 #define CLOCK_DLY_2_CYC \
49 _ASM_NOP_; \
50 _ASM_NOP_
51 #define CLOCK_DLY_3_CYC \
52 _ASM_NOP_; \
53 _ASM_NOP_; \
54 _ASM_NOP_
55 #define CLOCK_DLY_4_CYC \
56 _ASM_NOP_; \
57 _ASM_NOP_; \
58 _ASM_NOP_; \
59 _ASM_NOP_
60 #define CLOCK_DLY_5_CYC \
61 _ASM_NOP_; \
62 _ASM_NOP_; \
63 _ASM_NOP_; \
64 _ASM_NOP_; \
65 _ASM_NOP_
66 #define CLOCK_DLY_6_CYC \
67 _ASM_NOP_; \
68 _ASM_NOP_; \
69 _ASM_NOP_; \
70 _ASM_NOP_; \
71 _ASM_NOP_; \
72 _ASM_NOP_
73 #define CLOCK_DLY_7_CYC \
74 _ASM_NOP_; \
75 _ASM_NOP_; \
76 _ASM_NOP_; \
77 _ASM_NOP_; \
78 _ASM_NOP_; \
79 _ASM_NOP_; \
80 _ASM_NOP_
81 #define CLOCK_DLY_8_CYC \
82 _ASM_NOP_; \
83 _ASM_NOP_; \
84 _ASM_NOP_; \
85 _ASM_NOP_; \
86 _ASM_NOP_; \
87 _ASM_NOP_; \
88 _ASM_NOP_; \
89 _ASM_NOP_
90 #define CLOCK_DLY_9_CYC \
91 _ASM_NOP_; \
92 _ASM_NOP_; \
93 _ASM_NOP_; \
94 _ASM_NOP_; \
95 _ASM_NOP_; \
96 _ASM_NOP_; \
97 _ASM_NOP_; \
98 _ASM_NOP_; \
99 _ASM_NOP_
100 #define CLOCK_DLY_10_CYC \
101 _ASM_NOP_; \
102 _ASM_NOP_; \
103 _ASM_NOP_; \
104 _ASM_NOP_; \
105 _ASM_NOP_; \
106 _ASM_NOP_; \
107 _ASM_NOP_; \
108 _ASM_NOP_; \
109 _ASM_NOP_; \
110 _ASM_NOP_
111
112 #define FLASH_R_BASE_ADDR 0x20000000
113 #define REG_RW_BASE_ADDR 0x80000000
114 #define REG_ADDR8(a) (*(volatile unsigned char *)(REG_RW_BASE_ADDR | (a)))
115 #define REG_ADDR16(a) (*(volatile unsigned short *)(REG_RW_BASE_ADDR | (a)))
116 #define REG_ADDR32(a) (*(volatile unsigned long *)(REG_RW_BASE_ADDR | (a)))
117
118 #define write_reg8(addr, v) (*(volatile unsigned char *)(REG_RW_BASE_ADDR | (addr)) = (unsigned char)(v))
119 #define write_reg16(addr, v) (*(volatile unsigned short *)(REG_RW_BASE_ADDR | (addr)) = (unsigned short)(v))
120 #define write_reg32(addr, v) (*(volatile unsigned long *)(REG_RW_BASE_ADDR | (addr)) = (unsigned long)(v))
121
122 #define read_reg8(addr) (*(volatile unsigned char *)(REG_RW_BASE_ADDR | (addr)))
123 #define read_reg16(addr) (*(volatile unsigned short *)(REG_RW_BASE_ADDR | (addr)))
124 #define read_reg32(addr) (*(volatile unsigned long *)(REG_RW_BASE_ADDR | (addr)))
125
126 #define write_sram8(addr, v) (*(volatile unsigned char *)((addr)) = (unsigned char)(v))
127 #define write_sram16(addr, v) (*(volatile unsigned short *)((addr)) = (unsigned short)(v))
128 #define write_sram32(addr, v) (*(volatile unsigned long *)((addr)) = (unsigned long)(v))
129
130 #define read_sram8(addr) (*(volatile unsigned char *)((addr)))
131 #define read_sram16(addr) (*(volatile unsigned short *)((addr)))
132 #define read_sram32(addr) (*(volatile unsigned long *)((addr)))
133 #define TCMD_UNDER_BOTH 0xc0
134 #define TCMD_UNDER_RD 0x80
135 #define TCMD_UNDER_WR 0x40
136
137 #define TCMD_MASK 0x3f
138
139 #define TCMD_WRITE 0x3
140 #define TCMD_WAIT 0x7
141 #define TCMD_WAREG 0x8
142
143 #define convert_ram_addr_cpu2bus(addr) ((unsigned int)(addr) + 0xc0180000)
144
145 #define convert_ram_addr_bus2cpu(addr) \
146 (((((unsigned int)(addr)) >= 0xc0200000) ? (((unsigned int)(addr)) + 0x80000 - 0xc0200000) \
147 : (((unsigned int)(addr)) - 0xc0000000)))
148
149 /**********************************************************************************************************************
150 * global data type *
151 *********************************************************************************************************************/
152
153 /**
154 * @brief Power type for different application
155 */
156 typedef enum {
157 LDO_1P4_LDO_1P8 = 0x00, /**< 1.4V-LDO & 1.8V-LDO mode */
158 DCDC_1P4_LDO_1P8 = 0x01, /**< 1.4V-DCDC & 1.8V-LDO mode */
159 DCDC_1P4_DCDC_1P8 = 0x03, /**< 1.4V-DCDC & 1.8V-DCDC mode */
160 } power_mode_e;
161
162 /**
163 * @brief The maximum voltage that the chip can withstand is 3.6V.
164 * When the vbat power supply voltage is lower than 3.6V,
165 * it is configured as VBAT_MAX_VALUE_LESS_THAN_3V6 mode,
166 * bypass is turned on, and the vbat voltage directly supplies power to the chip.
167 * When the vbat power supply voltage may be higher than 3.6V, it is configured as
168 * VBAT_MAX_VALUE_GREATER_THAN_3V6 mode,
169 * the bypass is closed, and the vbat voltage passes through an LDO to supply power to the chip.
170 */
171 typedef enum {
172 VBAT_MAX_VALUE_GREATER_THAN_3V6 = 0x00, /* VBAT may be greater than 3.6V. */
173 VBAT_MAX_VALUE_LESS_THAN_3V6 = BIT(3), /* VBAT must be below 3.6V. */
174 } vbat_type_e;
175
176 /**
177 * @brief command table for special registers
178 */
179 typedef struct tbl_cmd_set_t {
180 unsigned int adr;
181 unsigned char dat;
182 unsigned char cmd;
183 } tbl_cmd_set_t;
184
185 /**********************************************************************************************************************
186 * global variable declaration *
187 *********************************************************************************************************************/
188
189 extern unsigned int g_chip_version;
190
191 /**********************************************************************************************************************
192 * global function prototype *
193 *********************************************************************************************************************/
194 /**
195 * @brief This function reboot mcu.
196 * @return none
197 */
sys_reboot(void)198 static inline void sys_reboot(void)
199 {
200 write_reg8(0x1401ef, 0x20);
201 }
202 /**
203 * @brief This function serves to initialize system.
204 * @param[in] power_mode - power mode(LDO/DCDC/LDO_DCDC)
205 * @param[in] vbat_v - vbat voltage type: 0 vbat may be greater than 3.6V, 1 vbat must be below 3.6V.
206 * @return none
207 */
208 void sys_init(power_mode_e power_mode, vbat_type_e vbat_v);
209
210 /**
211 * @brief This function performs a series of operations of writing digital or analog registers
212 * according to a command table
213 * @param[in] pt - pointer to a command table containing several writing commands
214 * @param[in] size - number of commands in the table
215 * @return number of commands are carried out
216 */
217
218 int write_reg_table(const tbl_cmd_set_t *pt, int size);
219
220 #endif
221