1 /******************************************************************************
2 * Copyright (c) 2022 Telink Semiconductor (Shanghai) Co., Ltd. ("TELINK")
3 * All rights reserved.
4 *
5 * Licensed under the Apache License, Version 2.0 (the "License");
6 * you may not use this file except in compliance with the License.
7 * You may obtain a copy of the License at
8 *
9 * http://www.apache.org/licenses/LICENSE-2.0
10 *
11 * Unless required by applicable law or agreed to in writing, software
12 * distributed under the License is distributed on an "AS IS" BASIS,
13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14 * See the License for the specific language governing permissions and
15 * limitations under the License.
16 *
17 *****************************************************************************/
18
19 #include <target_config.h>
20
21 #include <los_compiler.h>
22
23 #include <B91/clock.h>
24 #include <B91/sys.h>
25
26 #include <B91/ext_driver/ext_pm.h>
27
28 /****************************************************************************
29 * Pre-processor Definitions
30 ****************************************************************************/
31
32 /* Define 48 MHz and 96 MHz CCLK clock options (not present in HAL) */
33 #define CCLK_64M_HCLK_32M_PCLK_16M \
34 clock_init(PLL_CLK_192M, PAD_PLL_DIV, PLL_DIV3_TO_CCLK, CCLK_DIV2_TO_HCLK, HCLK_DIV2_TO_PCLK, PLL_DIV4_TO_MSPI_CLK)
35
36 #define CCLK_96M_HCLK_48M_PCLK_24M \
37 clock_init(PLL_CLK_192M, PAD_PLL_DIV, PLL_DIV2_TO_CCLK, CCLK_DIV2_TO_HCLK, HCLK_DIV2_TO_PCLK, PLL_DIV4_TO_MSPI_CLK)
38
39 #if LOSCFG_TELINK_B91_CPU_FREQ == 16000000
40 #define CLOCK_INIT CCLK_16M_HCLK_16M_PCLK_16M
41 #elif LOSCFG_TELINK_B91_CPU_FREQ == 24000000
42 #define CLOCK_INIT CCLK_24M_HCLK_24M_PCLK_24M
43 #elif LOSCFG_TELINK_B91_CPU_FREQ == 32000000
44 #define CLOCK_INIT CCLK_32M_HCLK_32M_PCLK_16M
45 #elif LOSCFG_TELINK_B91_CPU_FREQ == 48000000
46 #define CLOCK_INIT CCLK_48M_HCLK_48M_PCLK_24M
47 #elif LOSCFG_TELINK_B91_CPU_FREQ == 64000000
48 #define CLOCK_INIT CCLK_64M_HCLK_32M_PCLK_16M
49 #elif LOSCFG_TELINK_B91_CPU_FREQ == 96000000
50 #define CLOCK_INIT CCLK_96M_HCLK_48M_PCLK_24M
51 #else /* LOSCFG_TELINK_B91_CPU_FREQ == 16000000 */
52 #error Unsupported clock frequency. See LOSCFG_TELINK_B91_CPU_FREQ
53 #endif /* LOSCFG_TELINK_B91_CPU_FREQ == 16000000 */
54
55 /****************************************************************************
56 * Public Functions
57 ****************************************************************************/
58
59 #if defined(LOSCFG_POWER_MODE_LDO_1P4_LDO_1P8)
60 #define POWER_MODE LDO_1P4_LDO_1P8
61 #elif defined(LOSCFG_POWER_MODE_DCDC_1P4_LDO_1P8)
62 #define POWER_MODE DCDC_1P4_LDO_1P8
63 #elif defined(LOSCFG_POWER_MODE_DCDC_1P4_DCDC_1P8)
64 #define POWER_MODE DCDC_1P4_DCDC_1P8
65 #else /* defined(LOSCFG_POWER_MODE_LDO_1P4_LDO_1P8) */
66 #error Unsupported Power mode
67 #endif /* defined(LOSCFG_POWER_MODE_LDO_1P4_LDO_1P8) */
68
69 #if defined(LOSCFG_VBAT_TYPE_MAX_VALUE_GREATER_THAN_3V6)
70 #define VBAT_TYPE VBAT_MAX_VALUE_GREATER_THAN_3V6
71 #elif defined(LOSCFG_VBAT_TYPE_MAX_VALUE_LESS_THAN_3V6)
72 #define VBAT_TYPE VBAT_MAX_VALUE_LESS_THAN_3V6
73 #else /* defined(LOSCFG_VBAT_TYPE_MAX_VALUE_GREATER_THAN_3V6) */
74 #error Unsupported VBat type
75 #endif /* defined(LOSCFG_VBAT_TYPE_MAX_VALUE_GREATER_THAN_3V6) */
76
SystemInit(VOID)77 VOID SystemInit(VOID)
78 {
79 blc_pm_select_internal_32k_crystal();
80
81 sys_init(POWER_MODE, VBAT_TYPE);
82 CLOCK_INIT;
83
84 clock_32k_init(CLK_32K_RC);
85 clock_cal_32k_rc();
86 }
87