1 /* 2 * Copyright (c) 2022 Winner Microelectronics Co., Ltd. All rights reserved. 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 */ 15 16 /** 17 * @file wm_cpu.c 18 * 19 * @brief cpu driver module 20 * 21 * @author kevin 22 * 23 * Copyright (c) 2014 Winner Microelectronics Co., Ltd. 24 */ 25 #include "wm_debug.h" 26 #include "wm_regs.h" 27 #include "wm_irq.h" 28 #include "wm_pwm.h" 29 #include "wm_cpu.h" 30 31 /** 32 * @brief This function is used to set cpu clock 33 * 34 * @param[in] clk select cpu clock 35 * clk == CPU_CLK_80M 80M 36 * clk == CPU_CLK_40M 40M 37 * 38 * @return None 39 * 40 * @note None 41 */ tls_sys_clk_set(u32 clk)42void tls_sys_clk_set(u32 clk) 43 { 44 #ifndef TLS_CONFIG_FPGA 45 u32 RegValue; 46 u8 wlanDiv, cpuDiv = clk; 47 u8 bus2Fac; 48 49 if ((clk < 2) || (clk > 240)) { 50 return; 51 } 52 53 RegValue = tls_reg_read32(HR_CLK_DIV_CTL); 54 wlanDiv = (RegValue>>8)&0xFF; 55 RegValue &= 0xFF000000; 56 RegValue |= 0x80000000; 57 if (cpuDiv > 12) { 58 bus2Fac = 1; 59 wlanDiv = cpuDiv/4; 60 } else { /* wlan can run */ 61 wlanDiv=3; 62 bus2Fac = (wlanDiv*4/cpuDiv)&0xFF; 63 } 64 RegValue |= (bus2Fac<<16) | (wlanDiv<<8) | cpuDiv; 65 tls_reg_write32(HR_CLK_DIV_CTL, RegValue); 66 SysTick_Config(W800_PLL_CLK_MHZ*UNIT_MHZ/cpuDiv/HZ); 67 #endif 68 return; 69 } 70 71 /** 72 * @brief This function is used to get cpu clock 73 * 74 * @param[out] *sysclk point to the addr for system clk output 75 * 76 * @return None 77 * 78 * @note None 79 */ tls_sys_clk_get(tls_sys_clk * sysclk)80void tls_sys_clk_get(tls_sys_clk *sysclk) 81 { 82 #ifndef TLS_CONFIG_FPGA 83 clk_div_reg clk_div; 84 85 clk_div.w = tls_reg_read32(HR_CLK_DIV_CTL); 86 sysclk->cpuclk = W800_PLL_CLK_MHZ/(clk_div.b.CPU); 87 sysclk->wlanclk = W800_PLL_CLK_MHZ/(clk_div.b.WLAN); 88 sysclk->apbclk = sysclk->cpuclk / clk_div.b.BUS2; 89 #else 90 sysclk->apbclk = 91 sysclk->cpuclk = 92 sysclk->wlanclk = 40; 93 #endif 94 } 95 96