1// SPDX-License-Identifier: GPL-2.0+ 2#include <dt-bindings/clock/aspeed-clock.h> 3 4/ { 5 model = "Aspeed BMC"; 6 compatible = "aspeed,ast2400"; 7 #address-cells = <1>; 8 #size-cells = <1>; 9 interrupt-parent = <&vic>; 10 11 aliases { 12 i2c0 = &i2c0; 13 i2c1 = &i2c1; 14 i2c2 = &i2c2; 15 i2c3 = &i2c3; 16 i2c4 = &i2c4; 17 i2c5 = &i2c5; 18 i2c6 = &i2c6; 19 i2c7 = &i2c7; 20 i2c8 = &i2c8; 21 i2c9 = &i2c9; 22 i2c10 = &i2c10; 23 i2c11 = &i2c11; 24 i2c12 = &i2c12; 25 i2c13 = &i2c13; 26 serial0 = &uart1; 27 serial1 = &uart2; 28 serial2 = &uart3; 29 serial3 = &uart4; 30 serial4 = &uart5; 31 serial5 = &vuart; 32 }; 33 34 cpus { 35 #address-cells = <1>; 36 #size-cells = <0>; 37 38 cpu@0 { 39 compatible = "arm,arm926ej-s"; 40 device_type = "cpu"; 41 reg = <0>; 42 }; 43 }; 44 45 memory@40000000 { 46 device_type = "memory"; 47 reg = <0x40000000 0>; 48 }; 49 50 ahb { 51 compatible = "simple-bus"; 52 #address-cells = <1>; 53 #size-cells = <1>; 54 ranges; 55 56 fmc: spi@1e620000 { 57 reg = < 0x1e620000 0x94 58 0x20000000 0x10000000 >; 59 #address-cells = <1>; 60 #size-cells = <0>; 61 compatible = "aspeed,ast2400-fmc"; 62 clocks = <&syscon ASPEED_CLK_AHB>; 63 status = "disabled"; 64 interrupts = <19>; 65 flash@0 { 66 reg = < 0 >; 67 compatible = "jedec,spi-nor"; 68 spi-max-frequency = <50000000>; 69 status = "disabled"; 70 }; 71 flash@1 { 72 reg = < 1 >; 73 compatible = "jedec,spi-nor"; 74 status = "disabled"; 75 }; 76 flash@2 { 77 reg = < 2 >; 78 compatible = "jedec,spi-nor"; 79 status = "disabled"; 80 }; 81 flash@3 { 82 reg = < 3 >; 83 compatible = "jedec,spi-nor"; 84 status = "disabled"; 85 }; 86 flash@4 { 87 reg = < 4 >; 88 compatible = "jedec,spi-nor"; 89 status = "disabled"; 90 }; 91 }; 92 93 spi: spi@1e630000 { 94 reg = < 0x1e630000 0x18 95 0x30000000 0x10000000 >; 96 #address-cells = <1>; 97 #size-cells = <0>; 98 compatible = "aspeed,ast2400-spi"; 99 clocks = <&syscon ASPEED_CLK_AHB>; 100 status = "disabled"; 101 flash@0 { 102 reg = < 0 >; 103 compatible = "jedec,spi-nor"; 104 spi-max-frequency = <50000000>; 105 status = "disabled"; 106 }; 107 }; 108 109 vic: interrupt-controller@1e6c0080 { 110 compatible = "aspeed,ast2400-vic"; 111 interrupt-controller; 112 #interrupt-cells = <1>; 113 valid-sources = <0xffffffff 0x0007ffff>; 114 reg = <0x1e6c0080 0x80>; 115 }; 116 117 cvic: copro-interrupt-controller@1e6c2000 { 118 compatible = "aspeed,ast2400-cvic", "aspeed-cvic"; 119 valid-sources = <0x7fffffff>; 120 reg = <0x1e6c2000 0x80>; 121 }; 122 123 mac0: ethernet@1e660000 { 124 compatible = "aspeed,ast2400-mac", "faraday,ftgmac100"; 125 reg = <0x1e660000 0x180>; 126 interrupts = <2>; 127 clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>; 128 status = "disabled"; 129 }; 130 131 mac1: ethernet@1e680000 { 132 compatible = "aspeed,ast2400-mac", "faraday,ftgmac100"; 133 reg = <0x1e680000 0x180>; 134 interrupts = <3>; 135 clocks = <&syscon ASPEED_CLK_GATE_MAC2CLK>; 136 status = "disabled"; 137 }; 138 139 ehci0: usb@1e6a1000 { 140 compatible = "aspeed,ast2400-ehci", "generic-ehci"; 141 reg = <0x1e6a1000 0x100>; 142 interrupts = <5>; 143 clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>; 144 pinctrl-names = "default"; 145 pinctrl-0 = <&pinctrl_usb2h_default>; 146 status = "disabled"; 147 }; 148 149 uhci: usb@1e6b0000 { 150 compatible = "aspeed,ast2400-uhci", "generic-uhci"; 151 reg = <0x1e6b0000 0x100>; 152 interrupts = <14>; 153 #ports = <3>; 154 clocks = <&syscon ASPEED_CLK_GATE_USBUHCICLK>; 155 status = "disabled"; 156 /* 157 * No default pinmux, it will follow EHCI, use an explicit pinmux 158 * override if you don't enable EHCI 159 */ 160 }; 161 162 vhub: usb-vhub@1e6a0000 { 163 compatible = "aspeed,ast2400-usb-vhub"; 164 reg = <0x1e6a0000 0x300>; 165 interrupts = <5>; 166 clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>; 167 aspeed,vhub-downstream-ports = <5>; 168 aspeed,vhub-generic-endpoints = <15>; 169 pinctrl-names = "default"; 170 pinctrl-0 = <&pinctrl_usb2d_default>; 171 status = "disabled"; 172 }; 173 174 apb { 175 compatible = "simple-bus"; 176 #address-cells = <1>; 177 #size-cells = <1>; 178 ranges; 179 180 syscon: syscon@1e6e2000 { 181 compatible = "aspeed,ast2400-scu", "syscon", "simple-mfd"; 182 reg = <0x1e6e2000 0x1a8>; 183 #address-cells = <1>; 184 #size-cells = <1>; 185 ranges = <0 0x1e6e2000 0x1000>; 186 #clock-cells = <1>; 187 #reset-cells = <1>; 188 189 p2a: p2a-control@2c { 190 reg = <0x2c 0x4>; 191 compatible = "aspeed,ast2400-p2a-ctrl"; 192 status = "disabled"; 193 }; 194 195 pinctrl: pinctrl@80 { 196 reg = <0x80 0x18>, <0xa0 0x10>; 197 compatible = "aspeed,ast2400-pinctrl"; 198 }; 199 }; 200 201 rng: hwrng@1e6e2078 { 202 compatible = "timeriomem_rng"; 203 reg = <0x1e6e2078 0x4>; 204 period = <1>; 205 quality = <100>; 206 }; 207 208 adc: adc@1e6e9000 { 209 compatible = "aspeed,ast2400-adc"; 210 reg = <0x1e6e9000 0xb0>; 211 clocks = <&syscon ASPEED_CLK_APB>; 212 resets = <&syscon ASPEED_RESET_ADC>; 213 #io-channel-cells = <1>; 214 status = "disabled"; 215 }; 216 217 sram: sram@1e720000 { 218 compatible = "mmio-sram"; 219 reg = <0x1e720000 0x8000>; // 32K 220 }; 221 222 video: video@1e700000 { 223 compatible = "aspeed,ast2400-video-engine"; 224 reg = <0x1e700000 0x1000>; 225 clocks = <&syscon ASPEED_CLK_GATE_VCLK>, 226 <&syscon ASPEED_CLK_GATE_ECLK>; 227 clock-names = "vclk", "eclk"; 228 interrupts = <7>; 229 status = "disabled"; 230 }; 231 232 sdmmc: sd-controller@1e740000 { 233 compatible = "aspeed,ast2400-sd-controller"; 234 reg = <0x1e740000 0x100>; 235 #address-cells = <1>; 236 #size-cells = <1>; 237 ranges = <0 0x1e740000 0x10000>; 238 clocks = <&syscon ASPEED_CLK_GATE_SDCLK>; 239 status = "disabled"; 240 241 sdhci0: sdhci@100 { 242 compatible = "aspeed,ast2400-sdhci"; 243 reg = <0x100 0x100>; 244 interrupts = <26>; 245 sdhci,auto-cmd12; 246 clocks = <&syscon ASPEED_CLK_SDIO>; 247 status = "disabled"; 248 }; 249 250 sdhci1: sdhci@200 { 251 compatible = "aspeed,ast2400-sdhci"; 252 reg = <0x200 0x100>; 253 interrupts = <26>; 254 sdhci,auto-cmd12; 255 clocks = <&syscon ASPEED_CLK_SDIO>; 256 status = "disabled"; 257 }; 258 }; 259 260 gpio: gpio@1e780000 { 261 #gpio-cells = <2>; 262 gpio-controller; 263 compatible = "aspeed,ast2400-gpio"; 264 reg = <0x1e780000 0x1000>; 265 interrupts = <20>; 266 gpio-ranges = <&pinctrl 0 0 220>; 267 clocks = <&syscon ASPEED_CLK_APB>; 268 interrupt-controller; 269 #interrupt-cells = <2>; 270 }; 271 272 timer: timer@1e782000 { 273 /* This timer is a Faraday FTTMR010 derivative */ 274 compatible = "aspeed,ast2400-timer"; 275 reg = <0x1e782000 0x90>; 276 interrupts = <16 17 18 35 36 37 38 39>; 277 clocks = <&syscon ASPEED_CLK_APB>; 278 clock-names = "PCLK"; 279 }; 280 281 rtc: rtc@1e781000 { 282 compatible = "aspeed,ast2400-rtc"; 283 reg = <0x1e781000 0x18>; 284 status = "disabled"; 285 }; 286 287 uart1: serial@1e783000 { 288 compatible = "ns16550a"; 289 reg = <0x1e783000 0x20>; 290 reg-shift = <2>; 291 interrupts = <9>; 292 clocks = <&syscon ASPEED_CLK_GATE_UART1CLK>; 293 resets = <&lpc_reset 4>; 294 no-loopback-test; 295 status = "disabled"; 296 }; 297 298 uart5: serial@1e784000 { 299 compatible = "ns16550a"; 300 reg = <0x1e784000 0x20>; 301 reg-shift = <2>; 302 interrupts = <10>; 303 clocks = <&syscon ASPEED_CLK_GATE_UART5CLK>; 304 no-loopback-test; 305 status = "disabled"; 306 }; 307 308 wdt1: watchdog@1e785000 { 309 compatible = "aspeed,ast2400-wdt"; 310 reg = <0x1e785000 0x1c>; 311 clocks = <&syscon ASPEED_CLK_APB>; 312 }; 313 314 wdt2: watchdog@1e785020 { 315 compatible = "aspeed,ast2400-wdt"; 316 reg = <0x1e785020 0x1c>; 317 clocks = <&syscon ASPEED_CLK_APB>; 318 }; 319 320 pwm_tacho: pwm-tacho-controller@1e786000 { 321 compatible = "aspeed,ast2400-pwm-tacho"; 322 #address-cells = <1>; 323 #size-cells = <0>; 324 reg = <0x1e786000 0x1000>; 325 clocks = <&syscon ASPEED_CLK_24M>; 326 resets = <&syscon ASPEED_RESET_PWM>; 327 status = "disabled"; 328 }; 329 330 vuart: serial@1e787000 { 331 compatible = "aspeed,ast2400-vuart"; 332 reg = <0x1e787000 0x40>; 333 reg-shift = <2>; 334 interrupts = <8>; 335 clocks = <&syscon ASPEED_CLK_APB>; 336 no-loopback-test; 337 status = "disabled"; 338 }; 339 340 lpc: lpc@1e789000 { 341 compatible = "aspeed,ast2400-lpc", "simple-mfd"; 342 reg = <0x1e789000 0x1000>; 343 344 #address-cells = <1>; 345 #size-cells = <1>; 346 ranges = <0x0 0x1e789000 0x1000>; 347 348 lpc_bmc: lpc-bmc@0 { 349 compatible = "aspeed,ast2400-lpc-bmc"; 350 reg = <0x0 0x80>; 351 }; 352 353 lpc_host: lpc-host@80 { 354 compatible = "aspeed,ast2400-lpc-host", "simple-mfd", "syscon"; 355 reg = <0x80 0x1e0>; 356 reg-io-width = <4>; 357 358 #address-cells = <1>; 359 #size-cells = <1>; 360 ranges = <0x0 0x80 0x1e0>; 361 362 lpc_ctrl: lpc-ctrl@0 { 363 compatible = "aspeed,ast2400-lpc-ctrl"; 364 reg = <0x0 0x10>; 365 clocks = <&syscon ASPEED_CLK_GATE_LCLK>; 366 status = "disabled"; 367 }; 368 369 lpc_snoop: lpc-snoop@10 { 370 compatible = "aspeed,ast2400-lpc-snoop"; 371 reg = <0x10 0x8>; 372 interrupts = <8>; 373 clocks = <&syscon ASPEED_CLK_GATE_LCLK>; 374 status = "disabled"; 375 }; 376 377 lhc: lhc@20 { 378 compatible = "aspeed,ast2400-lhc"; 379 reg = <0x20 0x24 0x48 0x8>; 380 }; 381 382 lpc_reset: reset-controller@18 { 383 compatible = "aspeed,ast2400-lpc-reset"; 384 reg = <0x18 0x4>; 385 #reset-cells = <1>; 386 }; 387 388 ibt: ibt@c0 { 389 compatible = "aspeed,ast2400-ibt-bmc"; 390 reg = <0xc0 0x18>; 391 interrupts = <8>; 392 status = "disabled"; 393 }; 394 }; 395 }; 396 397 uart2: serial@1e78d000 { 398 compatible = "ns16550a"; 399 reg = <0x1e78d000 0x20>; 400 reg-shift = <2>; 401 interrupts = <32>; 402 clocks = <&syscon ASPEED_CLK_GATE_UART2CLK>; 403 resets = <&lpc_reset 5>; 404 no-loopback-test; 405 status = "disabled"; 406 }; 407 408 uart3: serial@1e78e000 { 409 compatible = "ns16550a"; 410 reg = <0x1e78e000 0x20>; 411 reg-shift = <2>; 412 interrupts = <33>; 413 clocks = <&syscon ASPEED_CLK_GATE_UART3CLK>; 414 resets = <&lpc_reset 6>; 415 no-loopback-test; 416 status = "disabled"; 417 }; 418 419 uart4: serial@1e78f000 { 420 compatible = "ns16550a"; 421 reg = <0x1e78f000 0x20>; 422 reg-shift = <2>; 423 interrupts = <34>; 424 clocks = <&syscon ASPEED_CLK_GATE_UART4CLK>; 425 resets = <&lpc_reset 7>; 426 no-loopback-test; 427 status = "disabled"; 428 }; 429 430 i2c: bus@1e78a000 { 431 compatible = "simple-bus"; 432 #address-cells = <1>; 433 #size-cells = <1>; 434 ranges = <0 0x1e78a000 0x1000>; 435 }; 436 }; 437 }; 438}; 439 440&i2c { 441 i2c_ic: interrupt-controller@0 { 442 #interrupt-cells = <1>; 443 compatible = "aspeed,ast2400-i2c-ic"; 444 reg = <0x0 0x40>; 445 interrupts = <12>; 446 interrupt-controller; 447 }; 448 449 i2c0: i2c-bus@40 { 450 #address-cells = <1>; 451 #size-cells = <0>; 452 #interrupt-cells = <1>; 453 454 reg = <0x40 0x40>; 455 compatible = "aspeed,ast2400-i2c-bus"; 456 clocks = <&syscon ASPEED_CLK_APB>; 457 resets = <&syscon ASPEED_RESET_I2C>; 458 bus-frequency = <100000>; 459 interrupts = <0>; 460 interrupt-parent = <&i2c_ic>; 461 status = "disabled"; 462 /* Does not need pinctrl properties */ 463 }; 464 465 i2c1: i2c-bus@80 { 466 #address-cells = <1>; 467 #size-cells = <0>; 468 #interrupt-cells = <1>; 469 470 reg = <0x80 0x40>; 471 compatible = "aspeed,ast2400-i2c-bus"; 472 clocks = <&syscon ASPEED_CLK_APB>; 473 resets = <&syscon ASPEED_RESET_I2C>; 474 bus-frequency = <100000>; 475 interrupts = <1>; 476 interrupt-parent = <&i2c_ic>; 477 status = "disabled"; 478 /* Does not need pinctrl properties */ 479 }; 480 481 i2c2: i2c-bus@c0 { 482 #address-cells = <1>; 483 #size-cells = <0>; 484 #interrupt-cells = <1>; 485 486 reg = <0xc0 0x40>; 487 compatible = "aspeed,ast2400-i2c-bus"; 488 clocks = <&syscon ASPEED_CLK_APB>; 489 resets = <&syscon ASPEED_RESET_I2C>; 490 bus-frequency = <100000>; 491 interrupts = <2>; 492 interrupt-parent = <&i2c_ic>; 493 pinctrl-names = "default"; 494 pinctrl-0 = <&pinctrl_i2c3_default>; 495 status = "disabled"; 496 }; 497 498 i2c3: i2c-bus@100 { 499 #address-cells = <1>; 500 #size-cells = <0>; 501 #interrupt-cells = <1>; 502 503 reg = <0x100 0x40>; 504 compatible = "aspeed,ast2400-i2c-bus"; 505 clocks = <&syscon ASPEED_CLK_APB>; 506 resets = <&syscon ASPEED_RESET_I2C>; 507 bus-frequency = <100000>; 508 interrupts = <3>; 509 interrupt-parent = <&i2c_ic>; 510 pinctrl-names = "default"; 511 pinctrl-0 = <&pinctrl_i2c4_default>; 512 status = "disabled"; 513 }; 514 515 i2c4: i2c-bus@140 { 516 #address-cells = <1>; 517 #size-cells = <0>; 518 #interrupt-cells = <1>; 519 520 reg = <0x140 0x40>; 521 compatible = "aspeed,ast2400-i2c-bus"; 522 clocks = <&syscon ASPEED_CLK_APB>; 523 resets = <&syscon ASPEED_RESET_I2C>; 524 bus-frequency = <100000>; 525 interrupts = <4>; 526 interrupt-parent = <&i2c_ic>; 527 pinctrl-names = "default"; 528 pinctrl-0 = <&pinctrl_i2c5_default>; 529 status = "disabled"; 530 }; 531 532 i2c5: i2c-bus@180 { 533 #address-cells = <1>; 534 #size-cells = <0>; 535 #interrupt-cells = <1>; 536 537 reg = <0x180 0x40>; 538 compatible = "aspeed,ast2400-i2c-bus"; 539 clocks = <&syscon ASPEED_CLK_APB>; 540 resets = <&syscon ASPEED_RESET_I2C>; 541 bus-frequency = <100000>; 542 interrupts = <5>; 543 interrupt-parent = <&i2c_ic>; 544 pinctrl-names = "default"; 545 pinctrl-0 = <&pinctrl_i2c6_default>; 546 status = "disabled"; 547 }; 548 549 i2c6: i2c-bus@1c0 { 550 #address-cells = <1>; 551 #size-cells = <0>; 552 #interrupt-cells = <1>; 553 554 reg = <0x1c0 0x40>; 555 compatible = "aspeed,ast2400-i2c-bus"; 556 clocks = <&syscon ASPEED_CLK_APB>; 557 resets = <&syscon ASPEED_RESET_I2C>; 558 bus-frequency = <100000>; 559 interrupts = <6>; 560 interrupt-parent = <&i2c_ic>; 561 pinctrl-names = "default"; 562 pinctrl-0 = <&pinctrl_i2c7_default>; 563 status = "disabled"; 564 }; 565 566 i2c7: i2c-bus@300 { 567 #address-cells = <1>; 568 #size-cells = <0>; 569 #interrupt-cells = <1>; 570 571 reg = <0x300 0x40>; 572 compatible = "aspeed,ast2400-i2c-bus"; 573 clocks = <&syscon ASPEED_CLK_APB>; 574 resets = <&syscon ASPEED_RESET_I2C>; 575 bus-frequency = <100000>; 576 interrupts = <7>; 577 interrupt-parent = <&i2c_ic>; 578 pinctrl-names = "default"; 579 pinctrl-0 = <&pinctrl_i2c8_default>; 580 status = "disabled"; 581 }; 582 583 i2c8: i2c-bus@340 { 584 #address-cells = <1>; 585 #size-cells = <0>; 586 #interrupt-cells = <1>; 587 588 reg = <0x340 0x40>; 589 compatible = "aspeed,ast2400-i2c-bus"; 590 clocks = <&syscon ASPEED_CLK_APB>; 591 resets = <&syscon ASPEED_RESET_I2C>; 592 bus-frequency = <100000>; 593 interrupts = <8>; 594 interrupt-parent = <&i2c_ic>; 595 pinctrl-names = "default"; 596 pinctrl-0 = <&pinctrl_i2c9_default>; 597 status = "disabled"; 598 }; 599 600 i2c9: i2c-bus@380 { 601 #address-cells = <1>; 602 #size-cells = <0>; 603 #interrupt-cells = <1>; 604 605 reg = <0x380 0x40>; 606 compatible = "aspeed,ast2400-i2c-bus"; 607 clocks = <&syscon ASPEED_CLK_APB>; 608 resets = <&syscon ASPEED_RESET_I2C>; 609 bus-frequency = <100000>; 610 interrupts = <9>; 611 interrupt-parent = <&i2c_ic>; 612 pinctrl-names = "default"; 613 pinctrl-0 = <&pinctrl_i2c10_default>; 614 status = "disabled"; 615 }; 616 617 i2c10: i2c-bus@3c0 { 618 #address-cells = <1>; 619 #size-cells = <0>; 620 #interrupt-cells = <1>; 621 622 reg = <0x3c0 0x40>; 623 compatible = "aspeed,ast2400-i2c-bus"; 624 clocks = <&syscon ASPEED_CLK_APB>; 625 resets = <&syscon ASPEED_RESET_I2C>; 626 bus-frequency = <100000>; 627 interrupts = <10>; 628 interrupt-parent = <&i2c_ic>; 629 pinctrl-names = "default"; 630 pinctrl-0 = <&pinctrl_i2c11_default>; 631 status = "disabled"; 632 }; 633 634 i2c11: i2c-bus@400 { 635 #address-cells = <1>; 636 #size-cells = <0>; 637 #interrupt-cells = <1>; 638 639 reg = <0x400 0x40>; 640 compatible = "aspeed,ast2400-i2c-bus"; 641 clocks = <&syscon ASPEED_CLK_APB>; 642 resets = <&syscon ASPEED_RESET_I2C>; 643 bus-frequency = <100000>; 644 interrupts = <11>; 645 interrupt-parent = <&i2c_ic>; 646 pinctrl-names = "default"; 647 pinctrl-0 = <&pinctrl_i2c12_default>; 648 status = "disabled"; 649 }; 650 651 i2c12: i2c-bus@440 { 652 #address-cells = <1>; 653 #size-cells = <0>; 654 #interrupt-cells = <1>; 655 656 reg = <0x440 0x40>; 657 compatible = "aspeed,ast2400-i2c-bus"; 658 clocks = <&syscon ASPEED_CLK_APB>; 659 resets = <&syscon ASPEED_RESET_I2C>; 660 bus-frequency = <100000>; 661 interrupts = <12>; 662 interrupt-parent = <&i2c_ic>; 663 pinctrl-names = "default"; 664 pinctrl-0 = <&pinctrl_i2c13_default>; 665 status = "disabled"; 666 }; 667 668 i2c13: i2c-bus@480 { 669 #address-cells = <1>; 670 #size-cells = <0>; 671 #interrupt-cells = <1>; 672 673 reg = <0x480 0x40>; 674 compatible = "aspeed,ast2400-i2c-bus"; 675 clocks = <&syscon ASPEED_CLK_APB>; 676 resets = <&syscon ASPEED_RESET_I2C>; 677 bus-frequency = <100000>; 678 interrupts = <13>; 679 interrupt-parent = <&i2c_ic>; 680 pinctrl-names = "default"; 681 pinctrl-0 = <&pinctrl_i2c14_default>; 682 status = "disabled"; 683 }; 684}; 685 686&pinctrl { 687 pinctrl_acpi_default: acpi_default { 688 function = "ACPI"; 689 groups = "ACPI"; 690 }; 691 692 pinctrl_adc0_default: adc0_default { 693 function = "ADC0"; 694 groups = "ADC0"; 695 }; 696 697 pinctrl_adc1_default: adc1_default { 698 function = "ADC1"; 699 groups = "ADC1"; 700 }; 701 702 pinctrl_adc10_default: adc10_default { 703 function = "ADC10"; 704 groups = "ADC10"; 705 }; 706 707 pinctrl_adc11_default: adc11_default { 708 function = "ADC11"; 709 groups = "ADC11"; 710 }; 711 712 pinctrl_adc12_default: adc12_default { 713 function = "ADC12"; 714 groups = "ADC12"; 715 }; 716 717 pinctrl_adc13_default: adc13_default { 718 function = "ADC13"; 719 groups = "ADC13"; 720 }; 721 722 pinctrl_adc14_default: adc14_default { 723 function = "ADC14"; 724 groups = "ADC14"; 725 }; 726 727 pinctrl_adc15_default: adc15_default { 728 function = "ADC15"; 729 groups = "ADC15"; 730 }; 731 732 pinctrl_adc2_default: adc2_default { 733 function = "ADC2"; 734 groups = "ADC2"; 735 }; 736 737 pinctrl_adc3_default: adc3_default { 738 function = "ADC3"; 739 groups = "ADC3"; 740 }; 741 742 pinctrl_adc4_default: adc4_default { 743 function = "ADC4"; 744 groups = "ADC4"; 745 }; 746 747 pinctrl_adc5_default: adc5_default { 748 function = "ADC5"; 749 groups = "ADC5"; 750 }; 751 752 pinctrl_adc6_default: adc6_default { 753 function = "ADC6"; 754 groups = "ADC6"; 755 }; 756 757 pinctrl_adc7_default: adc7_default { 758 function = "ADC7"; 759 groups = "ADC7"; 760 }; 761 762 pinctrl_adc8_default: adc8_default { 763 function = "ADC8"; 764 groups = "ADC8"; 765 }; 766 767 pinctrl_adc9_default: adc9_default { 768 function = "ADC9"; 769 groups = "ADC9"; 770 }; 771 772 pinctrl_bmcint_default: bmcint_default { 773 function = "BMCINT"; 774 groups = "BMCINT"; 775 }; 776 777 pinctrl_ddcclk_default: ddcclk_default { 778 function = "DDCCLK"; 779 groups = "DDCCLK"; 780 }; 781 782 pinctrl_ddcdat_default: ddcdat_default { 783 function = "DDCDAT"; 784 groups = "DDCDAT"; 785 }; 786 787 pinctrl_extrst_default: extrst_default { 788 function = "EXTRST"; 789 groups = "EXTRST"; 790 }; 791 792 pinctrl_flack_default: flack_default { 793 function = "FLACK"; 794 groups = "FLACK"; 795 }; 796 797 pinctrl_flbusy_default: flbusy_default { 798 function = "FLBUSY"; 799 groups = "FLBUSY"; 800 }; 801 802 pinctrl_flwp_default: flwp_default { 803 function = "FLWP"; 804 groups = "FLWP"; 805 }; 806 807 pinctrl_gpid_default: gpid_default { 808 function = "GPID"; 809 groups = "GPID"; 810 }; 811 812 pinctrl_gpid0_default: gpid0_default { 813 function = "GPID0"; 814 groups = "GPID0"; 815 }; 816 817 pinctrl_gpid2_default: gpid2_default { 818 function = "GPID2"; 819 groups = "GPID2"; 820 }; 821 822 pinctrl_gpid4_default: gpid4_default { 823 function = "GPID4"; 824 groups = "GPID4"; 825 }; 826 827 pinctrl_gpid6_default: gpid6_default { 828 function = "GPID6"; 829 groups = "GPID6"; 830 }; 831 832 pinctrl_gpie0_default: gpie0_default { 833 function = "GPIE0"; 834 groups = "GPIE0"; 835 }; 836 837 pinctrl_gpie2_default: gpie2_default { 838 function = "GPIE2"; 839 groups = "GPIE2"; 840 }; 841 842 pinctrl_gpie4_default: gpie4_default { 843 function = "GPIE4"; 844 groups = "GPIE4"; 845 }; 846 847 pinctrl_gpie6_default: gpie6_default { 848 function = "GPIE6"; 849 groups = "GPIE6"; 850 }; 851 852 pinctrl_i2c10_default: i2c10_default { 853 function = "I2C10"; 854 groups = "I2C10"; 855 }; 856 857 pinctrl_i2c11_default: i2c11_default { 858 function = "I2C11"; 859 groups = "I2C11"; 860 }; 861 862 pinctrl_i2c12_default: i2c12_default { 863 function = "I2C12"; 864 groups = "I2C12"; 865 }; 866 867 pinctrl_i2c13_default: i2c13_default { 868 function = "I2C13"; 869 groups = "I2C13"; 870 }; 871 872 pinctrl_i2c14_default: i2c14_default { 873 function = "I2C14"; 874 groups = "I2C14"; 875 }; 876 877 pinctrl_i2c3_default: i2c3_default { 878 function = "I2C3"; 879 groups = "I2C3"; 880 }; 881 882 pinctrl_i2c4_default: i2c4_default { 883 function = "I2C4"; 884 groups = "I2C4"; 885 }; 886 887 pinctrl_i2c5_default: i2c5_default { 888 function = "I2C5"; 889 groups = "I2C5"; 890 }; 891 892 pinctrl_i2c6_default: i2c6_default { 893 function = "I2C6"; 894 groups = "I2C6"; 895 }; 896 897 pinctrl_i2c7_default: i2c7_default { 898 function = "I2C7"; 899 groups = "I2C7"; 900 }; 901 902 pinctrl_i2c8_default: i2c8_default { 903 function = "I2C8"; 904 groups = "I2C8"; 905 }; 906 907 pinctrl_i2c9_default: i2c9_default { 908 function = "I2C9"; 909 groups = "I2C9"; 910 }; 911 912 pinctrl_lpcpd_default: lpcpd_default { 913 function = "LPCPD"; 914 groups = "LPCPD"; 915 }; 916 917 pinctrl_lpcpme_default: lpcpme_default { 918 function = "LPCPME"; 919 groups = "LPCPME"; 920 }; 921 922 pinctrl_lpcrst_default: lpcrst_default { 923 function = "LPCRST"; 924 groups = "LPCRST"; 925 }; 926 927 pinctrl_lpcsmi_default: lpcsmi_default { 928 function = "LPCSMI"; 929 groups = "LPCSMI"; 930 }; 931 932 pinctrl_mac1link_default: mac1link_default { 933 function = "MAC1LINK"; 934 groups = "MAC1LINK"; 935 }; 936 937 pinctrl_mac2link_default: mac2link_default { 938 function = "MAC2LINK"; 939 groups = "MAC2LINK"; 940 }; 941 942 pinctrl_mdio1_default: mdio1_default { 943 function = "MDIO1"; 944 groups = "MDIO1"; 945 }; 946 947 pinctrl_mdio2_default: mdio2_default { 948 function = "MDIO2"; 949 groups = "MDIO2"; 950 }; 951 952 pinctrl_ncts1_default: ncts1_default { 953 function = "NCTS1"; 954 groups = "NCTS1"; 955 }; 956 957 pinctrl_ncts2_default: ncts2_default { 958 function = "NCTS2"; 959 groups = "NCTS2"; 960 }; 961 962 pinctrl_ncts3_default: ncts3_default { 963 function = "NCTS3"; 964 groups = "NCTS3"; 965 }; 966 967 pinctrl_ncts4_default: ncts4_default { 968 function = "NCTS4"; 969 groups = "NCTS4"; 970 }; 971 972 pinctrl_ndcd1_default: ndcd1_default { 973 function = "NDCD1"; 974 groups = "NDCD1"; 975 }; 976 977 pinctrl_ndcd2_default: ndcd2_default { 978 function = "NDCD2"; 979 groups = "NDCD2"; 980 }; 981 982 pinctrl_ndcd3_default: ndcd3_default { 983 function = "NDCD3"; 984 groups = "NDCD3"; 985 }; 986 987 pinctrl_ndcd4_default: ndcd4_default { 988 function = "NDCD4"; 989 groups = "NDCD4"; 990 }; 991 992 pinctrl_ndsr1_default: ndsr1_default { 993 function = "NDSR1"; 994 groups = "NDSR1"; 995 }; 996 997 pinctrl_ndsr2_default: ndsr2_default { 998 function = "NDSR2"; 999 groups = "NDSR2"; 1000 }; 1001 1002 pinctrl_ndsr3_default: ndsr3_default { 1003 function = "NDSR3"; 1004 groups = "NDSR3"; 1005 }; 1006 1007 pinctrl_ndsr4_default: ndsr4_default { 1008 function = "NDSR4"; 1009 groups = "NDSR4"; 1010 }; 1011 1012 pinctrl_ndtr1_default: ndtr1_default { 1013 function = "NDTR1"; 1014 groups = "NDTR1"; 1015 }; 1016 1017 pinctrl_ndtr2_default: ndtr2_default { 1018 function = "NDTR2"; 1019 groups = "NDTR2"; 1020 }; 1021 1022 pinctrl_ndtr3_default: ndtr3_default { 1023 function = "NDTR3"; 1024 groups = "NDTR3"; 1025 }; 1026 1027 pinctrl_ndtr4_default: ndtr4_default { 1028 function = "NDTR4"; 1029 groups = "NDTR4"; 1030 }; 1031 1032 pinctrl_ndts4_default: ndts4_default { 1033 function = "NDTS4"; 1034 groups = "NDTS4"; 1035 }; 1036 1037 pinctrl_nri1_default: nri1_default { 1038 function = "NRI1"; 1039 groups = "NRI1"; 1040 }; 1041 1042 pinctrl_nri2_default: nri2_default { 1043 function = "NRI2"; 1044 groups = "NRI2"; 1045 }; 1046 1047 pinctrl_nri3_default: nri3_default { 1048 function = "NRI3"; 1049 groups = "NRI3"; 1050 }; 1051 1052 pinctrl_nri4_default: nri4_default { 1053 function = "NRI4"; 1054 groups = "NRI4"; 1055 }; 1056 1057 pinctrl_nrts1_default: nrts1_default { 1058 function = "NRTS1"; 1059 groups = "NRTS1"; 1060 }; 1061 1062 pinctrl_nrts2_default: nrts2_default { 1063 function = "NRTS2"; 1064 groups = "NRTS2"; 1065 }; 1066 1067 pinctrl_nrts3_default: nrts3_default { 1068 function = "NRTS3"; 1069 groups = "NRTS3"; 1070 }; 1071 1072 pinctrl_oscclk_default: oscclk_default { 1073 function = "OSCCLK"; 1074 groups = "OSCCLK"; 1075 }; 1076 1077 pinctrl_pwm0_default: pwm0_default { 1078 function = "PWM0"; 1079 groups = "PWM0"; 1080 }; 1081 1082 pinctrl_pwm1_default: pwm1_default { 1083 function = "PWM1"; 1084 groups = "PWM1"; 1085 }; 1086 1087 pinctrl_pwm2_default: pwm2_default { 1088 function = "PWM2"; 1089 groups = "PWM2"; 1090 }; 1091 1092 pinctrl_pwm3_default: pwm3_default { 1093 function = "PWM3"; 1094 groups = "PWM3"; 1095 }; 1096 1097 pinctrl_pwm4_default: pwm4_default { 1098 function = "PWM4"; 1099 groups = "PWM4"; 1100 }; 1101 1102 pinctrl_pwm5_default: pwm5_default { 1103 function = "PWM5"; 1104 groups = "PWM5"; 1105 }; 1106 1107 pinctrl_pwm6_default: pwm6_default { 1108 function = "PWM6"; 1109 groups = "PWM6"; 1110 }; 1111 1112 pinctrl_pwm7_default: pwm7_default { 1113 function = "PWM7"; 1114 groups = "PWM7"; 1115 }; 1116 1117 pinctrl_rgmii1_default: rgmii1_default { 1118 function = "RGMII1"; 1119 groups = "RGMII1"; 1120 }; 1121 1122 pinctrl_rgmii2_default: rgmii2_default { 1123 function = "RGMII2"; 1124 groups = "RGMII2"; 1125 }; 1126 1127 pinctrl_rmii1_default: rmii1_default { 1128 function = "RMII1"; 1129 groups = "RMII1"; 1130 }; 1131 1132 pinctrl_rmii2_default: rmii2_default { 1133 function = "RMII2"; 1134 groups = "RMII2"; 1135 }; 1136 1137 pinctrl_rom16_default: rom16_default { 1138 function = "ROM16"; 1139 groups = "ROM16"; 1140 }; 1141 1142 pinctrl_rom8_default: rom8_default { 1143 function = "ROM8"; 1144 groups = "ROM8"; 1145 }; 1146 1147 pinctrl_romcs1_default: romcs1_default { 1148 function = "ROMCS1"; 1149 groups = "ROMCS1"; 1150 }; 1151 1152 pinctrl_romcs2_default: romcs2_default { 1153 function = "ROMCS2"; 1154 groups = "ROMCS2"; 1155 }; 1156 1157 pinctrl_romcs3_default: romcs3_default { 1158 function = "ROMCS3"; 1159 groups = "ROMCS3"; 1160 }; 1161 1162 pinctrl_romcs4_default: romcs4_default { 1163 function = "ROMCS4"; 1164 groups = "ROMCS4"; 1165 }; 1166 1167 pinctrl_rxd1_default: rxd1_default { 1168 function = "RXD1"; 1169 groups = "RXD1"; 1170 }; 1171 1172 pinctrl_rxd2_default: rxd2_default { 1173 function = "RXD2"; 1174 groups = "RXD2"; 1175 }; 1176 1177 pinctrl_rxd3_default: rxd3_default { 1178 function = "RXD3"; 1179 groups = "RXD3"; 1180 }; 1181 1182 pinctrl_rxd4_default: rxd4_default { 1183 function = "RXD4"; 1184 groups = "RXD4"; 1185 }; 1186 1187 pinctrl_salt1_default: salt1_default { 1188 function = "SALT1"; 1189 groups = "SALT1"; 1190 }; 1191 1192 pinctrl_salt2_default: salt2_default { 1193 function = "SALT2"; 1194 groups = "SALT2"; 1195 }; 1196 1197 pinctrl_salt3_default: salt3_default { 1198 function = "SALT3"; 1199 groups = "SALT3"; 1200 }; 1201 1202 pinctrl_salt4_default: salt4_default { 1203 function = "SALT4"; 1204 groups = "SALT4"; 1205 }; 1206 1207 pinctrl_sd1_default: sd1_default { 1208 function = "SD1"; 1209 groups = "SD1"; 1210 }; 1211 1212 pinctrl_sd2_default: sd2_default { 1213 function = "SD2"; 1214 groups = "SD2"; 1215 }; 1216 1217 pinctrl_sgpmck_default: sgpmck_default { 1218 function = "SGPMCK"; 1219 groups = "SGPMCK"; 1220 }; 1221 1222 pinctrl_sgpmi_default: sgpmi_default { 1223 function = "SGPMI"; 1224 groups = "SGPMI"; 1225 }; 1226 1227 pinctrl_sgpmld_default: sgpmld_default { 1228 function = "SGPMLD"; 1229 groups = "SGPMLD"; 1230 }; 1231 1232 pinctrl_sgpmo_default: sgpmo_default { 1233 function = "SGPMO"; 1234 groups = "SGPMO"; 1235 }; 1236 1237 pinctrl_sgpsck_default: sgpsck_default { 1238 function = "SGPSCK"; 1239 groups = "SGPSCK"; 1240 }; 1241 1242 pinctrl_sgpsi0_default: sgpsi0_default { 1243 function = "SGPSI0"; 1244 groups = "SGPSI0"; 1245 }; 1246 1247 pinctrl_sgpsi1_default: sgpsi1_default { 1248 function = "SGPSI1"; 1249 groups = "SGPSI1"; 1250 }; 1251 1252 pinctrl_sgpsld_default: sgpsld_default { 1253 function = "SGPSLD"; 1254 groups = "SGPSLD"; 1255 }; 1256 1257 pinctrl_sioonctrl_default: sioonctrl_default { 1258 function = "SIOONCTRL"; 1259 groups = "SIOONCTRL"; 1260 }; 1261 1262 pinctrl_siopbi_default: siopbi_default { 1263 function = "SIOPBI"; 1264 groups = "SIOPBI"; 1265 }; 1266 1267 pinctrl_siopbo_default: siopbo_default { 1268 function = "SIOPBO"; 1269 groups = "SIOPBO"; 1270 }; 1271 1272 pinctrl_siopwreq_default: siopwreq_default { 1273 function = "SIOPWREQ"; 1274 groups = "SIOPWREQ"; 1275 }; 1276 1277 pinctrl_siopwrgd_default: siopwrgd_default { 1278 function = "SIOPWRGD"; 1279 groups = "SIOPWRGD"; 1280 }; 1281 1282 pinctrl_sios3_default: sios3_default { 1283 function = "SIOS3"; 1284 groups = "SIOS3"; 1285 }; 1286 1287 pinctrl_sios5_default: sios5_default { 1288 function = "SIOS5"; 1289 groups = "SIOS5"; 1290 }; 1291 1292 pinctrl_siosci_default: siosci_default { 1293 function = "SIOSCI"; 1294 groups = "SIOSCI"; 1295 }; 1296 1297 pinctrl_spi1_default: spi1_default { 1298 function = "SPI1"; 1299 groups = "SPI1"; 1300 }; 1301 1302 pinctrl_spi1debug_default: spi1debug_default { 1303 function = "SPI1DEBUG"; 1304 groups = "SPI1DEBUG"; 1305 }; 1306 1307 pinctrl_spi1passthru_default: spi1passthru_default { 1308 function = "SPI1PASSTHRU"; 1309 groups = "SPI1PASSTHRU"; 1310 }; 1311 1312 pinctrl_spics1_default: spics1_default { 1313 function = "SPICS1"; 1314 groups = "SPICS1"; 1315 }; 1316 1317 pinctrl_timer3_default: timer3_default { 1318 function = "TIMER3"; 1319 groups = "TIMER3"; 1320 }; 1321 1322 pinctrl_timer4_default: timer4_default { 1323 function = "TIMER4"; 1324 groups = "TIMER4"; 1325 }; 1326 1327 pinctrl_timer5_default: timer5_default { 1328 function = "TIMER5"; 1329 groups = "TIMER5"; 1330 }; 1331 1332 pinctrl_timer6_default: timer6_default { 1333 function = "TIMER6"; 1334 groups = "TIMER6"; 1335 }; 1336 1337 pinctrl_timer7_default: timer7_default { 1338 function = "TIMER7"; 1339 groups = "TIMER7"; 1340 }; 1341 1342 pinctrl_timer8_default: timer8_default { 1343 function = "TIMER8"; 1344 groups = "TIMER8"; 1345 }; 1346 1347 pinctrl_txd1_default: txd1_default { 1348 function = "TXD1"; 1349 groups = "TXD1"; 1350 }; 1351 1352 pinctrl_txd2_default: txd2_default { 1353 function = "TXD2"; 1354 groups = "TXD2"; 1355 }; 1356 1357 pinctrl_txd3_default: txd3_default { 1358 function = "TXD3"; 1359 groups = "TXD3"; 1360 }; 1361 1362 pinctrl_txd4_default: txd4_default { 1363 function = "TXD4"; 1364 groups = "TXD4"; 1365 }; 1366 1367 pinctrl_uart6_default: uart6_default { 1368 function = "UART6"; 1369 groups = "UART6"; 1370 }; 1371 1372 pinctrl_usbcki_default: usbcki_default { 1373 function = "USBCKI"; 1374 groups = "USBCKI"; 1375 }; 1376 1377 pinctrl_usb2h_default: usb2h_default { 1378 function = "USB2H1"; 1379 groups = "USB2H1"; 1380 }; 1381 1382 pinctrl_usb2d_default: usb2d_default { 1383 function = "USB2D1"; 1384 groups = "USB2D1"; 1385 }; 1386 1387 pinctrl_vgabios_rom_default: vgabios_rom_default { 1388 function = "VGABIOS_ROM"; 1389 groups = "VGABIOS_ROM"; 1390 }; 1391 1392 pinctrl_vgahs_default: vgahs_default { 1393 function = "VGAHS"; 1394 groups = "VGAHS"; 1395 }; 1396 1397 pinctrl_vgavs_default: vgavs_default { 1398 function = "VGAVS"; 1399 groups = "VGAVS"; 1400 }; 1401 1402 pinctrl_vpi18_default: vpi18_default { 1403 function = "VPI18"; 1404 groups = "VPI18"; 1405 }; 1406 1407 pinctrl_vpi24_default: vpi24_default { 1408 function = "VPI24"; 1409 groups = "VPI24"; 1410 }; 1411 1412 pinctrl_vpi30_default: vpi30_default { 1413 function = "VPI30"; 1414 groups = "VPI30"; 1415 }; 1416 1417 pinctrl_vpo12_default: vpo12_default { 1418 function = "VPO12"; 1419 groups = "VPO12"; 1420 }; 1421 1422 pinctrl_vpo24_default: vpo24_default { 1423 function = "VPO24"; 1424 groups = "VPO24"; 1425 }; 1426 1427 pinctrl_wdtrst1_default: wdtrst1_default { 1428 function = "WDTRST1"; 1429 groups = "WDTRST1"; 1430 }; 1431 1432 pinctrl_wdtrst2_default: wdtrst2_default { 1433 function = "WDTRST2"; 1434 groups = "WDTRST2"; 1435 }; 1436}; 1437