1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/ 4 */ 5/dts-v1/; 6 7#include "dra76x.dtsi" 8#include "dra7-evm-common.dtsi" 9#include "dra76x-mmc-iodelay.dtsi" 10#include <dt-bindings/net/ti-dp83867.h> 11 12/ { 13 model = "TI DRA762 EVM"; 14 compatible = "ti,dra76-evm", "ti,dra762", "ti,dra7"; 15 16 aliases { 17 display0 = &hdmi0; 18 19 sound0 = &sound0; 20 sound1 = &hdmi; 21 }; 22 23 memory@0 { 24 device_type = "memory"; 25 reg = <0x0 0x80000000 0x0 0x80000000>; 26 }; 27 28 reserved-memory { 29 #address-cells = <2>; 30 #size-cells = <2>; 31 ranges; 32 33 ipu2_cma_pool: ipu2_cma@95800000 { 34 compatible = "shared-dma-pool"; 35 reg = <0x0 0x95800000 0x0 0x3800000>; 36 reusable; 37 status = "okay"; 38 }; 39 40 dsp1_cma_pool: dsp1_cma@99000000 { 41 compatible = "shared-dma-pool"; 42 reg = <0x0 0x99000000 0x0 0x4000000>; 43 reusable; 44 status = "okay"; 45 }; 46 47 ipu1_cma_pool: ipu1_cma@9d000000 { 48 compatible = "shared-dma-pool"; 49 reg = <0x0 0x9d000000 0x0 0x2000000>; 50 reusable; 51 status = "okay"; 52 }; 53 54 dsp2_cma_pool: dsp2_cma@9f000000 { 55 compatible = "shared-dma-pool"; 56 reg = <0x0 0x9f000000 0x0 0x800000>; 57 reusable; 58 status = "okay"; 59 }; 60 }; 61 62 vsys_12v0: fixedregulator-vsys12v0 { 63 /* main supply */ 64 compatible = "regulator-fixed"; 65 regulator-name = "vsys_12v0"; 66 regulator-min-microvolt = <12000000>; 67 regulator-max-microvolt = <12000000>; 68 regulator-always-on; 69 regulator-boot-on; 70 }; 71 72 vsys_5v0: fixedregulator-vsys5v0 { 73 /* Output of Cntlr B of TPS43351-Q1 on dra76-evm */ 74 compatible = "regulator-fixed"; 75 regulator-name = "vsys_5v0"; 76 regulator-min-microvolt = <5000000>; 77 regulator-max-microvolt = <5000000>; 78 vin-supply = <&vsys_12v0>; 79 regulator-always-on; 80 regulator-boot-on; 81 }; 82 83 vio_3v6: fixedregulator-vio_3v6 { 84 compatible = "regulator-fixed"; 85 regulator-name = "vio_3v6"; 86 regulator-min-microvolt = <3600000>; 87 regulator-max-microvolt = <3600000>; 88 vin-supply = <&vsys_5v0>; 89 regulator-always-on; 90 regulator-boot-on; 91 }; 92 93 vsys_3v3: fixedregulator-vsys3v3 { 94 /* Output of Cntlr A of TPS43351-Q1 on dra76-evm */ 95 compatible = "regulator-fixed"; 96 regulator-name = "vsys_3v3"; 97 regulator-min-microvolt = <3300000>; 98 regulator-max-microvolt = <3300000>; 99 vin-supply = <&vsys_12v0>; 100 regulator-always-on; 101 regulator-boot-on; 102 }; 103 104 vio_3v3: fixedregulator-vio_3v3 { 105 compatible = "regulator-fixed"; 106 regulator-name = "vio_3v3"; 107 regulator-min-microvolt = <3300000>; 108 regulator-max-microvolt = <3300000>; 109 vin-supply = <&vsys_3v3>; 110 regulator-always-on; 111 regulator-boot-on; 112 }; 113 114 vio_3v3_sd: fixedregulator-sd { 115 compatible = "regulator-fixed"; 116 regulator-name = "vio_3v3_sd"; 117 regulator-min-microvolt = <3300000>; 118 regulator-max-microvolt = <3300000>; 119 vin-supply = <&vio_3v3>; 120 enable-active-high; 121 gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>; 122 }; 123 124 vio_1v8: fixedregulator-vio_1v8 { 125 compatible = "regulator-fixed"; 126 regulator-name = "vio_1v8"; 127 regulator-min-microvolt = <1800000>; 128 regulator-max-microvolt = <1800000>; 129 vin-supply = <&smps5_reg>; 130 }; 131 132 vmmcwl_fixed: fixedregulator-mmcwl { 133 compatible = "regulator-fixed"; 134 regulator-name = "vmmcwl_fixed"; 135 regulator-min-microvolt = <1800000>; 136 regulator-max-microvolt = <1800000>; 137 gpio = <&gpio5 8 0>; /* gpio5_8 */ 138 startup-delay-us = <70000>; 139 enable-active-high; 140 }; 141 142 vtt_fixed: fixedregulator-vtt { 143 compatible = "regulator-fixed"; 144 regulator-name = "vtt_fixed"; 145 regulator-min-microvolt = <1350000>; 146 regulator-max-microvolt = <1350000>; 147 vin-supply = <&vsys_3v3>; 148 regulator-always-on; 149 regulator-boot-on; 150 }; 151 152 aic_dvdd: fixedregulator-aic_dvdd { 153 /* TPS77018DBVT */ 154 compatible = "regulator-fixed"; 155 regulator-name = "aic_dvdd"; 156 vin-supply = <&vio_3v3>; 157 regulator-min-microvolt = <1800000>; 158 regulator-max-microvolt = <1800000>; 159 }; 160 161 clk_ov5640_fixed: clock { 162 compatible = "fixed-clock"; 163 #clock-cells = <0>; 164 clock-frequency = <24000000>; 165 }; 166 167 hdmi0: connector { 168 compatible = "hdmi-connector"; 169 label = "hdmi"; 170 171 type = "a"; 172 173 port { 174 hdmi_connector_in: endpoint { 175 remote-endpoint = <&tpd12s015_out>; 176 }; 177 }; 178 }; 179 180 tpd12s015: encoder { 181 compatible = "ti,tpd12s015"; 182 183 gpios = <&gpio7 30 GPIO_ACTIVE_HIGH>, /* gpio7_30, CT CP HPD */ 184 <&gpio7 31 GPIO_ACTIVE_HIGH>, /* gpio7_31, LS OE */ 185 <&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */ 186 187 ports { 188 #address-cells = <1>; 189 #size-cells = <0>; 190 191 port@0 { 192 reg = <0>; 193 194 tpd12s015_in: endpoint { 195 remote-endpoint = <&hdmi_out>; 196 }; 197 }; 198 199 port@1 { 200 reg = <1>; 201 202 tpd12s015_out: endpoint { 203 remote-endpoint = <&hdmi_connector_in>; 204 }; 205 }; 206 }; 207 }; 208}; 209 210&i2c1 { 211 status = "okay"; 212 clock-frequency = <400000>; 213 214 tps65917: tps65917@58 { 215 compatible = "ti,tps65917"; 216 reg = <0x58>; 217 ti,system-power-controller; 218 ti,palmas-override-powerhold; 219 interrupt-controller; 220 #interrupt-cells = <2>; 221 222 tps65917_pmic { 223 compatible = "ti,tps65917-pmic"; 224 225 smps12-in-supply = <&vsys_3v3>; 226 smps3-in-supply = <&vsys_3v3>; 227 smps4-in-supply = <&vsys_3v3>; 228 smps5-in-supply = <&vsys_3v3>; 229 ldo1-in-supply = <&vsys_3v3>; 230 ldo2-in-supply = <&vsys_3v3>; 231 ldo3-in-supply = <&vsys_5v0>; 232 ldo4-in-supply = <&vsys_5v0>; 233 ldo5-in-supply = <&vsys_3v3>; 234 235 tps65917_regulators: regulators { 236 smps12_reg: smps12 { 237 /* VDD_DSPEVE */ 238 regulator-name = "smps12"; 239 regulator-min-microvolt = <850000>; 240 regulator-max-microvolt = <1250000>; 241 regulator-always-on; 242 regulator-boot-on; 243 }; 244 245 smps3_reg: smps3 { 246 /* VDD_CORE */ 247 regulator-name = "smps3"; 248 regulator-min-microvolt = <850000>; 249 regulator-max-microvolt = <1250000>; 250 regulator-boot-on; 251 regulator-always-on; 252 }; 253 254 smps4_reg: smps4 { 255 /* VDD_IVA */ 256 regulator-name = "smps4"; 257 regulator-min-microvolt = <850000>; 258 regulator-max-microvolt = <1250000>; 259 regulator-always-on; 260 regulator-boot-on; 261 }; 262 263 smps5_reg: smps5 { 264 /* VDDS1V8 */ 265 regulator-name = "smps5"; 266 regulator-min-microvolt = <1800000>; 267 regulator-max-microvolt = <1800000>; 268 regulator-boot-on; 269 regulator-always-on; 270 }; 271 272 ldo1_reg: ldo1 { 273 /* LDO1_OUT --> VDA_PHY1_1V8 */ 274 regulator-name = "ldo1"; 275 regulator-min-microvolt = <1800000>; 276 regulator-max-microvolt = <1800000>; 277 regulator-always-on; 278 regulator-boot-on; 279 regulator-allow-bypass; 280 }; 281 282 ldo2_reg: ldo2 { 283 /* LDO2_OUT --> VDA_PHY2_1V8 */ 284 regulator-name = "ldo2"; 285 regulator-min-microvolt = <1800000>; 286 regulator-max-microvolt = <1800000>; 287 regulator-allow-bypass; 288 regulator-always-on; 289 }; 290 291 ldo3_reg: ldo3 { 292 /* VDA_USB_3V3 */ 293 regulator-name = "ldo3"; 294 regulator-min-microvolt = <3300000>; 295 regulator-max-microvolt = <3300000>; 296 regulator-boot-on; 297 regulator-always-on; 298 }; 299 300 ldo5_reg: ldo5 { 301 /* VDDA_1V8_PLL */ 302 regulator-name = "ldo5"; 303 regulator-min-microvolt = <1800000>; 304 regulator-max-microvolt = <1800000>; 305 regulator-always-on; 306 regulator-boot-on; 307 }; 308 309 ldo4_reg: ldo4 { 310 /* VDD_SDIO_DV */ 311 regulator-name = "ldo4"; 312 regulator-min-microvolt = <1800000>; 313 regulator-max-microvolt = <3300000>; 314 regulator-boot-on; 315 regulator-always-on; 316 }; 317 }; 318 }; 319 320 tps65917_power_button { 321 compatible = "ti,palmas-pwrbutton"; 322 interrupt-parent = <&tps65917>; 323 interrupts = <1 IRQ_TYPE_NONE>; 324 wakeup-source; 325 ti,palmas-long-press-seconds = <6>; 326 }; 327 }; 328 329 lp87565: lp87565@60 { 330 compatible = "ti,lp87565-q1"; 331 reg = <0x60>; 332 333 buck10-in-supply =<&vsys_3v3>; 334 buck23-in-supply =<&vsys_3v3>; 335 336 regulators: regulators { 337 buck10_reg: buck10 { 338 /*VDD_MPU*/ 339 regulator-name = "buck10"; 340 regulator-min-microvolt = <850000>; 341 regulator-max-microvolt = <1250000>; 342 regulator-always-on; 343 regulator-boot-on; 344 }; 345 346 buck23_reg: buck23 { 347 /* VDD_GPU*/ 348 regulator-name = "buck23"; 349 regulator-min-microvolt = <850000>; 350 regulator-max-microvolt = <1250000>; 351 regulator-boot-on; 352 regulator-always-on; 353 }; 354 }; 355 }; 356 357 pcf_lcd: pcf8757@20 { 358 compatible = "ti,pcf8575", "nxp,pcf8575"; 359 reg = <0x20>; 360 gpio-controller; 361 #gpio-cells = <2>; 362 interrupt-controller; 363 #interrupt-cells = <2>; 364 interrupt-parent = <&gpio1>; 365 interrupts = <3 IRQ_TYPE_EDGE_FALLING>; 366 }; 367 368 pcf_gpio_21: pcf8757@21 { 369 compatible = "ti,pcf8575", "nxp,pcf8575"; 370 reg = <0x21>; 371 gpio-controller; 372 #gpio-cells = <2>; 373 interrupt-parent = <&gpio1>; 374 interrupts = <3 IRQ_TYPE_EDGE_FALLING>; 375 interrupt-controller; 376 #interrupt-cells = <2>; 377 }; 378 379 pcf_hdmi: pcf8575@26 { 380 compatible = "ti,pcf8575", "nxp,pcf8575"; 381 reg = <0x26>; 382 gpio-controller; 383 #gpio-cells = <2>; 384 p1 { 385 /* vin6_sel_s0: high: VIN6, low: audio */ 386 gpio-hog; 387 gpios = <1 GPIO_ACTIVE_HIGH>; 388 output-low; 389 line-name = "vin6_sel_s0"; 390 }; 391 }; 392 393 tlv320aic3106: tlv320aic3106@19 { 394 #sound-dai-cells = <0>; 395 compatible = "ti,tlv320aic3106"; 396 reg = <0x19>; 397 adc-settle-ms = <40>; 398 ai3x-micbias-vg = <1>; /* 2.0V */ 399 status = "okay"; 400 401 /* Regulators */ 402 AVDD-supply = <&vio_3v3>; 403 IOVDD-supply = <&vio_3v3>; 404 DRVDD-supply = <&vio_3v3>; 405 DVDD-supply = <&aic_dvdd>; 406 }; 407}; 408 409&i2c5 { 410 status = "okay"; 411 clock-frequency = <400000>; 412 413 ov5640@3c { 414 compatible = "ovti,ov5640"; 415 reg = <0x3c>; 416 417 clocks = <&clk_ov5640_fixed>; 418 clock-names = "xclk"; 419 420 port { 421 csi2_cam0: endpoint { 422 remote-endpoint = <&csi2_phy0>; 423 clock-lanes = <0>; 424 data-lanes = <1 2>; 425 }; 426 }; 427 }; 428}; 429 430&cpu0 { 431 vdd-supply = <&buck10_reg>; 432}; 433 434&mmc1 { 435 status = "okay"; 436 vmmc-supply = <&vio_3v3_sd>; 437 vqmmc-supply = <&ldo4_reg>; 438 bus-width = <4>; 439 /* 440 * SDCD signal is not being used here - using the fact that GPIO mode 441 * is always hardwired. 442 */ 443 cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; 444 pinctrl-names = "default", "hs"; 445 pinctrl-0 = <&mmc1_pins_default>; 446 pinctrl-1 = <&mmc1_pins_hs>; 447}; 448 449&mmc2 { 450 status = "okay"; 451 vmmc-supply = <&vio_1v8>; 452 vqmmc-supply = <&vio_1v8>; 453 bus-width = <8>; 454 non-removable; 455 pinctrl-names = "default", "hs", "ddr_1_8v", "hs200_1_8v"; 456 pinctrl-0 = <&mmc2_pins_default>; 457 pinctrl-1 = <&mmc2_pins_default>; 458 pinctrl-2 = <&mmc2_pins_default>; 459 pinctrl-3 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_conf>; 460}; 461 462&mmc4 { 463 status = "okay"; 464 vmmc-supply = <&vio_3v6>; 465 vqmmc-supply = <&vmmcwl_fixed>; 466 pinctrl-names = "default", "hs", "sdr12", "sdr25"; 467 pinctrl-0 = <&mmc4_pins_hs &mmc4_iodelay_default_conf>; 468 pinctrl-1 = <&mmc4_pins_hs &mmc4_iodelay_manual1_conf>; 469 pinctrl-2 = <&mmc4_pins_hs &mmc4_iodelay_manual1_conf>; 470 pinctrl-3 = <&mmc4_pins_hs &mmc4_iodelay_manual1_conf>; 471}; 472 473/* No RTC on this device */ 474&rtc { 475 status = "disabled"; 476}; 477 478&mac_sw { 479 status = "okay"; 480}; 481 482&cpsw_port1 { 483 phy-handle = <&dp83867_0>; 484 phy-mode = "rgmii-id"; 485 ti,dual-emac-pvid = <1>; 486}; 487 488&cpsw_port2 { 489 phy-handle = <&dp83867_1>; 490 phy-mode = "rgmii-id"; 491 ti,dual-emac-pvid = <2>; 492}; 493 494&davinci_mdio_sw { 495 dp83867_0: ethernet-phy@2 { 496 reg = <2>; 497 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; 498 ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>; 499 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>; 500 ti,min-output-impedance; 501 ti,dp83867-rxctrl-strap-quirk; 502 }; 503 504 dp83867_1: ethernet-phy@3 { 505 reg = <3>; 506 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; 507 ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>; 508 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>; 509 ti,min-output-impedance; 510 ti,dp83867-rxctrl-strap-quirk; 511 }; 512}; 513 514&usb2_phy1 { 515 phy-supply = <&ldo3_reg>; 516}; 517 518&usb2_phy2 { 519 phy-supply = <&ldo3_reg>; 520}; 521 522&dss { 523 status = "okay"; 524 vdda_video-supply = <&ldo5_reg>; 525}; 526 527&hdmi { 528 status = "okay"; 529 530 vdda-supply = <&ldo1_reg>; 531 532 port { 533 hdmi_out: endpoint { 534 remote-endpoint = <&tpd12s015_in>; 535 }; 536 }; 537}; 538 539&qspi { 540 spi-max-frequency = <96000000>; 541 m25p80@0 { 542 spi-max-frequency = <96000000>; 543 }; 544}; 545 546&pcie2_phy { 547 status = "okay"; 548}; 549 550&pcie1_rc { 551 num-lanes = <2>; 552 phys = <&pcie1_phy>, <&pcie2_phy>; 553 phy-names = "pcie-phy0", "pcie-phy1"; 554}; 555 556&pcie1_ep { 557 num-lanes = <2>; 558 phys = <&pcie1_phy>, <&pcie2_phy>; 559 phy-names = "pcie-phy0", "pcie-phy1"; 560}; 561 562&extcon_usb1 { 563 vbus-gpio = <&pcf_lcd 14 GPIO_ACTIVE_HIGH>; 564}; 565 566&extcon_usb2 { 567 vbus-gpio = <&pcf_lcd 15 GPIO_ACTIVE_HIGH>; 568}; 569 570&m_can0 { 571 can-transceiver { 572 max-bitrate = <5000000>; 573 }; 574}; 575 576&csi2_0 { 577 csi2_phy0: endpoint { 578 remote-endpoint = <&csi2_cam0>; 579 clock-lanes = <0>; 580 data-lanes = <1 2>; 581 }; 582}; 583 584&ipu2 { 585 status = "okay"; 586 memory-region = <&ipu2_cma_pool>; 587}; 588 589&ipu1 { 590 status = "okay"; 591 memory-region = <&ipu1_cma_pool>; 592}; 593 594&dsp1 { 595 status = "okay"; 596 memory-region = <&dsp1_cma_pool>; 597}; 598 599&dsp2 { 600 status = "okay"; 601 memory-region = <&dsp2_cma_pool>; 602}; 603