1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for J7200 SoC Family MCU/WAKEUP Domain peripherals 4 * 5 * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8&cbass_mcu_wakeup { 9 dmsc: dmsc@44083000 { 10 compatible = "ti,k2g-sci"; 11 ti,host-id = <12>; 12 13 mbox-names = "rx", "tx"; 14 15 mboxes= <&secure_proxy_main 11>, 16 <&secure_proxy_main 13>; 17 18 reg-names = "debug_messages"; 19 reg = <0x00 0x44083000 0x00 0x1000>; 20 21 k3_pds: power-controller { 22 compatible = "ti,sci-pm-domain"; 23 #power-domain-cells = <2>; 24 }; 25 26 k3_clks: clocks { 27 compatible = "ti,k2g-sci-clk"; 28 #clock-cells = <2>; 29 }; 30 31 k3_reset: reset-controller { 32 compatible = "ti,sci-reset"; 33 #reset-cells = <2>; 34 }; 35 }; 36 37 mcu_conf: syscon@40f00000 { 38 compatible = "syscon", "simple-mfd"; 39 reg = <0x00 0x40f00000 0x00 0x20000>; 40 #address-cells = <1>; 41 #size-cells = <1>; 42 ranges = <0x00 0x00 0x40f00000 0x20000>; 43 44 phy_gmii_sel: phy@4040 { 45 compatible = "ti,am654-phy-gmii-sel"; 46 reg = <0x4040 0x4>; 47 #phy-cells = <1>; 48 }; 49 }; 50 51 chipid@43000014 { 52 compatible = "ti,am654-chipid"; 53 reg = <0x00 0x43000014 0x00 0x4>; 54 }; 55 56 wkup_pmx0: pinctrl@4301c000 { 57 compatible = "pinctrl-single"; 58 /* Proxy 0 addressing */ 59 reg = <0x00 0x4301c000 0x00 0x34>; 60 #pinctrl-cells = <1>; 61 pinctrl-single,register-width = <32>; 62 pinctrl-single,function-mask = <0xffffffff>; 63 }; 64 65 wkup_pmx1: pinctrl@0x4301c038 { 66 compatible = "pinctrl-single"; 67 /* Proxy 0 addressing */ 68 reg = <0x00 0x4301c038 0x00 0x8>; 69 #pinctrl-cells = <1>; 70 pinctrl-single,register-width = <32>; 71 pinctrl-single,function-mask = <0xffffffff>; 72 }; 73 74 wkup_pmx2: pinctrl@0x4301c068 { 75 compatible = "pinctrl-single"; 76 /* Proxy 0 addressing */ 77 reg = <0x00 0x4301c068 0x00 0xec>; 78 #pinctrl-cells = <1>; 79 pinctrl-single,register-width = <32>; 80 pinctrl-single,function-mask = <0xffffffff>; 81 }; 82 83 wkup_pmx3: pinctrl@0x4301c174 { 84 compatible = "pinctrl-single"; 85 /* Proxy 0 addressing */ 86 reg = <0x00 0x4301c174 0x00 0x20>; 87 #pinctrl-cells = <1>; 88 pinctrl-single,register-width = <32>; 89 pinctrl-single,function-mask = <0xffffffff>; 90 }; 91 92 mcu_ram: sram@41c00000 { 93 compatible = "mmio-sram"; 94 reg = <0x00 0x41c00000 0x00 0x100000>; 95 ranges = <0x00 0x00 0x41c00000 0x100000>; 96 #address-cells = <1>; 97 #size-cells = <1>; 98 }; 99 100 wkup_uart0: serial@42300000 { 101 compatible = "ti,j721e-uart", "ti,am654-uart"; 102 reg = <0x00 0x42300000 0x00 0x100>; 103 reg-shift = <2>; 104 reg-io-width = <4>; 105 interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>; 106 clock-frequency = <48000000>; 107 current-speed = <115200>; 108 power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>; 109 clocks = <&k3_clks 287 2>; 110 clock-names = "fclk"; 111 }; 112 113 mcu_uart0: serial@40a00000 { 114 compatible = "ti,j721e-uart", "ti,am654-uart"; 115 reg = <0x00 0x40a00000 0x00 0x100>; 116 reg-shift = <2>; 117 reg-io-width = <4>; 118 interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>; 119 clock-frequency = <96000000>; 120 current-speed = <115200>; 121 power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; 122 clocks = <&k3_clks 149 2>; 123 clock-names = "fclk"; 124 }; 125 126 wkup_gpio_intr: interrupt-controller2 { 127 compatible = "ti,sci-intr"; 128 ti,intr-trigger-type = <1>; 129 interrupt-controller; 130 interrupt-parent = <&gic500>; 131 #interrupt-cells = <1>; 132 ti,sci = <&dmsc>; 133 ti,sci-dev-id = <137>; 134 ti,interrupt-ranges = <16 960 16>; 135 }; 136 137 mcu_navss: bus@28380000 { 138 compatible = "simple-mfd"; 139 #address-cells = <2>; 140 #size-cells = <2>; 141 ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>; 142 dma-coherent; 143 dma-ranges; 144 ti,sci-dev-id = <232>; 145 146 mcu_ringacc: ringacc@2b800000 { 147 compatible = "ti,am654-navss-ringacc"; 148 reg = <0x00 0x2b800000 0x00 0x400000>, 149 <0x00 0x2b000000 0x00 0x400000>, 150 <0x00 0x28590000 0x00 0x100>, 151 <0x00 0x2a500000 0x00 0x40000>; 152 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; 153 ti,num-rings = <286>; 154 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ 155 ti,sci = <&dmsc>; 156 ti,sci-dev-id = <235>; 157 msi-parent = <&main_udmass_inta>; 158 }; 159 160 mcu_udmap: dma-controller@285c0000 { 161 compatible = "ti,j721e-navss-mcu-udmap"; 162 reg = <0x00 0x285c0000 0x00 0x100>, 163 <0x00 0x2a800000 0x00 0x40000>, 164 <0x00 0x2aa00000 0x00 0x40000>; 165 reg-names = "gcfg", "rchanrt", "tchanrt"; 166 msi-parent = <&main_udmass_inta>; 167 #dma-cells = <1>; 168 169 ti,sci = <&dmsc>; 170 ti,sci-dev-id = <236>; 171 ti,ringacc = <&mcu_ringacc>; 172 173 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ 174 <0x0f>; /* TX_HCHAN */ 175 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ 176 <0x0b>; /* RX_HCHAN */ 177 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ 178 }; 179 }; 180 181 mcu_cpsw: ethernet@46000000 { 182 compatible = "ti,j721e-cpsw-nuss"; 183 #address-cells = <2>; 184 #size-cells = <2>; 185 reg = <0x00 0x46000000 0x00 0x200000>; 186 reg-names = "cpsw_nuss"; 187 ranges = <0x00 0x00 0x00 0x46000000 0x00 0x200000>; 188 dma-coherent; 189 clocks = <&k3_clks 18 21>; 190 clock-names = "fck"; 191 power-domains = <&k3_pds 18 TI_SCI_PD_EXCLUSIVE>; 192 193 dmas = <&mcu_udmap 0xf000>, 194 <&mcu_udmap 0xf001>, 195 <&mcu_udmap 0xf002>, 196 <&mcu_udmap 0xf003>, 197 <&mcu_udmap 0xf004>, 198 <&mcu_udmap 0xf005>, 199 <&mcu_udmap 0xf006>, 200 <&mcu_udmap 0xf007>, 201 <&mcu_udmap 0x7000>; 202 dma-names = "tx0", "tx1", "tx2", "tx3", 203 "tx4", "tx5", "tx6", "tx7", 204 "rx"; 205 206 ethernet-ports { 207 #address-cells = <1>; 208 #size-cells = <0>; 209 210 cpsw_port1: port@1 { 211 reg = <1>; 212 ti,mac-only; 213 label = "port1"; 214 ti,syscon-efuse = <&mcu_conf 0x200>; 215 phys = <&phy_gmii_sel 1>; 216 }; 217 }; 218 219 davinci_mdio: mdio@f00 { 220 compatible = "ti,cpsw-mdio","ti,davinci_mdio"; 221 reg = <0x00 0xf00 0x00 0x100>; 222 #address-cells = <1>; 223 #size-cells = <0>; 224 clocks = <&k3_clks 18 21>; 225 clock-names = "fck"; 226 bus_freq = <1000000>; 227 }; 228 229 cpts@3d000 { 230 compatible = "ti,am65-cpts"; 231 reg = <0x00 0x3d000 0x00 0x400>; 232 clocks = <&k3_clks 18 2>; 233 clock-names = "cpts"; 234 interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>; 235 interrupt-names = "cpts"; 236 ti,cpts-ext-ts-inputs = <4>; 237 ti,cpts-periodic-outputs = <2>; 238 }; 239 }; 240 241 mcu_i2c0: i2c@40b00000 { 242 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 243 reg = <0x00 0x40b00000 0x00 0x100>; 244 interrupts = <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>; 245 #address-cells = <1>; 246 #size-cells = <0>; 247 clock-names = "fck"; 248 clocks = <&k3_clks 194 1>; 249 power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>; 250 }; 251 252 mcu_i2c1: i2c@40b10000 { 253 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 254 reg = <0x00 0x40b10000 0x00 0x100>; 255 interrupts = <GIC_SPI 853 IRQ_TYPE_LEVEL_HIGH>; 256 #address-cells = <1>; 257 #size-cells = <0>; 258 clock-names = "fck"; 259 clocks = <&k3_clks 195 1>; 260 power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>; 261 }; 262 263 wkup_i2c0: i2c@42120000 { 264 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 265 reg = <0x00 0x42120000 0x00 0x100>; 266 interrupts = <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>; 267 #address-cells = <1>; 268 #size-cells = <0>; 269 clock-names = "fck"; 270 clocks = <&k3_clks 197 1>; 271 power-domains = <&k3_pds 197 TI_SCI_PD_SHARED>; 272 }; 273 274 fss: syscon@47000000 { 275 compatible = "syscon", "simple-mfd"; 276 reg = <0x00 0x47000000 0x00 0x100>; 277 #address-cells = <2>; 278 #size-cells = <2>; 279 ranges; 280 281 hbmc_mux: hbmc-mux { 282 compatible = "mmio-mux"; 283 #mux-control-cells = <1>; 284 mux-reg-masks = <0x4 0x2>; /* HBMC select */ 285 }; 286 287 hbmc: hyperbus@47034000 { 288 compatible = "ti,am654-hbmc"; 289 reg = <0x00 0x47034000 0x00 0x100>, 290 <0x05 0x00000000 0x01 0x0000000>; 291 power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; 292 clocks = <&k3_clks 102 0>; 293 assigned-clocks = <&k3_clks 102 5>; 294 assigned-clock-rates = <333333333>; 295 #address-cells = <2>; 296 #size-cells = <1>; 297 mux-controls = <&hbmc_mux 0>; 298 }; 299 }; 300}; 301