1 // SPDX-License-Identifier: GPL-2.0+
2 //
3 // drivers/dma/imx-sdma.c
4 //
5 // This file contains a driver for the Freescale Smart DMA engine
6 //
7 // Copyright 2010 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
8 //
9 // Based on code from Freescale:
10 //
11 // Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
12
13 #include <linux/init.h>
14 #include <linux/iopoll.h>
15 #include <linux/module.h>
16 #include <linux/types.h>
17 #include <linux/bitops.h>
18 #include <linux/mm.h>
19 #include <linux/interrupt.h>
20 #include <linux/clk.h>
21 #include <linux/delay.h>
22 #include <linux/sched.h>
23 #include <linux/semaphore.h>
24 #include <linux/spinlock.h>
25 #include <linux/device.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/firmware.h>
28 #include <linux/slab.h>
29 #include <linux/platform_device.h>
30 #include <linux/dmaengine.h>
31 #include <linux/of.h>
32 #include <linux/of_address.h>
33 #include <linux/of_device.h>
34 #include <linux/of_dma.h>
35 #include <linux/workqueue.h>
36
37 #include <asm/irq.h>
38 #include <linux/platform_data/dma-imx-sdma.h>
39 #include <linux/platform_data/dma-imx.h>
40 #include <linux/regmap.h>
41 #include <linux/mfd/syscon.h>
42 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
43
44 #include "dmaengine.h"
45 #include "virt-dma.h"
46
47 /* SDMA registers */
48 #define SDMA_H_C0PTR 0x000
49 #define SDMA_H_INTR 0x004
50 #define SDMA_H_STATSTOP 0x008
51 #define SDMA_H_START 0x00c
52 #define SDMA_H_EVTOVR 0x010
53 #define SDMA_H_DSPOVR 0x014
54 #define SDMA_H_HOSTOVR 0x018
55 #define SDMA_H_EVTPEND 0x01c
56 #define SDMA_H_DSPENBL 0x020
57 #define SDMA_H_RESET 0x024
58 #define SDMA_H_EVTERR 0x028
59 #define SDMA_H_INTRMSK 0x02c
60 #define SDMA_H_PSW 0x030
61 #define SDMA_H_EVTERRDBG 0x034
62 #define SDMA_H_CONFIG 0x038
63 #define SDMA_ONCE_ENB 0x040
64 #define SDMA_ONCE_DATA 0x044
65 #define SDMA_ONCE_INSTR 0x048
66 #define SDMA_ONCE_STAT 0x04c
67 #define SDMA_ONCE_CMD 0x050
68 #define SDMA_EVT_MIRROR 0x054
69 #define SDMA_ILLINSTADDR 0x058
70 #define SDMA_CHN0ADDR 0x05c
71 #define SDMA_ONCE_RTB 0x060
72 #define SDMA_XTRIG_CONF1 0x070
73 #define SDMA_XTRIG_CONF2 0x074
74 #define SDMA_CHNENBL0_IMX35 0x200
75 #define SDMA_CHNENBL0_IMX31 0x080
76 #define SDMA_CHNPRI_0 0x100
77
78 /*
79 * Buffer descriptor status values.
80 */
81 #define BD_DONE 0x01
82 #define BD_WRAP 0x02
83 #define BD_CONT 0x04
84 #define BD_INTR 0x08
85 #define BD_RROR 0x10
86 #define BD_LAST 0x20
87 #define BD_EXTD 0x80
88
89 /*
90 * Data Node descriptor status values.
91 */
92 #define DND_END_OF_FRAME 0x80
93 #define DND_END_OF_XFER 0x40
94 #define DND_DONE 0x20
95 #define DND_UNUSED 0x01
96
97 /*
98 * IPCV2 descriptor status values.
99 */
100 #define BD_IPCV2_END_OF_FRAME 0x40
101
102 #define IPCV2_MAX_NODES 50
103 /*
104 * Error bit set in the CCB status field by the SDMA,
105 * in setbd routine, in case of a transfer error
106 */
107 #define DATA_ERROR 0x10000000
108
109 /*
110 * Buffer descriptor commands.
111 */
112 #define C0_ADDR 0x01
113 #define C0_LOAD 0x02
114 #define C0_DUMP 0x03
115 #define C0_SETCTX 0x07
116 #define C0_GETCTX 0x03
117 #define C0_SETDM 0x01
118 #define C0_SETPM 0x04
119 #define C0_GETDM 0x02
120 #define C0_GETPM 0x08
121 /*
122 * Change endianness indicator in the BD command field
123 */
124 #define CHANGE_ENDIANNESS 0x80
125
126 /*
127 * p_2_p watermark_level description
128 * Bits Name Description
129 * 0-7 Lower WML Lower watermark level
130 * 8 PS 1: Pad Swallowing
131 * 0: No Pad Swallowing
132 * 9 PA 1: Pad Adding
133 * 0: No Pad Adding
134 * 10 SPDIF If this bit is set both source
135 * and destination are on SPBA
136 * 11 Source Bit(SP) 1: Source on SPBA
137 * 0: Source on AIPS
138 * 12 Destination Bit(DP) 1: Destination on SPBA
139 * 0: Destination on AIPS
140 * 13-15 --------- MUST BE 0
141 * 16-23 Higher WML HWML
142 * 24-27 N Total number of samples after
143 * which Pad adding/Swallowing
144 * must be done. It must be odd.
145 * 28 Lower WML Event(LWE) SDMA events reg to check for
146 * LWML event mask
147 * 0: LWE in EVENTS register
148 * 1: LWE in EVENTS2 register
149 * 29 Higher WML Event(HWE) SDMA events reg to check for
150 * HWML event mask
151 * 0: HWE in EVENTS register
152 * 1: HWE in EVENTS2 register
153 * 30 --------- MUST BE 0
154 * 31 CONT 1: Amount of samples to be
155 * transferred is unknown and
156 * script will keep on
157 * transferring samples as long as
158 * both events are detected and
159 * script must be manually stopped
160 * by the application
161 * 0: The amount of samples to be
162 * transferred is equal to the
163 * count field of mode word
164 */
165 #define SDMA_WATERMARK_LEVEL_LWML 0xFF
166 #define SDMA_WATERMARK_LEVEL_PS BIT(8)
167 #define SDMA_WATERMARK_LEVEL_PA BIT(9)
168 #define SDMA_WATERMARK_LEVEL_SPDIF BIT(10)
169 #define SDMA_WATERMARK_LEVEL_SP BIT(11)
170 #define SDMA_WATERMARK_LEVEL_DP BIT(12)
171 #define SDMA_WATERMARK_LEVEL_HWML (0xFF << 16)
172 #define SDMA_WATERMARK_LEVEL_LWE BIT(28)
173 #define SDMA_WATERMARK_LEVEL_HWE BIT(29)
174 #define SDMA_WATERMARK_LEVEL_CONT BIT(31)
175
176 #define SDMA_DMA_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
177 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
178 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES))
179
180 #define SDMA_DMA_DIRECTIONS (BIT(DMA_DEV_TO_MEM) | \
181 BIT(DMA_MEM_TO_DEV) | \
182 BIT(DMA_DEV_TO_DEV))
183
184 /*
185 * Mode/Count of data node descriptors - IPCv2
186 */
187 struct sdma_mode_count {
188 #define SDMA_BD_MAX_CNT 0xffff
189 u32 count : 16; /* size of the buffer pointed by this BD */
190 u32 status : 8; /* E,R,I,C,W,D status bits stored here */
191 u32 command : 8; /* command mostly used for channel 0 */
192 };
193
194 /*
195 * Buffer descriptor
196 */
197 struct sdma_buffer_descriptor {
198 struct sdma_mode_count mode;
199 u32 buffer_addr; /* address of the buffer described */
200 u32 ext_buffer_addr; /* extended buffer address */
201 } __attribute__ ((packed));
202
203 /**
204 * struct sdma_channel_control - Channel control Block
205 *
206 * @current_bd_ptr: current buffer descriptor processed
207 * @base_bd_ptr: first element of buffer descriptor array
208 * @unused: padding. The SDMA engine expects an array of 128 byte
209 * control blocks
210 */
211 struct sdma_channel_control {
212 u32 current_bd_ptr;
213 u32 base_bd_ptr;
214 u32 unused[2];
215 } __attribute__ ((packed));
216
217 /**
218 * struct sdma_state_registers - SDMA context for a channel
219 *
220 * @pc: program counter
221 * @unused1: unused
222 * @t: test bit: status of arithmetic & test instruction
223 * @rpc: return program counter
224 * @unused0: unused
225 * @sf: source fault while loading data
226 * @spc: loop start program counter
227 * @unused2: unused
228 * @df: destination fault while storing data
229 * @epc: loop end program counter
230 * @lm: loop mode
231 */
232 struct sdma_state_registers {
233 u32 pc :14;
234 u32 unused1: 1;
235 u32 t : 1;
236 u32 rpc :14;
237 u32 unused0: 1;
238 u32 sf : 1;
239 u32 spc :14;
240 u32 unused2: 1;
241 u32 df : 1;
242 u32 epc :14;
243 u32 lm : 2;
244 } __attribute__ ((packed));
245
246 /**
247 * struct sdma_context_data - sdma context specific to a channel
248 *
249 * @channel_state: channel state bits
250 * @gReg: general registers
251 * @mda: burst dma destination address register
252 * @msa: burst dma source address register
253 * @ms: burst dma status register
254 * @md: burst dma data register
255 * @pda: peripheral dma destination address register
256 * @psa: peripheral dma source address register
257 * @ps: peripheral dma status register
258 * @pd: peripheral dma data register
259 * @ca: CRC polynomial register
260 * @cs: CRC accumulator register
261 * @dda: dedicated core destination address register
262 * @dsa: dedicated core source address register
263 * @ds: dedicated core status register
264 * @dd: dedicated core data register
265 * @scratch0: 1st word of dedicated ram for context switch
266 * @scratch1: 2nd word of dedicated ram for context switch
267 * @scratch2: 3rd word of dedicated ram for context switch
268 * @scratch3: 4th word of dedicated ram for context switch
269 * @scratch4: 5th word of dedicated ram for context switch
270 * @scratch5: 6th word of dedicated ram for context switch
271 * @scratch6: 7th word of dedicated ram for context switch
272 * @scratch7: 8th word of dedicated ram for context switch
273 */
274 struct sdma_context_data {
275 struct sdma_state_registers channel_state;
276 u32 gReg[8];
277 u32 mda;
278 u32 msa;
279 u32 ms;
280 u32 md;
281 u32 pda;
282 u32 psa;
283 u32 ps;
284 u32 pd;
285 u32 ca;
286 u32 cs;
287 u32 dda;
288 u32 dsa;
289 u32 ds;
290 u32 dd;
291 u32 scratch0;
292 u32 scratch1;
293 u32 scratch2;
294 u32 scratch3;
295 u32 scratch4;
296 u32 scratch5;
297 u32 scratch6;
298 u32 scratch7;
299 } __attribute__ ((packed));
300
301
302 struct sdma_engine;
303
304 /**
305 * struct sdma_desc - descriptor structor for one transfer
306 * @vd: descriptor for virt dma
307 * @num_bd: number of descriptors currently handling
308 * @bd_phys: physical address of bd
309 * @buf_tail: ID of the buffer that was processed
310 * @buf_ptail: ID of the previous buffer that was processed
311 * @period_len: period length, used in cyclic.
312 * @chn_real_count: the real count updated from bd->mode.count
313 * @chn_count: the transfer count set
314 * @sdmac: sdma_channel pointer
315 * @bd: pointer of allocate bd
316 */
317 struct sdma_desc {
318 struct virt_dma_desc vd;
319 unsigned int num_bd;
320 dma_addr_t bd_phys;
321 unsigned int buf_tail;
322 unsigned int buf_ptail;
323 unsigned int period_len;
324 unsigned int chn_real_count;
325 unsigned int chn_count;
326 struct sdma_channel *sdmac;
327 struct sdma_buffer_descriptor *bd;
328 };
329
330 /**
331 * struct sdma_channel - housekeeping for a SDMA channel
332 *
333 * @vc: virt_dma base structure
334 * @desc: sdma description including vd and other special member
335 * @sdma: pointer to the SDMA engine for this channel
336 * @channel: the channel number, matches dmaengine chan_id + 1
337 * @direction: transfer type. Needed for setting SDMA script
338 * @slave_config: Slave configuration
339 * @peripheral_type: Peripheral type. Needed for setting SDMA script
340 * @event_id0: aka dma request line
341 * @event_id1: for channels that use 2 events
342 * @word_size: peripheral access size
343 * @pc_from_device: script address for those device_2_memory
344 * @pc_to_device: script address for those memory_2_device
345 * @device_to_device: script address for those device_2_device
346 * @pc_to_pc: script address for those memory_2_memory
347 * @flags: loop mode or not
348 * @per_address: peripheral source or destination address in common case
349 * destination address in p_2_p case
350 * @per_address2: peripheral source address in p_2_p case
351 * @event_mask: event mask used in p_2_p script
352 * @watermark_level: value for gReg[7], some script will extend it from
353 * basic watermark such as p_2_p
354 * @shp_addr: value for gReg[6]
355 * @per_addr: value for gReg[2]
356 * @status: status of dma channel
357 * @context_loaded: ensure context is only loaded once
358 * @data: specific sdma interface structure
359 * @bd_pool: dma_pool for bd
360 * @terminate_worker: used to call back into terminate work function
361 */
362 struct sdma_channel {
363 struct virt_dma_chan vc;
364 struct sdma_desc *desc;
365 struct sdma_engine *sdma;
366 unsigned int channel;
367 enum dma_transfer_direction direction;
368 struct dma_slave_config slave_config;
369 enum sdma_peripheral_type peripheral_type;
370 unsigned int event_id0;
371 unsigned int event_id1;
372 enum dma_slave_buswidth word_size;
373 unsigned int pc_from_device, pc_to_device;
374 unsigned int device_to_device;
375 unsigned int pc_to_pc;
376 unsigned long flags;
377 dma_addr_t per_address, per_address2;
378 unsigned long event_mask[2];
379 unsigned long watermark_level;
380 u32 shp_addr, per_addr;
381 enum dma_status status;
382 struct imx_dma_data data;
383 struct work_struct terminate_worker;
384 };
385
386 #define IMX_DMA_SG_LOOP BIT(0)
387
388 #define MAX_DMA_CHANNELS 32
389 #define MXC_SDMA_DEFAULT_PRIORITY 1
390 #define MXC_SDMA_MIN_PRIORITY 1
391 #define MXC_SDMA_MAX_PRIORITY 7
392
393 #define SDMA_FIRMWARE_MAGIC 0x414d4453
394
395 /**
396 * struct sdma_firmware_header - Layout of the firmware image
397 *
398 * @magic: "SDMA"
399 * @version_major: increased whenever layout of struct
400 * sdma_script_start_addrs changes.
401 * @version_minor: firmware minor version (for binary compatible changes)
402 * @script_addrs_start: offset of struct sdma_script_start_addrs in this image
403 * @num_script_addrs: Number of script addresses in this image
404 * @ram_code_start: offset of SDMA ram image in this firmware image
405 * @ram_code_size: size of SDMA ram image
406 * @script_addrs: Stores the start address of the SDMA scripts
407 * (in SDMA memory space)
408 */
409 struct sdma_firmware_header {
410 u32 magic;
411 u32 version_major;
412 u32 version_minor;
413 u32 script_addrs_start;
414 u32 num_script_addrs;
415 u32 ram_code_start;
416 u32 ram_code_size;
417 };
418
419 struct sdma_driver_data {
420 int chnenbl0;
421 int num_events;
422 struct sdma_script_start_addrs *script_addrs;
423 bool check_ratio;
424 };
425
426 struct sdma_engine {
427 struct device *dev;
428 struct sdma_channel channel[MAX_DMA_CHANNELS];
429 struct sdma_channel_control *channel_control;
430 void __iomem *regs;
431 struct sdma_context_data *context;
432 dma_addr_t context_phys;
433 struct dma_device dma_device;
434 struct clk *clk_ipg;
435 struct clk *clk_ahb;
436 spinlock_t channel_0_lock;
437 u32 script_number;
438 struct sdma_script_start_addrs *script_addrs;
439 const struct sdma_driver_data *drvdata;
440 u32 spba_start_addr;
441 u32 spba_end_addr;
442 unsigned int irq;
443 dma_addr_t bd0_phys;
444 struct sdma_buffer_descriptor *bd0;
445 /* clock ratio for AHB:SDMA core. 1:1 is 1, 2:1 is 0*/
446 bool clk_ratio;
447 };
448
449 static int sdma_config_write(struct dma_chan *chan,
450 struct dma_slave_config *dmaengine_cfg,
451 enum dma_transfer_direction direction);
452
453 static struct sdma_driver_data sdma_imx31 = {
454 .chnenbl0 = SDMA_CHNENBL0_IMX31,
455 .num_events = 32,
456 };
457
458 static struct sdma_script_start_addrs sdma_script_imx25 = {
459 .ap_2_ap_addr = 729,
460 .uart_2_mcu_addr = 904,
461 .per_2_app_addr = 1255,
462 .mcu_2_app_addr = 834,
463 .uartsh_2_mcu_addr = 1120,
464 .per_2_shp_addr = 1329,
465 .mcu_2_shp_addr = 1048,
466 .ata_2_mcu_addr = 1560,
467 .mcu_2_ata_addr = 1479,
468 .app_2_per_addr = 1189,
469 .app_2_mcu_addr = 770,
470 .shp_2_per_addr = 1407,
471 .shp_2_mcu_addr = 979,
472 };
473
474 static struct sdma_driver_data sdma_imx25 = {
475 .chnenbl0 = SDMA_CHNENBL0_IMX35,
476 .num_events = 48,
477 .script_addrs = &sdma_script_imx25,
478 };
479
480 static struct sdma_driver_data sdma_imx35 = {
481 .chnenbl0 = SDMA_CHNENBL0_IMX35,
482 .num_events = 48,
483 };
484
485 static struct sdma_script_start_addrs sdma_script_imx51 = {
486 .ap_2_ap_addr = 642,
487 .uart_2_mcu_addr = 817,
488 .mcu_2_app_addr = 747,
489 .mcu_2_shp_addr = 961,
490 .ata_2_mcu_addr = 1473,
491 .mcu_2_ata_addr = 1392,
492 .app_2_per_addr = 1033,
493 .app_2_mcu_addr = 683,
494 .shp_2_per_addr = 1251,
495 .shp_2_mcu_addr = 892,
496 };
497
498 static struct sdma_driver_data sdma_imx51 = {
499 .chnenbl0 = SDMA_CHNENBL0_IMX35,
500 .num_events = 48,
501 .script_addrs = &sdma_script_imx51,
502 };
503
504 static struct sdma_script_start_addrs sdma_script_imx53 = {
505 .ap_2_ap_addr = 642,
506 .app_2_mcu_addr = 683,
507 .mcu_2_app_addr = 747,
508 .uart_2_mcu_addr = 817,
509 .shp_2_mcu_addr = 891,
510 .mcu_2_shp_addr = 960,
511 .uartsh_2_mcu_addr = 1032,
512 .spdif_2_mcu_addr = 1100,
513 .mcu_2_spdif_addr = 1134,
514 .firi_2_mcu_addr = 1193,
515 .mcu_2_firi_addr = 1290,
516 };
517
518 static struct sdma_driver_data sdma_imx53 = {
519 .chnenbl0 = SDMA_CHNENBL0_IMX35,
520 .num_events = 48,
521 .script_addrs = &sdma_script_imx53,
522 };
523
524 static struct sdma_script_start_addrs sdma_script_imx6q = {
525 .ap_2_ap_addr = 642,
526 .uart_2_mcu_addr = 817,
527 .mcu_2_app_addr = 747,
528 .per_2_per_addr = 6331,
529 .uartsh_2_mcu_addr = 1032,
530 .mcu_2_shp_addr = 960,
531 .app_2_mcu_addr = 683,
532 .shp_2_mcu_addr = 891,
533 .spdif_2_mcu_addr = 1100,
534 .mcu_2_spdif_addr = 1134,
535 };
536
537 static struct sdma_driver_data sdma_imx6q = {
538 .chnenbl0 = SDMA_CHNENBL0_IMX35,
539 .num_events = 48,
540 .script_addrs = &sdma_script_imx6q,
541 };
542
543 static struct sdma_script_start_addrs sdma_script_imx7d = {
544 .ap_2_ap_addr = 644,
545 .uart_2_mcu_addr = 819,
546 .mcu_2_app_addr = 749,
547 .uartsh_2_mcu_addr = 1034,
548 .mcu_2_shp_addr = 962,
549 .app_2_mcu_addr = 685,
550 .shp_2_mcu_addr = 893,
551 .spdif_2_mcu_addr = 1102,
552 .mcu_2_spdif_addr = 1136,
553 };
554
555 static struct sdma_driver_data sdma_imx7d = {
556 .chnenbl0 = SDMA_CHNENBL0_IMX35,
557 .num_events = 48,
558 .script_addrs = &sdma_script_imx7d,
559 };
560
561 static struct sdma_driver_data sdma_imx8mq = {
562 .chnenbl0 = SDMA_CHNENBL0_IMX35,
563 .num_events = 48,
564 .script_addrs = &sdma_script_imx7d,
565 .check_ratio = 1,
566 };
567
568 static const struct platform_device_id sdma_devtypes[] = {
569 {
570 .name = "imx25-sdma",
571 .driver_data = (unsigned long)&sdma_imx25,
572 }, {
573 .name = "imx31-sdma",
574 .driver_data = (unsigned long)&sdma_imx31,
575 }, {
576 .name = "imx35-sdma",
577 .driver_data = (unsigned long)&sdma_imx35,
578 }, {
579 .name = "imx51-sdma",
580 .driver_data = (unsigned long)&sdma_imx51,
581 }, {
582 .name = "imx53-sdma",
583 .driver_data = (unsigned long)&sdma_imx53,
584 }, {
585 .name = "imx6q-sdma",
586 .driver_data = (unsigned long)&sdma_imx6q,
587 }, {
588 .name = "imx7d-sdma",
589 .driver_data = (unsigned long)&sdma_imx7d,
590 }, {
591 .name = "imx8mq-sdma",
592 .driver_data = (unsigned long)&sdma_imx8mq,
593 }, {
594 /* sentinel */
595 }
596 };
597 MODULE_DEVICE_TABLE(platform, sdma_devtypes);
598
599 static const struct of_device_id sdma_dt_ids[] = {
600 { .compatible = "fsl,imx6q-sdma", .data = &sdma_imx6q, },
601 { .compatible = "fsl,imx53-sdma", .data = &sdma_imx53, },
602 { .compatible = "fsl,imx51-sdma", .data = &sdma_imx51, },
603 { .compatible = "fsl,imx35-sdma", .data = &sdma_imx35, },
604 { .compatible = "fsl,imx31-sdma", .data = &sdma_imx31, },
605 { .compatible = "fsl,imx25-sdma", .data = &sdma_imx25, },
606 { .compatible = "fsl,imx7d-sdma", .data = &sdma_imx7d, },
607 { .compatible = "fsl,imx8mq-sdma", .data = &sdma_imx8mq, },
608 { /* sentinel */ }
609 };
610 MODULE_DEVICE_TABLE(of, sdma_dt_ids);
611
612 #define SDMA_H_CONFIG_DSPDMA BIT(12) /* indicates if the DSPDMA is used */
613 #define SDMA_H_CONFIG_RTD_PINS BIT(11) /* indicates if Real-Time Debug pins are enabled */
614 #define SDMA_H_CONFIG_ACR BIT(4) /* indicates if AHB freq /core freq = 2 or 1 */
615 #define SDMA_H_CONFIG_CSM (3) /* indicates which context switch mode is selected*/
616
chnenbl_ofs(struct sdma_engine * sdma,unsigned int event)617 static inline u32 chnenbl_ofs(struct sdma_engine *sdma, unsigned int event)
618 {
619 u32 chnenbl0 = sdma->drvdata->chnenbl0;
620 return chnenbl0 + event * 4;
621 }
622
sdma_config_ownership(struct sdma_channel * sdmac,bool event_override,bool mcu_override,bool dsp_override)623 static int sdma_config_ownership(struct sdma_channel *sdmac,
624 bool event_override, bool mcu_override, bool dsp_override)
625 {
626 struct sdma_engine *sdma = sdmac->sdma;
627 int channel = sdmac->channel;
628 unsigned long evt, mcu, dsp;
629
630 if (event_override && mcu_override && dsp_override)
631 return -EINVAL;
632
633 evt = readl_relaxed(sdma->regs + SDMA_H_EVTOVR);
634 mcu = readl_relaxed(sdma->regs + SDMA_H_HOSTOVR);
635 dsp = readl_relaxed(sdma->regs + SDMA_H_DSPOVR);
636
637 if (dsp_override)
638 __clear_bit(channel, &dsp);
639 else
640 __set_bit(channel, &dsp);
641
642 if (event_override)
643 __clear_bit(channel, &evt);
644 else
645 __set_bit(channel, &evt);
646
647 if (mcu_override)
648 __clear_bit(channel, &mcu);
649 else
650 __set_bit(channel, &mcu);
651
652 writel_relaxed(evt, sdma->regs + SDMA_H_EVTOVR);
653 writel_relaxed(mcu, sdma->regs + SDMA_H_HOSTOVR);
654 writel_relaxed(dsp, sdma->regs + SDMA_H_DSPOVR);
655
656 return 0;
657 }
658
sdma_enable_channel(struct sdma_engine * sdma,int channel)659 static void sdma_enable_channel(struct sdma_engine *sdma, int channel)
660 {
661 writel(BIT(channel), sdma->regs + SDMA_H_START);
662 }
663
664 /*
665 * sdma_run_channel0 - run a channel and wait till it's done
666 */
sdma_run_channel0(struct sdma_engine * sdma)667 static int sdma_run_channel0(struct sdma_engine *sdma)
668 {
669 int ret;
670 u32 reg;
671
672 sdma_enable_channel(sdma, 0);
673
674 ret = readl_relaxed_poll_timeout_atomic(sdma->regs + SDMA_H_STATSTOP,
675 reg, !(reg & 1), 1, 500);
676 if (ret)
677 dev_err(sdma->dev, "Timeout waiting for CH0 ready\n");
678
679 /* Set bits of CONFIG register with dynamic context switching */
680 reg = readl(sdma->regs + SDMA_H_CONFIG);
681 if ((reg & SDMA_H_CONFIG_CSM) == 0) {
682 reg |= SDMA_H_CONFIG_CSM;
683 writel_relaxed(reg, sdma->regs + SDMA_H_CONFIG);
684 }
685
686 return ret;
687 }
688
sdma_load_script(struct sdma_engine * sdma,void * buf,int size,u32 address)689 static int sdma_load_script(struct sdma_engine *sdma, void *buf, int size,
690 u32 address)
691 {
692 struct sdma_buffer_descriptor *bd0 = sdma->bd0;
693 void *buf_virt;
694 dma_addr_t buf_phys;
695 int ret;
696 unsigned long flags;
697
698 buf_virt = dma_alloc_coherent(sdma->dev, size, &buf_phys, GFP_KERNEL);
699 if (!buf_virt) {
700 return -ENOMEM;
701 }
702
703 spin_lock_irqsave(&sdma->channel_0_lock, flags);
704
705 bd0->mode.command = C0_SETPM;
706 bd0->mode.status = BD_DONE | BD_WRAP | BD_EXTD;
707 bd0->mode.count = size / 2;
708 bd0->buffer_addr = buf_phys;
709 bd0->ext_buffer_addr = address;
710
711 memcpy(buf_virt, buf, size);
712
713 ret = sdma_run_channel0(sdma);
714
715 spin_unlock_irqrestore(&sdma->channel_0_lock, flags);
716
717 dma_free_coherent(sdma->dev, size, buf_virt, buf_phys);
718
719 return ret;
720 }
721
sdma_event_enable(struct sdma_channel * sdmac,unsigned int event)722 static void sdma_event_enable(struct sdma_channel *sdmac, unsigned int event)
723 {
724 struct sdma_engine *sdma = sdmac->sdma;
725 int channel = sdmac->channel;
726 unsigned long val;
727 u32 chnenbl = chnenbl_ofs(sdma, event);
728
729 val = readl_relaxed(sdma->regs + chnenbl);
730 __set_bit(channel, &val);
731 writel_relaxed(val, sdma->regs + chnenbl);
732 }
733
sdma_event_disable(struct sdma_channel * sdmac,unsigned int event)734 static void sdma_event_disable(struct sdma_channel *sdmac, unsigned int event)
735 {
736 struct sdma_engine *sdma = sdmac->sdma;
737 int channel = sdmac->channel;
738 u32 chnenbl = chnenbl_ofs(sdma, event);
739 unsigned long val;
740
741 val = readl_relaxed(sdma->regs + chnenbl);
742 __clear_bit(channel, &val);
743 writel_relaxed(val, sdma->regs + chnenbl);
744 }
745
to_sdma_desc(struct dma_async_tx_descriptor * t)746 static struct sdma_desc *to_sdma_desc(struct dma_async_tx_descriptor *t)
747 {
748 return container_of(t, struct sdma_desc, vd.tx);
749 }
750
sdma_start_desc(struct sdma_channel * sdmac)751 static void sdma_start_desc(struct sdma_channel *sdmac)
752 {
753 struct virt_dma_desc *vd = vchan_next_desc(&sdmac->vc);
754 struct sdma_desc *desc;
755 struct sdma_engine *sdma = sdmac->sdma;
756 int channel = sdmac->channel;
757
758 if (!vd) {
759 sdmac->desc = NULL;
760 return;
761 }
762 sdmac->desc = desc = to_sdma_desc(&vd->tx);
763
764 list_del(&vd->node);
765
766 sdma->channel_control[channel].base_bd_ptr = desc->bd_phys;
767 sdma->channel_control[channel].current_bd_ptr = desc->bd_phys;
768 sdma_enable_channel(sdma, sdmac->channel);
769 }
770
sdma_update_channel_loop(struct sdma_channel * sdmac)771 static void sdma_update_channel_loop(struct sdma_channel *sdmac)
772 {
773 struct sdma_buffer_descriptor *bd;
774 int error = 0;
775 enum dma_status old_status = sdmac->status;
776
777 /*
778 * loop mode. Iterate over descriptors, re-setup them and
779 * call callback function.
780 */
781 while (sdmac->desc) {
782 struct sdma_desc *desc = sdmac->desc;
783
784 bd = &desc->bd[desc->buf_tail];
785
786 if (bd->mode.status & BD_DONE)
787 break;
788
789 if (bd->mode.status & BD_RROR) {
790 bd->mode.status &= ~BD_RROR;
791 sdmac->status = DMA_ERROR;
792 error = -EIO;
793 }
794
795 /*
796 * We use bd->mode.count to calculate the residue, since contains
797 * the number of bytes present in the current buffer descriptor.
798 */
799
800 desc->chn_real_count = bd->mode.count;
801 bd->mode.status |= BD_DONE;
802 bd->mode.count = desc->period_len;
803 desc->buf_ptail = desc->buf_tail;
804 desc->buf_tail = (desc->buf_tail + 1) % desc->num_bd;
805
806 /*
807 * The callback is called from the interrupt context in order
808 * to reduce latency and to avoid the risk of altering the
809 * SDMA transaction status by the time the client tasklet is
810 * executed.
811 */
812 spin_unlock(&sdmac->vc.lock);
813 dmaengine_desc_get_callback_invoke(&desc->vd.tx, NULL);
814 spin_lock(&sdmac->vc.lock);
815
816 if (error)
817 sdmac->status = old_status;
818 }
819 }
820
mxc_sdma_handle_channel_normal(struct sdma_channel * data)821 static void mxc_sdma_handle_channel_normal(struct sdma_channel *data)
822 {
823 struct sdma_channel *sdmac = (struct sdma_channel *) data;
824 struct sdma_buffer_descriptor *bd;
825 int i, error = 0;
826
827 sdmac->desc->chn_real_count = 0;
828 /*
829 * non loop mode. Iterate over all descriptors, collect
830 * errors and call callback function
831 */
832 for (i = 0; i < sdmac->desc->num_bd; i++) {
833 bd = &sdmac->desc->bd[i];
834
835 if (bd->mode.status & (BD_DONE | BD_RROR))
836 error = -EIO;
837 sdmac->desc->chn_real_count += bd->mode.count;
838 }
839
840 if (error)
841 sdmac->status = DMA_ERROR;
842 else
843 sdmac->status = DMA_COMPLETE;
844 }
845
sdma_int_handler(int irq,void * dev_id)846 static irqreturn_t sdma_int_handler(int irq, void *dev_id)
847 {
848 struct sdma_engine *sdma = dev_id;
849 unsigned long stat;
850
851 stat = readl_relaxed(sdma->regs + SDMA_H_INTR);
852 writel_relaxed(stat, sdma->regs + SDMA_H_INTR);
853 /* channel 0 is special and not handled here, see run_channel0() */
854 stat &= ~1;
855
856 while (stat) {
857 int channel = fls(stat) - 1;
858 struct sdma_channel *sdmac = &sdma->channel[channel];
859 struct sdma_desc *desc;
860
861 spin_lock(&sdmac->vc.lock);
862 desc = sdmac->desc;
863 if (desc) {
864 if (sdmac->flags & IMX_DMA_SG_LOOP) {
865 sdma_update_channel_loop(sdmac);
866 } else {
867 mxc_sdma_handle_channel_normal(sdmac);
868 vchan_cookie_complete(&desc->vd);
869 sdma_start_desc(sdmac);
870 }
871 }
872
873 spin_unlock(&sdmac->vc.lock);
874 __clear_bit(channel, &stat);
875 }
876
877 return IRQ_HANDLED;
878 }
879
880 /*
881 * sets the pc of SDMA script according to the peripheral type
882 */
sdma_get_pc(struct sdma_channel * sdmac,enum sdma_peripheral_type peripheral_type)883 static void sdma_get_pc(struct sdma_channel *sdmac,
884 enum sdma_peripheral_type peripheral_type)
885 {
886 struct sdma_engine *sdma = sdmac->sdma;
887 int per_2_emi = 0, emi_2_per = 0;
888 /*
889 * These are needed once we start to support transfers between
890 * two peripherals or memory-to-memory transfers
891 */
892 int per_2_per = 0, emi_2_emi = 0;
893
894 sdmac->pc_from_device = 0;
895 sdmac->pc_to_device = 0;
896 sdmac->device_to_device = 0;
897 sdmac->pc_to_pc = 0;
898
899 switch (peripheral_type) {
900 case IMX_DMATYPE_MEMORY:
901 emi_2_emi = sdma->script_addrs->ap_2_ap_addr;
902 break;
903 case IMX_DMATYPE_DSP:
904 emi_2_per = sdma->script_addrs->bp_2_ap_addr;
905 per_2_emi = sdma->script_addrs->ap_2_bp_addr;
906 break;
907 case IMX_DMATYPE_FIRI:
908 per_2_emi = sdma->script_addrs->firi_2_mcu_addr;
909 emi_2_per = sdma->script_addrs->mcu_2_firi_addr;
910 break;
911 case IMX_DMATYPE_UART:
912 per_2_emi = sdma->script_addrs->uart_2_mcu_addr;
913 emi_2_per = sdma->script_addrs->mcu_2_app_addr;
914 break;
915 case IMX_DMATYPE_UART_SP:
916 per_2_emi = sdma->script_addrs->uartsh_2_mcu_addr;
917 emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
918 break;
919 case IMX_DMATYPE_ATA:
920 per_2_emi = sdma->script_addrs->ata_2_mcu_addr;
921 emi_2_per = sdma->script_addrs->mcu_2_ata_addr;
922 break;
923 case IMX_DMATYPE_CSPI:
924 case IMX_DMATYPE_EXT:
925 case IMX_DMATYPE_SSI:
926 case IMX_DMATYPE_SAI:
927 per_2_emi = sdma->script_addrs->app_2_mcu_addr;
928 emi_2_per = sdma->script_addrs->mcu_2_app_addr;
929 break;
930 case IMX_DMATYPE_SSI_DUAL:
931 per_2_emi = sdma->script_addrs->ssish_2_mcu_addr;
932 emi_2_per = sdma->script_addrs->mcu_2_ssish_addr;
933 break;
934 case IMX_DMATYPE_SSI_SP:
935 case IMX_DMATYPE_MMC:
936 case IMX_DMATYPE_SDHC:
937 case IMX_DMATYPE_CSPI_SP:
938 case IMX_DMATYPE_ESAI:
939 case IMX_DMATYPE_MSHC_SP:
940 per_2_emi = sdma->script_addrs->shp_2_mcu_addr;
941 emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
942 break;
943 case IMX_DMATYPE_ASRC:
944 per_2_emi = sdma->script_addrs->asrc_2_mcu_addr;
945 emi_2_per = sdma->script_addrs->asrc_2_mcu_addr;
946 per_2_per = sdma->script_addrs->per_2_per_addr;
947 break;
948 case IMX_DMATYPE_ASRC_SP:
949 per_2_emi = sdma->script_addrs->shp_2_mcu_addr;
950 emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
951 per_2_per = sdma->script_addrs->per_2_per_addr;
952 break;
953 case IMX_DMATYPE_MSHC:
954 per_2_emi = sdma->script_addrs->mshc_2_mcu_addr;
955 emi_2_per = sdma->script_addrs->mcu_2_mshc_addr;
956 break;
957 case IMX_DMATYPE_CCM:
958 per_2_emi = sdma->script_addrs->dptc_dvfs_addr;
959 break;
960 case IMX_DMATYPE_SPDIF:
961 per_2_emi = sdma->script_addrs->spdif_2_mcu_addr;
962 emi_2_per = sdma->script_addrs->mcu_2_spdif_addr;
963 break;
964 case IMX_DMATYPE_IPU_MEMORY:
965 emi_2_per = sdma->script_addrs->ext_mem_2_ipu_addr;
966 break;
967 default:
968 break;
969 }
970
971 sdmac->pc_from_device = per_2_emi;
972 sdmac->pc_to_device = emi_2_per;
973 sdmac->device_to_device = per_2_per;
974 sdmac->pc_to_pc = emi_2_emi;
975 }
976
sdma_load_context(struct sdma_channel * sdmac)977 static int sdma_load_context(struct sdma_channel *sdmac)
978 {
979 struct sdma_engine *sdma = sdmac->sdma;
980 int channel = sdmac->channel;
981 int load_address;
982 struct sdma_context_data *context = sdma->context;
983 struct sdma_buffer_descriptor *bd0 = sdma->bd0;
984 int ret;
985 unsigned long flags;
986
987 if (sdmac->direction == DMA_DEV_TO_MEM)
988 load_address = sdmac->pc_from_device;
989 else if (sdmac->direction == DMA_DEV_TO_DEV)
990 load_address = sdmac->device_to_device;
991 else if (sdmac->direction == DMA_MEM_TO_MEM)
992 load_address = sdmac->pc_to_pc;
993 else
994 load_address = sdmac->pc_to_device;
995
996 if (load_address < 0)
997 return load_address;
998
999 dev_dbg(sdma->dev, "load_address = %d\n", load_address);
1000 dev_dbg(sdma->dev, "wml = 0x%08x\n", (u32)sdmac->watermark_level);
1001 dev_dbg(sdma->dev, "shp_addr = 0x%08x\n", sdmac->shp_addr);
1002 dev_dbg(sdma->dev, "per_addr = 0x%08x\n", sdmac->per_addr);
1003 dev_dbg(sdma->dev, "event_mask0 = 0x%08x\n", (u32)sdmac->event_mask[0]);
1004 dev_dbg(sdma->dev, "event_mask1 = 0x%08x\n", (u32)sdmac->event_mask[1]);
1005
1006 spin_lock_irqsave(&sdma->channel_0_lock, flags);
1007
1008 memset(context, 0, sizeof(*context));
1009 context->channel_state.pc = load_address;
1010
1011 /* Send by context the event mask,base address for peripheral
1012 * and watermark level
1013 */
1014 context->gReg[0] = sdmac->event_mask[1];
1015 context->gReg[1] = sdmac->event_mask[0];
1016 context->gReg[2] = sdmac->per_addr;
1017 context->gReg[6] = sdmac->shp_addr;
1018 context->gReg[7] = sdmac->watermark_level;
1019
1020 bd0->mode.command = C0_SETDM;
1021 bd0->mode.status = BD_DONE | BD_WRAP | BD_EXTD;
1022 bd0->mode.count = sizeof(*context) / 4;
1023 bd0->buffer_addr = sdma->context_phys;
1024 bd0->ext_buffer_addr = 2048 + (sizeof(*context) / 4) * channel;
1025 ret = sdma_run_channel0(sdma);
1026
1027 spin_unlock_irqrestore(&sdma->channel_0_lock, flags);
1028
1029 return ret;
1030 }
1031
to_sdma_chan(struct dma_chan * chan)1032 static struct sdma_channel *to_sdma_chan(struct dma_chan *chan)
1033 {
1034 return container_of(chan, struct sdma_channel, vc.chan);
1035 }
1036
sdma_disable_channel(struct dma_chan * chan)1037 static int sdma_disable_channel(struct dma_chan *chan)
1038 {
1039 struct sdma_channel *sdmac = to_sdma_chan(chan);
1040 struct sdma_engine *sdma = sdmac->sdma;
1041 int channel = sdmac->channel;
1042
1043 writel_relaxed(BIT(channel), sdma->regs + SDMA_H_STATSTOP);
1044 sdmac->status = DMA_ERROR;
1045
1046 return 0;
1047 }
sdma_channel_terminate_work(struct work_struct * work)1048 static void sdma_channel_terminate_work(struct work_struct *work)
1049 {
1050 struct sdma_channel *sdmac = container_of(work, struct sdma_channel,
1051 terminate_worker);
1052 unsigned long flags;
1053 LIST_HEAD(head);
1054
1055 /*
1056 * According to NXP R&D team a delay of one BD SDMA cost time
1057 * (maximum is 1ms) should be added after disable of the channel
1058 * bit, to ensure SDMA core has really been stopped after SDMA
1059 * clients call .device_terminate_all.
1060 */
1061 usleep_range(1000, 2000);
1062
1063 spin_lock_irqsave(&sdmac->vc.lock, flags);
1064 vchan_get_all_descriptors(&sdmac->vc, &head);
1065 spin_unlock_irqrestore(&sdmac->vc.lock, flags);
1066 vchan_dma_desc_free_list(&sdmac->vc, &head);
1067 }
1068
sdma_terminate_all(struct dma_chan * chan)1069 static int sdma_terminate_all(struct dma_chan *chan)
1070 {
1071 struct sdma_channel *sdmac = to_sdma_chan(chan);
1072 unsigned long flags;
1073
1074 spin_lock_irqsave(&sdmac->vc.lock, flags);
1075
1076 sdma_disable_channel(chan);
1077
1078 if (sdmac->desc) {
1079 vchan_terminate_vdesc(&sdmac->desc->vd);
1080 sdmac->desc = NULL;
1081 schedule_work(&sdmac->terminate_worker);
1082 }
1083
1084 spin_unlock_irqrestore(&sdmac->vc.lock, flags);
1085
1086 return 0;
1087 }
1088
sdma_channel_synchronize(struct dma_chan * chan)1089 static void sdma_channel_synchronize(struct dma_chan *chan)
1090 {
1091 struct sdma_channel *sdmac = to_sdma_chan(chan);
1092
1093 vchan_synchronize(&sdmac->vc);
1094
1095 flush_work(&sdmac->terminate_worker);
1096 }
1097
sdma_set_watermarklevel_for_p2p(struct sdma_channel * sdmac)1098 static void sdma_set_watermarklevel_for_p2p(struct sdma_channel *sdmac)
1099 {
1100 struct sdma_engine *sdma = sdmac->sdma;
1101
1102 int lwml = sdmac->watermark_level & SDMA_WATERMARK_LEVEL_LWML;
1103 int hwml = (sdmac->watermark_level & SDMA_WATERMARK_LEVEL_HWML) >> 16;
1104
1105 set_bit(sdmac->event_id0 % 32, &sdmac->event_mask[1]);
1106 set_bit(sdmac->event_id1 % 32, &sdmac->event_mask[0]);
1107
1108 if (sdmac->event_id0 > 31)
1109 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_LWE;
1110
1111 if (sdmac->event_id1 > 31)
1112 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_HWE;
1113
1114 /*
1115 * If LWML(src_maxburst) > HWML(dst_maxburst), we need
1116 * swap LWML and HWML of INFO(A.3.2.5.1), also need swap
1117 * r0(event_mask[1]) and r1(event_mask[0]).
1118 */
1119 if (lwml > hwml) {
1120 sdmac->watermark_level &= ~(SDMA_WATERMARK_LEVEL_LWML |
1121 SDMA_WATERMARK_LEVEL_HWML);
1122 sdmac->watermark_level |= hwml;
1123 sdmac->watermark_level |= lwml << 16;
1124 swap(sdmac->event_mask[0], sdmac->event_mask[1]);
1125 }
1126
1127 if (sdmac->per_address2 >= sdma->spba_start_addr &&
1128 sdmac->per_address2 <= sdma->spba_end_addr)
1129 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_SP;
1130
1131 if (sdmac->per_address >= sdma->spba_start_addr &&
1132 sdmac->per_address <= sdma->spba_end_addr)
1133 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_DP;
1134
1135 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_CONT;
1136 }
1137
sdma_config_channel(struct dma_chan * chan)1138 static int sdma_config_channel(struct dma_chan *chan)
1139 {
1140 struct sdma_channel *sdmac = to_sdma_chan(chan);
1141
1142 sdma_disable_channel(chan);
1143
1144 sdmac->event_mask[0] = 0;
1145 sdmac->event_mask[1] = 0;
1146 sdmac->shp_addr = 0;
1147 sdmac->per_addr = 0;
1148
1149 switch (sdmac->peripheral_type) {
1150 case IMX_DMATYPE_DSP:
1151 sdma_config_ownership(sdmac, false, true, true);
1152 break;
1153 case IMX_DMATYPE_MEMORY:
1154 sdma_config_ownership(sdmac, false, true, false);
1155 break;
1156 default:
1157 sdma_config_ownership(sdmac, true, true, false);
1158 break;
1159 }
1160
1161 sdma_get_pc(sdmac, sdmac->peripheral_type);
1162
1163 if ((sdmac->peripheral_type != IMX_DMATYPE_MEMORY) &&
1164 (sdmac->peripheral_type != IMX_DMATYPE_DSP)) {
1165 /* Handle multiple event channels differently */
1166 if (sdmac->event_id1) {
1167 if (sdmac->peripheral_type == IMX_DMATYPE_ASRC_SP ||
1168 sdmac->peripheral_type == IMX_DMATYPE_ASRC)
1169 sdma_set_watermarklevel_for_p2p(sdmac);
1170 } else
1171 __set_bit(sdmac->event_id0, sdmac->event_mask);
1172
1173 /* Address */
1174 sdmac->shp_addr = sdmac->per_address;
1175 sdmac->per_addr = sdmac->per_address2;
1176 } else {
1177 sdmac->watermark_level = 0; /* FIXME: M3_BASE_ADDRESS */
1178 }
1179
1180 return 0;
1181 }
1182
sdma_set_channel_priority(struct sdma_channel * sdmac,unsigned int priority)1183 static int sdma_set_channel_priority(struct sdma_channel *sdmac,
1184 unsigned int priority)
1185 {
1186 struct sdma_engine *sdma = sdmac->sdma;
1187 int channel = sdmac->channel;
1188
1189 if (priority < MXC_SDMA_MIN_PRIORITY
1190 || priority > MXC_SDMA_MAX_PRIORITY) {
1191 return -EINVAL;
1192 }
1193
1194 writel_relaxed(priority, sdma->regs + SDMA_CHNPRI_0 + 4 * channel);
1195
1196 return 0;
1197 }
1198
sdma_request_channel0(struct sdma_engine * sdma)1199 static int sdma_request_channel0(struct sdma_engine *sdma)
1200 {
1201 int ret = -EBUSY;
1202
1203 sdma->bd0 = dma_alloc_coherent(sdma->dev, PAGE_SIZE, &sdma->bd0_phys,
1204 GFP_NOWAIT);
1205 if (!sdma->bd0) {
1206 ret = -ENOMEM;
1207 goto out;
1208 }
1209
1210 sdma->channel_control[0].base_bd_ptr = sdma->bd0_phys;
1211 sdma->channel_control[0].current_bd_ptr = sdma->bd0_phys;
1212
1213 sdma_set_channel_priority(&sdma->channel[0], MXC_SDMA_DEFAULT_PRIORITY);
1214 return 0;
1215 out:
1216
1217 return ret;
1218 }
1219
1220
sdma_alloc_bd(struct sdma_desc * desc)1221 static int sdma_alloc_bd(struct sdma_desc *desc)
1222 {
1223 u32 bd_size = desc->num_bd * sizeof(struct sdma_buffer_descriptor);
1224 int ret = 0;
1225
1226 desc->bd = dma_alloc_coherent(desc->sdmac->sdma->dev, bd_size,
1227 &desc->bd_phys, GFP_NOWAIT);
1228 if (!desc->bd) {
1229 ret = -ENOMEM;
1230 goto out;
1231 }
1232 out:
1233 return ret;
1234 }
1235
sdma_free_bd(struct sdma_desc * desc)1236 static void sdma_free_bd(struct sdma_desc *desc)
1237 {
1238 u32 bd_size = desc->num_bd * sizeof(struct sdma_buffer_descriptor);
1239
1240 dma_free_coherent(desc->sdmac->sdma->dev, bd_size, desc->bd,
1241 desc->bd_phys);
1242 }
1243
sdma_desc_free(struct virt_dma_desc * vd)1244 static void sdma_desc_free(struct virt_dma_desc *vd)
1245 {
1246 struct sdma_desc *desc = container_of(vd, struct sdma_desc, vd);
1247
1248 sdma_free_bd(desc);
1249 kfree(desc);
1250 }
1251
sdma_alloc_chan_resources(struct dma_chan * chan)1252 static int sdma_alloc_chan_resources(struct dma_chan *chan)
1253 {
1254 struct sdma_channel *sdmac = to_sdma_chan(chan);
1255 struct imx_dma_data *data = chan->private;
1256 struct imx_dma_data mem_data;
1257 int prio, ret;
1258
1259 /*
1260 * MEMCPY may never setup chan->private by filter function such as
1261 * dmatest, thus create 'struct imx_dma_data mem_data' for this case.
1262 * Please note in any other slave case, you have to setup chan->private
1263 * with 'struct imx_dma_data' in your own filter function if you want to
1264 * request dma channel by dma_request_channel() rather than
1265 * dma_request_slave_channel(). Othwise, 'MEMCPY in case?' will appear
1266 * to warn you to correct your filter function.
1267 */
1268 if (!data) {
1269 dev_dbg(sdmac->sdma->dev, "MEMCPY in case?\n");
1270 mem_data.priority = 2;
1271 mem_data.peripheral_type = IMX_DMATYPE_MEMORY;
1272 mem_data.dma_request = 0;
1273 mem_data.dma_request2 = 0;
1274 data = &mem_data;
1275
1276 sdma_get_pc(sdmac, IMX_DMATYPE_MEMORY);
1277 }
1278
1279 switch (data->priority) {
1280 case DMA_PRIO_HIGH:
1281 prio = 3;
1282 break;
1283 case DMA_PRIO_MEDIUM:
1284 prio = 2;
1285 break;
1286 case DMA_PRIO_LOW:
1287 default:
1288 prio = 1;
1289 break;
1290 }
1291
1292 sdmac->peripheral_type = data->peripheral_type;
1293 sdmac->event_id0 = data->dma_request;
1294 sdmac->event_id1 = data->dma_request2;
1295
1296 ret = clk_enable(sdmac->sdma->clk_ipg);
1297 if (ret)
1298 return ret;
1299 ret = clk_enable(sdmac->sdma->clk_ahb);
1300 if (ret)
1301 goto disable_clk_ipg;
1302
1303 ret = sdma_set_channel_priority(sdmac, prio);
1304 if (ret)
1305 goto disable_clk_ahb;
1306
1307 return 0;
1308
1309 disable_clk_ahb:
1310 clk_disable(sdmac->sdma->clk_ahb);
1311 disable_clk_ipg:
1312 clk_disable(sdmac->sdma->clk_ipg);
1313 return ret;
1314 }
1315
sdma_free_chan_resources(struct dma_chan * chan)1316 static void sdma_free_chan_resources(struct dma_chan *chan)
1317 {
1318 struct sdma_channel *sdmac = to_sdma_chan(chan);
1319 struct sdma_engine *sdma = sdmac->sdma;
1320
1321 sdma_terminate_all(chan);
1322
1323 sdma_channel_synchronize(chan);
1324
1325 sdma_event_disable(sdmac, sdmac->event_id0);
1326 if (sdmac->event_id1)
1327 sdma_event_disable(sdmac, sdmac->event_id1);
1328
1329 sdmac->event_id0 = 0;
1330 sdmac->event_id1 = 0;
1331
1332 sdma_set_channel_priority(sdmac, 0);
1333
1334 clk_disable(sdma->clk_ipg);
1335 clk_disable(sdma->clk_ahb);
1336 }
1337
sdma_transfer_init(struct sdma_channel * sdmac,enum dma_transfer_direction direction,u32 bds)1338 static struct sdma_desc *sdma_transfer_init(struct sdma_channel *sdmac,
1339 enum dma_transfer_direction direction, u32 bds)
1340 {
1341 struct sdma_desc *desc;
1342
1343 desc = kzalloc((sizeof(*desc)), GFP_NOWAIT);
1344 if (!desc)
1345 goto err_out;
1346
1347 sdmac->status = DMA_IN_PROGRESS;
1348 sdmac->direction = direction;
1349 sdmac->flags = 0;
1350
1351 desc->chn_count = 0;
1352 desc->chn_real_count = 0;
1353 desc->buf_tail = 0;
1354 desc->buf_ptail = 0;
1355 desc->sdmac = sdmac;
1356 desc->num_bd = bds;
1357
1358 if (sdma_alloc_bd(desc))
1359 goto err_desc_out;
1360
1361 /* No slave_config called in MEMCPY case, so do here */
1362 if (direction == DMA_MEM_TO_MEM)
1363 sdma_config_ownership(sdmac, false, true, false);
1364
1365 if (sdma_load_context(sdmac))
1366 goto err_bd_out;
1367
1368 return desc;
1369
1370 err_bd_out:
1371 sdma_free_bd(desc);
1372 err_desc_out:
1373 kfree(desc);
1374 err_out:
1375 return NULL;
1376 }
1377
sdma_prep_memcpy(struct dma_chan * chan,dma_addr_t dma_dst,dma_addr_t dma_src,size_t len,unsigned long flags)1378 static struct dma_async_tx_descriptor *sdma_prep_memcpy(
1379 struct dma_chan *chan, dma_addr_t dma_dst,
1380 dma_addr_t dma_src, size_t len, unsigned long flags)
1381 {
1382 struct sdma_channel *sdmac = to_sdma_chan(chan);
1383 struct sdma_engine *sdma = sdmac->sdma;
1384 int channel = sdmac->channel;
1385 size_t count;
1386 int i = 0, param;
1387 struct sdma_buffer_descriptor *bd;
1388 struct sdma_desc *desc;
1389
1390 if (!chan || !len)
1391 return NULL;
1392
1393 dev_dbg(sdma->dev, "memcpy: %pad->%pad, len=%zu, channel=%d.\n",
1394 &dma_src, &dma_dst, len, channel);
1395
1396 desc = sdma_transfer_init(sdmac, DMA_MEM_TO_MEM,
1397 len / SDMA_BD_MAX_CNT + 1);
1398 if (!desc)
1399 return NULL;
1400
1401 do {
1402 count = min_t(size_t, len, SDMA_BD_MAX_CNT);
1403 bd = &desc->bd[i];
1404 bd->buffer_addr = dma_src;
1405 bd->ext_buffer_addr = dma_dst;
1406 bd->mode.count = count;
1407 desc->chn_count += count;
1408 bd->mode.command = 0;
1409
1410 dma_src += count;
1411 dma_dst += count;
1412 len -= count;
1413 i++;
1414
1415 param = BD_DONE | BD_EXTD | BD_CONT;
1416 /* last bd */
1417 if (!len) {
1418 param |= BD_INTR;
1419 param |= BD_LAST;
1420 param &= ~BD_CONT;
1421 }
1422
1423 dev_dbg(sdma->dev, "entry %d: count: %zd dma: 0x%x %s%s\n",
1424 i, count, bd->buffer_addr,
1425 param & BD_WRAP ? "wrap" : "",
1426 param & BD_INTR ? " intr" : "");
1427
1428 bd->mode.status = param;
1429 } while (len);
1430
1431 return vchan_tx_prep(&sdmac->vc, &desc->vd, flags);
1432 }
1433
sdma_prep_slave_sg(struct dma_chan * chan,struct scatterlist * sgl,unsigned int sg_len,enum dma_transfer_direction direction,unsigned long flags,void * context)1434 static struct dma_async_tx_descriptor *sdma_prep_slave_sg(
1435 struct dma_chan *chan, struct scatterlist *sgl,
1436 unsigned int sg_len, enum dma_transfer_direction direction,
1437 unsigned long flags, void *context)
1438 {
1439 struct sdma_channel *sdmac = to_sdma_chan(chan);
1440 struct sdma_engine *sdma = sdmac->sdma;
1441 int i, count;
1442 int channel = sdmac->channel;
1443 struct scatterlist *sg;
1444 struct sdma_desc *desc;
1445
1446 sdma_config_write(chan, &sdmac->slave_config, direction);
1447
1448 desc = sdma_transfer_init(sdmac, direction, sg_len);
1449 if (!desc)
1450 goto err_out;
1451
1452 dev_dbg(sdma->dev, "setting up %d entries for channel %d.\n",
1453 sg_len, channel);
1454
1455 for_each_sg(sgl, sg, sg_len, i) {
1456 struct sdma_buffer_descriptor *bd = &desc->bd[i];
1457 int param;
1458
1459 bd->buffer_addr = sg->dma_address;
1460
1461 count = sg_dma_len(sg);
1462
1463 if (count > SDMA_BD_MAX_CNT) {
1464 dev_err(sdma->dev, "SDMA channel %d: maximum bytes for sg entry exceeded: %d > %d\n",
1465 channel, count, SDMA_BD_MAX_CNT);
1466 goto err_bd_out;
1467 }
1468
1469 bd->mode.count = count;
1470 desc->chn_count += count;
1471
1472 if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES)
1473 goto err_bd_out;
1474
1475 switch (sdmac->word_size) {
1476 case DMA_SLAVE_BUSWIDTH_4_BYTES:
1477 bd->mode.command = 0;
1478 if (count & 3 || sg->dma_address & 3)
1479 goto err_bd_out;
1480 break;
1481 case DMA_SLAVE_BUSWIDTH_2_BYTES:
1482 bd->mode.command = 2;
1483 if (count & 1 || sg->dma_address & 1)
1484 goto err_bd_out;
1485 break;
1486 case DMA_SLAVE_BUSWIDTH_1_BYTE:
1487 bd->mode.command = 1;
1488 break;
1489 default:
1490 goto err_bd_out;
1491 }
1492
1493 param = BD_DONE | BD_EXTD | BD_CONT;
1494
1495 if (i + 1 == sg_len) {
1496 param |= BD_INTR;
1497 param |= BD_LAST;
1498 param &= ~BD_CONT;
1499 }
1500
1501 dev_dbg(sdma->dev, "entry %d: count: %d dma: %#llx %s%s\n",
1502 i, count, (u64)sg->dma_address,
1503 param & BD_WRAP ? "wrap" : "",
1504 param & BD_INTR ? " intr" : "");
1505
1506 bd->mode.status = param;
1507 }
1508
1509 return vchan_tx_prep(&sdmac->vc, &desc->vd, flags);
1510 err_bd_out:
1511 sdma_free_bd(desc);
1512 kfree(desc);
1513 err_out:
1514 sdmac->status = DMA_ERROR;
1515 return NULL;
1516 }
1517
sdma_prep_dma_cyclic(struct dma_chan * chan,dma_addr_t dma_addr,size_t buf_len,size_t period_len,enum dma_transfer_direction direction,unsigned long flags)1518 static struct dma_async_tx_descriptor *sdma_prep_dma_cyclic(
1519 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
1520 size_t period_len, enum dma_transfer_direction direction,
1521 unsigned long flags)
1522 {
1523 struct sdma_channel *sdmac = to_sdma_chan(chan);
1524 struct sdma_engine *sdma = sdmac->sdma;
1525 int num_periods = buf_len / period_len;
1526 int channel = sdmac->channel;
1527 int i = 0, buf = 0;
1528 struct sdma_desc *desc;
1529
1530 dev_dbg(sdma->dev, "%s channel: %d\n", __func__, channel);
1531
1532 sdma_config_write(chan, &sdmac->slave_config, direction);
1533
1534 desc = sdma_transfer_init(sdmac, direction, num_periods);
1535 if (!desc)
1536 goto err_out;
1537
1538 desc->period_len = period_len;
1539
1540 sdmac->flags |= IMX_DMA_SG_LOOP;
1541
1542 if (period_len > SDMA_BD_MAX_CNT) {
1543 dev_err(sdma->dev, "SDMA channel %d: maximum period size exceeded: %zu > %d\n",
1544 channel, period_len, SDMA_BD_MAX_CNT);
1545 goto err_bd_out;
1546 }
1547
1548 while (buf < buf_len) {
1549 struct sdma_buffer_descriptor *bd = &desc->bd[i];
1550 int param;
1551
1552 bd->buffer_addr = dma_addr;
1553
1554 bd->mode.count = period_len;
1555
1556 if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES)
1557 goto err_bd_out;
1558 if (sdmac->word_size == DMA_SLAVE_BUSWIDTH_4_BYTES)
1559 bd->mode.command = 0;
1560 else
1561 bd->mode.command = sdmac->word_size;
1562
1563 param = BD_DONE | BD_EXTD | BD_CONT | BD_INTR;
1564 if (i + 1 == num_periods)
1565 param |= BD_WRAP;
1566
1567 dev_dbg(sdma->dev, "entry %d: count: %zu dma: %#llx %s%s\n",
1568 i, period_len, (u64)dma_addr,
1569 param & BD_WRAP ? "wrap" : "",
1570 param & BD_INTR ? " intr" : "");
1571
1572 bd->mode.status = param;
1573
1574 dma_addr += period_len;
1575 buf += period_len;
1576
1577 i++;
1578 }
1579
1580 return vchan_tx_prep(&sdmac->vc, &desc->vd, flags);
1581 err_bd_out:
1582 sdma_free_bd(desc);
1583 kfree(desc);
1584 err_out:
1585 sdmac->status = DMA_ERROR;
1586 return NULL;
1587 }
1588
sdma_config_write(struct dma_chan * chan,struct dma_slave_config * dmaengine_cfg,enum dma_transfer_direction direction)1589 static int sdma_config_write(struct dma_chan *chan,
1590 struct dma_slave_config *dmaengine_cfg,
1591 enum dma_transfer_direction direction)
1592 {
1593 struct sdma_channel *sdmac = to_sdma_chan(chan);
1594
1595 if (direction == DMA_DEV_TO_MEM) {
1596 sdmac->per_address = dmaengine_cfg->src_addr;
1597 sdmac->watermark_level = dmaengine_cfg->src_maxburst *
1598 dmaengine_cfg->src_addr_width;
1599 sdmac->word_size = dmaengine_cfg->src_addr_width;
1600 } else if (direction == DMA_DEV_TO_DEV) {
1601 sdmac->per_address2 = dmaengine_cfg->src_addr;
1602 sdmac->per_address = dmaengine_cfg->dst_addr;
1603 sdmac->watermark_level = dmaengine_cfg->src_maxburst &
1604 SDMA_WATERMARK_LEVEL_LWML;
1605 sdmac->watermark_level |= (dmaengine_cfg->dst_maxburst << 16) &
1606 SDMA_WATERMARK_LEVEL_HWML;
1607 sdmac->word_size = dmaengine_cfg->dst_addr_width;
1608 } else {
1609 sdmac->per_address = dmaengine_cfg->dst_addr;
1610 sdmac->watermark_level = dmaengine_cfg->dst_maxburst *
1611 dmaengine_cfg->dst_addr_width;
1612 sdmac->word_size = dmaengine_cfg->dst_addr_width;
1613 }
1614 sdmac->direction = direction;
1615 return sdma_config_channel(chan);
1616 }
1617
sdma_config(struct dma_chan * chan,struct dma_slave_config * dmaengine_cfg)1618 static int sdma_config(struct dma_chan *chan,
1619 struct dma_slave_config *dmaengine_cfg)
1620 {
1621 struct sdma_channel *sdmac = to_sdma_chan(chan);
1622
1623 memcpy(&sdmac->slave_config, dmaengine_cfg, sizeof(*dmaengine_cfg));
1624
1625 /* Set ENBLn earlier to make sure dma request triggered after that */
1626 if (sdmac->event_id0 >= sdmac->sdma->drvdata->num_events)
1627 return -EINVAL;
1628 sdma_event_enable(sdmac, sdmac->event_id0);
1629
1630 if (sdmac->event_id1) {
1631 if (sdmac->event_id1 >= sdmac->sdma->drvdata->num_events)
1632 return -EINVAL;
1633 sdma_event_enable(sdmac, sdmac->event_id1);
1634 }
1635
1636 return 0;
1637 }
1638
sdma_tx_status(struct dma_chan * chan,dma_cookie_t cookie,struct dma_tx_state * txstate)1639 static enum dma_status sdma_tx_status(struct dma_chan *chan,
1640 dma_cookie_t cookie,
1641 struct dma_tx_state *txstate)
1642 {
1643 struct sdma_channel *sdmac = to_sdma_chan(chan);
1644 struct sdma_desc *desc = NULL;
1645 u32 residue;
1646 struct virt_dma_desc *vd;
1647 enum dma_status ret;
1648 unsigned long flags;
1649
1650 ret = dma_cookie_status(chan, cookie, txstate);
1651 if (ret == DMA_COMPLETE || !txstate)
1652 return ret;
1653
1654 spin_lock_irqsave(&sdmac->vc.lock, flags);
1655
1656 vd = vchan_find_desc(&sdmac->vc, cookie);
1657 if (vd)
1658 desc = to_sdma_desc(&vd->tx);
1659 else if (sdmac->desc && sdmac->desc->vd.tx.cookie == cookie)
1660 desc = sdmac->desc;
1661
1662 if (desc) {
1663 if (sdmac->flags & IMX_DMA_SG_LOOP)
1664 residue = (desc->num_bd - desc->buf_ptail) *
1665 desc->period_len - desc->chn_real_count;
1666 else
1667 residue = desc->chn_count - desc->chn_real_count;
1668 } else {
1669 residue = 0;
1670 }
1671
1672 spin_unlock_irqrestore(&sdmac->vc.lock, flags);
1673
1674 dma_set_tx_state(txstate, chan->completed_cookie, chan->cookie,
1675 residue);
1676
1677 return sdmac->status;
1678 }
1679
sdma_issue_pending(struct dma_chan * chan)1680 static void sdma_issue_pending(struct dma_chan *chan)
1681 {
1682 struct sdma_channel *sdmac = to_sdma_chan(chan);
1683 unsigned long flags;
1684
1685 spin_lock_irqsave(&sdmac->vc.lock, flags);
1686 if (vchan_issue_pending(&sdmac->vc) && !sdmac->desc)
1687 sdma_start_desc(sdmac);
1688 spin_unlock_irqrestore(&sdmac->vc.lock, flags);
1689 }
1690
1691 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1 34
1692 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V2 38
1693 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V3 41
1694 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V4 42
1695
sdma_add_scripts(struct sdma_engine * sdma,const struct sdma_script_start_addrs * addr)1696 static void sdma_add_scripts(struct sdma_engine *sdma,
1697 const struct sdma_script_start_addrs *addr)
1698 {
1699 s32 *addr_arr = (u32 *)addr;
1700 s32 *saddr_arr = (u32 *)sdma->script_addrs;
1701 int i;
1702
1703 /* use the default firmware in ROM if missing external firmware */
1704 if (!sdma->script_number)
1705 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1;
1706
1707 if (sdma->script_number > sizeof(struct sdma_script_start_addrs)
1708 / sizeof(s32)) {
1709 dev_err(sdma->dev,
1710 "SDMA script number %d not match with firmware.\n",
1711 sdma->script_number);
1712 return;
1713 }
1714
1715 for (i = 0; i < sdma->script_number; i++)
1716 if (addr_arr[i] > 0)
1717 saddr_arr[i] = addr_arr[i];
1718 }
1719
sdma_load_firmware(const struct firmware * fw,void * context)1720 static void sdma_load_firmware(const struct firmware *fw, void *context)
1721 {
1722 struct sdma_engine *sdma = context;
1723 const struct sdma_firmware_header *header;
1724 const struct sdma_script_start_addrs *addr;
1725 unsigned short *ram_code;
1726
1727 if (!fw) {
1728 dev_info(sdma->dev, "external firmware not found, using ROM firmware\n");
1729 /* In this case we just use the ROM firmware. */
1730 return;
1731 }
1732
1733 if (fw->size < sizeof(*header))
1734 goto err_firmware;
1735
1736 header = (struct sdma_firmware_header *)fw->data;
1737
1738 if (header->magic != SDMA_FIRMWARE_MAGIC)
1739 goto err_firmware;
1740 if (header->ram_code_start + header->ram_code_size > fw->size)
1741 goto err_firmware;
1742 switch (header->version_major) {
1743 case 1:
1744 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1;
1745 break;
1746 case 2:
1747 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V2;
1748 break;
1749 case 3:
1750 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V3;
1751 break;
1752 case 4:
1753 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V4;
1754 break;
1755 default:
1756 dev_err(sdma->dev, "unknown firmware version\n");
1757 goto err_firmware;
1758 }
1759
1760 addr = (void *)header + header->script_addrs_start;
1761 ram_code = (void *)header + header->ram_code_start;
1762
1763 clk_enable(sdma->clk_ipg);
1764 clk_enable(sdma->clk_ahb);
1765 /* download the RAM image for SDMA */
1766 sdma_load_script(sdma, ram_code,
1767 header->ram_code_size,
1768 addr->ram_code_start_addr);
1769 clk_disable(sdma->clk_ipg);
1770 clk_disable(sdma->clk_ahb);
1771
1772 sdma_add_scripts(sdma, addr);
1773
1774 dev_info(sdma->dev, "loaded firmware %d.%d\n",
1775 header->version_major,
1776 header->version_minor);
1777
1778 err_firmware:
1779 release_firmware(fw);
1780 }
1781
1782 #define EVENT_REMAP_CELLS 3
1783
sdma_event_remap(struct sdma_engine * sdma)1784 static int sdma_event_remap(struct sdma_engine *sdma)
1785 {
1786 struct device_node *np = sdma->dev->of_node;
1787 struct device_node *gpr_np = of_parse_phandle(np, "gpr", 0);
1788 struct property *event_remap;
1789 struct regmap *gpr;
1790 char propname[] = "fsl,sdma-event-remap";
1791 u32 reg, val, shift, num_map, i;
1792 int ret = 0;
1793
1794 if (IS_ERR(np) || !gpr_np)
1795 goto out;
1796
1797 event_remap = of_find_property(np, propname, NULL);
1798 num_map = event_remap ? (event_remap->length / sizeof(u32)) : 0;
1799 if (!num_map) {
1800 dev_dbg(sdma->dev, "no event needs to be remapped\n");
1801 goto out;
1802 } else if (num_map % EVENT_REMAP_CELLS) {
1803 dev_err(sdma->dev, "the property %s must modulo %d\n",
1804 propname, EVENT_REMAP_CELLS);
1805 ret = -EINVAL;
1806 goto out;
1807 }
1808
1809 gpr = syscon_node_to_regmap(gpr_np);
1810 if (IS_ERR(gpr)) {
1811 dev_err(sdma->dev, "failed to get gpr regmap\n");
1812 ret = PTR_ERR(gpr);
1813 goto out;
1814 }
1815
1816 for (i = 0; i < num_map; i += EVENT_REMAP_CELLS) {
1817 ret = of_property_read_u32_index(np, propname, i, ®);
1818 if (ret) {
1819 dev_err(sdma->dev, "failed to read property %s index %d\n",
1820 propname, i);
1821 goto out;
1822 }
1823
1824 ret = of_property_read_u32_index(np, propname, i + 1, &shift);
1825 if (ret) {
1826 dev_err(sdma->dev, "failed to read property %s index %d\n",
1827 propname, i + 1);
1828 goto out;
1829 }
1830
1831 ret = of_property_read_u32_index(np, propname, i + 2, &val);
1832 if (ret) {
1833 dev_err(sdma->dev, "failed to read property %s index %d\n",
1834 propname, i + 2);
1835 goto out;
1836 }
1837
1838 regmap_update_bits(gpr, reg, BIT(shift), val << shift);
1839 }
1840
1841 out:
1842 if (gpr_np)
1843 of_node_put(gpr_np);
1844
1845 return ret;
1846 }
1847
sdma_get_firmware(struct sdma_engine * sdma,const char * fw_name)1848 static int sdma_get_firmware(struct sdma_engine *sdma,
1849 const char *fw_name)
1850 {
1851 int ret;
1852
1853 ret = request_firmware_nowait(THIS_MODULE,
1854 FW_ACTION_HOTPLUG, fw_name, sdma->dev,
1855 GFP_KERNEL, sdma, sdma_load_firmware);
1856
1857 return ret;
1858 }
1859
sdma_init(struct sdma_engine * sdma)1860 static int sdma_init(struct sdma_engine *sdma)
1861 {
1862 int i, ret;
1863 dma_addr_t ccb_phys;
1864
1865 ret = clk_enable(sdma->clk_ipg);
1866 if (ret)
1867 return ret;
1868 ret = clk_enable(sdma->clk_ahb);
1869 if (ret)
1870 goto disable_clk_ipg;
1871
1872 if (sdma->drvdata->check_ratio &&
1873 (clk_get_rate(sdma->clk_ahb) == clk_get_rate(sdma->clk_ipg)))
1874 sdma->clk_ratio = 1;
1875
1876 /* Be sure SDMA has not started yet */
1877 writel_relaxed(0, sdma->regs + SDMA_H_C0PTR);
1878
1879 sdma->channel_control = dma_alloc_coherent(sdma->dev,
1880 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control) +
1881 sizeof(struct sdma_context_data),
1882 &ccb_phys, GFP_KERNEL);
1883
1884 if (!sdma->channel_control) {
1885 ret = -ENOMEM;
1886 goto err_dma_alloc;
1887 }
1888
1889 sdma->context = (void *)sdma->channel_control +
1890 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control);
1891 sdma->context_phys = ccb_phys +
1892 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control);
1893
1894 /* disable all channels */
1895 for (i = 0; i < sdma->drvdata->num_events; i++)
1896 writel_relaxed(0, sdma->regs + chnenbl_ofs(sdma, i));
1897
1898 /* All channels have priority 0 */
1899 for (i = 0; i < MAX_DMA_CHANNELS; i++)
1900 writel_relaxed(0, sdma->regs + SDMA_CHNPRI_0 + i * 4);
1901
1902 ret = sdma_request_channel0(sdma);
1903 if (ret)
1904 goto err_dma_alloc;
1905
1906 sdma_config_ownership(&sdma->channel[0], false, true, false);
1907
1908 /* Set Command Channel (Channel Zero) */
1909 writel_relaxed(0x4050, sdma->regs + SDMA_CHN0ADDR);
1910
1911 /* Set bits of CONFIG register but with static context switching */
1912 if (sdma->clk_ratio)
1913 writel_relaxed(SDMA_H_CONFIG_ACR, sdma->regs + SDMA_H_CONFIG);
1914 else
1915 writel_relaxed(0, sdma->regs + SDMA_H_CONFIG);
1916
1917 writel_relaxed(ccb_phys, sdma->regs + SDMA_H_C0PTR);
1918
1919 /* Initializes channel's priorities */
1920 sdma_set_channel_priority(&sdma->channel[0], 7);
1921
1922 clk_disable(sdma->clk_ipg);
1923 clk_disable(sdma->clk_ahb);
1924
1925 return 0;
1926
1927 err_dma_alloc:
1928 clk_disable(sdma->clk_ahb);
1929 disable_clk_ipg:
1930 clk_disable(sdma->clk_ipg);
1931 dev_err(sdma->dev, "initialisation failed with %d\n", ret);
1932 return ret;
1933 }
1934
sdma_filter_fn(struct dma_chan * chan,void * fn_param)1935 static bool sdma_filter_fn(struct dma_chan *chan, void *fn_param)
1936 {
1937 struct sdma_channel *sdmac = to_sdma_chan(chan);
1938 struct imx_dma_data *data = fn_param;
1939
1940 if (!imx_dma_is_general_purpose(chan))
1941 return false;
1942
1943 sdmac->data = *data;
1944 chan->private = &sdmac->data;
1945
1946 return true;
1947 }
1948
sdma_xlate(struct of_phandle_args * dma_spec,struct of_dma * ofdma)1949 static struct dma_chan *sdma_xlate(struct of_phandle_args *dma_spec,
1950 struct of_dma *ofdma)
1951 {
1952 struct sdma_engine *sdma = ofdma->of_dma_data;
1953 dma_cap_mask_t mask = sdma->dma_device.cap_mask;
1954 struct imx_dma_data data;
1955
1956 if (dma_spec->args_count != 3)
1957 return NULL;
1958
1959 data.dma_request = dma_spec->args[0];
1960 data.peripheral_type = dma_spec->args[1];
1961 data.priority = dma_spec->args[2];
1962 /*
1963 * init dma_request2 to zero, which is not used by the dts.
1964 * For P2P, dma_request2 is init from dma_request_channel(),
1965 * chan->private will point to the imx_dma_data, and in
1966 * device_alloc_chan_resources(), imx_dma_data.dma_request2 will
1967 * be set to sdmac->event_id1.
1968 */
1969 data.dma_request2 = 0;
1970
1971 return __dma_request_channel(&mask, sdma_filter_fn, &data,
1972 ofdma->of_node);
1973 }
1974
sdma_probe(struct platform_device * pdev)1975 static int sdma_probe(struct platform_device *pdev)
1976 {
1977 const struct of_device_id *of_id =
1978 of_match_device(sdma_dt_ids, &pdev->dev);
1979 struct device_node *np = pdev->dev.of_node;
1980 struct device_node *spba_bus;
1981 const char *fw_name;
1982 int ret;
1983 int irq;
1984 struct resource *iores;
1985 struct resource spba_res;
1986 struct sdma_platform_data *pdata = dev_get_platdata(&pdev->dev);
1987 int i;
1988 struct sdma_engine *sdma;
1989 s32 *saddr_arr;
1990 const struct sdma_driver_data *drvdata = NULL;
1991
1992 if (of_id)
1993 drvdata = of_id->data;
1994 else if (pdev->id_entry)
1995 drvdata = (void *)pdev->id_entry->driver_data;
1996
1997 if (!drvdata) {
1998 dev_err(&pdev->dev, "unable to find driver data\n");
1999 return -EINVAL;
2000 }
2001
2002 ret = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
2003 if (ret)
2004 return ret;
2005
2006 sdma = devm_kzalloc(&pdev->dev, sizeof(*sdma), GFP_KERNEL);
2007 if (!sdma)
2008 return -ENOMEM;
2009
2010 spin_lock_init(&sdma->channel_0_lock);
2011
2012 sdma->dev = &pdev->dev;
2013 sdma->drvdata = drvdata;
2014
2015 irq = platform_get_irq(pdev, 0);
2016 if (irq < 0)
2017 return irq;
2018
2019 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2020 sdma->regs = devm_ioremap_resource(&pdev->dev, iores);
2021 if (IS_ERR(sdma->regs))
2022 return PTR_ERR(sdma->regs);
2023
2024 sdma->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
2025 if (IS_ERR(sdma->clk_ipg))
2026 return PTR_ERR(sdma->clk_ipg);
2027
2028 sdma->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
2029 if (IS_ERR(sdma->clk_ahb))
2030 return PTR_ERR(sdma->clk_ahb);
2031
2032 ret = clk_prepare(sdma->clk_ipg);
2033 if (ret)
2034 return ret;
2035
2036 ret = clk_prepare(sdma->clk_ahb);
2037 if (ret)
2038 goto err_clk;
2039
2040 ret = devm_request_irq(&pdev->dev, irq, sdma_int_handler, 0, "sdma",
2041 sdma);
2042 if (ret)
2043 goto err_irq;
2044
2045 sdma->irq = irq;
2046
2047 sdma->script_addrs = kzalloc(sizeof(*sdma->script_addrs), GFP_KERNEL);
2048 if (!sdma->script_addrs) {
2049 ret = -ENOMEM;
2050 goto err_irq;
2051 }
2052
2053 /* initially no scripts available */
2054 saddr_arr = (s32 *)sdma->script_addrs;
2055 for (i = 0; i < sizeof(*sdma->script_addrs) / sizeof(s32); i++)
2056 saddr_arr[i] = -EINVAL;
2057
2058 dma_cap_set(DMA_SLAVE, sdma->dma_device.cap_mask);
2059 dma_cap_set(DMA_CYCLIC, sdma->dma_device.cap_mask);
2060 dma_cap_set(DMA_MEMCPY, sdma->dma_device.cap_mask);
2061
2062 INIT_LIST_HEAD(&sdma->dma_device.channels);
2063 /* Initialize channel parameters */
2064 for (i = 0; i < MAX_DMA_CHANNELS; i++) {
2065 struct sdma_channel *sdmac = &sdma->channel[i];
2066
2067 sdmac->sdma = sdma;
2068
2069 sdmac->channel = i;
2070 sdmac->vc.desc_free = sdma_desc_free;
2071 INIT_WORK(&sdmac->terminate_worker,
2072 sdma_channel_terminate_work);
2073 /*
2074 * Add the channel to the DMAC list. Do not add channel 0 though
2075 * because we need it internally in the SDMA driver. This also means
2076 * that channel 0 in dmaengine counting matches sdma channel 1.
2077 */
2078 if (i)
2079 vchan_init(&sdmac->vc, &sdma->dma_device);
2080 }
2081
2082 ret = sdma_init(sdma);
2083 if (ret)
2084 goto err_init;
2085
2086 ret = sdma_event_remap(sdma);
2087 if (ret)
2088 goto err_init;
2089
2090 if (sdma->drvdata->script_addrs)
2091 sdma_add_scripts(sdma, sdma->drvdata->script_addrs);
2092 if (pdata && pdata->script_addrs)
2093 sdma_add_scripts(sdma, pdata->script_addrs);
2094
2095 sdma->dma_device.dev = &pdev->dev;
2096
2097 sdma->dma_device.device_alloc_chan_resources = sdma_alloc_chan_resources;
2098 sdma->dma_device.device_free_chan_resources = sdma_free_chan_resources;
2099 sdma->dma_device.device_tx_status = sdma_tx_status;
2100 sdma->dma_device.device_prep_slave_sg = sdma_prep_slave_sg;
2101 sdma->dma_device.device_prep_dma_cyclic = sdma_prep_dma_cyclic;
2102 sdma->dma_device.device_config = sdma_config;
2103 sdma->dma_device.device_terminate_all = sdma_terminate_all;
2104 sdma->dma_device.device_synchronize = sdma_channel_synchronize;
2105 sdma->dma_device.src_addr_widths = SDMA_DMA_BUSWIDTHS;
2106 sdma->dma_device.dst_addr_widths = SDMA_DMA_BUSWIDTHS;
2107 sdma->dma_device.directions = SDMA_DMA_DIRECTIONS;
2108 sdma->dma_device.residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT;
2109 sdma->dma_device.device_prep_dma_memcpy = sdma_prep_memcpy;
2110 sdma->dma_device.device_issue_pending = sdma_issue_pending;
2111 sdma->dma_device.copy_align = 2;
2112 dma_set_max_seg_size(sdma->dma_device.dev, SDMA_BD_MAX_CNT);
2113
2114 platform_set_drvdata(pdev, sdma);
2115
2116 ret = dma_async_device_register(&sdma->dma_device);
2117 if (ret) {
2118 dev_err(&pdev->dev, "unable to register\n");
2119 goto err_init;
2120 }
2121
2122 if (np) {
2123 ret = of_dma_controller_register(np, sdma_xlate, sdma);
2124 if (ret) {
2125 dev_err(&pdev->dev, "failed to register controller\n");
2126 goto err_register;
2127 }
2128
2129 spba_bus = of_find_compatible_node(NULL, NULL, "fsl,spba-bus");
2130 ret = of_address_to_resource(spba_bus, 0, &spba_res);
2131 if (!ret) {
2132 sdma->spba_start_addr = spba_res.start;
2133 sdma->spba_end_addr = spba_res.end;
2134 }
2135 of_node_put(spba_bus);
2136 }
2137
2138 /*
2139 * Kick off firmware loading as the very last step:
2140 * attempt to load firmware only if we're not on the error path, because
2141 * the firmware callback requires a fully functional and allocated sdma
2142 * instance.
2143 */
2144 if (pdata) {
2145 ret = sdma_get_firmware(sdma, pdata->fw_name);
2146 if (ret)
2147 dev_warn(&pdev->dev, "failed to get firmware from platform data\n");
2148 } else {
2149 /*
2150 * Because that device tree does not encode ROM script address,
2151 * the RAM script in firmware is mandatory for device tree
2152 * probe, otherwise it fails.
2153 */
2154 ret = of_property_read_string(np, "fsl,sdma-ram-script-name",
2155 &fw_name);
2156 if (ret) {
2157 dev_warn(&pdev->dev, "failed to get firmware name\n");
2158 } else {
2159 ret = sdma_get_firmware(sdma, fw_name);
2160 if (ret)
2161 dev_warn(&pdev->dev, "failed to get firmware from device tree\n");
2162 }
2163 }
2164
2165 return 0;
2166
2167 err_register:
2168 dma_async_device_unregister(&sdma->dma_device);
2169 err_init:
2170 kfree(sdma->script_addrs);
2171 err_irq:
2172 clk_unprepare(sdma->clk_ahb);
2173 err_clk:
2174 clk_unprepare(sdma->clk_ipg);
2175 return ret;
2176 }
2177
sdma_remove(struct platform_device * pdev)2178 static int sdma_remove(struct platform_device *pdev)
2179 {
2180 struct sdma_engine *sdma = platform_get_drvdata(pdev);
2181 int i;
2182
2183 devm_free_irq(&pdev->dev, sdma->irq, sdma);
2184 dma_async_device_unregister(&sdma->dma_device);
2185 kfree(sdma->script_addrs);
2186 clk_unprepare(sdma->clk_ahb);
2187 clk_unprepare(sdma->clk_ipg);
2188 /* Kill the tasklet */
2189 for (i = 0; i < MAX_DMA_CHANNELS; i++) {
2190 struct sdma_channel *sdmac = &sdma->channel[i];
2191
2192 tasklet_kill(&sdmac->vc.task);
2193 sdma_free_chan_resources(&sdmac->vc.chan);
2194 }
2195
2196 platform_set_drvdata(pdev, NULL);
2197 return 0;
2198 }
2199
2200 static struct platform_driver sdma_driver = {
2201 .driver = {
2202 .name = "imx-sdma",
2203 .of_match_table = sdma_dt_ids,
2204 },
2205 .id_table = sdma_devtypes,
2206 .remove = sdma_remove,
2207 .probe = sdma_probe,
2208 };
2209
2210 module_platform_driver(sdma_driver);
2211
2212 MODULE_AUTHOR("Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>");
2213 MODULE_DESCRIPTION("i.MX SDMA driver");
2214 #if IS_ENABLED(CONFIG_SOC_IMX6Q)
2215 MODULE_FIRMWARE("imx/sdma/sdma-imx6q.bin");
2216 #endif
2217 #if IS_ENABLED(CONFIG_SOC_IMX7D) || IS_ENABLED(CONFIG_SOC_IMX8M)
2218 MODULE_FIRMWARE("imx/sdma/sdma-imx7d.bin");
2219 #endif
2220 MODULE_LICENSE("GPL");
2221