1 /*
2 * Copyright 2017 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include <linux/delay.h>
25 #include <linux/fb.h>
26 #include <linux/module.h>
27 #include <linux/slab.h>
28
29 #include "hwmgr.h"
30 #include "amd_powerplay.h"
31 #include "vega12_smumgr.h"
32 #include "hardwaremanager.h"
33 #include "ppatomfwctrl.h"
34 #include "atomfirmware.h"
35 #include "cgs_common.h"
36 #include "vega12_inc.h"
37 #include "pppcielanes.h"
38 #include "vega12_hwmgr.h"
39 #include "vega12_processpptables.h"
40 #include "vega12_pptable.h"
41 #include "vega12_thermal.h"
42 #include "vega12_ppsmc.h"
43 #include "pp_debug.h"
44 #include "amd_pcie_helpers.h"
45 #include "ppinterrupt.h"
46 #include "pp_overdriver.h"
47 #include "pp_thermal.h"
48 #include "vega12_baco.h"
49
50 #define smnPCIE_LC_SPEED_CNTL 0x11140290
51 #define smnPCIE_LC_LINK_WIDTH_CNTL 0x11140288
52
53 #define LINK_WIDTH_MAX 6
54 #define LINK_SPEED_MAX 3
55 static int link_width[] = {0, 1, 2, 4, 8, 12, 16};
56 static int link_speed[] = {25, 50, 80, 160};
57
58 static int vega12_force_clock_level(struct pp_hwmgr *hwmgr,
59 enum pp_clock_type type, uint32_t mask);
60 static int vega12_get_clock_ranges(struct pp_hwmgr *hwmgr,
61 uint32_t *clock,
62 PPCLK_e clock_select,
63 bool max);
64
vega12_set_default_registry_data(struct pp_hwmgr * hwmgr)65 static void vega12_set_default_registry_data(struct pp_hwmgr *hwmgr)
66 {
67 struct vega12_hwmgr *data =
68 (struct vega12_hwmgr *)(hwmgr->backend);
69
70 data->gfxclk_average_alpha = PPVEGA12_VEGA12GFXCLKAVERAGEALPHA_DFLT;
71 data->socclk_average_alpha = PPVEGA12_VEGA12SOCCLKAVERAGEALPHA_DFLT;
72 data->uclk_average_alpha = PPVEGA12_VEGA12UCLKCLKAVERAGEALPHA_DFLT;
73 data->gfx_activity_average_alpha = PPVEGA12_VEGA12GFXACTIVITYAVERAGEALPHA_DFLT;
74 data->lowest_uclk_reserved_for_ulv = PPVEGA12_VEGA12LOWESTUCLKRESERVEDFORULV_DFLT;
75
76 data->display_voltage_mode = PPVEGA12_VEGA12DISPLAYVOLTAGEMODE_DFLT;
77 data->dcef_clk_quad_eqn_a = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT;
78 data->dcef_clk_quad_eqn_b = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT;
79 data->dcef_clk_quad_eqn_c = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT;
80 data->disp_clk_quad_eqn_a = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT;
81 data->disp_clk_quad_eqn_b = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT;
82 data->disp_clk_quad_eqn_c = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT;
83 data->pixel_clk_quad_eqn_a = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT;
84 data->pixel_clk_quad_eqn_b = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT;
85 data->pixel_clk_quad_eqn_c = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT;
86 data->phy_clk_quad_eqn_a = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT;
87 data->phy_clk_quad_eqn_b = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT;
88 data->phy_clk_quad_eqn_c = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT;
89
90 data->registry_data.disallowed_features = 0x0;
91 data->registry_data.od_state_in_dc_support = 0;
92 data->registry_data.thermal_support = 1;
93 data->registry_data.skip_baco_hardware = 0;
94
95 data->registry_data.log_avfs_param = 0;
96 data->registry_data.sclk_throttle_low_notification = 1;
97 data->registry_data.force_dpm_high = 0;
98 data->registry_data.stable_pstate_sclk_dpm_percentage = 75;
99
100 data->registry_data.didt_support = 0;
101 if (data->registry_data.didt_support) {
102 data->registry_data.didt_mode = 6;
103 data->registry_data.sq_ramping_support = 1;
104 data->registry_data.db_ramping_support = 0;
105 data->registry_data.td_ramping_support = 0;
106 data->registry_data.tcp_ramping_support = 0;
107 data->registry_data.dbr_ramping_support = 0;
108 data->registry_data.edc_didt_support = 1;
109 data->registry_data.gc_didt_support = 0;
110 data->registry_data.psm_didt_support = 0;
111 }
112
113 data->registry_data.pcie_lane_override = 0xff;
114 data->registry_data.pcie_speed_override = 0xff;
115 data->registry_data.pcie_clock_override = 0xffffffff;
116 data->registry_data.regulator_hot_gpio_support = 1;
117 data->registry_data.ac_dc_switch_gpio_support = 0;
118 data->registry_data.quick_transition_support = 0;
119 data->registry_data.zrpm_start_temp = 0xffff;
120 data->registry_data.zrpm_stop_temp = 0xffff;
121 data->registry_data.odn_feature_enable = 1;
122 data->registry_data.disable_water_mark = 0;
123 data->registry_data.disable_pp_tuning = 0;
124 data->registry_data.disable_xlpp_tuning = 0;
125 data->registry_data.disable_workload_policy = 0;
126 data->registry_data.perf_ui_tuning_profile_turbo = 0x19190F0F;
127 data->registry_data.perf_ui_tuning_profile_powerSave = 0x19191919;
128 data->registry_data.perf_ui_tuning_profile_xl = 0x00000F0A;
129 data->registry_data.force_workload_policy_mask = 0;
130 data->registry_data.disable_3d_fs_detection = 0;
131 data->registry_data.fps_support = 1;
132 data->registry_data.disable_auto_wattman = 1;
133 data->registry_data.auto_wattman_debug = 0;
134 data->registry_data.auto_wattman_sample_period = 100;
135 data->registry_data.auto_wattman_threshold = 50;
136 data->registry_data.pcie_dpm_key_disabled = !(hwmgr->feature_mask & PP_PCIE_DPM_MASK);
137 }
138
vega12_set_features_platform_caps(struct pp_hwmgr * hwmgr)139 static int vega12_set_features_platform_caps(struct pp_hwmgr *hwmgr)
140 {
141 struct vega12_hwmgr *data =
142 (struct vega12_hwmgr *)(hwmgr->backend);
143 struct amdgpu_device *adev = hwmgr->adev;
144
145 if (data->vddci_control == VEGA12_VOLTAGE_CONTROL_NONE)
146 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
147 PHM_PlatformCaps_ControlVDDCI);
148
149 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
150 PHM_PlatformCaps_TablelessHardwareInterface);
151
152 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
153 PHM_PlatformCaps_EnableSMU7ThermalManagement);
154
155 if (adev->pg_flags & AMD_PG_SUPPORT_UVD) {
156 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
157 PHM_PlatformCaps_UVDPowerGating);
158 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
159 PHM_PlatformCaps_UVDDynamicPowerGating);
160 }
161
162 if (adev->pg_flags & AMD_PG_SUPPORT_VCE)
163 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
164 PHM_PlatformCaps_VCEPowerGating);
165
166 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
167 PHM_PlatformCaps_UnTabledHardwareInterface);
168
169 if (data->registry_data.odn_feature_enable)
170 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
171 PHM_PlatformCaps_ODNinACSupport);
172 else {
173 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
174 PHM_PlatformCaps_OD6inACSupport);
175 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
176 PHM_PlatformCaps_OD6PlusinACSupport);
177 }
178
179 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
180 PHM_PlatformCaps_ActivityReporting);
181 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
182 PHM_PlatformCaps_FanSpeedInTableIsRPM);
183
184 if (data->registry_data.od_state_in_dc_support) {
185 if (data->registry_data.odn_feature_enable)
186 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
187 PHM_PlatformCaps_ODNinDCSupport);
188 else {
189 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
190 PHM_PlatformCaps_OD6inDCSupport);
191 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
192 PHM_PlatformCaps_OD6PlusinDCSupport);
193 }
194 }
195
196 if (data->registry_data.thermal_support
197 && data->registry_data.fuzzy_fan_control_support
198 && hwmgr->thermal_controller.advanceFanControlParameters.usTMax)
199 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
200 PHM_PlatformCaps_ODFuzzyFanControlSupport);
201
202 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
203 PHM_PlatformCaps_DynamicPowerManagement);
204 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
205 PHM_PlatformCaps_SMC);
206 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
207 PHM_PlatformCaps_ThermalPolicyDelay);
208
209 if (data->registry_data.force_dpm_high)
210 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
211 PHM_PlatformCaps_ExclusiveModeAlwaysHigh);
212
213 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
214 PHM_PlatformCaps_DynamicUVDState);
215
216 if (data->registry_data.sclk_throttle_low_notification)
217 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
218 PHM_PlatformCaps_SclkThrottleLowNotification);
219
220 /* power tune caps */
221 /* assume disabled */
222 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
223 PHM_PlatformCaps_PowerContainment);
224 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
225 PHM_PlatformCaps_DiDtSupport);
226 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
227 PHM_PlatformCaps_SQRamping);
228 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
229 PHM_PlatformCaps_DBRamping);
230 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
231 PHM_PlatformCaps_TDRamping);
232 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
233 PHM_PlatformCaps_TCPRamping);
234 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
235 PHM_PlatformCaps_DBRRamping);
236 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
237 PHM_PlatformCaps_DiDtEDCEnable);
238 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
239 PHM_PlatformCaps_GCEDC);
240 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
241 PHM_PlatformCaps_PSM);
242
243 if (data->registry_data.didt_support) {
244 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DiDtSupport);
245 if (data->registry_data.sq_ramping_support)
246 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SQRamping);
247 if (data->registry_data.db_ramping_support)
248 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DBRamping);
249 if (data->registry_data.td_ramping_support)
250 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TDRamping);
251 if (data->registry_data.tcp_ramping_support)
252 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TCPRamping);
253 if (data->registry_data.dbr_ramping_support)
254 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DBRRamping);
255 if (data->registry_data.edc_didt_support)
256 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DiDtEDCEnable);
257 if (data->registry_data.gc_didt_support)
258 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_GCEDC);
259 if (data->registry_data.psm_didt_support)
260 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PSM);
261 }
262
263 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
264 PHM_PlatformCaps_RegulatorHot);
265
266 if (data->registry_data.ac_dc_switch_gpio_support) {
267 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
268 PHM_PlatformCaps_AutomaticDCTransition);
269 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
270 PHM_PlatformCaps_SMCtoPPLIBAcdcGpioScheme);
271 }
272
273 if (data->registry_data.quick_transition_support) {
274 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
275 PHM_PlatformCaps_AutomaticDCTransition);
276 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
277 PHM_PlatformCaps_SMCtoPPLIBAcdcGpioScheme);
278 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
279 PHM_PlatformCaps_Falcon_QuickTransition);
280 }
281
282 if (data->lowest_uclk_reserved_for_ulv != PPVEGA12_VEGA12LOWESTUCLKRESERVEDFORULV_DFLT) {
283 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
284 PHM_PlatformCaps_LowestUclkReservedForUlv);
285 if (data->lowest_uclk_reserved_for_ulv == 1)
286 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
287 PHM_PlatformCaps_LowestUclkReservedForUlv);
288 }
289
290 if (data->registry_data.custom_fan_support)
291 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
292 PHM_PlatformCaps_CustomFanControlSupport);
293
294 return 0;
295 }
296
vega12_init_dpm_defaults(struct pp_hwmgr * hwmgr)297 static void vega12_init_dpm_defaults(struct pp_hwmgr *hwmgr)
298 {
299 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
300 struct amdgpu_device *adev = hwmgr->adev;
301 uint32_t top32, bottom32;
302 int i;
303
304 data->smu_features[GNLD_DPM_PREFETCHER].smu_feature_id =
305 FEATURE_DPM_PREFETCHER_BIT;
306 data->smu_features[GNLD_DPM_GFXCLK].smu_feature_id =
307 FEATURE_DPM_GFXCLK_BIT;
308 data->smu_features[GNLD_DPM_UCLK].smu_feature_id =
309 FEATURE_DPM_UCLK_BIT;
310 data->smu_features[GNLD_DPM_SOCCLK].smu_feature_id =
311 FEATURE_DPM_SOCCLK_BIT;
312 data->smu_features[GNLD_DPM_UVD].smu_feature_id =
313 FEATURE_DPM_UVD_BIT;
314 data->smu_features[GNLD_DPM_VCE].smu_feature_id =
315 FEATURE_DPM_VCE_BIT;
316 data->smu_features[GNLD_ULV].smu_feature_id =
317 FEATURE_ULV_BIT;
318 data->smu_features[GNLD_DPM_MP0CLK].smu_feature_id =
319 FEATURE_DPM_MP0CLK_BIT;
320 data->smu_features[GNLD_DPM_LINK].smu_feature_id =
321 FEATURE_DPM_LINK_BIT;
322 data->smu_features[GNLD_DPM_DCEFCLK].smu_feature_id =
323 FEATURE_DPM_DCEFCLK_BIT;
324 data->smu_features[GNLD_DS_GFXCLK].smu_feature_id =
325 FEATURE_DS_GFXCLK_BIT;
326 data->smu_features[GNLD_DS_SOCCLK].smu_feature_id =
327 FEATURE_DS_SOCCLK_BIT;
328 data->smu_features[GNLD_DS_LCLK].smu_feature_id =
329 FEATURE_DS_LCLK_BIT;
330 data->smu_features[GNLD_PPT].smu_feature_id =
331 FEATURE_PPT_BIT;
332 data->smu_features[GNLD_TDC].smu_feature_id =
333 FEATURE_TDC_BIT;
334 data->smu_features[GNLD_THERMAL].smu_feature_id =
335 FEATURE_THERMAL_BIT;
336 data->smu_features[GNLD_GFX_PER_CU_CG].smu_feature_id =
337 FEATURE_GFX_PER_CU_CG_BIT;
338 data->smu_features[GNLD_RM].smu_feature_id =
339 FEATURE_RM_BIT;
340 data->smu_features[GNLD_DS_DCEFCLK].smu_feature_id =
341 FEATURE_DS_DCEFCLK_BIT;
342 data->smu_features[GNLD_ACDC].smu_feature_id =
343 FEATURE_ACDC_BIT;
344 data->smu_features[GNLD_VR0HOT].smu_feature_id =
345 FEATURE_VR0HOT_BIT;
346 data->smu_features[GNLD_VR1HOT].smu_feature_id =
347 FEATURE_VR1HOT_BIT;
348 data->smu_features[GNLD_FW_CTF].smu_feature_id =
349 FEATURE_FW_CTF_BIT;
350 data->smu_features[GNLD_LED_DISPLAY].smu_feature_id =
351 FEATURE_LED_DISPLAY_BIT;
352 data->smu_features[GNLD_FAN_CONTROL].smu_feature_id =
353 FEATURE_FAN_CONTROL_BIT;
354 data->smu_features[GNLD_DIDT].smu_feature_id = FEATURE_GFX_EDC_BIT;
355 data->smu_features[GNLD_GFXOFF].smu_feature_id = FEATURE_GFXOFF_BIT;
356 data->smu_features[GNLD_CG].smu_feature_id = FEATURE_CG_BIT;
357 data->smu_features[GNLD_ACG].smu_feature_id = FEATURE_ACG_BIT;
358
359 for (i = 0; i < GNLD_FEATURES_MAX; i++) {
360 data->smu_features[i].smu_feature_bitmap =
361 (uint64_t)(1ULL << data->smu_features[i].smu_feature_id);
362 data->smu_features[i].allowed =
363 ((data->registry_data.disallowed_features >> i) & 1) ?
364 false : true;
365 }
366
367 /* Get the SN to turn into a Unique ID */
368 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumTop32, &top32);
369 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumBottom32, &bottom32);
370
371 adev->unique_id = ((uint64_t)bottom32 << 32) | top32;
372 }
373
vega12_set_private_data_based_on_pptable(struct pp_hwmgr * hwmgr)374 static int vega12_set_private_data_based_on_pptable(struct pp_hwmgr *hwmgr)
375 {
376 return 0;
377 }
378
vega12_hwmgr_backend_fini(struct pp_hwmgr * hwmgr)379 static int vega12_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
380 {
381 kfree(hwmgr->backend);
382 hwmgr->backend = NULL;
383
384 return 0;
385 }
386
vega12_hwmgr_backend_init(struct pp_hwmgr * hwmgr)387 static int vega12_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
388 {
389 int result = 0;
390 struct vega12_hwmgr *data;
391 struct amdgpu_device *adev = hwmgr->adev;
392
393 data = kzalloc(sizeof(struct vega12_hwmgr), GFP_KERNEL);
394 if (data == NULL)
395 return -ENOMEM;
396
397 hwmgr->backend = data;
398
399 vega12_set_default_registry_data(hwmgr);
400
401 data->disable_dpm_mask = 0xff;
402 data->workload_mask = 0xff;
403
404 /* need to set voltage control types before EVV patching */
405 data->vddc_control = VEGA12_VOLTAGE_CONTROL_NONE;
406 data->mvdd_control = VEGA12_VOLTAGE_CONTROL_NONE;
407 data->vddci_control = VEGA12_VOLTAGE_CONTROL_NONE;
408
409 data->water_marks_bitmap = 0;
410 data->avfs_exist = false;
411
412 vega12_set_features_platform_caps(hwmgr);
413
414 vega12_init_dpm_defaults(hwmgr);
415
416 /* Parse pptable data read from VBIOS */
417 vega12_set_private_data_based_on_pptable(hwmgr);
418
419 data->is_tlu_enabled = false;
420
421 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
422 VEGA12_MAX_HARDWARE_POWERLEVELS;
423 hwmgr->platform_descriptor.hardwarePerformanceLevels = 2;
424 hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;
425
426 hwmgr->platform_descriptor.vbiosInterruptId = 0x20000400; /* IRQ_SOURCE1_SW_INT */
427 /* The true clock step depends on the frequency, typically 4.5 or 9 MHz. Here we use 5. */
428 hwmgr->platform_descriptor.clockStep.engineClock = 500;
429 hwmgr->platform_descriptor.clockStep.memoryClock = 500;
430
431 data->total_active_cus = adev->gfx.cu_info.number;
432 /* Setup default Overdrive Fan control settings */
433 data->odn_fan_table.target_fan_speed =
434 hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM;
435 data->odn_fan_table.target_temperature =
436 hwmgr->thermal_controller.advanceFanControlParameters.ucTargetTemperature;
437 data->odn_fan_table.min_performance_clock =
438 hwmgr->thermal_controller.advanceFanControlParameters.ulMinFanSCLKAcousticLimit;
439 data->odn_fan_table.min_fan_limit =
440 hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMMinLimit *
441 hwmgr->thermal_controller.fanInfo.ulMaxRPM / 100;
442
443 if (hwmgr->feature_mask & PP_GFXOFF_MASK)
444 data->gfxoff_controlled_by_driver = true;
445 else
446 data->gfxoff_controlled_by_driver = false;
447
448 return result;
449 }
450
vega12_init_sclk_threshold(struct pp_hwmgr * hwmgr)451 static int vega12_init_sclk_threshold(struct pp_hwmgr *hwmgr)
452 {
453 struct vega12_hwmgr *data =
454 (struct vega12_hwmgr *)(hwmgr->backend);
455
456 data->low_sclk_interrupt_threshold = 0;
457
458 return 0;
459 }
460
vega12_setup_asic_task(struct pp_hwmgr * hwmgr)461 static int vega12_setup_asic_task(struct pp_hwmgr *hwmgr)
462 {
463 PP_ASSERT_WITH_CODE(!vega12_init_sclk_threshold(hwmgr),
464 "Failed to init sclk threshold!",
465 return -EINVAL);
466
467 return 0;
468 }
469
470 /*
471 * @fn vega12_init_dpm_state
472 * @brief Function to initialize all Soft Min/Max and Hard Min/Max to 0xff.
473 *
474 * @param dpm_state - the address of the DPM Table to initiailize.
475 * @return None.
476 */
vega12_init_dpm_state(struct vega12_dpm_state * dpm_state)477 static void vega12_init_dpm_state(struct vega12_dpm_state *dpm_state)
478 {
479 dpm_state->soft_min_level = 0x0;
480 dpm_state->soft_max_level = 0xffff;
481 dpm_state->hard_min_level = 0x0;
482 dpm_state->hard_max_level = 0xffff;
483 }
484
vega12_override_pcie_parameters(struct pp_hwmgr * hwmgr)485 static int vega12_override_pcie_parameters(struct pp_hwmgr *hwmgr)
486 {
487 struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
488 struct vega12_hwmgr *data =
489 (struct vega12_hwmgr *)(hwmgr->backend);
490 uint32_t pcie_gen = 0, pcie_width = 0, smu_pcie_arg, pcie_gen_arg, pcie_width_arg;
491 PPTable_t *pp_table = &(data->smc_state_table.pp_table);
492 int i;
493 int ret;
494
495 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4)
496 pcie_gen = 3;
497 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
498 pcie_gen = 2;
499 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
500 pcie_gen = 1;
501 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1)
502 pcie_gen = 0;
503
504 if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16)
505 pcie_width = 6;
506 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12)
507 pcie_width = 5;
508 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8)
509 pcie_width = 4;
510 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4)
511 pcie_width = 3;
512 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2)
513 pcie_width = 2;
514 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1)
515 pcie_width = 1;
516
517 /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1
518 * Bit 15:8: PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4
519 * Bit 7:0: PCIE lane width, 1 to 7 corresponds is x1 to x32
520 */
521 for (i = 0; i < NUM_LINK_LEVELS; i++) {
522 pcie_gen_arg = (pp_table->PcieGenSpeed[i] > pcie_gen) ? pcie_gen :
523 pp_table->PcieGenSpeed[i];
524 pcie_width_arg = (pp_table->PcieLaneCount[i] > pcie_width) ? pcie_width :
525 pp_table->PcieLaneCount[i];
526
527 if (pcie_gen_arg != pp_table->PcieGenSpeed[i] || pcie_width_arg !=
528 pp_table->PcieLaneCount[i]) {
529 smu_pcie_arg = (i << 16) | (pcie_gen_arg << 8) | pcie_width_arg;
530 ret = smum_send_msg_to_smc_with_parameter(hwmgr,
531 PPSMC_MSG_OverridePcieParameters, smu_pcie_arg,
532 NULL);
533 PP_ASSERT_WITH_CODE(!ret,
534 "[OverridePcieParameters] Attempt to override pcie params failed!",
535 return ret);
536 }
537
538 /* update the pptable */
539 pp_table->PcieGenSpeed[i] = pcie_gen_arg;
540 pp_table->PcieLaneCount[i] = pcie_width_arg;
541 }
542
543 /* override to the highest if it's disabled from ppfeaturmask */
544 if (data->registry_data.pcie_dpm_key_disabled) {
545 for (i = 0; i < NUM_LINK_LEVELS; i++) {
546 smu_pcie_arg = (i << 16) | (pcie_gen << 8) | pcie_width;
547 ret = smum_send_msg_to_smc_with_parameter(hwmgr,
548 PPSMC_MSG_OverridePcieParameters, smu_pcie_arg,
549 NULL);
550 PP_ASSERT_WITH_CODE(!ret,
551 "[OverridePcieParameters] Attempt to override pcie params failed!",
552 return ret);
553
554 pp_table->PcieGenSpeed[i] = pcie_gen;
555 pp_table->PcieLaneCount[i] = pcie_width;
556 }
557 ret = vega12_enable_smc_features(hwmgr,
558 false,
559 data->smu_features[GNLD_DPM_LINK].smu_feature_bitmap);
560 PP_ASSERT_WITH_CODE(!ret,
561 "Attempt to Disable DPM LINK Failed!",
562 return ret);
563 data->smu_features[GNLD_DPM_LINK].enabled = false;
564 data->smu_features[GNLD_DPM_LINK].supported = false;
565 }
566 return 0;
567 }
568
vega12_get_number_of_dpm_level(struct pp_hwmgr * hwmgr,PPCLK_e clk_id,uint32_t * num_of_levels)569 static int vega12_get_number_of_dpm_level(struct pp_hwmgr *hwmgr,
570 PPCLK_e clk_id, uint32_t *num_of_levels)
571 {
572 int ret = 0;
573
574 ret = smum_send_msg_to_smc_with_parameter(hwmgr,
575 PPSMC_MSG_GetDpmFreqByIndex,
576 (clk_id << 16 | 0xFF),
577 num_of_levels);
578 PP_ASSERT_WITH_CODE(!ret,
579 "[GetNumOfDpmLevel] failed to get dpm levels!",
580 return ret);
581
582 return ret;
583 }
584
vega12_get_dpm_frequency_by_index(struct pp_hwmgr * hwmgr,PPCLK_e clkID,uint32_t index,uint32_t * clock)585 static int vega12_get_dpm_frequency_by_index(struct pp_hwmgr *hwmgr,
586 PPCLK_e clkID, uint32_t index, uint32_t *clock)
587 {
588 /*
589 *SMU expects the Clock ID to be in the top 16 bits.
590 *Lower 16 bits specify the level
591 */
592 PP_ASSERT_WITH_CODE(smum_send_msg_to_smc_with_parameter(hwmgr,
593 PPSMC_MSG_GetDpmFreqByIndex, (clkID << 16 | index),
594 clock) == 0,
595 "[GetDpmFrequencyByIndex] Failed to get dpm frequency from SMU!",
596 return -EINVAL);
597
598 return 0;
599 }
600
vega12_setup_single_dpm_table(struct pp_hwmgr * hwmgr,struct vega12_single_dpm_table * dpm_table,PPCLK_e clk_id)601 static int vega12_setup_single_dpm_table(struct pp_hwmgr *hwmgr,
602 struct vega12_single_dpm_table *dpm_table, PPCLK_e clk_id)
603 {
604 int ret = 0;
605 uint32_t i, num_of_levels, clk;
606
607 ret = vega12_get_number_of_dpm_level(hwmgr, clk_id, &num_of_levels);
608 PP_ASSERT_WITH_CODE(!ret,
609 "[SetupSingleDpmTable] failed to get clk levels!",
610 return ret);
611
612 dpm_table->count = num_of_levels;
613
614 for (i = 0; i < num_of_levels; i++) {
615 ret = vega12_get_dpm_frequency_by_index(hwmgr, clk_id, i, &clk);
616 PP_ASSERT_WITH_CODE(!ret,
617 "[SetupSingleDpmTable] failed to get clk of specific level!",
618 return ret);
619 dpm_table->dpm_levels[i].value = clk;
620 dpm_table->dpm_levels[i].enabled = true;
621 }
622
623 return ret;
624 }
625
626 /*
627 * This function is to initialize all DPM state tables
628 * for SMU based on the dependency table.
629 * Dynamic state patching function will then trim these
630 * state tables to the allowed range based
631 * on the power policy or external client requests,
632 * such as UVD request, etc.
633 */
vega12_setup_default_dpm_tables(struct pp_hwmgr * hwmgr)634 static int vega12_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
635 {
636
637 struct vega12_hwmgr *data =
638 (struct vega12_hwmgr *)(hwmgr->backend);
639 struct vega12_single_dpm_table *dpm_table;
640 int ret = 0;
641
642 memset(&data->dpm_table, 0, sizeof(data->dpm_table));
643
644 /* socclk */
645 dpm_table = &(data->dpm_table.soc_table);
646 if (data->smu_features[GNLD_DPM_SOCCLK].enabled) {
647 ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_SOCCLK);
648 PP_ASSERT_WITH_CODE(!ret,
649 "[SetupDefaultDpmTable] failed to get socclk dpm levels!",
650 return ret);
651 } else {
652 dpm_table->count = 1;
653 dpm_table->dpm_levels[0].value = data->vbios_boot_state.soc_clock / 100;
654 }
655 vega12_init_dpm_state(&(dpm_table->dpm_state));
656
657 /* gfxclk */
658 dpm_table = &(data->dpm_table.gfx_table);
659 if (data->smu_features[GNLD_DPM_GFXCLK].enabled) {
660 ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_GFXCLK);
661 PP_ASSERT_WITH_CODE(!ret,
662 "[SetupDefaultDpmTable] failed to get gfxclk dpm levels!",
663 return ret);
664 } else {
665 dpm_table->count = 1;
666 dpm_table->dpm_levels[0].value = data->vbios_boot_state.gfx_clock / 100;
667 }
668 vega12_init_dpm_state(&(dpm_table->dpm_state));
669
670 /* memclk */
671 dpm_table = &(data->dpm_table.mem_table);
672 if (data->smu_features[GNLD_DPM_UCLK].enabled) {
673 ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_UCLK);
674 PP_ASSERT_WITH_CODE(!ret,
675 "[SetupDefaultDpmTable] failed to get memclk dpm levels!",
676 return ret);
677 } else {
678 dpm_table->count = 1;
679 dpm_table->dpm_levels[0].value = data->vbios_boot_state.mem_clock / 100;
680 }
681 vega12_init_dpm_state(&(dpm_table->dpm_state));
682
683 /* eclk */
684 dpm_table = &(data->dpm_table.eclk_table);
685 if (data->smu_features[GNLD_DPM_VCE].enabled) {
686 ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_ECLK);
687 PP_ASSERT_WITH_CODE(!ret,
688 "[SetupDefaultDpmTable] failed to get eclk dpm levels!",
689 return ret);
690 } else {
691 dpm_table->count = 1;
692 dpm_table->dpm_levels[0].value = data->vbios_boot_state.eclock / 100;
693 }
694 vega12_init_dpm_state(&(dpm_table->dpm_state));
695
696 /* vclk */
697 dpm_table = &(data->dpm_table.vclk_table);
698 if (data->smu_features[GNLD_DPM_UVD].enabled) {
699 ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_VCLK);
700 PP_ASSERT_WITH_CODE(!ret,
701 "[SetupDefaultDpmTable] failed to get vclk dpm levels!",
702 return ret);
703 } else {
704 dpm_table->count = 1;
705 dpm_table->dpm_levels[0].value = data->vbios_boot_state.vclock / 100;
706 }
707 vega12_init_dpm_state(&(dpm_table->dpm_state));
708
709 /* dclk */
710 dpm_table = &(data->dpm_table.dclk_table);
711 if (data->smu_features[GNLD_DPM_UVD].enabled) {
712 ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_DCLK);
713 PP_ASSERT_WITH_CODE(!ret,
714 "[SetupDefaultDpmTable] failed to get dclk dpm levels!",
715 return ret);
716 } else {
717 dpm_table->count = 1;
718 dpm_table->dpm_levels[0].value = data->vbios_boot_state.dclock / 100;
719 }
720 vega12_init_dpm_state(&(dpm_table->dpm_state));
721
722 /* dcefclk */
723 dpm_table = &(data->dpm_table.dcef_table);
724 if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
725 ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_DCEFCLK);
726 PP_ASSERT_WITH_CODE(!ret,
727 "[SetupDefaultDpmTable] failed to get dcefclk dpm levels!",
728 return ret);
729 } else {
730 dpm_table->count = 1;
731 dpm_table->dpm_levels[0].value = data->vbios_boot_state.dcef_clock / 100;
732 }
733 vega12_init_dpm_state(&(dpm_table->dpm_state));
734
735 /* pixclk */
736 dpm_table = &(data->dpm_table.pixel_table);
737 if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
738 ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_PIXCLK);
739 PP_ASSERT_WITH_CODE(!ret,
740 "[SetupDefaultDpmTable] failed to get pixclk dpm levels!",
741 return ret);
742 } else
743 dpm_table->count = 0;
744 vega12_init_dpm_state(&(dpm_table->dpm_state));
745
746 /* dispclk */
747 dpm_table = &(data->dpm_table.display_table);
748 if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
749 ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_DISPCLK);
750 PP_ASSERT_WITH_CODE(!ret,
751 "[SetupDefaultDpmTable] failed to get dispclk dpm levels!",
752 return ret);
753 } else
754 dpm_table->count = 0;
755 vega12_init_dpm_state(&(dpm_table->dpm_state));
756
757 /* phyclk */
758 dpm_table = &(data->dpm_table.phy_table);
759 if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
760 ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_PHYCLK);
761 PP_ASSERT_WITH_CODE(!ret,
762 "[SetupDefaultDpmTable] failed to get phyclk dpm levels!",
763 return ret);
764 } else
765 dpm_table->count = 0;
766 vega12_init_dpm_state(&(dpm_table->dpm_state));
767
768 /* save a copy of the default DPM table */
769 memcpy(&(data->golden_dpm_table), &(data->dpm_table),
770 sizeof(struct vega12_dpm_table));
771
772 return 0;
773 }
774
775 #if 0
776 static int vega12_save_default_power_profile(struct pp_hwmgr *hwmgr)
777 {
778 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
779 struct vega12_single_dpm_table *dpm_table = &(data->dpm_table.gfx_table);
780 uint32_t min_level;
781
782 hwmgr->default_gfx_power_profile.type = AMD_PP_GFX_PROFILE;
783 hwmgr->default_compute_power_profile.type = AMD_PP_COMPUTE_PROFILE;
784
785 /* Optimize compute power profile: Use only highest
786 * 2 power levels (if more than 2 are available)
787 */
788 if (dpm_table->count > 2)
789 min_level = dpm_table->count - 2;
790 else if (dpm_table->count == 2)
791 min_level = 1;
792 else
793 min_level = 0;
794
795 hwmgr->default_compute_power_profile.min_sclk =
796 dpm_table->dpm_levels[min_level].value;
797
798 hwmgr->gfx_power_profile = hwmgr->default_gfx_power_profile;
799 hwmgr->compute_power_profile = hwmgr->default_compute_power_profile;
800
801 return 0;
802 }
803 #endif
804
805 /**
806 * Initializes the SMC table and uploads it
807 *
808 * @param hwmgr the address of the powerplay hardware manager.
809 * @param pInput the pointer to input data (PowerState)
810 * @return always 0
811 */
vega12_init_smc_table(struct pp_hwmgr * hwmgr)812 static int vega12_init_smc_table(struct pp_hwmgr *hwmgr)
813 {
814 int result;
815 struct vega12_hwmgr *data =
816 (struct vega12_hwmgr *)(hwmgr->backend);
817 PPTable_t *pp_table = &(data->smc_state_table.pp_table);
818 struct pp_atomfwctrl_bios_boot_up_values boot_up_values;
819 struct phm_ppt_v3_information *pptable_information =
820 (struct phm_ppt_v3_information *)hwmgr->pptable;
821
822 result = pp_atomfwctrl_get_vbios_bootup_values(hwmgr, &boot_up_values);
823 if (!result) {
824 data->vbios_boot_state.vddc = boot_up_values.usVddc;
825 data->vbios_boot_state.vddci = boot_up_values.usVddci;
826 data->vbios_boot_state.mvddc = boot_up_values.usMvddc;
827 data->vbios_boot_state.gfx_clock = boot_up_values.ulGfxClk;
828 data->vbios_boot_state.mem_clock = boot_up_values.ulUClk;
829 data->vbios_boot_state.soc_clock = boot_up_values.ulSocClk;
830 data->vbios_boot_state.dcef_clock = boot_up_values.ulDCEFClk;
831 data->vbios_boot_state.uc_cooling_id = boot_up_values.ucCoolingID;
832 data->vbios_boot_state.eclock = boot_up_values.ulEClk;
833 data->vbios_boot_state.dclock = boot_up_values.ulDClk;
834 data->vbios_boot_state.vclock = boot_up_values.ulVClk;
835 smum_send_msg_to_smc_with_parameter(hwmgr,
836 PPSMC_MSG_SetMinDeepSleepDcefclk,
837 (uint32_t)(data->vbios_boot_state.dcef_clock / 100),
838 NULL);
839 }
840
841 memcpy(pp_table, pptable_information->smc_pptable, sizeof(PPTable_t));
842
843 result = smum_smc_table_manager(hwmgr,
844 (uint8_t *)pp_table, TABLE_PPTABLE, false);
845 PP_ASSERT_WITH_CODE(!result,
846 "Failed to upload PPtable!", return result);
847
848 return 0;
849 }
850
vega12_run_acg_btc(struct pp_hwmgr * hwmgr)851 static int vega12_run_acg_btc(struct pp_hwmgr *hwmgr)
852 {
853 uint32_t result;
854
855 PP_ASSERT_WITH_CODE(
856 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_RunAcgBtc, &result) == 0,
857 "[Run_ACG_BTC] Attempt to run ACG BTC failed!",
858 return -EINVAL);
859
860 PP_ASSERT_WITH_CODE(result == 1,
861 "Failed to run ACG BTC!", return -EINVAL);
862
863 return 0;
864 }
865
vega12_set_allowed_featuresmask(struct pp_hwmgr * hwmgr)866 static int vega12_set_allowed_featuresmask(struct pp_hwmgr *hwmgr)
867 {
868 struct vega12_hwmgr *data =
869 (struct vega12_hwmgr *)(hwmgr->backend);
870 int i;
871 uint32_t allowed_features_low = 0, allowed_features_high = 0;
872
873 for (i = 0; i < GNLD_FEATURES_MAX; i++)
874 if (data->smu_features[i].allowed)
875 data->smu_features[i].smu_feature_id > 31 ?
876 (allowed_features_high |= ((data->smu_features[i].smu_feature_bitmap >> SMU_FEATURES_HIGH_SHIFT) & 0xFFFFFFFF)) :
877 (allowed_features_low |= ((data->smu_features[i].smu_feature_bitmap >> SMU_FEATURES_LOW_SHIFT) & 0xFFFFFFFF));
878
879 PP_ASSERT_WITH_CODE(
880 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetAllowedFeaturesMaskHigh, allowed_features_high,
881 NULL) == 0,
882 "[SetAllowedFeaturesMask] Attempt to set allowed features mask (high) failed!",
883 return -1);
884
885 PP_ASSERT_WITH_CODE(
886 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetAllowedFeaturesMaskLow, allowed_features_low,
887 NULL) == 0,
888 "[SetAllowedFeaturesMask] Attempt to set allowed features mask (low) failed!",
889 return -1);
890
891 return 0;
892 }
893
vega12_init_powergate_state(struct pp_hwmgr * hwmgr)894 static void vega12_init_powergate_state(struct pp_hwmgr *hwmgr)
895 {
896 struct vega12_hwmgr *data =
897 (struct vega12_hwmgr *)(hwmgr->backend);
898
899 data->uvd_power_gated = true;
900 data->vce_power_gated = true;
901
902 if (data->smu_features[GNLD_DPM_UVD].enabled)
903 data->uvd_power_gated = false;
904
905 if (data->smu_features[GNLD_DPM_VCE].enabled)
906 data->vce_power_gated = false;
907 }
908
vega12_enable_all_smu_features(struct pp_hwmgr * hwmgr)909 static int vega12_enable_all_smu_features(struct pp_hwmgr *hwmgr)
910 {
911 struct vega12_hwmgr *data =
912 (struct vega12_hwmgr *)(hwmgr->backend);
913 uint64_t features_enabled;
914 int i;
915 bool enabled;
916
917 PP_ASSERT_WITH_CODE(
918 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_EnableAllSmuFeatures, NULL) == 0,
919 "[EnableAllSMUFeatures] Failed to enable all smu features!",
920 return -1);
921
922 if (vega12_get_enabled_smc_features(hwmgr, &features_enabled) == 0) {
923 for (i = 0; i < GNLD_FEATURES_MAX; i++) {
924 enabled = (features_enabled & data->smu_features[i].smu_feature_bitmap) ? true : false;
925 data->smu_features[i].enabled = enabled;
926 data->smu_features[i].supported = enabled;
927 }
928 }
929
930 vega12_init_powergate_state(hwmgr);
931
932 return 0;
933 }
934
vega12_disable_all_smu_features(struct pp_hwmgr * hwmgr)935 static int vega12_disable_all_smu_features(struct pp_hwmgr *hwmgr)
936 {
937 struct vega12_hwmgr *data =
938 (struct vega12_hwmgr *)(hwmgr->backend);
939 uint64_t features_enabled;
940 int i;
941 bool enabled;
942
943 PP_ASSERT_WITH_CODE(
944 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DisableAllSmuFeatures, NULL) == 0,
945 "[DisableAllSMUFeatures] Failed to disable all smu features!",
946 return -1);
947
948 if (vega12_get_enabled_smc_features(hwmgr, &features_enabled) == 0) {
949 for (i = 0; i < GNLD_FEATURES_MAX; i++) {
950 enabled = (features_enabled & data->smu_features[i].smu_feature_bitmap) ? true : false;
951 data->smu_features[i].enabled = enabled;
952 data->smu_features[i].supported = enabled;
953 }
954 }
955
956 return 0;
957 }
958
vega12_odn_initialize_default_settings(struct pp_hwmgr * hwmgr)959 static int vega12_odn_initialize_default_settings(
960 struct pp_hwmgr *hwmgr)
961 {
962 return 0;
963 }
964
vega12_set_overdrive_target_percentage(struct pp_hwmgr * hwmgr,uint32_t adjust_percent)965 static int vega12_set_overdrive_target_percentage(struct pp_hwmgr *hwmgr,
966 uint32_t adjust_percent)
967 {
968 return smum_send_msg_to_smc_with_parameter(hwmgr,
969 PPSMC_MSG_OverDriveSetPercentage, adjust_percent,
970 NULL);
971 }
972
vega12_power_control_set_level(struct pp_hwmgr * hwmgr)973 static int vega12_power_control_set_level(struct pp_hwmgr *hwmgr)
974 {
975 int adjust_percent, result = 0;
976
977 if (PP_CAP(PHM_PlatformCaps_PowerContainment)) {
978 adjust_percent =
979 hwmgr->platform_descriptor.TDPAdjustmentPolarity ?
980 hwmgr->platform_descriptor.TDPAdjustment :
981 (-1 * hwmgr->platform_descriptor.TDPAdjustment);
982 result = vega12_set_overdrive_target_percentage(hwmgr,
983 (uint32_t)adjust_percent);
984 }
985 return result;
986 }
987
vega12_get_all_clock_ranges_helper(struct pp_hwmgr * hwmgr,PPCLK_e clkid,struct vega12_clock_range * clock)988 static int vega12_get_all_clock_ranges_helper(struct pp_hwmgr *hwmgr,
989 PPCLK_e clkid, struct vega12_clock_range *clock)
990 {
991 /* AC Max */
992 PP_ASSERT_WITH_CODE(
993 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetMaxDpmFreq, (clkid << 16),
994 &(clock->ACMax)) == 0,
995 "[GetClockRanges] Failed to get max ac clock from SMC!",
996 return -EINVAL);
997
998 /* AC Min */
999 PP_ASSERT_WITH_CODE(
1000 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetMinDpmFreq, (clkid << 16),
1001 &(clock->ACMin)) == 0,
1002 "[GetClockRanges] Failed to get min ac clock from SMC!",
1003 return -EINVAL);
1004
1005 /* DC Max */
1006 PP_ASSERT_WITH_CODE(
1007 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetDcModeMaxDpmFreq, (clkid << 16),
1008 &(clock->DCMax)) == 0,
1009 "[GetClockRanges] Failed to get max dc clock from SMC!",
1010 return -EINVAL);
1011
1012 return 0;
1013 }
1014
vega12_get_all_clock_ranges(struct pp_hwmgr * hwmgr)1015 static int vega12_get_all_clock_ranges(struct pp_hwmgr *hwmgr)
1016 {
1017 struct vega12_hwmgr *data =
1018 (struct vega12_hwmgr *)(hwmgr->backend);
1019 uint32_t i;
1020
1021 for (i = 0; i < PPCLK_COUNT; i++)
1022 PP_ASSERT_WITH_CODE(!vega12_get_all_clock_ranges_helper(hwmgr,
1023 i, &(data->clk_range[i])),
1024 "Failed to get clk range from SMC!",
1025 return -EINVAL);
1026
1027 return 0;
1028 }
1029
vega12_enable_dpm_tasks(struct pp_hwmgr * hwmgr)1030 static int vega12_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
1031 {
1032 int tmp_result, result = 0;
1033
1034 smum_send_msg_to_smc_with_parameter(hwmgr,
1035 PPSMC_MSG_NumOfDisplays, 0, NULL);
1036
1037 result = vega12_set_allowed_featuresmask(hwmgr);
1038 PP_ASSERT_WITH_CODE(result == 0,
1039 "[EnableDPMTasks] Failed to set allowed featuresmask!\n",
1040 return result);
1041
1042 tmp_result = vega12_init_smc_table(hwmgr);
1043 PP_ASSERT_WITH_CODE(!tmp_result,
1044 "Failed to initialize SMC table!",
1045 result = tmp_result);
1046
1047 tmp_result = vega12_run_acg_btc(hwmgr);
1048 PP_ASSERT_WITH_CODE(!tmp_result,
1049 "Failed to run ACG BTC!",
1050 result = tmp_result);
1051
1052 result = vega12_enable_all_smu_features(hwmgr);
1053 PP_ASSERT_WITH_CODE(!result,
1054 "Failed to enable all smu features!",
1055 return result);
1056
1057 result = vega12_override_pcie_parameters(hwmgr);
1058 PP_ASSERT_WITH_CODE(!result,
1059 "[EnableDPMTasks] Failed to override pcie parameters!",
1060 return result);
1061
1062 tmp_result = vega12_power_control_set_level(hwmgr);
1063 PP_ASSERT_WITH_CODE(!tmp_result,
1064 "Failed to power control set level!",
1065 result = tmp_result);
1066
1067 result = vega12_get_all_clock_ranges(hwmgr);
1068 PP_ASSERT_WITH_CODE(!result,
1069 "Failed to get all clock ranges!",
1070 return result);
1071
1072 result = vega12_odn_initialize_default_settings(hwmgr);
1073 PP_ASSERT_WITH_CODE(!result,
1074 "Failed to power control set level!",
1075 return result);
1076
1077 result = vega12_setup_default_dpm_tables(hwmgr);
1078 PP_ASSERT_WITH_CODE(!result,
1079 "Failed to setup default DPM tables!",
1080 return result);
1081 return result;
1082 }
1083
vega12_patch_boot_state(struct pp_hwmgr * hwmgr,struct pp_hw_power_state * hw_ps)1084 static int vega12_patch_boot_state(struct pp_hwmgr *hwmgr,
1085 struct pp_hw_power_state *hw_ps)
1086 {
1087 return 0;
1088 }
1089
vega12_find_lowest_dpm_level(struct vega12_single_dpm_table * table)1090 static uint32_t vega12_find_lowest_dpm_level(
1091 struct vega12_single_dpm_table *table)
1092 {
1093 uint32_t i;
1094
1095 for (i = 0; i < table->count; i++) {
1096 if (table->dpm_levels[i].enabled)
1097 break;
1098 }
1099
1100 if (i >= table->count) {
1101 i = 0;
1102 table->dpm_levels[i].enabled = true;
1103 }
1104
1105 return i;
1106 }
1107
vega12_find_highest_dpm_level(struct vega12_single_dpm_table * table)1108 static uint32_t vega12_find_highest_dpm_level(
1109 struct vega12_single_dpm_table *table)
1110 {
1111 int32_t i = 0;
1112 PP_ASSERT_WITH_CODE(table->count <= MAX_REGULAR_DPM_NUMBER,
1113 "[FindHighestDPMLevel] DPM Table has too many entries!",
1114 return MAX_REGULAR_DPM_NUMBER - 1);
1115
1116 for (i = table->count - 1; i >= 0; i--) {
1117 if (table->dpm_levels[i].enabled)
1118 break;
1119 }
1120
1121 if (i < 0) {
1122 i = 0;
1123 table->dpm_levels[i].enabled = true;
1124 }
1125
1126 return (uint32_t)i;
1127 }
1128
vega12_upload_dpm_min_level(struct pp_hwmgr * hwmgr)1129 static int vega12_upload_dpm_min_level(struct pp_hwmgr *hwmgr)
1130 {
1131 struct vega12_hwmgr *data = hwmgr->backend;
1132 uint32_t min_freq;
1133 int ret = 0;
1134
1135 if (data->smu_features[GNLD_DPM_GFXCLK].enabled) {
1136 min_freq = data->dpm_table.gfx_table.dpm_state.soft_min_level;
1137 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1138 hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1139 (PPCLK_GFXCLK << 16) | (min_freq & 0xffff),
1140 NULL)),
1141 "Failed to set soft min gfxclk !",
1142 return ret);
1143 }
1144
1145 if (data->smu_features[GNLD_DPM_UCLK].enabled) {
1146 min_freq = data->dpm_table.mem_table.dpm_state.soft_min_level;
1147 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1148 hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1149 (PPCLK_UCLK << 16) | (min_freq & 0xffff),
1150 NULL)),
1151 "Failed to set soft min memclk !",
1152 return ret);
1153
1154 min_freq = data->dpm_table.mem_table.dpm_state.hard_min_level;
1155 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1156 hwmgr, PPSMC_MSG_SetHardMinByFreq,
1157 (PPCLK_UCLK << 16) | (min_freq & 0xffff),
1158 NULL)),
1159 "Failed to set hard min memclk !",
1160 return ret);
1161 }
1162
1163 if (data->smu_features[GNLD_DPM_UVD].enabled) {
1164 min_freq = data->dpm_table.vclk_table.dpm_state.soft_min_level;
1165
1166 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1167 hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1168 (PPCLK_VCLK << 16) | (min_freq & 0xffff),
1169 NULL)),
1170 "Failed to set soft min vclk!",
1171 return ret);
1172
1173 min_freq = data->dpm_table.dclk_table.dpm_state.soft_min_level;
1174
1175 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1176 hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1177 (PPCLK_DCLK << 16) | (min_freq & 0xffff),
1178 NULL)),
1179 "Failed to set soft min dclk!",
1180 return ret);
1181 }
1182
1183 if (data->smu_features[GNLD_DPM_VCE].enabled) {
1184 min_freq = data->dpm_table.eclk_table.dpm_state.soft_min_level;
1185
1186 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1187 hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1188 (PPCLK_ECLK << 16) | (min_freq & 0xffff),
1189 NULL)),
1190 "Failed to set soft min eclk!",
1191 return ret);
1192 }
1193
1194 if (data->smu_features[GNLD_DPM_SOCCLK].enabled) {
1195 min_freq = data->dpm_table.soc_table.dpm_state.soft_min_level;
1196
1197 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1198 hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1199 (PPCLK_SOCCLK << 16) | (min_freq & 0xffff),
1200 NULL)),
1201 "Failed to set soft min socclk!",
1202 return ret);
1203 }
1204
1205 if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
1206 min_freq = data->dpm_table.dcef_table.dpm_state.hard_min_level;
1207
1208 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1209 hwmgr, PPSMC_MSG_SetHardMinByFreq,
1210 (PPCLK_DCEFCLK << 16) | (min_freq & 0xffff),
1211 NULL)),
1212 "Failed to set hard min dcefclk!",
1213 return ret);
1214 }
1215
1216 return ret;
1217
1218 }
1219
vega12_upload_dpm_max_level(struct pp_hwmgr * hwmgr)1220 static int vega12_upload_dpm_max_level(struct pp_hwmgr *hwmgr)
1221 {
1222 struct vega12_hwmgr *data = hwmgr->backend;
1223 uint32_t max_freq;
1224 int ret = 0;
1225
1226 if (data->smu_features[GNLD_DPM_GFXCLK].enabled) {
1227 max_freq = data->dpm_table.gfx_table.dpm_state.soft_max_level;
1228
1229 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1230 hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1231 (PPCLK_GFXCLK << 16) | (max_freq & 0xffff),
1232 NULL)),
1233 "Failed to set soft max gfxclk!",
1234 return ret);
1235 }
1236
1237 if (data->smu_features[GNLD_DPM_UCLK].enabled) {
1238 max_freq = data->dpm_table.mem_table.dpm_state.soft_max_level;
1239
1240 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1241 hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1242 (PPCLK_UCLK << 16) | (max_freq & 0xffff),
1243 NULL)),
1244 "Failed to set soft max memclk!",
1245 return ret);
1246 }
1247
1248 if (data->smu_features[GNLD_DPM_UVD].enabled) {
1249 max_freq = data->dpm_table.vclk_table.dpm_state.soft_max_level;
1250
1251 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1252 hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1253 (PPCLK_VCLK << 16) | (max_freq & 0xffff),
1254 NULL)),
1255 "Failed to set soft max vclk!",
1256 return ret);
1257
1258 max_freq = data->dpm_table.dclk_table.dpm_state.soft_max_level;
1259 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1260 hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1261 (PPCLK_DCLK << 16) | (max_freq & 0xffff),
1262 NULL)),
1263 "Failed to set soft max dclk!",
1264 return ret);
1265 }
1266
1267 if (data->smu_features[GNLD_DPM_VCE].enabled) {
1268 max_freq = data->dpm_table.eclk_table.dpm_state.soft_max_level;
1269
1270 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1271 hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1272 (PPCLK_ECLK << 16) | (max_freq & 0xffff),
1273 NULL)),
1274 "Failed to set soft max eclk!",
1275 return ret);
1276 }
1277
1278 if (data->smu_features[GNLD_DPM_SOCCLK].enabled) {
1279 max_freq = data->dpm_table.soc_table.dpm_state.soft_max_level;
1280
1281 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1282 hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1283 (PPCLK_SOCCLK << 16) | (max_freq & 0xffff),
1284 NULL)),
1285 "Failed to set soft max socclk!",
1286 return ret);
1287 }
1288
1289 return ret;
1290 }
1291
vega12_enable_disable_vce_dpm(struct pp_hwmgr * hwmgr,bool enable)1292 int vega12_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
1293 {
1294 struct vega12_hwmgr *data =
1295 (struct vega12_hwmgr *)(hwmgr->backend);
1296
1297 if (data->smu_features[GNLD_DPM_VCE].supported) {
1298 PP_ASSERT_WITH_CODE(!vega12_enable_smc_features(hwmgr,
1299 enable,
1300 data->smu_features[GNLD_DPM_VCE].smu_feature_bitmap),
1301 "Attempt to Enable/Disable DPM VCE Failed!",
1302 return -1);
1303 data->smu_features[GNLD_DPM_VCE].enabled = enable;
1304 }
1305
1306 return 0;
1307 }
1308
vega12_dpm_get_sclk(struct pp_hwmgr * hwmgr,bool low)1309 static uint32_t vega12_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
1310 {
1311 struct vega12_hwmgr *data =
1312 (struct vega12_hwmgr *)(hwmgr->backend);
1313 uint32_t gfx_clk;
1314
1315 if (!data->smu_features[GNLD_DPM_GFXCLK].enabled)
1316 return -1;
1317
1318 if (low)
1319 PP_ASSERT_WITH_CODE(
1320 vega12_get_clock_ranges(hwmgr, &gfx_clk, PPCLK_GFXCLK, false) == 0,
1321 "[GetSclks]: fail to get min PPCLK_GFXCLK\n",
1322 return -1);
1323 else
1324 PP_ASSERT_WITH_CODE(
1325 vega12_get_clock_ranges(hwmgr, &gfx_clk, PPCLK_GFXCLK, true) == 0,
1326 "[GetSclks]: fail to get max PPCLK_GFXCLK\n",
1327 return -1);
1328
1329 return (gfx_clk * 100);
1330 }
1331
vega12_dpm_get_mclk(struct pp_hwmgr * hwmgr,bool low)1332 static uint32_t vega12_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
1333 {
1334 struct vega12_hwmgr *data =
1335 (struct vega12_hwmgr *)(hwmgr->backend);
1336 uint32_t mem_clk;
1337
1338 if (!data->smu_features[GNLD_DPM_UCLK].enabled)
1339 return -1;
1340
1341 if (low)
1342 PP_ASSERT_WITH_CODE(
1343 vega12_get_clock_ranges(hwmgr, &mem_clk, PPCLK_UCLK, false) == 0,
1344 "[GetMclks]: fail to get min PPCLK_UCLK\n",
1345 return -1);
1346 else
1347 PP_ASSERT_WITH_CODE(
1348 vega12_get_clock_ranges(hwmgr, &mem_clk, PPCLK_UCLK, true) == 0,
1349 "[GetMclks]: fail to get max PPCLK_UCLK\n",
1350 return -1);
1351
1352 return (mem_clk * 100);
1353 }
1354
vega12_get_metrics_table(struct pp_hwmgr * hwmgr,SmuMetrics_t * metrics_table,bool bypass_cache)1355 static int vega12_get_metrics_table(struct pp_hwmgr *hwmgr,
1356 SmuMetrics_t *metrics_table,
1357 bool bypass_cache)
1358 {
1359 struct vega12_hwmgr *data =
1360 (struct vega12_hwmgr *)(hwmgr->backend);
1361 int ret = 0;
1362
1363 if (bypass_cache ||
1364 !data->metrics_time ||
1365 time_after(jiffies, data->metrics_time + msecs_to_jiffies(1))) {
1366 ret = smum_smc_table_manager(hwmgr,
1367 (uint8_t *)(&data->metrics_table),
1368 TABLE_SMU_METRICS,
1369 true);
1370 if (ret) {
1371 pr_info("Failed to export SMU metrics table!\n");
1372 return ret;
1373 }
1374 data->metrics_time = jiffies;
1375 }
1376
1377 if (metrics_table)
1378 memcpy(metrics_table, &data->metrics_table, sizeof(SmuMetrics_t));
1379
1380 return ret;
1381 }
1382
vega12_get_gpu_power(struct pp_hwmgr * hwmgr,uint32_t * query)1383 static int vega12_get_gpu_power(struct pp_hwmgr *hwmgr, uint32_t *query)
1384 {
1385 SmuMetrics_t metrics_table;
1386 int ret = 0;
1387
1388 ret = vega12_get_metrics_table(hwmgr, &metrics_table, false);
1389 if (ret)
1390 return ret;
1391
1392 *query = metrics_table.CurrSocketPower << 8;
1393
1394 return ret;
1395 }
1396
vega12_get_current_gfx_clk_freq(struct pp_hwmgr * hwmgr,uint32_t * gfx_freq)1397 static int vega12_get_current_gfx_clk_freq(struct pp_hwmgr *hwmgr, uint32_t *gfx_freq)
1398 {
1399 uint32_t gfx_clk = 0;
1400
1401 *gfx_freq = 0;
1402
1403 PP_ASSERT_WITH_CODE(smum_send_msg_to_smc_with_parameter(hwmgr,
1404 PPSMC_MSG_GetDpmClockFreq, (PPCLK_GFXCLK << 16),
1405 &gfx_clk) == 0,
1406 "[GetCurrentGfxClkFreq] Attempt to get Current GFXCLK Frequency Failed!",
1407 return -EINVAL);
1408
1409 *gfx_freq = gfx_clk * 100;
1410
1411 return 0;
1412 }
1413
vega12_get_current_mclk_freq(struct pp_hwmgr * hwmgr,uint32_t * mclk_freq)1414 static int vega12_get_current_mclk_freq(struct pp_hwmgr *hwmgr, uint32_t *mclk_freq)
1415 {
1416 uint32_t mem_clk = 0;
1417
1418 *mclk_freq = 0;
1419
1420 PP_ASSERT_WITH_CODE(
1421 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetDpmClockFreq, (PPCLK_UCLK << 16),
1422 &mem_clk) == 0,
1423 "[GetCurrentMClkFreq] Attempt to get Current MCLK Frequency Failed!",
1424 return -EINVAL);
1425
1426 *mclk_freq = mem_clk * 100;
1427
1428 return 0;
1429 }
1430
vega12_get_current_activity_percent(struct pp_hwmgr * hwmgr,int idx,uint32_t * activity_percent)1431 static int vega12_get_current_activity_percent(
1432 struct pp_hwmgr *hwmgr,
1433 int idx,
1434 uint32_t *activity_percent)
1435 {
1436 SmuMetrics_t metrics_table;
1437 int ret = 0;
1438
1439 ret = vega12_get_metrics_table(hwmgr, &metrics_table, false);
1440 if (ret)
1441 return ret;
1442
1443 switch (idx) {
1444 case AMDGPU_PP_SENSOR_GPU_LOAD:
1445 *activity_percent = metrics_table.AverageGfxActivity;
1446 break;
1447 case AMDGPU_PP_SENSOR_MEM_LOAD:
1448 *activity_percent = metrics_table.AverageUclkActivity;
1449 break;
1450 default:
1451 pr_err("Invalid index for retrieving clock activity\n");
1452 return -EINVAL;
1453 }
1454
1455 return ret;
1456 }
1457
vega12_read_sensor(struct pp_hwmgr * hwmgr,int idx,void * value,int * size)1458 static int vega12_read_sensor(struct pp_hwmgr *hwmgr, int idx,
1459 void *value, int *size)
1460 {
1461 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
1462 SmuMetrics_t metrics_table;
1463 int ret = 0;
1464
1465 switch (idx) {
1466 case AMDGPU_PP_SENSOR_GFX_SCLK:
1467 ret = vega12_get_current_gfx_clk_freq(hwmgr, (uint32_t *)value);
1468 if (!ret)
1469 *size = 4;
1470 break;
1471 case AMDGPU_PP_SENSOR_GFX_MCLK:
1472 ret = vega12_get_current_mclk_freq(hwmgr, (uint32_t *)value);
1473 if (!ret)
1474 *size = 4;
1475 break;
1476 case AMDGPU_PP_SENSOR_GPU_LOAD:
1477 case AMDGPU_PP_SENSOR_MEM_LOAD:
1478 ret = vega12_get_current_activity_percent(hwmgr, idx, (uint32_t *)value);
1479 if (!ret)
1480 *size = 4;
1481 break;
1482 case AMDGPU_PP_SENSOR_GPU_TEMP:
1483 *((uint32_t *)value) = vega12_thermal_get_temperature(hwmgr);
1484 *size = 4;
1485 break;
1486 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1487 ret = vega12_get_metrics_table(hwmgr, &metrics_table, false);
1488 if (ret)
1489 return ret;
1490
1491 *((uint32_t *)value) = metrics_table.TemperatureHotspot *
1492 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
1493 *size = 4;
1494 break;
1495 case AMDGPU_PP_SENSOR_MEM_TEMP:
1496 ret = vega12_get_metrics_table(hwmgr, &metrics_table, false);
1497 if (ret)
1498 return ret;
1499
1500 *((uint32_t *)value) = metrics_table.TemperatureHBM *
1501 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
1502 *size = 4;
1503 break;
1504 case AMDGPU_PP_SENSOR_UVD_POWER:
1505 *((uint32_t *)value) = data->uvd_power_gated ? 0 : 1;
1506 *size = 4;
1507 break;
1508 case AMDGPU_PP_SENSOR_VCE_POWER:
1509 *((uint32_t *)value) = data->vce_power_gated ? 0 : 1;
1510 *size = 4;
1511 break;
1512 case AMDGPU_PP_SENSOR_GPU_POWER:
1513 ret = vega12_get_gpu_power(hwmgr, (uint32_t *)value);
1514 if (!ret)
1515 *size = 4;
1516 break;
1517 case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK:
1518 ret = vega12_get_enabled_smc_features(hwmgr, (uint64_t *)value);
1519 if (!ret)
1520 *size = 8;
1521 break;
1522 default:
1523 ret = -EINVAL;
1524 break;
1525 }
1526 return ret;
1527 }
1528
vega12_notify_smc_display_change(struct pp_hwmgr * hwmgr,bool has_disp)1529 static int vega12_notify_smc_display_change(struct pp_hwmgr *hwmgr,
1530 bool has_disp)
1531 {
1532 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
1533
1534 if (data->smu_features[GNLD_DPM_UCLK].enabled)
1535 return smum_send_msg_to_smc_with_parameter(hwmgr,
1536 PPSMC_MSG_SetUclkFastSwitch,
1537 has_disp ? 1 : 0,
1538 NULL);
1539
1540 return 0;
1541 }
1542
vega12_display_clock_voltage_request(struct pp_hwmgr * hwmgr,struct pp_display_clock_request * clock_req)1543 static int vega12_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
1544 struct pp_display_clock_request *clock_req)
1545 {
1546 int result = 0;
1547 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
1548 enum amd_pp_clock_type clk_type = clock_req->clock_type;
1549 uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;
1550 PPCLK_e clk_select = 0;
1551 uint32_t clk_request = 0;
1552
1553 if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
1554 switch (clk_type) {
1555 case amd_pp_dcef_clock:
1556 clk_select = PPCLK_DCEFCLK;
1557 break;
1558 case amd_pp_disp_clock:
1559 clk_select = PPCLK_DISPCLK;
1560 break;
1561 case amd_pp_pixel_clock:
1562 clk_select = PPCLK_PIXCLK;
1563 break;
1564 case amd_pp_phy_clock:
1565 clk_select = PPCLK_PHYCLK;
1566 break;
1567 default:
1568 pr_info("[DisplayClockVoltageRequest]Invalid Clock Type!");
1569 result = -1;
1570 break;
1571 }
1572
1573 if (!result) {
1574 clk_request = (clk_select << 16) | clk_freq;
1575 result = smum_send_msg_to_smc_with_parameter(hwmgr,
1576 PPSMC_MSG_SetHardMinByFreq,
1577 clk_request,
1578 NULL);
1579 }
1580 }
1581
1582 return result;
1583 }
1584
vega12_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr * hwmgr)1585 static int vega12_notify_smc_display_config_after_ps_adjustment(
1586 struct pp_hwmgr *hwmgr)
1587 {
1588 struct vega12_hwmgr *data =
1589 (struct vega12_hwmgr *)(hwmgr->backend);
1590 struct PP_Clocks min_clocks = {0};
1591 struct pp_display_clock_request clock_req;
1592
1593 if ((hwmgr->display_config->num_display > 1) &&
1594 !hwmgr->display_config->multi_monitor_in_sync &&
1595 !hwmgr->display_config->nb_pstate_switch_disable)
1596 vega12_notify_smc_display_change(hwmgr, false);
1597 else
1598 vega12_notify_smc_display_change(hwmgr, true);
1599
1600 min_clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk;
1601 min_clocks.dcefClockInSR = hwmgr->display_config->min_dcef_deep_sleep_set_clk;
1602 min_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock;
1603
1604 if (data->smu_features[GNLD_DPM_DCEFCLK].supported) {
1605 clock_req.clock_type = amd_pp_dcef_clock;
1606 clock_req.clock_freq_in_khz = min_clocks.dcefClock/10;
1607 if (!vega12_display_clock_voltage_request(hwmgr, &clock_req)) {
1608 if (data->smu_features[GNLD_DS_DCEFCLK].supported)
1609 PP_ASSERT_WITH_CODE(
1610 !smum_send_msg_to_smc_with_parameter(
1611 hwmgr, PPSMC_MSG_SetMinDeepSleepDcefclk,
1612 min_clocks.dcefClockInSR /100,
1613 NULL),
1614 "Attempt to set divider for DCEFCLK Failed!",
1615 return -1);
1616 } else {
1617 pr_info("Attempt to set Hard Min for DCEFCLK Failed!");
1618 }
1619 }
1620
1621 return 0;
1622 }
1623
vega12_force_dpm_highest(struct pp_hwmgr * hwmgr)1624 static int vega12_force_dpm_highest(struct pp_hwmgr *hwmgr)
1625 {
1626 struct vega12_hwmgr *data =
1627 (struct vega12_hwmgr *)(hwmgr->backend);
1628
1629 uint32_t soft_level;
1630
1631 soft_level = vega12_find_highest_dpm_level(&(data->dpm_table.gfx_table));
1632
1633 data->dpm_table.gfx_table.dpm_state.soft_min_level =
1634 data->dpm_table.gfx_table.dpm_state.soft_max_level =
1635 data->dpm_table.gfx_table.dpm_levels[soft_level].value;
1636
1637 soft_level = vega12_find_highest_dpm_level(&(data->dpm_table.mem_table));
1638
1639 data->dpm_table.mem_table.dpm_state.soft_min_level =
1640 data->dpm_table.mem_table.dpm_state.soft_max_level =
1641 data->dpm_table.mem_table.dpm_levels[soft_level].value;
1642
1643 PP_ASSERT_WITH_CODE(!vega12_upload_dpm_min_level(hwmgr),
1644 "Failed to upload boot level to highest!",
1645 return -1);
1646
1647 PP_ASSERT_WITH_CODE(!vega12_upload_dpm_max_level(hwmgr),
1648 "Failed to upload dpm max level to highest!",
1649 return -1);
1650
1651 return 0;
1652 }
1653
vega12_force_dpm_lowest(struct pp_hwmgr * hwmgr)1654 static int vega12_force_dpm_lowest(struct pp_hwmgr *hwmgr)
1655 {
1656 struct vega12_hwmgr *data =
1657 (struct vega12_hwmgr *)(hwmgr->backend);
1658 uint32_t soft_level;
1659
1660 soft_level = vega12_find_lowest_dpm_level(&(data->dpm_table.gfx_table));
1661
1662 data->dpm_table.gfx_table.dpm_state.soft_min_level =
1663 data->dpm_table.gfx_table.dpm_state.soft_max_level =
1664 data->dpm_table.gfx_table.dpm_levels[soft_level].value;
1665
1666 soft_level = vega12_find_lowest_dpm_level(&(data->dpm_table.mem_table));
1667
1668 data->dpm_table.mem_table.dpm_state.soft_min_level =
1669 data->dpm_table.mem_table.dpm_state.soft_max_level =
1670 data->dpm_table.mem_table.dpm_levels[soft_level].value;
1671
1672 PP_ASSERT_WITH_CODE(!vega12_upload_dpm_min_level(hwmgr),
1673 "Failed to upload boot level to highest!",
1674 return -1);
1675
1676 PP_ASSERT_WITH_CODE(!vega12_upload_dpm_max_level(hwmgr),
1677 "Failed to upload dpm max level to highest!",
1678 return -1);
1679
1680 return 0;
1681
1682 }
1683
vega12_unforce_dpm_levels(struct pp_hwmgr * hwmgr)1684 static int vega12_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
1685 {
1686 PP_ASSERT_WITH_CODE(!vega12_upload_dpm_min_level(hwmgr),
1687 "Failed to upload DPM Bootup Levels!",
1688 return -1);
1689
1690 PP_ASSERT_WITH_CODE(!vega12_upload_dpm_max_level(hwmgr),
1691 "Failed to upload DPM Max Levels!",
1692 return -1);
1693
1694 return 0;
1695 }
1696
vega12_get_profiling_clk_mask(struct pp_hwmgr * hwmgr,enum amd_dpm_forced_level level,uint32_t * sclk_mask,uint32_t * mclk_mask,uint32_t * soc_mask)1697 static int vega12_get_profiling_clk_mask(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level,
1698 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask)
1699 {
1700 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
1701 struct vega12_single_dpm_table *gfx_dpm_table = &(data->dpm_table.gfx_table);
1702 struct vega12_single_dpm_table *mem_dpm_table = &(data->dpm_table.mem_table);
1703 struct vega12_single_dpm_table *soc_dpm_table = &(data->dpm_table.soc_table);
1704
1705 *sclk_mask = 0;
1706 *mclk_mask = 0;
1707 *soc_mask = 0;
1708
1709 if (gfx_dpm_table->count > VEGA12_UMD_PSTATE_GFXCLK_LEVEL &&
1710 mem_dpm_table->count > VEGA12_UMD_PSTATE_MCLK_LEVEL &&
1711 soc_dpm_table->count > VEGA12_UMD_PSTATE_SOCCLK_LEVEL) {
1712 *sclk_mask = VEGA12_UMD_PSTATE_GFXCLK_LEVEL;
1713 *mclk_mask = VEGA12_UMD_PSTATE_MCLK_LEVEL;
1714 *soc_mask = VEGA12_UMD_PSTATE_SOCCLK_LEVEL;
1715 }
1716
1717 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
1718 *sclk_mask = 0;
1719 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
1720 *mclk_mask = 0;
1721 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
1722 *sclk_mask = gfx_dpm_table->count - 1;
1723 *mclk_mask = mem_dpm_table->count - 1;
1724 *soc_mask = soc_dpm_table->count - 1;
1725 }
1726
1727 return 0;
1728 }
1729
vega12_set_fan_control_mode(struct pp_hwmgr * hwmgr,uint32_t mode)1730 static void vega12_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
1731 {
1732 switch (mode) {
1733 case AMD_FAN_CTRL_NONE:
1734 break;
1735 case AMD_FAN_CTRL_MANUAL:
1736 if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
1737 vega12_fan_ctrl_stop_smc_fan_control(hwmgr);
1738 break;
1739 case AMD_FAN_CTRL_AUTO:
1740 if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
1741 vega12_fan_ctrl_start_smc_fan_control(hwmgr);
1742 break;
1743 default:
1744 break;
1745 }
1746 }
1747
vega12_dpm_force_dpm_level(struct pp_hwmgr * hwmgr,enum amd_dpm_forced_level level)1748 static int vega12_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
1749 enum amd_dpm_forced_level level)
1750 {
1751 int ret = 0;
1752 uint32_t sclk_mask = 0;
1753 uint32_t mclk_mask = 0;
1754 uint32_t soc_mask = 0;
1755
1756 switch (level) {
1757 case AMD_DPM_FORCED_LEVEL_HIGH:
1758 ret = vega12_force_dpm_highest(hwmgr);
1759 break;
1760 case AMD_DPM_FORCED_LEVEL_LOW:
1761 ret = vega12_force_dpm_lowest(hwmgr);
1762 break;
1763 case AMD_DPM_FORCED_LEVEL_AUTO:
1764 ret = vega12_unforce_dpm_levels(hwmgr);
1765 break;
1766 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1767 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1768 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1769 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1770 ret = vega12_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask);
1771 if (ret)
1772 return ret;
1773 vega12_force_clock_level(hwmgr, PP_SCLK, 1 << sclk_mask);
1774 vega12_force_clock_level(hwmgr, PP_MCLK, 1 << mclk_mask);
1775 break;
1776 case AMD_DPM_FORCED_LEVEL_MANUAL:
1777 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
1778 default:
1779 break;
1780 }
1781
1782 return ret;
1783 }
1784
vega12_get_fan_control_mode(struct pp_hwmgr * hwmgr)1785 static uint32_t vega12_get_fan_control_mode(struct pp_hwmgr *hwmgr)
1786 {
1787 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
1788
1789 if (data->smu_features[GNLD_FAN_CONTROL].enabled == false)
1790 return AMD_FAN_CTRL_MANUAL;
1791 else
1792 return AMD_FAN_CTRL_AUTO;
1793 }
1794
vega12_get_dal_power_level(struct pp_hwmgr * hwmgr,struct amd_pp_simple_clock_info * info)1795 static int vega12_get_dal_power_level(struct pp_hwmgr *hwmgr,
1796 struct amd_pp_simple_clock_info *info)
1797 {
1798 #if 0
1799 struct phm_ppt_v2_information *table_info =
1800 (struct phm_ppt_v2_information *)hwmgr->pptable;
1801 struct phm_clock_and_voltage_limits *max_limits =
1802 &table_info->max_clock_voltage_on_ac;
1803
1804 info->engine_max_clock = max_limits->sclk;
1805 info->memory_max_clock = max_limits->mclk;
1806 #endif
1807 return 0;
1808 }
1809
vega12_get_clock_ranges(struct pp_hwmgr * hwmgr,uint32_t * clock,PPCLK_e clock_select,bool max)1810 static int vega12_get_clock_ranges(struct pp_hwmgr *hwmgr,
1811 uint32_t *clock,
1812 PPCLK_e clock_select,
1813 bool max)
1814 {
1815 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
1816
1817 if (max)
1818 *clock = data->clk_range[clock_select].ACMax;
1819 else
1820 *clock = data->clk_range[clock_select].ACMin;
1821
1822 return 0;
1823 }
1824
vega12_get_sclks(struct pp_hwmgr * hwmgr,struct pp_clock_levels_with_latency * clocks)1825 static int vega12_get_sclks(struct pp_hwmgr *hwmgr,
1826 struct pp_clock_levels_with_latency *clocks)
1827 {
1828 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
1829 uint32_t ucount;
1830 int i;
1831 struct vega12_single_dpm_table *dpm_table;
1832
1833 if (!data->smu_features[GNLD_DPM_GFXCLK].enabled)
1834 return -1;
1835
1836 dpm_table = &(data->dpm_table.gfx_table);
1837 ucount = (dpm_table->count > MAX_NUM_CLOCKS) ?
1838 MAX_NUM_CLOCKS : dpm_table->count;
1839
1840 for (i = 0; i < ucount; i++) {
1841 clocks->data[i].clocks_in_khz =
1842 dpm_table->dpm_levels[i].value * 1000;
1843
1844 clocks->data[i].latency_in_us = 0;
1845 }
1846
1847 clocks->num_levels = ucount;
1848
1849 return 0;
1850 }
1851
vega12_get_mem_latency(struct pp_hwmgr * hwmgr,uint32_t clock)1852 static uint32_t vega12_get_mem_latency(struct pp_hwmgr *hwmgr,
1853 uint32_t clock)
1854 {
1855 return 25;
1856 }
1857
vega12_get_memclocks(struct pp_hwmgr * hwmgr,struct pp_clock_levels_with_latency * clocks)1858 static int vega12_get_memclocks(struct pp_hwmgr *hwmgr,
1859 struct pp_clock_levels_with_latency *clocks)
1860 {
1861 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
1862 uint32_t ucount;
1863 int i;
1864 struct vega12_single_dpm_table *dpm_table;
1865 if (!data->smu_features[GNLD_DPM_UCLK].enabled)
1866 return -1;
1867
1868 dpm_table = &(data->dpm_table.mem_table);
1869 ucount = (dpm_table->count > MAX_NUM_CLOCKS) ?
1870 MAX_NUM_CLOCKS : dpm_table->count;
1871
1872 for (i = 0; i < ucount; i++) {
1873 clocks->data[i].clocks_in_khz = dpm_table->dpm_levels[i].value * 1000;
1874 data->mclk_latency_table.entries[i].frequency = dpm_table->dpm_levels[i].value * 100;
1875 clocks->data[i].latency_in_us =
1876 data->mclk_latency_table.entries[i].latency =
1877 vega12_get_mem_latency(hwmgr, dpm_table->dpm_levels[i].value);
1878 }
1879
1880 clocks->num_levels = data->mclk_latency_table.count = ucount;
1881
1882 return 0;
1883 }
1884
vega12_get_dcefclocks(struct pp_hwmgr * hwmgr,struct pp_clock_levels_with_latency * clocks)1885 static int vega12_get_dcefclocks(struct pp_hwmgr *hwmgr,
1886 struct pp_clock_levels_with_latency *clocks)
1887 {
1888 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
1889 uint32_t ucount;
1890 int i;
1891 struct vega12_single_dpm_table *dpm_table;
1892
1893 if (!data->smu_features[GNLD_DPM_DCEFCLK].enabled)
1894 return -1;
1895
1896
1897 dpm_table = &(data->dpm_table.dcef_table);
1898 ucount = (dpm_table->count > MAX_NUM_CLOCKS) ?
1899 MAX_NUM_CLOCKS : dpm_table->count;
1900
1901 for (i = 0; i < ucount; i++) {
1902 clocks->data[i].clocks_in_khz =
1903 dpm_table->dpm_levels[i].value * 1000;
1904
1905 clocks->data[i].latency_in_us = 0;
1906 }
1907
1908 clocks->num_levels = ucount;
1909
1910 return 0;
1911 }
1912
vega12_get_socclocks(struct pp_hwmgr * hwmgr,struct pp_clock_levels_with_latency * clocks)1913 static int vega12_get_socclocks(struct pp_hwmgr *hwmgr,
1914 struct pp_clock_levels_with_latency *clocks)
1915 {
1916 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
1917 uint32_t ucount;
1918 int i;
1919 struct vega12_single_dpm_table *dpm_table;
1920
1921 if (!data->smu_features[GNLD_DPM_SOCCLK].enabled)
1922 return -1;
1923
1924
1925 dpm_table = &(data->dpm_table.soc_table);
1926 ucount = (dpm_table->count > MAX_NUM_CLOCKS) ?
1927 MAX_NUM_CLOCKS : dpm_table->count;
1928
1929 for (i = 0; i < ucount; i++) {
1930 clocks->data[i].clocks_in_khz =
1931 dpm_table->dpm_levels[i].value * 1000;
1932
1933 clocks->data[i].latency_in_us = 0;
1934 }
1935
1936 clocks->num_levels = ucount;
1937
1938 return 0;
1939
1940 }
1941
vega12_get_clock_by_type_with_latency(struct pp_hwmgr * hwmgr,enum amd_pp_clock_type type,struct pp_clock_levels_with_latency * clocks)1942 static int vega12_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr,
1943 enum amd_pp_clock_type type,
1944 struct pp_clock_levels_with_latency *clocks)
1945 {
1946 int ret;
1947
1948 switch (type) {
1949 case amd_pp_sys_clock:
1950 ret = vega12_get_sclks(hwmgr, clocks);
1951 break;
1952 case amd_pp_mem_clock:
1953 ret = vega12_get_memclocks(hwmgr, clocks);
1954 break;
1955 case amd_pp_dcef_clock:
1956 ret = vega12_get_dcefclocks(hwmgr, clocks);
1957 break;
1958 case amd_pp_soc_clock:
1959 ret = vega12_get_socclocks(hwmgr, clocks);
1960 break;
1961 default:
1962 return -EINVAL;
1963 }
1964
1965 return ret;
1966 }
1967
vega12_get_clock_by_type_with_voltage(struct pp_hwmgr * hwmgr,enum amd_pp_clock_type type,struct pp_clock_levels_with_voltage * clocks)1968 static int vega12_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr,
1969 enum amd_pp_clock_type type,
1970 struct pp_clock_levels_with_voltage *clocks)
1971 {
1972 clocks->num_levels = 0;
1973
1974 return 0;
1975 }
1976
vega12_set_watermarks_for_clocks_ranges(struct pp_hwmgr * hwmgr,void * clock_ranges)1977 static int vega12_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
1978 void *clock_ranges)
1979 {
1980 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
1981 Watermarks_t *table = &(data->smc_state_table.water_marks_table);
1982 struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges = clock_ranges;
1983
1984 if (!data->registry_data.disable_water_mark &&
1985 data->smu_features[GNLD_DPM_DCEFCLK].supported &&
1986 data->smu_features[GNLD_DPM_SOCCLK].supported) {
1987 smu_set_watermarks_for_clocks_ranges(table, wm_with_clock_ranges);
1988 data->water_marks_bitmap |= WaterMarksExist;
1989 data->water_marks_bitmap &= ~WaterMarksLoaded;
1990 }
1991
1992 return 0;
1993 }
1994
vega12_force_clock_level(struct pp_hwmgr * hwmgr,enum pp_clock_type type,uint32_t mask)1995 static int vega12_force_clock_level(struct pp_hwmgr *hwmgr,
1996 enum pp_clock_type type, uint32_t mask)
1997 {
1998 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
1999 uint32_t soft_min_level, soft_max_level, hard_min_level;
2000 int ret = 0;
2001
2002 switch (type) {
2003 case PP_SCLK:
2004 soft_min_level = mask ? (ffs(mask) - 1) : 0;
2005 soft_max_level = mask ? (fls(mask) - 1) : 0;
2006
2007 data->dpm_table.gfx_table.dpm_state.soft_min_level =
2008 data->dpm_table.gfx_table.dpm_levels[soft_min_level].value;
2009 data->dpm_table.gfx_table.dpm_state.soft_max_level =
2010 data->dpm_table.gfx_table.dpm_levels[soft_max_level].value;
2011
2012 ret = vega12_upload_dpm_min_level(hwmgr);
2013 PP_ASSERT_WITH_CODE(!ret,
2014 "Failed to upload boot level to lowest!",
2015 return ret);
2016
2017 ret = vega12_upload_dpm_max_level(hwmgr);
2018 PP_ASSERT_WITH_CODE(!ret,
2019 "Failed to upload dpm max level to highest!",
2020 return ret);
2021 break;
2022
2023 case PP_MCLK:
2024 soft_min_level = mask ? (ffs(mask) - 1) : 0;
2025 soft_max_level = mask ? (fls(mask) - 1) : 0;
2026
2027 data->dpm_table.mem_table.dpm_state.soft_min_level =
2028 data->dpm_table.mem_table.dpm_levels[soft_min_level].value;
2029 data->dpm_table.mem_table.dpm_state.soft_max_level =
2030 data->dpm_table.mem_table.dpm_levels[soft_max_level].value;
2031
2032 ret = vega12_upload_dpm_min_level(hwmgr);
2033 PP_ASSERT_WITH_CODE(!ret,
2034 "Failed to upload boot level to lowest!",
2035 return ret);
2036
2037 ret = vega12_upload_dpm_max_level(hwmgr);
2038 PP_ASSERT_WITH_CODE(!ret,
2039 "Failed to upload dpm max level to highest!",
2040 return ret);
2041
2042 break;
2043
2044 case PP_SOCCLK:
2045 soft_min_level = mask ? (ffs(mask) - 1) : 0;
2046 soft_max_level = mask ? (fls(mask) - 1) : 0;
2047
2048 if (soft_max_level >= data->dpm_table.soc_table.count) {
2049 pr_err("Clock level specified %d is over max allowed %d\n",
2050 soft_max_level,
2051 data->dpm_table.soc_table.count - 1);
2052 return -EINVAL;
2053 }
2054
2055 data->dpm_table.soc_table.dpm_state.soft_min_level =
2056 data->dpm_table.soc_table.dpm_levels[soft_min_level].value;
2057 data->dpm_table.soc_table.dpm_state.soft_max_level =
2058 data->dpm_table.soc_table.dpm_levels[soft_max_level].value;
2059
2060 ret = vega12_upload_dpm_min_level(hwmgr);
2061 PP_ASSERT_WITH_CODE(!ret,
2062 "Failed to upload boot level to lowest!",
2063 return ret);
2064
2065 ret = vega12_upload_dpm_max_level(hwmgr);
2066 PP_ASSERT_WITH_CODE(!ret,
2067 "Failed to upload dpm max level to highest!",
2068 return ret);
2069
2070 break;
2071
2072 case PP_DCEFCLK:
2073 hard_min_level = mask ? (ffs(mask) - 1) : 0;
2074
2075 if (hard_min_level >= data->dpm_table.dcef_table.count) {
2076 pr_err("Clock level specified %d is over max allowed %d\n",
2077 hard_min_level,
2078 data->dpm_table.dcef_table.count - 1);
2079 return -EINVAL;
2080 }
2081
2082 data->dpm_table.dcef_table.dpm_state.hard_min_level =
2083 data->dpm_table.dcef_table.dpm_levels[hard_min_level].value;
2084
2085 ret = vega12_upload_dpm_min_level(hwmgr);
2086 PP_ASSERT_WITH_CODE(!ret,
2087 "Failed to upload boot level to lowest!",
2088 return ret);
2089
2090 //TODO: Setting DCEFCLK max dpm level is not supported
2091
2092 break;
2093
2094 case PP_PCIE:
2095 break;
2096
2097 default:
2098 break;
2099 }
2100
2101 return 0;
2102 }
2103
vega12_get_ppfeature_status(struct pp_hwmgr * hwmgr,char * buf)2104 static int vega12_get_ppfeature_status(struct pp_hwmgr *hwmgr, char *buf)
2105 {
2106 static const char *ppfeature_name[] = {
2107 "DPM_PREFETCHER",
2108 "GFXCLK_DPM",
2109 "UCLK_DPM",
2110 "SOCCLK_DPM",
2111 "UVD_DPM",
2112 "VCE_DPM",
2113 "ULV",
2114 "MP0CLK_DPM",
2115 "LINK_DPM",
2116 "DCEFCLK_DPM",
2117 "GFXCLK_DS",
2118 "SOCCLK_DS",
2119 "LCLK_DS",
2120 "PPT",
2121 "TDC",
2122 "THERMAL",
2123 "GFX_PER_CU_CG",
2124 "RM",
2125 "DCEFCLK_DS",
2126 "ACDC",
2127 "VR0HOT",
2128 "VR1HOT",
2129 "FW_CTF",
2130 "LED_DISPLAY",
2131 "FAN_CONTROL",
2132 "DIDT",
2133 "GFXOFF",
2134 "CG",
2135 "ACG"};
2136 static const char *output_title[] = {
2137 "FEATURES",
2138 "BITMASK",
2139 "ENABLEMENT"};
2140 uint64_t features_enabled;
2141 int i;
2142 int ret = 0;
2143 int size = 0;
2144
2145 ret = vega12_get_enabled_smc_features(hwmgr, &features_enabled);
2146 PP_ASSERT_WITH_CODE(!ret,
2147 "[EnableAllSmuFeatures] Failed to get enabled smc features!",
2148 return ret);
2149
2150 size += sprintf(buf + size, "Current ppfeatures: 0x%016llx\n", features_enabled);
2151 size += sprintf(buf + size, "%-19s %-22s %s\n",
2152 output_title[0],
2153 output_title[1],
2154 output_title[2]);
2155 for (i = 0; i < GNLD_FEATURES_MAX; i++) {
2156 size += sprintf(buf + size, "%-19s 0x%016llx %6s\n",
2157 ppfeature_name[i],
2158 1ULL << i,
2159 (features_enabled & (1ULL << i)) ? "Y" : "N");
2160 }
2161
2162 return size;
2163 }
2164
vega12_set_ppfeature_status(struct pp_hwmgr * hwmgr,uint64_t new_ppfeature_masks)2165 static int vega12_set_ppfeature_status(struct pp_hwmgr *hwmgr, uint64_t new_ppfeature_masks)
2166 {
2167 uint64_t features_enabled;
2168 uint64_t features_to_enable;
2169 uint64_t features_to_disable;
2170 int ret = 0;
2171
2172 if (new_ppfeature_masks >= (1ULL << GNLD_FEATURES_MAX))
2173 return -EINVAL;
2174
2175 ret = vega12_get_enabled_smc_features(hwmgr, &features_enabled);
2176 if (ret)
2177 return ret;
2178
2179 features_to_disable =
2180 features_enabled & ~new_ppfeature_masks;
2181 features_to_enable =
2182 ~features_enabled & new_ppfeature_masks;
2183
2184 pr_debug("features_to_disable 0x%llx\n", features_to_disable);
2185 pr_debug("features_to_enable 0x%llx\n", features_to_enable);
2186
2187 if (features_to_disable) {
2188 ret = vega12_enable_smc_features(hwmgr, false, features_to_disable);
2189 if (ret)
2190 return ret;
2191 }
2192
2193 if (features_to_enable) {
2194 ret = vega12_enable_smc_features(hwmgr, true, features_to_enable);
2195 if (ret)
2196 return ret;
2197 }
2198
2199 return 0;
2200 }
2201
vega12_get_current_pcie_link_width_level(struct pp_hwmgr * hwmgr)2202 static int vega12_get_current_pcie_link_width_level(struct pp_hwmgr *hwmgr)
2203 {
2204 struct amdgpu_device *adev = hwmgr->adev;
2205
2206 return (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) &
2207 PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK)
2208 >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
2209 }
2210
vega12_get_current_pcie_link_width(struct pp_hwmgr * hwmgr)2211 static int vega12_get_current_pcie_link_width(struct pp_hwmgr *hwmgr)
2212 {
2213 uint32_t width_level;
2214
2215 width_level = vega12_get_current_pcie_link_width_level(hwmgr);
2216 if (width_level > LINK_WIDTH_MAX)
2217 width_level = 0;
2218
2219 return link_width[width_level];
2220 }
2221
vega12_get_current_pcie_link_speed_level(struct pp_hwmgr * hwmgr)2222 static int vega12_get_current_pcie_link_speed_level(struct pp_hwmgr *hwmgr)
2223 {
2224 struct amdgpu_device *adev = hwmgr->adev;
2225
2226 return (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
2227 PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK)
2228 >> PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
2229 }
2230
vega12_get_current_pcie_link_speed(struct pp_hwmgr * hwmgr)2231 static int vega12_get_current_pcie_link_speed(struct pp_hwmgr *hwmgr)
2232 {
2233 uint32_t speed_level;
2234
2235 speed_level = vega12_get_current_pcie_link_speed_level(hwmgr);
2236 if (speed_level > LINK_SPEED_MAX)
2237 speed_level = 0;
2238
2239 return link_speed[speed_level];
2240 }
2241
vega12_print_clock_levels(struct pp_hwmgr * hwmgr,enum pp_clock_type type,char * buf)2242 static int vega12_print_clock_levels(struct pp_hwmgr *hwmgr,
2243 enum pp_clock_type type, char *buf)
2244 {
2245 int i, now, size = 0;
2246 struct pp_clock_levels_with_latency clocks;
2247
2248 switch (type) {
2249 case PP_SCLK:
2250 PP_ASSERT_WITH_CODE(
2251 vega12_get_current_gfx_clk_freq(hwmgr, &now) == 0,
2252 "Attempt to get current gfx clk Failed!",
2253 return -1);
2254
2255 PP_ASSERT_WITH_CODE(
2256 vega12_get_sclks(hwmgr, &clocks) == 0,
2257 "Attempt to get gfx clk levels Failed!",
2258 return -1);
2259 for (i = 0; i < clocks.num_levels; i++)
2260 size += sprintf(buf + size, "%d: %uMhz %s\n",
2261 i, clocks.data[i].clocks_in_khz / 1000,
2262 (clocks.data[i].clocks_in_khz / 1000 == now / 100) ? "*" : "");
2263 break;
2264
2265 case PP_MCLK:
2266 PP_ASSERT_WITH_CODE(
2267 vega12_get_current_mclk_freq(hwmgr, &now) == 0,
2268 "Attempt to get current mclk freq Failed!",
2269 return -1);
2270
2271 PP_ASSERT_WITH_CODE(
2272 vega12_get_memclocks(hwmgr, &clocks) == 0,
2273 "Attempt to get memory clk levels Failed!",
2274 return -1);
2275 for (i = 0; i < clocks.num_levels; i++)
2276 size += sprintf(buf + size, "%d: %uMhz %s\n",
2277 i, clocks.data[i].clocks_in_khz / 1000,
2278 (clocks.data[i].clocks_in_khz / 1000 == now / 100) ? "*" : "");
2279 break;
2280
2281 case PP_SOCCLK:
2282 PP_ASSERT_WITH_CODE(
2283 smum_send_msg_to_smc_with_parameter(hwmgr,
2284 PPSMC_MSG_GetDpmClockFreq, (PPCLK_SOCCLK << 16),
2285 &now) == 0,
2286 "Attempt to get Current SOCCLK Frequency Failed!",
2287 return -EINVAL);
2288
2289 PP_ASSERT_WITH_CODE(
2290 vega12_get_socclocks(hwmgr, &clocks) == 0,
2291 "Attempt to get soc clk levels Failed!",
2292 return -1);
2293 for (i = 0; i < clocks.num_levels; i++)
2294 size += sprintf(buf + size, "%d: %uMhz %s\n",
2295 i, clocks.data[i].clocks_in_khz / 1000,
2296 (clocks.data[i].clocks_in_khz / 1000 == now) ? "*" : "");
2297 break;
2298
2299 case PP_DCEFCLK:
2300 PP_ASSERT_WITH_CODE(
2301 smum_send_msg_to_smc_with_parameter(hwmgr,
2302 PPSMC_MSG_GetDpmClockFreq, (PPCLK_DCEFCLK << 16),
2303 &now) == 0,
2304 "Attempt to get Current DCEFCLK Frequency Failed!",
2305 return -EINVAL);
2306
2307 PP_ASSERT_WITH_CODE(
2308 vega12_get_dcefclocks(hwmgr, &clocks) == 0,
2309 "Attempt to get dcef clk levels Failed!",
2310 return -1);
2311 for (i = 0; i < clocks.num_levels; i++)
2312 size += sprintf(buf + size, "%d: %uMhz %s\n",
2313 i, clocks.data[i].clocks_in_khz / 1000,
2314 (clocks.data[i].clocks_in_khz / 1000 == now) ? "*" : "");
2315 break;
2316
2317 case PP_PCIE:
2318 break;
2319
2320 default:
2321 break;
2322 }
2323 return size;
2324 }
2325
vega12_apply_clocks_adjust_rules(struct pp_hwmgr * hwmgr)2326 static int vega12_apply_clocks_adjust_rules(struct pp_hwmgr *hwmgr)
2327 {
2328 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
2329 struct vega12_single_dpm_table *dpm_table;
2330 bool vblank_too_short = false;
2331 bool disable_mclk_switching;
2332 uint32_t i, latency;
2333
2334 disable_mclk_switching = ((1 < hwmgr->display_config->num_display) &&
2335 !hwmgr->display_config->multi_monitor_in_sync) ||
2336 vblank_too_short;
2337 latency = hwmgr->display_config->dce_tolerable_mclk_in_active_latency;
2338
2339 /* gfxclk */
2340 dpm_table = &(data->dpm_table.gfx_table);
2341 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2342 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2343 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
2344 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2345
2346 if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
2347 if (VEGA12_UMD_PSTATE_GFXCLK_LEVEL < dpm_table->count) {
2348 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_GFXCLK_LEVEL].value;
2349 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_GFXCLK_LEVEL].value;
2350 }
2351
2352 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
2353 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2354 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[0].value;
2355 }
2356
2357 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2358 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2359 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2360 }
2361 }
2362
2363 /* memclk */
2364 dpm_table = &(data->dpm_table.mem_table);
2365 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2366 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2367 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
2368 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2369
2370 if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
2371 if (VEGA12_UMD_PSTATE_MCLK_LEVEL < dpm_table->count) {
2372 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_MCLK_LEVEL].value;
2373 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_MCLK_LEVEL].value;
2374 }
2375
2376 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
2377 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2378 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[0].value;
2379 }
2380
2381 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2382 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2383 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2384 }
2385 }
2386
2387 /* honour DAL's UCLK Hardmin */
2388 if (dpm_table->dpm_state.hard_min_level < (hwmgr->display_config->min_mem_set_clock / 100))
2389 dpm_table->dpm_state.hard_min_level = hwmgr->display_config->min_mem_set_clock / 100;
2390
2391 /* Hardmin is dependent on displayconfig */
2392 if (disable_mclk_switching) {
2393 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2394 for (i = 0; i < data->mclk_latency_table.count - 1; i++) {
2395 if (data->mclk_latency_table.entries[i].latency <= latency) {
2396 if (dpm_table->dpm_levels[i].value >= (hwmgr->display_config->min_mem_set_clock / 100)) {
2397 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[i].value;
2398 break;
2399 }
2400 }
2401 }
2402 }
2403
2404 if (hwmgr->display_config->nb_pstate_switch_disable)
2405 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2406
2407 /* vclk */
2408 dpm_table = &(data->dpm_table.vclk_table);
2409 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2410 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2411 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
2412 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2413
2414 if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
2415 if (VEGA12_UMD_PSTATE_UVDCLK_LEVEL < dpm_table->count) {
2416 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_UVDCLK_LEVEL].value;
2417 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_UVDCLK_LEVEL].value;
2418 }
2419
2420 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2421 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2422 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2423 }
2424 }
2425
2426 /* dclk */
2427 dpm_table = &(data->dpm_table.dclk_table);
2428 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2429 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2430 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
2431 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2432
2433 if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
2434 if (VEGA12_UMD_PSTATE_UVDCLK_LEVEL < dpm_table->count) {
2435 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_UVDCLK_LEVEL].value;
2436 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_UVDCLK_LEVEL].value;
2437 }
2438
2439 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2440 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2441 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2442 }
2443 }
2444
2445 /* socclk */
2446 dpm_table = &(data->dpm_table.soc_table);
2447 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2448 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2449 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
2450 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2451
2452 if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
2453 if (VEGA12_UMD_PSTATE_SOCCLK_LEVEL < dpm_table->count) {
2454 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_SOCCLK_LEVEL].value;
2455 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_SOCCLK_LEVEL].value;
2456 }
2457
2458 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2459 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2460 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2461 }
2462 }
2463
2464 /* eclk */
2465 dpm_table = &(data->dpm_table.eclk_table);
2466 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2467 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2468 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
2469 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2470
2471 if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
2472 if (VEGA12_UMD_PSTATE_VCEMCLK_LEVEL < dpm_table->count) {
2473 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_VCEMCLK_LEVEL].value;
2474 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_VCEMCLK_LEVEL].value;
2475 }
2476
2477 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2478 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2479 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2480 }
2481 }
2482
2483 return 0;
2484 }
2485
vega12_set_uclk_to_highest_dpm_level(struct pp_hwmgr * hwmgr,struct vega12_single_dpm_table * dpm_table)2486 static int vega12_set_uclk_to_highest_dpm_level(struct pp_hwmgr *hwmgr,
2487 struct vega12_single_dpm_table *dpm_table)
2488 {
2489 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
2490 int ret = 0;
2491
2492 if (data->smu_features[GNLD_DPM_UCLK].enabled) {
2493 PP_ASSERT_WITH_CODE(dpm_table->count > 0,
2494 "[SetUclkToHightestDpmLevel] Dpm table has no entry!",
2495 return -EINVAL);
2496 PP_ASSERT_WITH_CODE(dpm_table->count <= NUM_UCLK_DPM_LEVELS,
2497 "[SetUclkToHightestDpmLevel] Dpm table has too many entries!",
2498 return -EINVAL);
2499
2500 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2501 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(hwmgr,
2502 PPSMC_MSG_SetHardMinByFreq,
2503 (PPCLK_UCLK << 16 ) | dpm_table->dpm_state.hard_min_level,
2504 NULL)),
2505 "[SetUclkToHightestDpmLevel] Set hard min uclk failed!",
2506 return ret);
2507 }
2508
2509 return ret;
2510 }
2511
vega12_pre_display_configuration_changed_task(struct pp_hwmgr * hwmgr)2512 static int vega12_pre_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
2513 {
2514 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
2515 int ret = 0;
2516
2517 smum_send_msg_to_smc_with_parameter(hwmgr,
2518 PPSMC_MSG_NumOfDisplays, 0,
2519 NULL);
2520
2521 ret = vega12_set_uclk_to_highest_dpm_level(hwmgr,
2522 &data->dpm_table.mem_table);
2523
2524 return ret;
2525 }
2526
vega12_display_configuration_changed_task(struct pp_hwmgr * hwmgr)2527 static int vega12_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
2528 {
2529 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
2530 int result = 0;
2531 Watermarks_t *wm_table = &(data->smc_state_table.water_marks_table);
2532
2533 if ((data->water_marks_bitmap & WaterMarksExist) &&
2534 !(data->water_marks_bitmap & WaterMarksLoaded)) {
2535 result = smum_smc_table_manager(hwmgr,
2536 (uint8_t *)wm_table, TABLE_WATERMARKS, false);
2537 PP_ASSERT_WITH_CODE(result, "Failed to update WMTABLE!", return -EINVAL);
2538 data->water_marks_bitmap |= WaterMarksLoaded;
2539 }
2540
2541 if ((data->water_marks_bitmap & WaterMarksExist) &&
2542 data->smu_features[GNLD_DPM_DCEFCLK].supported &&
2543 data->smu_features[GNLD_DPM_SOCCLK].supported)
2544 smum_send_msg_to_smc_with_parameter(hwmgr,
2545 PPSMC_MSG_NumOfDisplays, hwmgr->display_config->num_display,
2546 NULL);
2547
2548 return result;
2549 }
2550
vega12_enable_disable_uvd_dpm(struct pp_hwmgr * hwmgr,bool enable)2551 static int vega12_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
2552 {
2553 struct vega12_hwmgr *data =
2554 (struct vega12_hwmgr *)(hwmgr->backend);
2555
2556 if (data->smu_features[GNLD_DPM_UVD].supported) {
2557 PP_ASSERT_WITH_CODE(!vega12_enable_smc_features(hwmgr,
2558 enable,
2559 data->smu_features[GNLD_DPM_UVD].smu_feature_bitmap),
2560 "Attempt to Enable/Disable DPM UVD Failed!",
2561 return -1);
2562 data->smu_features[GNLD_DPM_UVD].enabled = enable;
2563 }
2564
2565 return 0;
2566 }
2567
vega12_power_gate_vce(struct pp_hwmgr * hwmgr,bool bgate)2568 static void vega12_power_gate_vce(struct pp_hwmgr *hwmgr, bool bgate)
2569 {
2570 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
2571
2572 if (data->vce_power_gated == bgate)
2573 return;
2574
2575 data->vce_power_gated = bgate;
2576 vega12_enable_disable_vce_dpm(hwmgr, !bgate);
2577 }
2578
vega12_power_gate_uvd(struct pp_hwmgr * hwmgr,bool bgate)2579 static void vega12_power_gate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
2580 {
2581 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
2582
2583 if (data->uvd_power_gated == bgate)
2584 return;
2585
2586 data->uvd_power_gated = bgate;
2587 vega12_enable_disable_uvd_dpm(hwmgr, !bgate);
2588 }
2589
2590 static bool
vega12_check_smc_update_required_for_display_configuration(struct pp_hwmgr * hwmgr)2591 vega12_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
2592 {
2593 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
2594 bool is_update_required = false;
2595
2596 if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display)
2597 is_update_required = true;
2598
2599 if (data->registry_data.gfx_clk_deep_sleep_support) {
2600 if (data->display_timing.min_clock_in_sr != hwmgr->display_config->min_core_set_clock_in_sr)
2601 is_update_required = true;
2602 }
2603
2604 return is_update_required;
2605 }
2606
vega12_disable_dpm_tasks(struct pp_hwmgr * hwmgr)2607 static int vega12_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
2608 {
2609 int tmp_result, result = 0;
2610
2611 tmp_result = vega12_disable_all_smu_features(hwmgr);
2612 PP_ASSERT_WITH_CODE((tmp_result == 0),
2613 "Failed to disable all smu features!", result = tmp_result);
2614
2615 return result;
2616 }
2617
vega12_power_off_asic(struct pp_hwmgr * hwmgr)2618 static int vega12_power_off_asic(struct pp_hwmgr *hwmgr)
2619 {
2620 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
2621 int result;
2622
2623 result = vega12_disable_dpm_tasks(hwmgr);
2624 PP_ASSERT_WITH_CODE((0 == result),
2625 "[disable_dpm_tasks] Failed to disable DPM!",
2626 );
2627 data->water_marks_bitmap &= ~(WaterMarksLoaded);
2628
2629 return result;
2630 }
2631
2632 #if 0
2633 static void vega12_find_min_clock_index(struct pp_hwmgr *hwmgr,
2634 uint32_t *sclk_idx, uint32_t *mclk_idx,
2635 uint32_t min_sclk, uint32_t min_mclk)
2636 {
2637 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
2638 struct vega12_dpm_table *dpm_table = &(data->dpm_table);
2639 uint32_t i;
2640
2641 for (i = 0; i < dpm_table->gfx_table.count; i++) {
2642 if (dpm_table->gfx_table.dpm_levels[i].enabled &&
2643 dpm_table->gfx_table.dpm_levels[i].value >= min_sclk) {
2644 *sclk_idx = i;
2645 break;
2646 }
2647 }
2648
2649 for (i = 0; i < dpm_table->mem_table.count; i++) {
2650 if (dpm_table->mem_table.dpm_levels[i].enabled &&
2651 dpm_table->mem_table.dpm_levels[i].value >= min_mclk) {
2652 *mclk_idx = i;
2653 break;
2654 }
2655 }
2656 }
2657 #endif
2658
2659 #if 0
2660 static int vega12_set_power_profile_state(struct pp_hwmgr *hwmgr,
2661 struct amd_pp_profile *request)
2662 {
2663 return 0;
2664 }
2665
2666 static int vega12_get_sclk_od(struct pp_hwmgr *hwmgr)
2667 {
2668 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
2669 struct vega12_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table);
2670 struct vega12_single_dpm_table *golden_sclk_table =
2671 &(data->golden_dpm_table.gfx_table);
2672 int value = sclk_table->dpm_levels[sclk_table->count - 1].value;
2673 int golden_value = golden_sclk_table->dpm_levels
2674 [golden_sclk_table->count - 1].value;
2675
2676 value -= golden_value;
2677 value = DIV_ROUND_UP(value * 100, golden_value);
2678
2679 return value;
2680 }
2681
2682 static int vega12_set_sclk_od(struct pp_hwmgr *hwmgr, uint32_t value)
2683 {
2684 return 0;
2685 }
2686
2687 static int vega12_get_mclk_od(struct pp_hwmgr *hwmgr)
2688 {
2689 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
2690 struct vega12_single_dpm_table *mclk_table = &(data->dpm_table.mem_table);
2691 struct vega12_single_dpm_table *golden_mclk_table =
2692 &(data->golden_dpm_table.mem_table);
2693 int value = mclk_table->dpm_levels[mclk_table->count - 1].value;
2694 int golden_value = golden_mclk_table->dpm_levels
2695 [golden_mclk_table->count - 1].value;
2696
2697 value -= golden_value;
2698 value = DIV_ROUND_UP(value * 100, golden_value);
2699
2700 return value;
2701 }
2702
2703 static int vega12_set_mclk_od(struct pp_hwmgr *hwmgr, uint32_t value)
2704 {
2705 return 0;
2706 }
2707 #endif
2708
vega12_notify_cac_buffer_info(struct pp_hwmgr * hwmgr,uint32_t virtual_addr_low,uint32_t virtual_addr_hi,uint32_t mc_addr_low,uint32_t mc_addr_hi,uint32_t size)2709 static int vega12_notify_cac_buffer_info(struct pp_hwmgr *hwmgr,
2710 uint32_t virtual_addr_low,
2711 uint32_t virtual_addr_hi,
2712 uint32_t mc_addr_low,
2713 uint32_t mc_addr_hi,
2714 uint32_t size)
2715 {
2716 smum_send_msg_to_smc_with_parameter(hwmgr,
2717 PPSMC_MSG_SetSystemVirtualDramAddrHigh,
2718 virtual_addr_hi,
2719 NULL);
2720 smum_send_msg_to_smc_with_parameter(hwmgr,
2721 PPSMC_MSG_SetSystemVirtualDramAddrLow,
2722 virtual_addr_low,
2723 NULL);
2724 smum_send_msg_to_smc_with_parameter(hwmgr,
2725 PPSMC_MSG_DramLogSetDramAddrHigh,
2726 mc_addr_hi,
2727 NULL);
2728
2729 smum_send_msg_to_smc_with_parameter(hwmgr,
2730 PPSMC_MSG_DramLogSetDramAddrLow,
2731 mc_addr_low,
2732 NULL);
2733
2734 smum_send_msg_to_smc_with_parameter(hwmgr,
2735 PPSMC_MSG_DramLogSetDramSize,
2736 size,
2737 NULL);
2738 return 0;
2739 }
2740
vega12_get_thermal_temperature_range(struct pp_hwmgr * hwmgr,struct PP_TemperatureRange * thermal_data)2741 static int vega12_get_thermal_temperature_range(struct pp_hwmgr *hwmgr,
2742 struct PP_TemperatureRange *thermal_data)
2743 {
2744 struct vega12_hwmgr *data =
2745 (struct vega12_hwmgr *)(hwmgr->backend);
2746 PPTable_t *pp_table = &(data->smc_state_table.pp_table);
2747
2748 memcpy(thermal_data, &SMU7ThermalWithDelayPolicy[0], sizeof(struct PP_TemperatureRange));
2749
2750 thermal_data->max = pp_table->TedgeLimit *
2751 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
2752 thermal_data->edge_emergency_max = (pp_table->TedgeLimit + CTF_OFFSET_EDGE) *
2753 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
2754 thermal_data->hotspot_crit_max = pp_table->ThotspotLimit *
2755 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
2756 thermal_data->hotspot_emergency_max = (pp_table->ThotspotLimit + CTF_OFFSET_HOTSPOT) *
2757 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
2758 thermal_data->mem_crit_max = pp_table->ThbmLimit *
2759 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
2760 thermal_data->mem_emergency_max = (pp_table->ThbmLimit + CTF_OFFSET_HBM)*
2761 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
2762
2763 return 0;
2764 }
2765
vega12_enable_gfx_off(struct pp_hwmgr * hwmgr)2766 static int vega12_enable_gfx_off(struct pp_hwmgr *hwmgr)
2767 {
2768 struct vega12_hwmgr *data =
2769 (struct vega12_hwmgr *)(hwmgr->backend);
2770 int ret = 0;
2771
2772 if (data->gfxoff_controlled_by_driver)
2773 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_AllowGfxOff, NULL);
2774
2775 return ret;
2776 }
2777
vega12_disable_gfx_off(struct pp_hwmgr * hwmgr)2778 static int vega12_disable_gfx_off(struct pp_hwmgr *hwmgr)
2779 {
2780 struct vega12_hwmgr *data =
2781 (struct vega12_hwmgr *)(hwmgr->backend);
2782 int ret = 0;
2783
2784 if (data->gfxoff_controlled_by_driver)
2785 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DisallowGfxOff, NULL);
2786
2787 return ret;
2788 }
2789
vega12_gfx_off_control(struct pp_hwmgr * hwmgr,bool enable)2790 static int vega12_gfx_off_control(struct pp_hwmgr *hwmgr, bool enable)
2791 {
2792 if (enable)
2793 return vega12_enable_gfx_off(hwmgr);
2794 else
2795 return vega12_disable_gfx_off(hwmgr);
2796 }
2797
vega12_get_performance_level(struct pp_hwmgr * hwmgr,const struct pp_hw_power_state * state,PHM_PerformanceLevelDesignation designation,uint32_t index,PHM_PerformanceLevel * level)2798 static int vega12_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state,
2799 PHM_PerformanceLevelDesignation designation, uint32_t index,
2800 PHM_PerformanceLevel *level)
2801 {
2802 return 0;
2803 }
2804
vega12_set_mp1_state(struct pp_hwmgr * hwmgr,enum pp_mp1_state mp1_state)2805 static int vega12_set_mp1_state(struct pp_hwmgr *hwmgr,
2806 enum pp_mp1_state mp1_state)
2807 {
2808 uint16_t msg;
2809 int ret;
2810
2811 switch (mp1_state) {
2812 case PP_MP1_STATE_UNLOAD:
2813 msg = PPSMC_MSG_PrepareMp1ForUnload;
2814 break;
2815 case PP_MP1_STATE_SHUTDOWN:
2816 case PP_MP1_STATE_RESET:
2817 case PP_MP1_STATE_NONE:
2818 default:
2819 return 0;
2820 }
2821
2822 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc(hwmgr, msg, NULL)) == 0,
2823 "[PrepareMp1] Failed!",
2824 return ret);
2825
2826 return 0;
2827 }
2828
vega12_init_gpu_metrics_v1_0(struct gpu_metrics_v1_0 * gpu_metrics)2829 static void vega12_init_gpu_metrics_v1_0(struct gpu_metrics_v1_0 *gpu_metrics)
2830 {
2831 memset(gpu_metrics, 0xFF, sizeof(struct gpu_metrics_v1_0));
2832
2833 gpu_metrics->common_header.structure_size =
2834 sizeof(struct gpu_metrics_v1_0);
2835 gpu_metrics->common_header.format_revision = 1;
2836 gpu_metrics->common_header.content_revision = 0;
2837
2838 gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
2839 }
2840
vega12_get_gpu_metrics(struct pp_hwmgr * hwmgr,void ** table)2841 static ssize_t vega12_get_gpu_metrics(struct pp_hwmgr *hwmgr,
2842 void **table)
2843 {
2844 struct vega12_hwmgr *data =
2845 (struct vega12_hwmgr *)(hwmgr->backend);
2846 struct gpu_metrics_v1_0 *gpu_metrics =
2847 &data->gpu_metrics_table;
2848 SmuMetrics_t metrics;
2849 uint32_t fan_speed_rpm;
2850 int ret;
2851
2852 ret = vega12_get_metrics_table(hwmgr, &metrics, true);
2853 if (ret)
2854 return ret;
2855
2856 vega12_init_gpu_metrics_v1_0(gpu_metrics);
2857
2858 gpu_metrics->temperature_edge = metrics.TemperatureEdge;
2859 gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot;
2860 gpu_metrics->temperature_mem = metrics.TemperatureHBM;
2861 gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx;
2862 gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem;
2863
2864 gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity;
2865 gpu_metrics->average_umc_activity = metrics.AverageUclkActivity;
2866
2867 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequency;
2868 gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency;
2869 gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequency;
2870
2871 gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK];
2872 gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK];
2873 gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK];
2874 gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK];
2875 gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK];
2876
2877 gpu_metrics->throttle_status = metrics.ThrottlerStatus;
2878
2879 vega12_fan_ctrl_get_fan_speed_rpm(hwmgr, &fan_speed_rpm);
2880 gpu_metrics->current_fan_speed = (uint16_t)fan_speed_rpm;
2881
2882 gpu_metrics->pcie_link_width =
2883 vega12_get_current_pcie_link_width(hwmgr);
2884 gpu_metrics->pcie_link_speed =
2885 vega12_get_current_pcie_link_speed(hwmgr);
2886
2887 *table = (void *)gpu_metrics;
2888
2889 return sizeof(struct gpu_metrics_v1_0);
2890 }
2891
2892 static const struct pp_hwmgr_func vega12_hwmgr_funcs = {
2893 .backend_init = vega12_hwmgr_backend_init,
2894 .backend_fini = vega12_hwmgr_backend_fini,
2895 .asic_setup = vega12_setup_asic_task,
2896 .dynamic_state_management_enable = vega12_enable_dpm_tasks,
2897 .dynamic_state_management_disable = vega12_disable_dpm_tasks,
2898 .patch_boot_state = vega12_patch_boot_state,
2899 .get_sclk = vega12_dpm_get_sclk,
2900 .get_mclk = vega12_dpm_get_mclk,
2901 .notify_smc_display_config_after_ps_adjustment =
2902 vega12_notify_smc_display_config_after_ps_adjustment,
2903 .force_dpm_level = vega12_dpm_force_dpm_level,
2904 .stop_thermal_controller = vega12_thermal_stop_thermal_controller,
2905 .get_fan_speed_info = vega12_fan_ctrl_get_fan_speed_info,
2906 .reset_fan_speed_to_default =
2907 vega12_fan_ctrl_reset_fan_speed_to_default,
2908 .get_fan_speed_rpm = vega12_fan_ctrl_get_fan_speed_rpm,
2909 .set_fan_control_mode = vega12_set_fan_control_mode,
2910 .get_fan_control_mode = vega12_get_fan_control_mode,
2911 .read_sensor = vega12_read_sensor,
2912 .get_dal_power_level = vega12_get_dal_power_level,
2913 .get_clock_by_type_with_latency = vega12_get_clock_by_type_with_latency,
2914 .get_clock_by_type_with_voltage = vega12_get_clock_by_type_with_voltage,
2915 .set_watermarks_for_clocks_ranges = vega12_set_watermarks_for_clocks_ranges,
2916 .display_clock_voltage_request = vega12_display_clock_voltage_request,
2917 .force_clock_level = vega12_force_clock_level,
2918 .print_clock_levels = vega12_print_clock_levels,
2919 .apply_clocks_adjust_rules =
2920 vega12_apply_clocks_adjust_rules,
2921 .pre_display_config_changed =
2922 vega12_pre_display_configuration_changed_task,
2923 .display_config_changed = vega12_display_configuration_changed_task,
2924 .powergate_uvd = vega12_power_gate_uvd,
2925 .powergate_vce = vega12_power_gate_vce,
2926 .check_smc_update_required_for_display_configuration =
2927 vega12_check_smc_update_required_for_display_configuration,
2928 .power_off_asic = vega12_power_off_asic,
2929 .disable_smc_firmware_ctf = vega12_thermal_disable_alert,
2930 #if 0
2931 .set_power_profile_state = vega12_set_power_profile_state,
2932 .get_sclk_od = vega12_get_sclk_od,
2933 .set_sclk_od = vega12_set_sclk_od,
2934 .get_mclk_od = vega12_get_mclk_od,
2935 .set_mclk_od = vega12_set_mclk_od,
2936 #endif
2937 .notify_cac_buffer_info = vega12_notify_cac_buffer_info,
2938 .get_thermal_temperature_range = vega12_get_thermal_temperature_range,
2939 .register_irq_handlers = smu9_register_irq_handlers,
2940 .start_thermal_controller = vega12_start_thermal_controller,
2941 .powergate_gfx = vega12_gfx_off_control,
2942 .get_performance_level = vega12_get_performance_level,
2943 .get_asic_baco_capability = smu9_baco_get_capability,
2944 .get_asic_baco_state = smu9_baco_get_state,
2945 .set_asic_baco_state = vega12_baco_set_state,
2946 .get_ppfeature_status = vega12_get_ppfeature_status,
2947 .set_ppfeature_status = vega12_set_ppfeature_status,
2948 .set_mp1_state = vega12_set_mp1_state,
2949 .get_gpu_metrics = vega12_get_gpu_metrics,
2950 };
2951
vega12_hwmgr_init(struct pp_hwmgr * hwmgr)2952 int vega12_hwmgr_init(struct pp_hwmgr *hwmgr)
2953 {
2954 hwmgr->hwmgr_func = &vega12_hwmgr_funcs;
2955 hwmgr->pptable_func = &vega12_pptable_funcs;
2956
2957 return 0;
2958 }
2959