1 /*
2 * Copyright (C) 2014 Broadcom Corporation
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation version 2.
7 *
8 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
9 * kind, whether express or implied; without even the implied warranty
10 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14 #include <linux/delay.h>
15 #include <linux/i2c.h>
16 #include <linux/interrupt.h>
17 #include <linux/io.h>
18 #include <linux/kernel.h>
19 #include <linux/module.h>
20 #include <linux/of_device.h>
21 #include <linux/platform_device.h>
22 #include <linux/slab.h>
23
24 #define IDM_CTRL_DIRECT_OFFSET 0x00
25 #define CFG_OFFSET 0x00
26 #define CFG_RESET_SHIFT 31
27 #define CFG_EN_SHIFT 30
28 #define CFG_SLAVE_ADDR_0_SHIFT 28
29 #define CFG_M_RETRY_CNT_SHIFT 16
30 #define CFG_M_RETRY_CNT_MASK 0x0f
31
32 #define TIM_CFG_OFFSET 0x04
33 #define TIM_CFG_MODE_400_SHIFT 31
34 #define TIM_RAND_SLAVE_STRETCH_SHIFT 24
35 #define TIM_RAND_SLAVE_STRETCH_MASK 0x7f
36 #define TIM_PERIODIC_SLAVE_STRETCH_SHIFT 16
37 #define TIM_PERIODIC_SLAVE_STRETCH_MASK 0x7f
38
39 #define S_CFG_SMBUS_ADDR_OFFSET 0x08
40 #define S_CFG_EN_NIC_SMB_ADDR3_SHIFT 31
41 #define S_CFG_NIC_SMB_ADDR3_SHIFT 24
42 #define S_CFG_NIC_SMB_ADDR3_MASK 0x7f
43 #define S_CFG_EN_NIC_SMB_ADDR2_SHIFT 23
44 #define S_CFG_NIC_SMB_ADDR2_SHIFT 16
45 #define S_CFG_NIC_SMB_ADDR2_MASK 0x7f
46 #define S_CFG_EN_NIC_SMB_ADDR1_SHIFT 15
47 #define S_CFG_NIC_SMB_ADDR1_SHIFT 8
48 #define S_CFG_NIC_SMB_ADDR1_MASK 0x7f
49 #define S_CFG_EN_NIC_SMB_ADDR0_SHIFT 7
50 #define S_CFG_NIC_SMB_ADDR0_SHIFT 0
51 #define S_CFG_NIC_SMB_ADDR0_MASK 0x7f
52
53 #define M_FIFO_CTRL_OFFSET 0x0c
54 #define M_FIFO_RX_FLUSH_SHIFT 31
55 #define M_FIFO_TX_FLUSH_SHIFT 30
56 #define M_FIFO_RX_CNT_SHIFT 16
57 #define M_FIFO_RX_CNT_MASK 0x7f
58 #define M_FIFO_RX_THLD_SHIFT 8
59 #define M_FIFO_RX_THLD_MASK 0x3f
60
61 #define S_FIFO_CTRL_OFFSET 0x10
62 #define S_FIFO_RX_FLUSH_SHIFT 31
63 #define S_FIFO_TX_FLUSH_SHIFT 30
64 #define S_FIFO_RX_CNT_SHIFT 16
65 #define S_FIFO_RX_CNT_MASK 0x7f
66 #define S_FIFO_RX_THLD_SHIFT 8
67 #define S_FIFO_RX_THLD_MASK 0x3f
68
69 #define M_CMD_OFFSET 0x30
70 #define M_CMD_START_BUSY_SHIFT 31
71 #define M_CMD_STATUS_SHIFT 25
72 #define M_CMD_STATUS_MASK 0x07
73 #define M_CMD_STATUS_SUCCESS 0x0
74 #define M_CMD_STATUS_LOST_ARB 0x1
75 #define M_CMD_STATUS_NACK_ADDR 0x2
76 #define M_CMD_STATUS_NACK_DATA 0x3
77 #define M_CMD_STATUS_TIMEOUT 0x4
78 #define M_CMD_STATUS_FIFO_UNDERRUN 0x5
79 #define M_CMD_STATUS_RX_FIFO_FULL 0x6
80 #define M_CMD_PROTOCOL_SHIFT 9
81 #define M_CMD_PROTOCOL_MASK 0xf
82 #define M_CMD_PROTOCOL_QUICK 0x0
83 #define M_CMD_PROTOCOL_BLK_WR 0x7
84 #define M_CMD_PROTOCOL_BLK_RD 0x8
85 #define M_CMD_PROTOCOL_PROCESS 0xa
86 #define M_CMD_PEC_SHIFT 8
87 #define M_CMD_RD_CNT_SHIFT 0
88 #define M_CMD_RD_CNT_MASK 0xff
89
90 #define S_CMD_OFFSET 0x34
91 #define S_CMD_START_BUSY_SHIFT 31
92 #define S_CMD_STATUS_SHIFT 23
93 #define S_CMD_STATUS_MASK 0x07
94 #define S_CMD_STATUS_SUCCESS 0x0
95 #define S_CMD_STATUS_TIMEOUT 0x5
96
97 #define IE_OFFSET 0x38
98 #define IE_M_RX_FIFO_FULL_SHIFT 31
99 #define IE_M_RX_THLD_SHIFT 30
100 #define IE_M_START_BUSY_SHIFT 28
101 #define IE_M_TX_UNDERRUN_SHIFT 27
102 #define IE_S_RX_FIFO_FULL_SHIFT 26
103 #define IE_S_RX_THLD_SHIFT 25
104 #define IE_S_RX_EVENT_SHIFT 24
105 #define IE_S_START_BUSY_SHIFT 23
106 #define IE_S_TX_UNDERRUN_SHIFT 22
107 #define IE_S_RD_EVENT_SHIFT 21
108
109 #define IS_OFFSET 0x3c
110 #define IS_M_RX_FIFO_FULL_SHIFT 31
111 #define IS_M_RX_THLD_SHIFT 30
112 #define IS_M_START_BUSY_SHIFT 28
113 #define IS_M_TX_UNDERRUN_SHIFT 27
114 #define IS_S_RX_FIFO_FULL_SHIFT 26
115 #define IS_S_RX_THLD_SHIFT 25
116 #define IS_S_RX_EVENT_SHIFT 24
117 #define IS_S_START_BUSY_SHIFT 23
118 #define IS_S_TX_UNDERRUN_SHIFT 22
119 #define IS_S_RD_EVENT_SHIFT 21
120
121 #define M_TX_OFFSET 0x40
122 #define M_TX_WR_STATUS_SHIFT 31
123 #define M_TX_DATA_SHIFT 0
124 #define M_TX_DATA_MASK 0xff
125
126 #define M_RX_OFFSET 0x44
127 #define M_RX_STATUS_SHIFT 30
128 #define M_RX_STATUS_MASK 0x03
129 #define M_RX_PEC_ERR_SHIFT 29
130 #define M_RX_DATA_SHIFT 0
131 #define M_RX_DATA_MASK 0xff
132
133 #define S_TX_OFFSET 0x48
134 #define S_TX_WR_STATUS_SHIFT 31
135 #define S_TX_DATA_SHIFT 0
136 #define S_TX_DATA_MASK 0xff
137
138 #define S_RX_OFFSET 0x4c
139 #define S_RX_STATUS_SHIFT 30
140 #define S_RX_STATUS_MASK 0x03
141 #define S_RX_PEC_ERR_SHIFT 29
142 #define S_RX_DATA_SHIFT 0
143 #define S_RX_DATA_MASK 0xff
144
145 #define I2C_TIMEOUT_MSEC 50000
146 #define M_TX_RX_FIFO_SIZE 64
147 #define M_RX_FIFO_MAX_THLD_VALUE (M_TX_RX_FIFO_SIZE - 1)
148
149 #define M_RX_MAX_READ_LEN 255
150 #define M_RX_FIFO_THLD_VALUE 50
151
152 #define IE_M_ALL_INTERRUPT_SHIFT 27
153 #define IE_M_ALL_INTERRUPT_MASK 0x1e
154
155 #define SLAVE_READ_WRITE_BIT_MASK 0x1
156 #define SLAVE_READ_WRITE_BIT_SHIFT 0x1
157 #define SLAVE_MAX_SIZE_TRANSACTION 64
158 #define SLAVE_CLOCK_STRETCH_TIME 25
159
160 #define IE_S_ALL_INTERRUPT_SHIFT 21
161 #define IE_S_ALL_INTERRUPT_MASK 0x3f
162 /*
163 * It takes ~18us to reading 10bytes of data, hence to keep tasklet
164 * running for less time, max slave read per tasklet is set to 10 bytes.
165 */
166 #define MAX_SLAVE_RX_PER_INT 10
167
168 enum i2c_slave_read_status {
169 I2C_SLAVE_RX_FIFO_EMPTY = 0,
170 I2C_SLAVE_RX_START,
171 I2C_SLAVE_RX_DATA,
172 I2C_SLAVE_RX_END,
173 };
174
175 enum bus_speed_index {
176 I2C_SPD_100K = 0,
177 I2C_SPD_400K,
178 };
179
180 enum bcm_iproc_i2c_type {
181 IPROC_I2C,
182 IPROC_I2C_NIC
183 };
184
185 struct bcm_iproc_i2c_dev {
186 struct device *device;
187 enum bcm_iproc_i2c_type type;
188 int irq;
189
190 void __iomem *base;
191 void __iomem *idm_base;
192
193 u32 ape_addr_mask;
194
195 /* lock for indirect access through IDM */
196 spinlock_t idm_lock;
197
198 struct i2c_adapter adapter;
199 unsigned int bus_speed;
200
201 struct completion done;
202 int xfer_is_done;
203
204 struct i2c_msg *msg;
205
206 struct i2c_client *slave;
207
208 /* bytes that have been transferred */
209 unsigned int tx_bytes;
210 /* bytes that have been read */
211 unsigned int rx_bytes;
212 unsigned int thld_bytes;
213
214 bool slave_rx_only;
215 bool rx_start_rcvd;
216 bool slave_read_complete;
217 u32 tx_underrun;
218 u32 slave_int_mask;
219 struct tasklet_struct slave_rx_tasklet;
220 };
221
222 /* tasklet to process slave rx data */
223 static void slave_rx_tasklet_fn(unsigned long);
224
225 /*
226 * Can be expanded in the future if more interrupt status bits are utilized
227 */
228 #define ISR_MASK (BIT(IS_M_START_BUSY_SHIFT) | BIT(IS_M_TX_UNDERRUN_SHIFT)\
229 | BIT(IS_M_RX_THLD_SHIFT))
230
231 #define ISR_MASK_SLAVE (BIT(IS_S_START_BUSY_SHIFT)\
232 | BIT(IS_S_RX_EVENT_SHIFT) | BIT(IS_S_RD_EVENT_SHIFT)\
233 | BIT(IS_S_TX_UNDERRUN_SHIFT) | BIT(IS_S_RX_FIFO_FULL_SHIFT)\
234 | BIT(IS_S_RX_THLD_SHIFT))
235
236 static int bcm_iproc_i2c_reg_slave(struct i2c_client *slave);
237 static int bcm_iproc_i2c_unreg_slave(struct i2c_client *slave);
238 static void bcm_iproc_i2c_enable_disable(struct bcm_iproc_i2c_dev *iproc_i2c,
239 bool enable);
240
iproc_i2c_rd_reg(struct bcm_iproc_i2c_dev * iproc_i2c,u32 offset)241 static inline u32 iproc_i2c_rd_reg(struct bcm_iproc_i2c_dev *iproc_i2c,
242 u32 offset)
243 {
244 u32 val;
245
246 if (iproc_i2c->idm_base) {
247 spin_lock(&iproc_i2c->idm_lock);
248 writel(iproc_i2c->ape_addr_mask,
249 iproc_i2c->idm_base + IDM_CTRL_DIRECT_OFFSET);
250 val = readl(iproc_i2c->base + offset);
251 spin_unlock(&iproc_i2c->idm_lock);
252 } else {
253 val = readl(iproc_i2c->base + offset);
254 }
255
256 return val;
257 }
258
iproc_i2c_wr_reg(struct bcm_iproc_i2c_dev * iproc_i2c,u32 offset,u32 val)259 static inline void iproc_i2c_wr_reg(struct bcm_iproc_i2c_dev *iproc_i2c,
260 u32 offset, u32 val)
261 {
262 if (iproc_i2c->idm_base) {
263 spin_lock(&iproc_i2c->idm_lock);
264 writel(iproc_i2c->ape_addr_mask,
265 iproc_i2c->idm_base + IDM_CTRL_DIRECT_OFFSET);
266 writel(val, iproc_i2c->base + offset);
267 spin_unlock(&iproc_i2c->idm_lock);
268 } else {
269 writel(val, iproc_i2c->base + offset);
270 }
271 }
272
bcm_iproc_i2c_slave_init(struct bcm_iproc_i2c_dev * iproc_i2c,bool need_reset)273 static void bcm_iproc_i2c_slave_init(
274 struct bcm_iproc_i2c_dev *iproc_i2c, bool need_reset)
275 {
276 u32 val;
277
278 iproc_i2c->tx_underrun = 0;
279 if (need_reset) {
280 /* put controller in reset */
281 val = iproc_i2c_rd_reg(iproc_i2c, CFG_OFFSET);
282 val |= BIT(CFG_RESET_SHIFT);
283 iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val);
284
285 /* wait 100 usec per spec */
286 udelay(100);
287
288 /* bring controller out of reset */
289 val &= ~(BIT(CFG_RESET_SHIFT));
290 iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val);
291 }
292
293 /* flush TX/RX FIFOs */
294 val = (BIT(S_FIFO_RX_FLUSH_SHIFT) | BIT(S_FIFO_TX_FLUSH_SHIFT));
295 iproc_i2c_wr_reg(iproc_i2c, S_FIFO_CTRL_OFFSET, val);
296
297 /* Maximum slave stretch time */
298 val = iproc_i2c_rd_reg(iproc_i2c, TIM_CFG_OFFSET);
299 val &= ~(TIM_RAND_SLAVE_STRETCH_MASK << TIM_RAND_SLAVE_STRETCH_SHIFT);
300 val |= (SLAVE_CLOCK_STRETCH_TIME << TIM_RAND_SLAVE_STRETCH_SHIFT);
301 iproc_i2c_wr_reg(iproc_i2c, TIM_CFG_OFFSET, val);
302
303 /* Configure the slave address */
304 val = iproc_i2c_rd_reg(iproc_i2c, S_CFG_SMBUS_ADDR_OFFSET);
305 val |= BIT(S_CFG_EN_NIC_SMB_ADDR3_SHIFT);
306 val &= ~(S_CFG_NIC_SMB_ADDR3_MASK << S_CFG_NIC_SMB_ADDR3_SHIFT);
307 val |= (iproc_i2c->slave->addr << S_CFG_NIC_SMB_ADDR3_SHIFT);
308 iproc_i2c_wr_reg(iproc_i2c, S_CFG_SMBUS_ADDR_OFFSET, val);
309
310 /* clear all pending slave interrupts */
311 iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, ISR_MASK_SLAVE);
312
313 /* Enable interrupt register to indicate a valid byte in receive fifo */
314 val = BIT(IE_S_RX_EVENT_SHIFT);
315 /* Enable interrupt register to indicate a Master read transaction */
316 val |= BIT(IE_S_RD_EVENT_SHIFT);
317 /* Enable interrupt register for the Slave BUSY command */
318 val |= BIT(IE_S_START_BUSY_SHIFT);
319 iproc_i2c->slave_int_mask = val;
320 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val);
321 }
322
bcm_iproc_i2c_check_slave_status(struct bcm_iproc_i2c_dev * iproc_i2c)323 static void bcm_iproc_i2c_check_slave_status(
324 struct bcm_iproc_i2c_dev *iproc_i2c)
325 {
326 u32 val;
327
328 val = iproc_i2c_rd_reg(iproc_i2c, S_CMD_OFFSET);
329 /* status is valid only when START_BUSY is cleared after it was set */
330 if (val & BIT(S_CMD_START_BUSY_SHIFT))
331 return;
332
333 val = (val >> S_CMD_STATUS_SHIFT) & S_CMD_STATUS_MASK;
334 if (val == S_CMD_STATUS_TIMEOUT) {
335 dev_err(iproc_i2c->device, "slave random stretch time timeout\n");
336
337 /* re-initialize i2c for recovery */
338 bcm_iproc_i2c_enable_disable(iproc_i2c, false);
339 bcm_iproc_i2c_slave_init(iproc_i2c, true);
340 bcm_iproc_i2c_enable_disable(iproc_i2c, true);
341 }
342 }
343
bcm_iproc_i2c_slave_read(struct bcm_iproc_i2c_dev * iproc_i2c)344 static void bcm_iproc_i2c_slave_read(struct bcm_iproc_i2c_dev *iproc_i2c)
345 {
346 u8 rx_data, rx_status;
347 u32 rx_bytes = 0;
348 u32 val;
349
350 while (rx_bytes < MAX_SLAVE_RX_PER_INT) {
351 val = iproc_i2c_rd_reg(iproc_i2c, S_RX_OFFSET);
352 rx_status = (val >> S_RX_STATUS_SHIFT) & S_RX_STATUS_MASK;
353 rx_data = ((val >> S_RX_DATA_SHIFT) & S_RX_DATA_MASK);
354
355 if (rx_status == I2C_SLAVE_RX_START) {
356 /* Start of SMBUS Master write */
357 i2c_slave_event(iproc_i2c->slave,
358 I2C_SLAVE_WRITE_REQUESTED, &rx_data);
359 iproc_i2c->rx_start_rcvd = true;
360 iproc_i2c->slave_read_complete = false;
361 } else if (rx_status == I2C_SLAVE_RX_DATA &&
362 iproc_i2c->rx_start_rcvd) {
363 /* Middle of SMBUS Master write */
364 i2c_slave_event(iproc_i2c->slave,
365 I2C_SLAVE_WRITE_RECEIVED, &rx_data);
366 } else if (rx_status == I2C_SLAVE_RX_END &&
367 iproc_i2c->rx_start_rcvd) {
368 /* End of SMBUS Master write */
369 if (iproc_i2c->slave_rx_only)
370 i2c_slave_event(iproc_i2c->slave,
371 I2C_SLAVE_WRITE_RECEIVED,
372 &rx_data);
373
374 i2c_slave_event(iproc_i2c->slave, I2C_SLAVE_STOP,
375 &rx_data);
376 } else if (rx_status == I2C_SLAVE_RX_FIFO_EMPTY) {
377 iproc_i2c->rx_start_rcvd = false;
378 iproc_i2c->slave_read_complete = true;
379 break;
380 }
381
382 rx_bytes++;
383 }
384 }
385
slave_rx_tasklet_fn(unsigned long data)386 static void slave_rx_tasklet_fn(unsigned long data)
387 {
388 struct bcm_iproc_i2c_dev *iproc_i2c = (struct bcm_iproc_i2c_dev *)data;
389 u32 int_clr;
390
391 bcm_iproc_i2c_slave_read(iproc_i2c);
392
393 /* clear pending IS_S_RX_EVENT_SHIFT interrupt */
394 int_clr = BIT(IS_S_RX_EVENT_SHIFT);
395
396 if (!iproc_i2c->slave_rx_only && iproc_i2c->slave_read_complete) {
397 /*
398 * In case of single byte master-read request,
399 * IS_S_TX_UNDERRUN_SHIFT event is generated before
400 * IS_S_START_BUSY_SHIFT event. Hence start slave data send
401 * from first IS_S_TX_UNDERRUN_SHIFT event.
402 *
403 * This means don't send any data from slave when
404 * IS_S_RD_EVENT_SHIFT event is generated else it will increment
405 * eeprom or other backend slave driver read pointer twice.
406 */
407 iproc_i2c->tx_underrun = 0;
408 iproc_i2c->slave_int_mask |= BIT(IE_S_TX_UNDERRUN_SHIFT);
409
410 /* clear IS_S_RD_EVENT_SHIFT interrupt */
411 int_clr |= BIT(IS_S_RD_EVENT_SHIFT);
412 }
413
414 /* clear slave interrupt */
415 iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, int_clr);
416 /* enable slave interrupts */
417 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, iproc_i2c->slave_int_mask);
418 }
419
bcm_iproc_i2c_slave_isr(struct bcm_iproc_i2c_dev * iproc_i2c,u32 status)420 static bool bcm_iproc_i2c_slave_isr(struct bcm_iproc_i2c_dev *iproc_i2c,
421 u32 status)
422 {
423 u32 val;
424 u8 value;
425
426 /*
427 * Slave events in case of master-write, master-write-read and,
428 * master-read
429 *
430 * Master-write : only IS_S_RX_EVENT_SHIFT event
431 * Master-write-read: both IS_S_RX_EVENT_SHIFT and IS_S_RD_EVENT_SHIFT
432 * events
433 * Master-read : both IS_S_RX_EVENT_SHIFT and IS_S_RD_EVENT_SHIFT
434 * events or only IS_S_RD_EVENT_SHIFT
435 */
436 if (status & BIT(IS_S_RX_EVENT_SHIFT) ||
437 status & BIT(IS_S_RD_EVENT_SHIFT)) {
438 /* disable slave interrupts */
439 val = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
440 val &= ~iproc_i2c->slave_int_mask;
441 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val);
442
443 if (status & BIT(IS_S_RD_EVENT_SHIFT))
444 /* Master-write-read request */
445 iproc_i2c->slave_rx_only = false;
446 else
447 /* Master-write request only */
448 iproc_i2c->slave_rx_only = true;
449
450 /* schedule tasklet to read data later */
451 tasklet_schedule(&iproc_i2c->slave_rx_tasklet);
452
453 /* clear only IS_S_RX_EVENT_SHIFT interrupt */
454 iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET,
455 BIT(IS_S_RX_EVENT_SHIFT));
456 }
457
458 if (status & BIT(IS_S_TX_UNDERRUN_SHIFT)) {
459 iproc_i2c->tx_underrun++;
460 if (iproc_i2c->tx_underrun == 1)
461 /* Start of SMBUS for Master Read */
462 i2c_slave_event(iproc_i2c->slave,
463 I2C_SLAVE_READ_REQUESTED,
464 &value);
465 else
466 /* Master read other than start */
467 i2c_slave_event(iproc_i2c->slave,
468 I2C_SLAVE_READ_PROCESSED,
469 &value);
470
471 iproc_i2c_wr_reg(iproc_i2c, S_TX_OFFSET, value);
472 /* start transfer */
473 val = BIT(S_CMD_START_BUSY_SHIFT);
474 iproc_i2c_wr_reg(iproc_i2c, S_CMD_OFFSET, val);
475
476 /* clear interrupt */
477 iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET,
478 BIT(IS_S_TX_UNDERRUN_SHIFT));
479 }
480
481 /* Stop received from master in case of master read transaction */
482 if (status & BIT(IS_S_START_BUSY_SHIFT)) {
483 /*
484 * Enable interrupt for TX FIFO becomes empty and
485 * less than PKT_LENGTH bytes were output on the SMBUS
486 */
487 iproc_i2c->slave_int_mask &= ~BIT(IE_S_TX_UNDERRUN_SHIFT);
488 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET,
489 iproc_i2c->slave_int_mask);
490
491 /* End of SMBUS for Master Read */
492 val = BIT(S_TX_WR_STATUS_SHIFT);
493 iproc_i2c_wr_reg(iproc_i2c, S_TX_OFFSET, val);
494
495 val = BIT(S_CMD_START_BUSY_SHIFT);
496 iproc_i2c_wr_reg(iproc_i2c, S_CMD_OFFSET, val);
497
498 /* flush TX FIFOs */
499 val = iproc_i2c_rd_reg(iproc_i2c, S_FIFO_CTRL_OFFSET);
500 val |= (BIT(S_FIFO_TX_FLUSH_SHIFT));
501 iproc_i2c_wr_reg(iproc_i2c, S_FIFO_CTRL_OFFSET, val);
502
503 i2c_slave_event(iproc_i2c->slave, I2C_SLAVE_STOP, &value);
504
505 /* clear interrupt */
506 iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET,
507 BIT(IS_S_START_BUSY_SHIFT));
508 }
509
510 /* check slave transmit status only if slave is transmitting */
511 if (!iproc_i2c->slave_rx_only)
512 bcm_iproc_i2c_check_slave_status(iproc_i2c);
513
514 return true;
515 }
516
bcm_iproc_i2c_read_valid_bytes(struct bcm_iproc_i2c_dev * iproc_i2c)517 static void bcm_iproc_i2c_read_valid_bytes(struct bcm_iproc_i2c_dev *iproc_i2c)
518 {
519 struct i2c_msg *msg = iproc_i2c->msg;
520 uint32_t val;
521
522 /* Read valid data from RX FIFO */
523 while (iproc_i2c->rx_bytes < msg->len) {
524 val = iproc_i2c_rd_reg(iproc_i2c, M_RX_OFFSET);
525
526 /* rx fifo empty */
527 if (!((val >> M_RX_STATUS_SHIFT) & M_RX_STATUS_MASK))
528 break;
529
530 msg->buf[iproc_i2c->rx_bytes] =
531 (val >> M_RX_DATA_SHIFT) & M_RX_DATA_MASK;
532 iproc_i2c->rx_bytes++;
533 }
534 }
535
bcm_iproc_i2c_send(struct bcm_iproc_i2c_dev * iproc_i2c)536 static void bcm_iproc_i2c_send(struct bcm_iproc_i2c_dev *iproc_i2c)
537 {
538 struct i2c_msg *msg = iproc_i2c->msg;
539 unsigned int tx_bytes = msg->len - iproc_i2c->tx_bytes;
540 unsigned int i;
541 u32 val;
542
543 /* can only fill up to the FIFO size */
544 tx_bytes = min_t(unsigned int, tx_bytes, M_TX_RX_FIFO_SIZE);
545 for (i = 0; i < tx_bytes; i++) {
546 /* start from where we left over */
547 unsigned int idx = iproc_i2c->tx_bytes + i;
548
549 val = msg->buf[idx];
550
551 /* mark the last byte */
552 if (idx == msg->len - 1) {
553 val |= BIT(M_TX_WR_STATUS_SHIFT);
554
555 if (iproc_i2c->irq) {
556 u32 tmp;
557
558 /*
559 * Since this is the last byte, we should now
560 * disable TX FIFO underrun interrupt
561 */
562 tmp = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
563 tmp &= ~BIT(IE_M_TX_UNDERRUN_SHIFT);
564 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET,
565 tmp);
566 }
567 }
568
569 /* load data into TX FIFO */
570 iproc_i2c_wr_reg(iproc_i2c, M_TX_OFFSET, val);
571 }
572
573 /* update number of transferred bytes */
574 iproc_i2c->tx_bytes += tx_bytes;
575 }
576
bcm_iproc_i2c_read(struct bcm_iproc_i2c_dev * iproc_i2c)577 static void bcm_iproc_i2c_read(struct bcm_iproc_i2c_dev *iproc_i2c)
578 {
579 struct i2c_msg *msg = iproc_i2c->msg;
580 u32 bytes_left, val;
581
582 bcm_iproc_i2c_read_valid_bytes(iproc_i2c);
583 bytes_left = msg->len - iproc_i2c->rx_bytes;
584 if (bytes_left == 0) {
585 if (iproc_i2c->irq) {
586 /* finished reading all data, disable rx thld event */
587 val = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
588 val &= ~BIT(IS_M_RX_THLD_SHIFT);
589 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val);
590 }
591 } else if (bytes_left < iproc_i2c->thld_bytes) {
592 /* set bytes left as threshold */
593 val = iproc_i2c_rd_reg(iproc_i2c, M_FIFO_CTRL_OFFSET);
594 val &= ~(M_FIFO_RX_THLD_MASK << M_FIFO_RX_THLD_SHIFT);
595 val |= (bytes_left << M_FIFO_RX_THLD_SHIFT);
596 iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, val);
597 iproc_i2c->thld_bytes = bytes_left;
598 }
599 /*
600 * bytes_left >= iproc_i2c->thld_bytes,
601 * hence no need to change the THRESHOLD SET.
602 * It will remain as iproc_i2c->thld_bytes itself
603 */
604 }
605
bcm_iproc_i2c_process_m_event(struct bcm_iproc_i2c_dev * iproc_i2c,u32 status)606 static void bcm_iproc_i2c_process_m_event(struct bcm_iproc_i2c_dev *iproc_i2c,
607 u32 status)
608 {
609 /* TX FIFO is empty and we have more data to send */
610 if (status & BIT(IS_M_TX_UNDERRUN_SHIFT))
611 bcm_iproc_i2c_send(iproc_i2c);
612
613 /* RX FIFO threshold is reached and data needs to be read out */
614 if (status & BIT(IS_M_RX_THLD_SHIFT))
615 bcm_iproc_i2c_read(iproc_i2c);
616
617 /* transfer is done */
618 if (status & BIT(IS_M_START_BUSY_SHIFT)) {
619 iproc_i2c->xfer_is_done = 1;
620 if (iproc_i2c->irq)
621 complete(&iproc_i2c->done);
622 }
623 }
624
bcm_iproc_i2c_isr(int irq,void * data)625 static irqreturn_t bcm_iproc_i2c_isr(int irq, void *data)
626 {
627 struct bcm_iproc_i2c_dev *iproc_i2c = data;
628 u32 slave_status;
629 u32 status;
630 bool ret;
631
632 status = iproc_i2c_rd_reg(iproc_i2c, IS_OFFSET);
633 /* process only slave interrupt which are enabled */
634 slave_status = status & iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET) &
635 ISR_MASK_SLAVE;
636
637 if (slave_status) {
638 ret = bcm_iproc_i2c_slave_isr(iproc_i2c, slave_status);
639 if (ret)
640 return IRQ_HANDLED;
641 else
642 return IRQ_NONE;
643 }
644
645 status &= ISR_MASK;
646 if (!status)
647 return IRQ_NONE;
648
649 /* process all master based events */
650 bcm_iproc_i2c_process_m_event(iproc_i2c, status);
651 iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, status);
652
653 return IRQ_HANDLED;
654 }
655
bcm_iproc_i2c_init(struct bcm_iproc_i2c_dev * iproc_i2c)656 static int bcm_iproc_i2c_init(struct bcm_iproc_i2c_dev *iproc_i2c)
657 {
658 u32 val;
659
660 /* put controller in reset */
661 val = iproc_i2c_rd_reg(iproc_i2c, CFG_OFFSET);
662 val |= BIT(CFG_RESET_SHIFT);
663 val &= ~(BIT(CFG_EN_SHIFT));
664 iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val);
665
666 /* wait 100 usec per spec */
667 udelay(100);
668
669 /* bring controller out of reset */
670 val &= ~(BIT(CFG_RESET_SHIFT));
671 iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val);
672
673 /* flush TX/RX FIFOs and set RX FIFO threshold to zero */
674 val = (BIT(M_FIFO_RX_FLUSH_SHIFT) | BIT(M_FIFO_TX_FLUSH_SHIFT));
675 iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, val);
676 /* disable all interrupts */
677 val = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
678 val &= ~(IE_M_ALL_INTERRUPT_MASK <<
679 IE_M_ALL_INTERRUPT_SHIFT);
680 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val);
681
682 /* clear all pending interrupts */
683 iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, 0xffffffff);
684
685 return 0;
686 }
687
bcm_iproc_i2c_enable_disable(struct bcm_iproc_i2c_dev * iproc_i2c,bool enable)688 static void bcm_iproc_i2c_enable_disable(struct bcm_iproc_i2c_dev *iproc_i2c,
689 bool enable)
690 {
691 u32 val;
692
693 val = iproc_i2c_rd_reg(iproc_i2c, CFG_OFFSET);
694 if (enable)
695 val |= BIT(CFG_EN_SHIFT);
696 else
697 val &= ~BIT(CFG_EN_SHIFT);
698 iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val);
699 }
700
bcm_iproc_i2c_check_status(struct bcm_iproc_i2c_dev * iproc_i2c,struct i2c_msg * msg)701 static int bcm_iproc_i2c_check_status(struct bcm_iproc_i2c_dev *iproc_i2c,
702 struct i2c_msg *msg)
703 {
704 u32 val;
705
706 val = iproc_i2c_rd_reg(iproc_i2c, M_CMD_OFFSET);
707 val = (val >> M_CMD_STATUS_SHIFT) & M_CMD_STATUS_MASK;
708
709 switch (val) {
710 case M_CMD_STATUS_SUCCESS:
711 return 0;
712
713 case M_CMD_STATUS_LOST_ARB:
714 dev_dbg(iproc_i2c->device, "lost bus arbitration\n");
715 return -EAGAIN;
716
717 case M_CMD_STATUS_NACK_ADDR:
718 dev_dbg(iproc_i2c->device, "NAK addr:0x%02x\n", msg->addr);
719 return -ENXIO;
720
721 case M_CMD_STATUS_NACK_DATA:
722 dev_dbg(iproc_i2c->device, "NAK data\n");
723 return -ENXIO;
724
725 case M_CMD_STATUS_TIMEOUT:
726 dev_dbg(iproc_i2c->device, "bus timeout\n");
727 return -ETIMEDOUT;
728
729 case M_CMD_STATUS_FIFO_UNDERRUN:
730 dev_dbg(iproc_i2c->device, "FIFO under-run\n");
731 return -ENXIO;
732
733 case M_CMD_STATUS_RX_FIFO_FULL:
734 dev_dbg(iproc_i2c->device, "RX FIFO full\n");
735 return -ETIMEDOUT;
736
737 default:
738 dev_dbg(iproc_i2c->device, "unknown error code=%d\n", val);
739
740 /* re-initialize i2c for recovery */
741 bcm_iproc_i2c_enable_disable(iproc_i2c, false);
742 bcm_iproc_i2c_init(iproc_i2c);
743 bcm_iproc_i2c_enable_disable(iproc_i2c, true);
744
745 return -EIO;
746 }
747 }
748
bcm_iproc_i2c_xfer_wait(struct bcm_iproc_i2c_dev * iproc_i2c,struct i2c_msg * msg,u32 cmd)749 static int bcm_iproc_i2c_xfer_wait(struct bcm_iproc_i2c_dev *iproc_i2c,
750 struct i2c_msg *msg,
751 u32 cmd)
752 {
753 unsigned long time_left = msecs_to_jiffies(I2C_TIMEOUT_MSEC);
754 u32 val, status;
755 int ret;
756
757 iproc_i2c_wr_reg(iproc_i2c, M_CMD_OFFSET, cmd);
758
759 if (iproc_i2c->irq) {
760 time_left = wait_for_completion_timeout(&iproc_i2c->done,
761 time_left);
762 /* disable all interrupts */
763 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, 0);
764 /* read it back to flush the write */
765 iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
766 /* make sure the interrupt handler isn't running */
767 synchronize_irq(iproc_i2c->irq);
768
769 } else { /* polling mode */
770 unsigned long timeout = jiffies + time_left;
771
772 do {
773 status = iproc_i2c_rd_reg(iproc_i2c,
774 IS_OFFSET) & ISR_MASK;
775 bcm_iproc_i2c_process_m_event(iproc_i2c, status);
776 iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, status);
777
778 if (time_after(jiffies, timeout)) {
779 time_left = 0;
780 break;
781 }
782
783 cpu_relax();
784 cond_resched();
785 } while (!iproc_i2c->xfer_is_done);
786 }
787
788 if (!time_left && !iproc_i2c->xfer_is_done) {
789 dev_err(iproc_i2c->device, "transaction timed out\n");
790
791 /* flush both TX/RX FIFOs */
792 val = BIT(M_FIFO_RX_FLUSH_SHIFT) | BIT(M_FIFO_TX_FLUSH_SHIFT);
793 iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, val);
794 return -ETIMEDOUT;
795 }
796
797 ret = bcm_iproc_i2c_check_status(iproc_i2c, msg);
798 if (ret) {
799 /* flush both TX/RX FIFOs */
800 val = BIT(M_FIFO_RX_FLUSH_SHIFT) | BIT(M_FIFO_TX_FLUSH_SHIFT);
801 iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, val);
802 return ret;
803 }
804
805 return 0;
806 }
807
808 /*
809 * If 'process_call' is true, then this is a multi-msg transfer that requires
810 * a repeated start between the messages.
811 * More specifically, it must be a write (reg) followed by a read (data).
812 * The i2c quirks are set to enforce this rule.
813 */
bcm_iproc_i2c_xfer_internal(struct bcm_iproc_i2c_dev * iproc_i2c,struct i2c_msg * msgs,bool process_call)814 static int bcm_iproc_i2c_xfer_internal(struct bcm_iproc_i2c_dev *iproc_i2c,
815 struct i2c_msg *msgs, bool process_call)
816 {
817 int i;
818 u8 addr;
819 u32 val, tmp, val_intr_en;
820 unsigned int tx_bytes;
821 struct i2c_msg *msg = &msgs[0];
822
823 /* check if bus is busy */
824 if (!!(iproc_i2c_rd_reg(iproc_i2c,
825 M_CMD_OFFSET) & BIT(M_CMD_START_BUSY_SHIFT))) {
826 dev_warn(iproc_i2c->device, "bus is busy\n");
827 return -EBUSY;
828 }
829
830 iproc_i2c->msg = msg;
831
832 /* format and load slave address into the TX FIFO */
833 addr = i2c_8bit_addr_from_msg(msg);
834 iproc_i2c_wr_reg(iproc_i2c, M_TX_OFFSET, addr);
835
836 /*
837 * For a write transaction, load data into the TX FIFO. Only allow
838 * loading up to TX FIFO size - 1 bytes of data since the first byte
839 * has been used up by the slave address
840 */
841 tx_bytes = min_t(unsigned int, msg->len, M_TX_RX_FIFO_SIZE - 1);
842 if (!(msg->flags & I2C_M_RD)) {
843 for (i = 0; i < tx_bytes; i++) {
844 val = msg->buf[i];
845
846 /* mark the last byte */
847 if (!process_call && (i == msg->len - 1))
848 val |= BIT(M_TX_WR_STATUS_SHIFT);
849
850 iproc_i2c_wr_reg(iproc_i2c, M_TX_OFFSET, val);
851 }
852 iproc_i2c->tx_bytes = tx_bytes;
853 }
854
855 /* Process the read message if this is process call */
856 if (process_call) {
857 msg++;
858 iproc_i2c->msg = msg; /* point to second msg */
859
860 /*
861 * The last byte to be sent out should be a slave
862 * address with read operation
863 */
864 addr = i2c_8bit_addr_from_msg(msg);
865 /* mark it the last byte out */
866 val = addr | BIT(M_TX_WR_STATUS_SHIFT);
867 iproc_i2c_wr_reg(iproc_i2c, M_TX_OFFSET, val);
868 }
869
870 /* mark as incomplete before starting the transaction */
871 if (iproc_i2c->irq)
872 reinit_completion(&iproc_i2c->done);
873
874 iproc_i2c->xfer_is_done = 0;
875
876 /*
877 * Enable the "start busy" interrupt, which will be triggered after the
878 * transaction is done, i.e., the internal start_busy bit, transitions
879 * from 1 to 0.
880 */
881 val_intr_en = BIT(IE_M_START_BUSY_SHIFT);
882
883 /*
884 * If TX data size is larger than the TX FIFO, need to enable TX
885 * underrun interrupt, which will be triggerred when the TX FIFO is
886 * empty. When that happens we can then pump more data into the FIFO
887 */
888 if (!process_call && !(msg->flags & I2C_M_RD) &&
889 msg->len > iproc_i2c->tx_bytes)
890 val_intr_en |= BIT(IE_M_TX_UNDERRUN_SHIFT);
891
892 /*
893 * Now we can activate the transfer. For a read operation, specify the
894 * number of bytes to read
895 */
896 val = BIT(M_CMD_START_BUSY_SHIFT);
897
898 if (msg->len == 0) {
899 /* SMBUS QUICK Command (Read/Write) */
900 val |= (M_CMD_PROTOCOL_QUICK << M_CMD_PROTOCOL_SHIFT);
901 } else if (msg->flags & I2C_M_RD) {
902 u32 protocol;
903
904 iproc_i2c->rx_bytes = 0;
905 if (msg->len > M_RX_FIFO_MAX_THLD_VALUE)
906 iproc_i2c->thld_bytes = M_RX_FIFO_THLD_VALUE;
907 else
908 iproc_i2c->thld_bytes = msg->len;
909
910 /* set threshold value */
911 tmp = iproc_i2c_rd_reg(iproc_i2c, M_FIFO_CTRL_OFFSET);
912 tmp &= ~(M_FIFO_RX_THLD_MASK << M_FIFO_RX_THLD_SHIFT);
913 tmp |= iproc_i2c->thld_bytes << M_FIFO_RX_THLD_SHIFT;
914 iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, tmp);
915
916 /* enable the RX threshold interrupt */
917 val_intr_en |= BIT(IE_M_RX_THLD_SHIFT);
918
919 protocol = process_call ?
920 M_CMD_PROTOCOL_PROCESS : M_CMD_PROTOCOL_BLK_RD;
921
922 val |= (protocol << M_CMD_PROTOCOL_SHIFT) |
923 (msg->len << M_CMD_RD_CNT_SHIFT);
924 } else {
925 val |= (M_CMD_PROTOCOL_BLK_WR << M_CMD_PROTOCOL_SHIFT);
926 }
927
928 if (iproc_i2c->irq)
929 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val_intr_en);
930
931 return bcm_iproc_i2c_xfer_wait(iproc_i2c, msg, val);
932 }
933
bcm_iproc_i2c_xfer(struct i2c_adapter * adapter,struct i2c_msg msgs[],int num)934 static int bcm_iproc_i2c_xfer(struct i2c_adapter *adapter,
935 struct i2c_msg msgs[], int num)
936 {
937 struct bcm_iproc_i2c_dev *iproc_i2c = i2c_get_adapdata(adapter);
938 bool process_call = false;
939 int ret;
940
941 if (num == 2) {
942 /* Repeated start, use process call */
943 process_call = true;
944 if (msgs[1].flags & I2C_M_NOSTART) {
945 dev_err(iproc_i2c->device, "Invalid repeated start\n");
946 return -EOPNOTSUPP;
947 }
948 }
949
950 ret = bcm_iproc_i2c_xfer_internal(iproc_i2c, msgs, process_call);
951 if (ret) {
952 dev_dbg(iproc_i2c->device, "xfer failed\n");
953 return ret;
954 }
955
956 return num;
957 }
958
bcm_iproc_i2c_functionality(struct i2c_adapter * adap)959 static uint32_t bcm_iproc_i2c_functionality(struct i2c_adapter *adap)
960 {
961 u32 val;
962
963 val = I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
964
965 if (adap->algo->reg_slave)
966 val |= I2C_FUNC_SLAVE;
967
968 return val;
969 }
970
971 static struct i2c_algorithm bcm_iproc_algo = {
972 .master_xfer = bcm_iproc_i2c_xfer,
973 .functionality = bcm_iproc_i2c_functionality,
974 .reg_slave = bcm_iproc_i2c_reg_slave,
975 .unreg_slave = bcm_iproc_i2c_unreg_slave,
976 };
977
978 static const struct i2c_adapter_quirks bcm_iproc_i2c_quirks = {
979 .flags = I2C_AQ_COMB_WRITE_THEN_READ,
980 .max_comb_1st_msg_len = M_TX_RX_FIFO_SIZE,
981 .max_read_len = M_RX_MAX_READ_LEN,
982 };
983
bcm_iproc_i2c_cfg_speed(struct bcm_iproc_i2c_dev * iproc_i2c)984 static int bcm_iproc_i2c_cfg_speed(struct bcm_iproc_i2c_dev *iproc_i2c)
985 {
986 unsigned int bus_speed;
987 u32 val;
988 int ret = of_property_read_u32(iproc_i2c->device->of_node,
989 "clock-frequency", &bus_speed);
990 if (ret < 0) {
991 dev_info(iproc_i2c->device,
992 "unable to interpret clock-frequency DT property\n");
993 bus_speed = I2C_MAX_STANDARD_MODE_FREQ;
994 }
995
996 if (bus_speed < I2C_MAX_STANDARD_MODE_FREQ) {
997 dev_err(iproc_i2c->device, "%d Hz bus speed not supported\n",
998 bus_speed);
999 dev_err(iproc_i2c->device,
1000 "valid speeds are 100khz and 400khz\n");
1001 return -EINVAL;
1002 } else if (bus_speed < I2C_MAX_FAST_MODE_FREQ) {
1003 bus_speed = I2C_MAX_STANDARD_MODE_FREQ;
1004 } else {
1005 bus_speed = I2C_MAX_FAST_MODE_FREQ;
1006 }
1007
1008 iproc_i2c->bus_speed = bus_speed;
1009 val = iproc_i2c_rd_reg(iproc_i2c, TIM_CFG_OFFSET);
1010 val &= ~BIT(TIM_CFG_MODE_400_SHIFT);
1011 val |= (bus_speed == I2C_MAX_FAST_MODE_FREQ) << TIM_CFG_MODE_400_SHIFT;
1012 iproc_i2c_wr_reg(iproc_i2c, TIM_CFG_OFFSET, val);
1013
1014 dev_info(iproc_i2c->device, "bus set to %u Hz\n", bus_speed);
1015
1016 return 0;
1017 }
1018
bcm_iproc_i2c_probe(struct platform_device * pdev)1019 static int bcm_iproc_i2c_probe(struct platform_device *pdev)
1020 {
1021 int irq, ret = 0;
1022 struct bcm_iproc_i2c_dev *iproc_i2c;
1023 struct i2c_adapter *adap;
1024 struct resource *res;
1025
1026 iproc_i2c = devm_kzalloc(&pdev->dev, sizeof(*iproc_i2c),
1027 GFP_KERNEL);
1028 if (!iproc_i2c)
1029 return -ENOMEM;
1030
1031 platform_set_drvdata(pdev, iproc_i2c);
1032 iproc_i2c->device = &pdev->dev;
1033 iproc_i2c->type =
1034 (enum bcm_iproc_i2c_type)of_device_get_match_data(&pdev->dev);
1035 init_completion(&iproc_i2c->done);
1036
1037 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1038 iproc_i2c->base = devm_ioremap_resource(iproc_i2c->device, res);
1039 if (IS_ERR(iproc_i2c->base))
1040 return PTR_ERR(iproc_i2c->base);
1041
1042 if (iproc_i2c->type == IPROC_I2C_NIC) {
1043 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1044 iproc_i2c->idm_base = devm_ioremap_resource(iproc_i2c->device,
1045 res);
1046 if (IS_ERR(iproc_i2c->idm_base))
1047 return PTR_ERR(iproc_i2c->idm_base);
1048
1049 ret = of_property_read_u32(iproc_i2c->device->of_node,
1050 "brcm,ape-hsls-addr-mask",
1051 &iproc_i2c->ape_addr_mask);
1052 if (ret < 0) {
1053 dev_err(iproc_i2c->device,
1054 "'brcm,ape-hsls-addr-mask' missing\n");
1055 return -EINVAL;
1056 }
1057
1058 spin_lock_init(&iproc_i2c->idm_lock);
1059
1060 /* no slave support */
1061 bcm_iproc_algo.reg_slave = NULL;
1062 bcm_iproc_algo.unreg_slave = NULL;
1063 }
1064
1065 ret = bcm_iproc_i2c_init(iproc_i2c);
1066 if (ret)
1067 return ret;
1068
1069 ret = bcm_iproc_i2c_cfg_speed(iproc_i2c);
1070 if (ret)
1071 return ret;
1072
1073 irq = platform_get_irq(pdev, 0);
1074 if (irq > 0) {
1075 ret = devm_request_irq(iproc_i2c->device, irq,
1076 bcm_iproc_i2c_isr, 0, pdev->name,
1077 iproc_i2c);
1078 if (ret < 0) {
1079 dev_err(iproc_i2c->device,
1080 "unable to request irq %i\n", irq);
1081 return ret;
1082 }
1083
1084 iproc_i2c->irq = irq;
1085 } else {
1086 dev_warn(iproc_i2c->device,
1087 "no irq resource, falling back to poll mode\n");
1088 }
1089
1090 bcm_iproc_i2c_enable_disable(iproc_i2c, true);
1091
1092 adap = &iproc_i2c->adapter;
1093 i2c_set_adapdata(adap, iproc_i2c);
1094 snprintf(adap->name, sizeof(adap->name),
1095 "Broadcom iProc (%s)",
1096 of_node_full_name(iproc_i2c->device->of_node));
1097 adap->algo = &bcm_iproc_algo;
1098 adap->quirks = &bcm_iproc_i2c_quirks;
1099 adap->dev.parent = &pdev->dev;
1100 adap->dev.of_node = pdev->dev.of_node;
1101
1102 return i2c_add_adapter(adap);
1103 }
1104
bcm_iproc_i2c_remove(struct platform_device * pdev)1105 static int bcm_iproc_i2c_remove(struct platform_device *pdev)
1106 {
1107 struct bcm_iproc_i2c_dev *iproc_i2c = platform_get_drvdata(pdev);
1108
1109 if (iproc_i2c->irq) {
1110 /*
1111 * Make sure there's no pending interrupt when we remove the
1112 * adapter
1113 */
1114 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, 0);
1115 iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
1116 synchronize_irq(iproc_i2c->irq);
1117 }
1118
1119 i2c_del_adapter(&iproc_i2c->adapter);
1120 bcm_iproc_i2c_enable_disable(iproc_i2c, false);
1121
1122 return 0;
1123 }
1124
1125 #ifdef CONFIG_PM_SLEEP
1126
bcm_iproc_i2c_suspend(struct device * dev)1127 static int bcm_iproc_i2c_suspend(struct device *dev)
1128 {
1129 struct bcm_iproc_i2c_dev *iproc_i2c = dev_get_drvdata(dev);
1130
1131 if (iproc_i2c->irq) {
1132 /*
1133 * Make sure there's no pending interrupt when we go into
1134 * suspend
1135 */
1136 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, 0);
1137 iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
1138 synchronize_irq(iproc_i2c->irq);
1139 }
1140
1141 /* now disable the controller */
1142 bcm_iproc_i2c_enable_disable(iproc_i2c, false);
1143
1144 return 0;
1145 }
1146
bcm_iproc_i2c_resume(struct device * dev)1147 static int bcm_iproc_i2c_resume(struct device *dev)
1148 {
1149 struct bcm_iproc_i2c_dev *iproc_i2c = dev_get_drvdata(dev);
1150 int ret;
1151 u32 val;
1152
1153 /*
1154 * Power domain could have been shut off completely in system deep
1155 * sleep, so re-initialize the block here
1156 */
1157 ret = bcm_iproc_i2c_init(iproc_i2c);
1158 if (ret)
1159 return ret;
1160
1161 /* configure to the desired bus speed */
1162 val = iproc_i2c_rd_reg(iproc_i2c, TIM_CFG_OFFSET);
1163 val &= ~BIT(TIM_CFG_MODE_400_SHIFT);
1164 val |= (iproc_i2c->bus_speed == I2C_MAX_FAST_MODE_FREQ) << TIM_CFG_MODE_400_SHIFT;
1165 iproc_i2c_wr_reg(iproc_i2c, TIM_CFG_OFFSET, val);
1166
1167 bcm_iproc_i2c_enable_disable(iproc_i2c, true);
1168
1169 return 0;
1170 }
1171
1172 static const struct dev_pm_ops bcm_iproc_i2c_pm_ops = {
1173 .suspend_late = &bcm_iproc_i2c_suspend,
1174 .resume_early = &bcm_iproc_i2c_resume
1175 };
1176
1177 #define BCM_IPROC_I2C_PM_OPS (&bcm_iproc_i2c_pm_ops)
1178 #else
1179 #define BCM_IPROC_I2C_PM_OPS NULL
1180 #endif /* CONFIG_PM_SLEEP */
1181
1182
bcm_iproc_i2c_reg_slave(struct i2c_client * slave)1183 static int bcm_iproc_i2c_reg_slave(struct i2c_client *slave)
1184 {
1185 struct bcm_iproc_i2c_dev *iproc_i2c = i2c_get_adapdata(slave->adapter);
1186
1187 if (iproc_i2c->slave)
1188 return -EBUSY;
1189
1190 if (slave->flags & I2C_CLIENT_TEN)
1191 return -EAFNOSUPPORT;
1192
1193 iproc_i2c->slave = slave;
1194
1195 tasklet_init(&iproc_i2c->slave_rx_tasklet, slave_rx_tasklet_fn,
1196 (unsigned long)iproc_i2c);
1197
1198 bcm_iproc_i2c_slave_init(iproc_i2c, false);
1199 return 0;
1200 }
1201
bcm_iproc_i2c_unreg_slave(struct i2c_client * slave)1202 static int bcm_iproc_i2c_unreg_slave(struct i2c_client *slave)
1203 {
1204 u32 tmp;
1205 struct bcm_iproc_i2c_dev *iproc_i2c = i2c_get_adapdata(slave->adapter);
1206
1207 if (!iproc_i2c->slave)
1208 return -EINVAL;
1209
1210 disable_irq(iproc_i2c->irq);
1211
1212 /* disable all slave interrupts */
1213 tmp = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
1214 tmp &= ~(IE_S_ALL_INTERRUPT_MASK <<
1215 IE_S_ALL_INTERRUPT_SHIFT);
1216 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, tmp);
1217
1218 tasklet_kill(&iproc_i2c->slave_rx_tasklet);
1219
1220 /* Erase the slave address programmed */
1221 tmp = iproc_i2c_rd_reg(iproc_i2c, S_CFG_SMBUS_ADDR_OFFSET);
1222 tmp &= ~BIT(S_CFG_EN_NIC_SMB_ADDR3_SHIFT);
1223 iproc_i2c_wr_reg(iproc_i2c, S_CFG_SMBUS_ADDR_OFFSET, tmp);
1224
1225 /* flush TX/RX FIFOs */
1226 tmp = (BIT(S_FIFO_RX_FLUSH_SHIFT) | BIT(S_FIFO_TX_FLUSH_SHIFT));
1227 iproc_i2c_wr_reg(iproc_i2c, S_FIFO_CTRL_OFFSET, tmp);
1228
1229 /* clear all pending slave interrupts */
1230 iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, ISR_MASK_SLAVE);
1231
1232 iproc_i2c->slave = NULL;
1233
1234 enable_irq(iproc_i2c->irq);
1235
1236 return 0;
1237 }
1238
1239 static const struct of_device_id bcm_iproc_i2c_of_match[] = {
1240 {
1241 .compatible = "brcm,iproc-i2c",
1242 .data = (int *)IPROC_I2C,
1243 }, {
1244 .compatible = "brcm,iproc-nic-i2c",
1245 .data = (int *)IPROC_I2C_NIC,
1246 },
1247 { /* sentinel */ }
1248 };
1249 MODULE_DEVICE_TABLE(of, bcm_iproc_i2c_of_match);
1250
1251 static struct platform_driver bcm_iproc_i2c_driver = {
1252 .driver = {
1253 .name = "bcm-iproc-i2c",
1254 .of_match_table = bcm_iproc_i2c_of_match,
1255 .pm = BCM_IPROC_I2C_PM_OPS,
1256 },
1257 .probe = bcm_iproc_i2c_probe,
1258 .remove = bcm_iproc_i2c_remove,
1259 };
1260 module_platform_driver(bcm_iproc_i2c_driver);
1261
1262 MODULE_AUTHOR("Ray Jui <rjui@broadcom.com>");
1263 MODULE_DESCRIPTION("Broadcom iProc I2C Driver");
1264 MODULE_LICENSE("GPL v2");
1265