1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Rockchip Successive Approximation Register (SAR) A/D Converter
4 * Copyright (C) 2014 ROCKCHIP, Inc.
5 */
6
7 #include <linux/module.h>
8 #include <linux/platform_device.h>
9 #include <linux/interrupt.h>
10 #include <linux/io.h>
11 #include <linux/of.h>
12 #include <linux/of_device.h>
13 #include <linux/clk.h>
14 #include <linux/completion.h>
15 #include <linux/delay.h>
16 #include <linux/reset.h>
17 #include <linux/regulator/consumer.h>
18 #include <linux/iio/buffer.h>
19 #include <linux/iio/iio.h>
20 #include <linux/iio/trigger_consumer.h>
21 #include <linux/iio/triggered_buffer.h>
22
23 #define SARADC_DATA 0x00
24
25 #define SARADC_STAS 0x04
26 #define SARADC_STAS_BUSY BIT(0)
27
28 #define SARADC_CTRL 0x08
29 #define SARADC_CTRL_IRQ_STATUS BIT(6)
30 #define SARADC_CTRL_IRQ_ENABLE BIT(5)
31 #define SARADC_CTRL_POWER_CTRL BIT(3)
32 #define SARADC_CTRL_CHN_MASK 0x7
33
34 #define SARADC_DLY_PU_SOC 0x0c
35 #define SARADC_DLY_PU_SOC_MASK 0x3f
36
37 #define SARADC_TIMEOUT msecs_to_jiffies(100)
38 #define SARADC_MAX_CHANNELS 6
39
40 struct rockchip_saradc_data {
41 const struct iio_chan_spec *channels;
42 int num_channels;
43 unsigned long clk_rate;
44 };
45
46 struct rockchip_saradc {
47 void __iomem *regs;
48 struct clk *pclk;
49 struct clk *clk;
50 struct completion completion;
51 struct regulator *vref;
52 struct reset_control *reset;
53 const struct rockchip_saradc_data *data;
54 u16 last_val;
55 const struct iio_chan_spec *last_chan;
56 };
57
rockchip_saradc_power_down(struct rockchip_saradc * info)58 static void rockchip_saradc_power_down(struct rockchip_saradc *info)
59 {
60 /* Clear irq & power down adc */
61 writel_relaxed(0, info->regs + SARADC_CTRL);
62 }
63
rockchip_saradc_conversion(struct rockchip_saradc * info,struct iio_chan_spec const * chan)64 static int rockchip_saradc_conversion(struct rockchip_saradc *info,
65 struct iio_chan_spec const *chan)
66 {
67 reinit_completion(&info->completion);
68
69 /* 8 clock periods as delay between power up and start cmd */
70 writel_relaxed(8, info->regs + SARADC_DLY_PU_SOC);
71
72 info->last_chan = chan;
73
74 /* Select the channel to be used and trigger conversion */
75 writel(SARADC_CTRL_POWER_CTRL
76 | (chan->channel & SARADC_CTRL_CHN_MASK)
77 | SARADC_CTRL_IRQ_ENABLE,
78 info->regs + SARADC_CTRL);
79
80 if (!wait_for_completion_timeout(&info->completion, SARADC_TIMEOUT))
81 return -ETIMEDOUT;
82
83 return 0;
84 }
85
rockchip_saradc_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)86 static int rockchip_saradc_read_raw(struct iio_dev *indio_dev,
87 struct iio_chan_spec const *chan,
88 int *val, int *val2, long mask)
89 {
90 struct rockchip_saradc *info = iio_priv(indio_dev);
91 int ret;
92
93 switch (mask) {
94 case IIO_CHAN_INFO_RAW:
95 mutex_lock(&indio_dev->mlock);
96
97 ret = rockchip_saradc_conversion(info, chan);
98 if (ret) {
99 rockchip_saradc_power_down(info);
100 mutex_unlock(&indio_dev->mlock);
101 return ret;
102 }
103
104 *val = info->last_val;
105 mutex_unlock(&indio_dev->mlock);
106 return IIO_VAL_INT;
107 case IIO_CHAN_INFO_SCALE:
108 ret = regulator_get_voltage(info->vref);
109 if (ret < 0) {
110 dev_err(&indio_dev->dev, "failed to get voltage\n");
111 return ret;
112 }
113
114 *val = ret / 1000;
115 *val2 = chan->scan_type.realbits;
116 return IIO_VAL_FRACTIONAL_LOG2;
117 default:
118 return -EINVAL;
119 }
120 }
121
rockchip_saradc_isr(int irq,void * dev_id)122 static irqreturn_t rockchip_saradc_isr(int irq, void *dev_id)
123 {
124 struct rockchip_saradc *info = dev_id;
125
126 /* Read value */
127 info->last_val = readl_relaxed(info->regs + SARADC_DATA);
128 info->last_val &= GENMASK(info->last_chan->scan_type.realbits - 1, 0);
129
130 rockchip_saradc_power_down(info);
131
132 complete(&info->completion);
133
134 return IRQ_HANDLED;
135 }
136
137 static const struct iio_info rockchip_saradc_iio_info = {
138 .read_raw = rockchip_saradc_read_raw,
139 };
140
141 #define SARADC_CHANNEL(_index, _id, _res) { \
142 .type = IIO_VOLTAGE, \
143 .indexed = 1, \
144 .channel = _index, \
145 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
146 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
147 .datasheet_name = _id, \
148 .scan_index = _index, \
149 .scan_type = { \
150 .sign = 'u', \
151 .realbits = _res, \
152 .storagebits = 16, \
153 .endianness = IIO_CPU, \
154 }, \
155 }
156
157 static const struct iio_chan_spec rockchip_saradc_iio_channels[] = {
158 SARADC_CHANNEL(0, "adc0", 10),
159 SARADC_CHANNEL(1, "adc1", 10),
160 SARADC_CHANNEL(2, "adc2", 10),
161 };
162
163 static const struct rockchip_saradc_data saradc_data = {
164 .channels = rockchip_saradc_iio_channels,
165 .num_channels = ARRAY_SIZE(rockchip_saradc_iio_channels),
166 .clk_rate = 1000000,
167 };
168
169 static const struct iio_chan_spec rockchip_rk3066_tsadc_iio_channels[] = {
170 SARADC_CHANNEL(0, "adc0", 12),
171 SARADC_CHANNEL(1, "adc1", 12),
172 };
173
174 static const struct rockchip_saradc_data rk3066_tsadc_data = {
175 .channels = rockchip_rk3066_tsadc_iio_channels,
176 .num_channels = ARRAY_SIZE(rockchip_rk3066_tsadc_iio_channels),
177 .clk_rate = 50000,
178 };
179
180 static const struct iio_chan_spec rockchip_rk3399_saradc_iio_channels[] = {
181 SARADC_CHANNEL(0, "adc0", 10),
182 SARADC_CHANNEL(1, "adc1", 10),
183 SARADC_CHANNEL(2, "adc2", 10),
184 SARADC_CHANNEL(3, "adc3", 10),
185 SARADC_CHANNEL(4, "adc4", 10),
186 SARADC_CHANNEL(5, "adc5", 10),
187 };
188
189 static const struct rockchip_saradc_data rk3399_saradc_data = {
190 .channels = rockchip_rk3399_saradc_iio_channels,
191 .num_channels = ARRAY_SIZE(rockchip_rk3399_saradc_iio_channels),
192 .clk_rate = 1000000,
193 };
194
195 static const struct of_device_id rockchip_saradc_match[] = {
196 {
197 .compatible = "rockchip,saradc",
198 .data = &saradc_data,
199 }, {
200 .compatible = "rockchip,rk3066-tsadc",
201 .data = &rk3066_tsadc_data,
202 }, {
203 .compatible = "rockchip,rk3399-saradc",
204 .data = &rk3399_saradc_data,
205 },
206 {},
207 };
208 MODULE_DEVICE_TABLE(of, rockchip_saradc_match);
209
210 /*
211 * Reset SARADC Controller.
212 */
rockchip_saradc_reset_controller(struct reset_control * reset)213 static void rockchip_saradc_reset_controller(struct reset_control *reset)
214 {
215 reset_control_assert(reset);
216 usleep_range(10, 20);
217 reset_control_deassert(reset);
218 }
219
rockchip_saradc_clk_disable(void * data)220 static void rockchip_saradc_clk_disable(void *data)
221 {
222 struct rockchip_saradc *info = data;
223
224 clk_disable_unprepare(info->clk);
225 }
226
rockchip_saradc_pclk_disable(void * data)227 static void rockchip_saradc_pclk_disable(void *data)
228 {
229 struct rockchip_saradc *info = data;
230
231 clk_disable_unprepare(info->pclk);
232 }
233
rockchip_saradc_regulator_disable(void * data)234 static void rockchip_saradc_regulator_disable(void *data)
235 {
236 struct rockchip_saradc *info = data;
237
238 regulator_disable(info->vref);
239 }
240
rockchip_saradc_trigger_handler(int irq,void * p)241 static irqreturn_t rockchip_saradc_trigger_handler(int irq, void *p)
242 {
243 struct iio_poll_func *pf = p;
244 struct iio_dev *i_dev = pf->indio_dev;
245 struct rockchip_saradc *info = iio_priv(i_dev);
246 /*
247 * @values: each channel takes an u16 value
248 * @timestamp: will be 8-byte aligned automatically
249 */
250 struct {
251 u16 values[SARADC_MAX_CHANNELS];
252 int64_t timestamp;
253 } data;
254 int ret;
255 int i, j = 0;
256
257 mutex_lock(&i_dev->mlock);
258
259 for_each_set_bit(i, i_dev->active_scan_mask, i_dev->masklength) {
260 const struct iio_chan_spec *chan = &i_dev->channels[i];
261
262 ret = rockchip_saradc_conversion(info, chan);
263 if (ret) {
264 rockchip_saradc_power_down(info);
265 goto out;
266 }
267
268 data.values[j] = info->last_val;
269 j++;
270 }
271
272 iio_push_to_buffers_with_timestamp(i_dev, &data, iio_get_time_ns(i_dev));
273 out:
274 mutex_unlock(&i_dev->mlock);
275
276 iio_trigger_notify_done(i_dev->trig);
277
278 return IRQ_HANDLED;
279 }
280
rockchip_saradc_probe(struct platform_device * pdev)281 static int rockchip_saradc_probe(struct platform_device *pdev)
282 {
283 struct rockchip_saradc *info = NULL;
284 struct device_node *np = pdev->dev.of_node;
285 struct iio_dev *indio_dev = NULL;
286 struct resource *mem;
287 const struct of_device_id *match;
288 int ret;
289 int irq;
290
291 if (!np)
292 return -ENODEV;
293
294 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*info));
295 if (!indio_dev) {
296 dev_err(&pdev->dev, "failed allocating iio device\n");
297 return -ENOMEM;
298 }
299 info = iio_priv(indio_dev);
300
301 match = of_match_device(rockchip_saradc_match, &pdev->dev);
302 if (!match) {
303 dev_err(&pdev->dev, "failed to match device\n");
304 return -ENODEV;
305 }
306
307 info->data = match->data;
308
309 /* Sanity check for possible later IP variants with more channels */
310 if (info->data->num_channels > SARADC_MAX_CHANNELS) {
311 dev_err(&pdev->dev, "max channels exceeded");
312 return -EINVAL;
313 }
314
315 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
316 info->regs = devm_ioremap_resource(&pdev->dev, mem);
317 if (IS_ERR(info->regs))
318 return PTR_ERR(info->regs);
319
320 /*
321 * The reset should be an optional property, as it should work
322 * with old devicetrees as well
323 */
324 info->reset = devm_reset_control_get_exclusive(&pdev->dev,
325 "saradc-apb");
326 if (IS_ERR(info->reset)) {
327 ret = PTR_ERR(info->reset);
328 if (ret != -ENOENT)
329 return ret;
330
331 dev_dbg(&pdev->dev, "no reset control found\n");
332 info->reset = NULL;
333 }
334
335 init_completion(&info->completion);
336
337 irq = platform_get_irq(pdev, 0);
338 if (irq < 0)
339 return irq;
340
341 ret = devm_request_irq(&pdev->dev, irq, rockchip_saradc_isr,
342 0, dev_name(&pdev->dev), info);
343 if (ret < 0) {
344 dev_err(&pdev->dev, "failed requesting irq %d\n", irq);
345 return ret;
346 }
347
348 info->pclk = devm_clk_get(&pdev->dev, "apb_pclk");
349 if (IS_ERR(info->pclk)) {
350 dev_err(&pdev->dev, "failed to get pclk\n");
351 return PTR_ERR(info->pclk);
352 }
353
354 info->clk = devm_clk_get(&pdev->dev, "saradc");
355 if (IS_ERR(info->clk)) {
356 dev_err(&pdev->dev, "failed to get adc clock\n");
357 return PTR_ERR(info->clk);
358 }
359
360 info->vref = devm_regulator_get(&pdev->dev, "vref");
361 if (IS_ERR(info->vref)) {
362 dev_err(&pdev->dev, "failed to get regulator, %ld\n",
363 PTR_ERR(info->vref));
364 return PTR_ERR(info->vref);
365 }
366
367 if (info->reset)
368 rockchip_saradc_reset_controller(info->reset);
369
370 /*
371 * Use a default value for the converter clock.
372 * This may become user-configurable in the future.
373 */
374 ret = clk_set_rate(info->clk, info->data->clk_rate);
375 if (ret < 0) {
376 dev_err(&pdev->dev, "failed to set adc clk rate, %d\n", ret);
377 return ret;
378 }
379
380 ret = regulator_enable(info->vref);
381 if (ret < 0) {
382 dev_err(&pdev->dev, "failed to enable vref regulator\n");
383 return ret;
384 }
385 ret = devm_add_action_or_reset(&pdev->dev,
386 rockchip_saradc_regulator_disable, info);
387 if (ret) {
388 dev_err(&pdev->dev, "failed to register devm action, %d\n",
389 ret);
390 return ret;
391 }
392
393 ret = clk_prepare_enable(info->pclk);
394 if (ret < 0) {
395 dev_err(&pdev->dev, "failed to enable pclk\n");
396 return ret;
397 }
398 ret = devm_add_action_or_reset(&pdev->dev,
399 rockchip_saradc_pclk_disable, info);
400 if (ret) {
401 dev_err(&pdev->dev, "failed to register devm action, %d\n",
402 ret);
403 return ret;
404 }
405
406 ret = clk_prepare_enable(info->clk);
407 if (ret < 0) {
408 dev_err(&pdev->dev, "failed to enable converter clock\n");
409 return ret;
410 }
411 ret = devm_add_action_or_reset(&pdev->dev,
412 rockchip_saradc_clk_disable, info);
413 if (ret) {
414 dev_err(&pdev->dev, "failed to register devm action, %d\n",
415 ret);
416 return ret;
417 }
418
419 platform_set_drvdata(pdev, indio_dev);
420
421 indio_dev->name = dev_name(&pdev->dev);
422 indio_dev->info = &rockchip_saradc_iio_info;
423 indio_dev->modes = INDIO_DIRECT_MODE;
424
425 indio_dev->channels = info->data->channels;
426 indio_dev->num_channels = info->data->num_channels;
427 ret = devm_iio_triggered_buffer_setup(&indio_dev->dev, indio_dev, NULL,
428 rockchip_saradc_trigger_handler,
429 NULL);
430 if (ret)
431 return ret;
432
433 return devm_iio_device_register(&pdev->dev, indio_dev);
434 }
435
436 #ifdef CONFIG_PM_SLEEP
rockchip_saradc_suspend(struct device * dev)437 static int rockchip_saradc_suspend(struct device *dev)
438 {
439 struct iio_dev *indio_dev = dev_get_drvdata(dev);
440 struct rockchip_saradc *info = iio_priv(indio_dev);
441
442 clk_disable_unprepare(info->clk);
443 clk_disable_unprepare(info->pclk);
444 regulator_disable(info->vref);
445
446 return 0;
447 }
448
rockchip_saradc_resume(struct device * dev)449 static int rockchip_saradc_resume(struct device *dev)
450 {
451 struct iio_dev *indio_dev = dev_get_drvdata(dev);
452 struct rockchip_saradc *info = iio_priv(indio_dev);
453 int ret;
454
455 ret = regulator_enable(info->vref);
456 if (ret)
457 return ret;
458
459 ret = clk_prepare_enable(info->pclk);
460 if (ret)
461 return ret;
462
463 ret = clk_prepare_enable(info->clk);
464 if (ret)
465 clk_disable_unprepare(info->pclk);
466
467 return ret;
468 }
469 #endif
470
471 static SIMPLE_DEV_PM_OPS(rockchip_saradc_pm_ops,
472 rockchip_saradc_suspend, rockchip_saradc_resume);
473
474 static struct platform_driver rockchip_saradc_driver = {
475 .probe = rockchip_saradc_probe,
476 .driver = {
477 .name = "rockchip-saradc",
478 .of_match_table = rockchip_saradc_match,
479 .pm = &rockchip_saradc_pm_ops,
480 },
481 };
482
483 module_platform_driver(rockchip_saradc_driver);
484
485 MODULE_AUTHOR("Heiko Stuebner <heiko@sntech.de>");
486 MODULE_DESCRIPTION("Rockchip SARADC driver");
487 MODULE_LICENSE("GPL v2");
488