1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
4 */
5
6 #include <linux/err.h>
7 #include <linux/init.h>
8 #include <linux/interrupt.h>
9 #include <linux/irq.h>
10 #include <linux/irqchip.h>
11 #include <linux/irqdomain.h>
12 #include <linux/io.h>
13 #include <linux/kernel.h>
14 #include <linux/of.h>
15 #include <linux/of_address.h>
16 #include <linux/of_device.h>
17 #include <linux/soc/qcom/irq.h>
18 #include <linux/spinlock.h>
19 #include <linux/slab.h>
20 #include <linux/types.h>
21
22 #define PDC_MAX_IRQS 168
23 #define PDC_MAX_GPIO_IRQS 256
24
25 #define CLEAR_INTR(reg, intr) (reg & ~(1 << intr))
26 #define ENABLE_INTR(reg, intr) (reg | (1 << intr))
27
28 #define IRQ_ENABLE_BANK 0x10
29 #define IRQ_i_CFG 0x110
30
31 #define PDC_NO_PARENT_IRQ ~0UL
32
33 struct pdc_pin_region {
34 u32 pin_base;
35 u32 parent_base;
36 u32 cnt;
37 };
38
39 static DEFINE_RAW_SPINLOCK(pdc_lock);
40 static void __iomem *pdc_base;
41 static struct pdc_pin_region *pdc_region;
42 static int pdc_region_cnt;
43
pdc_reg_write(int reg,u32 i,u32 val)44 static void pdc_reg_write(int reg, u32 i, u32 val)
45 {
46 writel_relaxed(val, pdc_base + reg + i * sizeof(u32));
47 }
48
pdc_reg_read(int reg,u32 i)49 static u32 pdc_reg_read(int reg, u32 i)
50 {
51 return readl_relaxed(pdc_base + reg + i * sizeof(u32));
52 }
53
qcom_pdc_gic_get_irqchip_state(struct irq_data * d,enum irqchip_irq_state which,bool * state)54 static int qcom_pdc_gic_get_irqchip_state(struct irq_data *d,
55 enum irqchip_irq_state which,
56 bool *state)
57 {
58 if (d->hwirq == GPIO_NO_WAKE_IRQ)
59 return 0;
60
61 return irq_chip_get_parent_state(d, which, state);
62 }
63
qcom_pdc_gic_set_irqchip_state(struct irq_data * d,enum irqchip_irq_state which,bool value)64 static int qcom_pdc_gic_set_irqchip_state(struct irq_data *d,
65 enum irqchip_irq_state which,
66 bool value)
67 {
68 if (d->hwirq == GPIO_NO_WAKE_IRQ)
69 return 0;
70
71 return irq_chip_set_parent_state(d, which, value);
72 }
73
pdc_enable_intr(struct irq_data * d,bool on)74 static void pdc_enable_intr(struct irq_data *d, bool on)
75 {
76 int pin_out = d->hwirq;
77 unsigned long flags;
78 u32 index, mask;
79 u32 enable;
80
81 index = pin_out / 32;
82 mask = pin_out % 32;
83
84 raw_spin_lock_irqsave(&pdc_lock, flags);
85 enable = pdc_reg_read(IRQ_ENABLE_BANK, index);
86 enable = on ? ENABLE_INTR(enable, mask) : CLEAR_INTR(enable, mask);
87 pdc_reg_write(IRQ_ENABLE_BANK, index, enable);
88 raw_spin_unlock_irqrestore(&pdc_lock, flags);
89 }
90
qcom_pdc_gic_disable(struct irq_data * d)91 static void qcom_pdc_gic_disable(struct irq_data *d)
92 {
93 if (d->hwirq == GPIO_NO_WAKE_IRQ)
94 return;
95
96 pdc_enable_intr(d, false);
97 irq_chip_disable_parent(d);
98 }
99
qcom_pdc_gic_enable(struct irq_data * d)100 static void qcom_pdc_gic_enable(struct irq_data *d)
101 {
102 if (d->hwirq == GPIO_NO_WAKE_IRQ)
103 return;
104
105 pdc_enable_intr(d, true);
106 irq_chip_enable_parent(d);
107 }
108
qcom_pdc_gic_mask(struct irq_data * d)109 static void qcom_pdc_gic_mask(struct irq_data *d)
110 {
111 if (d->hwirq == GPIO_NO_WAKE_IRQ)
112 return;
113
114 irq_chip_mask_parent(d);
115 }
116
qcom_pdc_gic_unmask(struct irq_data * d)117 static void qcom_pdc_gic_unmask(struct irq_data *d)
118 {
119 if (d->hwirq == GPIO_NO_WAKE_IRQ)
120 return;
121
122 irq_chip_unmask_parent(d);
123 }
124
125 /*
126 * GIC does not handle falling edge or active low. To allow falling edge and
127 * active low interrupts to be handled at GIC, PDC has an inverter that inverts
128 * falling edge into a rising edge and active low into an active high.
129 * For the inverter to work, the polarity bit in the IRQ_CONFIG register has to
130 * set as per the table below.
131 * Level sensitive active low LOW
132 * Rising edge sensitive NOT USED
133 * Falling edge sensitive LOW
134 * Dual Edge sensitive NOT USED
135 * Level sensitive active High HIGH
136 * Falling Edge sensitive NOT USED
137 * Rising edge sensitive HIGH
138 * Dual Edge sensitive HIGH
139 */
140 enum pdc_irq_config_bits {
141 PDC_LEVEL_LOW = 0b000,
142 PDC_EDGE_FALLING = 0b010,
143 PDC_LEVEL_HIGH = 0b100,
144 PDC_EDGE_RISING = 0b110,
145 PDC_EDGE_DUAL = 0b111,
146 };
147
148 /**
149 * qcom_pdc_gic_set_type: Configure PDC for the interrupt
150 *
151 * @d: the interrupt data
152 * @type: the interrupt type
153 *
154 * If @type is edge triggered, forward that as Rising edge as PDC
155 * takes care of converting falling edge to rising edge signal
156 * If @type is level, then forward that as level high as PDC
157 * takes care of converting falling edge to rising edge signal
158 */
qcom_pdc_gic_set_type(struct irq_data * d,unsigned int type)159 static int qcom_pdc_gic_set_type(struct irq_data *d, unsigned int type)
160 {
161 int pin_out = d->hwirq;
162 enum pdc_irq_config_bits pdc_type;
163 enum pdc_irq_config_bits old_pdc_type;
164 int ret;
165
166 if (pin_out == GPIO_NO_WAKE_IRQ)
167 return 0;
168
169 switch (type) {
170 case IRQ_TYPE_EDGE_RISING:
171 pdc_type = PDC_EDGE_RISING;
172 break;
173 case IRQ_TYPE_EDGE_FALLING:
174 pdc_type = PDC_EDGE_FALLING;
175 type = IRQ_TYPE_EDGE_RISING;
176 break;
177 case IRQ_TYPE_EDGE_BOTH:
178 pdc_type = PDC_EDGE_DUAL;
179 type = IRQ_TYPE_EDGE_RISING;
180 break;
181 case IRQ_TYPE_LEVEL_HIGH:
182 pdc_type = PDC_LEVEL_HIGH;
183 break;
184 case IRQ_TYPE_LEVEL_LOW:
185 pdc_type = PDC_LEVEL_LOW;
186 type = IRQ_TYPE_LEVEL_HIGH;
187 break;
188 default:
189 WARN_ON(1);
190 return -EINVAL;
191 }
192
193 old_pdc_type = pdc_reg_read(IRQ_i_CFG, pin_out);
194 pdc_reg_write(IRQ_i_CFG, pin_out, pdc_type);
195
196 ret = irq_chip_set_type_parent(d, type);
197 if (ret)
198 return ret;
199
200 /*
201 * When we change types the PDC can give a phantom interrupt.
202 * Clear it. Specifically the phantom shows up when reconfiguring
203 * polarity of interrupt without changing the state of the signal
204 * but let's be consistent and clear it always.
205 *
206 * Doing this works because we have IRQCHIP_SET_TYPE_MASKED so the
207 * interrupt will be cleared before the rest of the system sees it.
208 */
209 if (old_pdc_type != pdc_type)
210 irq_chip_set_parent_state(d, IRQCHIP_STATE_PENDING, false);
211
212 return 0;
213 }
214
215 static struct irq_chip qcom_pdc_gic_chip = {
216 .name = "PDC",
217 .irq_eoi = irq_chip_eoi_parent,
218 .irq_mask = qcom_pdc_gic_mask,
219 .irq_unmask = qcom_pdc_gic_unmask,
220 .irq_disable = qcom_pdc_gic_disable,
221 .irq_enable = qcom_pdc_gic_enable,
222 .irq_get_irqchip_state = qcom_pdc_gic_get_irqchip_state,
223 .irq_set_irqchip_state = qcom_pdc_gic_set_irqchip_state,
224 .irq_retrigger = irq_chip_retrigger_hierarchy,
225 .irq_set_type = qcom_pdc_gic_set_type,
226 .flags = IRQCHIP_MASK_ON_SUSPEND |
227 IRQCHIP_SET_TYPE_MASKED |
228 IRQCHIP_SKIP_SET_WAKE |
229 IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND,
230 .irq_set_vcpu_affinity = irq_chip_set_vcpu_affinity_parent,
231 .irq_set_affinity = irq_chip_set_affinity_parent,
232 };
233
get_parent_hwirq(int pin)234 static irq_hw_number_t get_parent_hwirq(int pin)
235 {
236 int i;
237 struct pdc_pin_region *region;
238
239 for (i = 0; i < pdc_region_cnt; i++) {
240 region = &pdc_region[i];
241 if (pin >= region->pin_base &&
242 pin < region->pin_base + region->cnt)
243 return (region->parent_base + pin - region->pin_base);
244 }
245
246 return PDC_NO_PARENT_IRQ;
247 }
248
qcom_pdc_translate(struct irq_domain * d,struct irq_fwspec * fwspec,unsigned long * hwirq,unsigned int * type)249 static int qcom_pdc_translate(struct irq_domain *d, struct irq_fwspec *fwspec,
250 unsigned long *hwirq, unsigned int *type)
251 {
252 if (is_of_node(fwspec->fwnode)) {
253 if (fwspec->param_count != 2)
254 return -EINVAL;
255
256 *hwirq = fwspec->param[0];
257 *type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK;
258 return 0;
259 }
260
261 return -EINVAL;
262 }
263
qcom_pdc_alloc(struct irq_domain * domain,unsigned int virq,unsigned int nr_irqs,void * data)264 static int qcom_pdc_alloc(struct irq_domain *domain, unsigned int virq,
265 unsigned int nr_irqs, void *data)
266 {
267 struct irq_fwspec *fwspec = data;
268 struct irq_fwspec parent_fwspec;
269 irq_hw_number_t hwirq, parent_hwirq;
270 unsigned int type;
271 int ret;
272
273 ret = qcom_pdc_translate(domain, fwspec, &hwirq, &type);
274 if (ret)
275 return ret;
276
277 ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
278 &qcom_pdc_gic_chip, NULL);
279 if (ret)
280 return ret;
281
282 parent_hwirq = get_parent_hwirq(hwirq);
283 if (parent_hwirq == PDC_NO_PARENT_IRQ)
284 return 0;
285
286 if (type & IRQ_TYPE_EDGE_BOTH)
287 type = IRQ_TYPE_EDGE_RISING;
288
289 if (type & IRQ_TYPE_LEVEL_MASK)
290 type = IRQ_TYPE_LEVEL_HIGH;
291
292 parent_fwspec.fwnode = domain->parent->fwnode;
293 parent_fwspec.param_count = 3;
294 parent_fwspec.param[0] = 0;
295 parent_fwspec.param[1] = parent_hwirq;
296 parent_fwspec.param[2] = type;
297
298 return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs,
299 &parent_fwspec);
300 }
301
302 static const struct irq_domain_ops qcom_pdc_ops = {
303 .translate = qcom_pdc_translate,
304 .alloc = qcom_pdc_alloc,
305 .free = irq_domain_free_irqs_common,
306 };
307
qcom_pdc_gpio_alloc(struct irq_domain * domain,unsigned int virq,unsigned int nr_irqs,void * data)308 static int qcom_pdc_gpio_alloc(struct irq_domain *domain, unsigned int virq,
309 unsigned int nr_irqs, void *data)
310 {
311 struct irq_fwspec *fwspec = data;
312 struct irq_fwspec parent_fwspec;
313 irq_hw_number_t hwirq, parent_hwirq;
314 unsigned int type;
315 int ret;
316
317 ret = qcom_pdc_translate(domain, fwspec, &hwirq, &type);
318 if (ret)
319 return ret;
320
321 ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
322 &qcom_pdc_gic_chip, NULL);
323 if (ret)
324 return ret;
325
326 if (hwirq == GPIO_NO_WAKE_IRQ)
327 return 0;
328
329 parent_hwirq = get_parent_hwirq(hwirq);
330 if (parent_hwirq == PDC_NO_PARENT_IRQ)
331 return 0;
332
333 if (type & IRQ_TYPE_EDGE_BOTH)
334 type = IRQ_TYPE_EDGE_RISING;
335
336 if (type & IRQ_TYPE_LEVEL_MASK)
337 type = IRQ_TYPE_LEVEL_HIGH;
338
339 parent_fwspec.fwnode = domain->parent->fwnode;
340 parent_fwspec.param_count = 3;
341 parent_fwspec.param[0] = 0;
342 parent_fwspec.param[1] = parent_hwirq;
343 parent_fwspec.param[2] = type;
344
345 return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs,
346 &parent_fwspec);
347 }
348
qcom_pdc_gpio_domain_select(struct irq_domain * d,struct irq_fwspec * fwspec,enum irq_domain_bus_token bus_token)349 static int qcom_pdc_gpio_domain_select(struct irq_domain *d,
350 struct irq_fwspec *fwspec,
351 enum irq_domain_bus_token bus_token)
352 {
353 return bus_token == DOMAIN_BUS_WAKEUP;
354 }
355
356 static const struct irq_domain_ops qcom_pdc_gpio_ops = {
357 .select = qcom_pdc_gpio_domain_select,
358 .alloc = qcom_pdc_gpio_alloc,
359 .free = irq_domain_free_irqs_common,
360 };
361
pdc_setup_pin_mapping(struct device_node * np)362 static int pdc_setup_pin_mapping(struct device_node *np)
363 {
364 int ret, n, i;
365 u32 irq_index, reg_index, val;
366
367 n = of_property_count_elems_of_size(np, "qcom,pdc-ranges", sizeof(u32));
368 if (n <= 0 || n % 3)
369 return -EINVAL;
370
371 pdc_region_cnt = n / 3;
372 pdc_region = kcalloc(pdc_region_cnt, sizeof(*pdc_region), GFP_KERNEL);
373 if (!pdc_region) {
374 pdc_region_cnt = 0;
375 return -ENOMEM;
376 }
377
378 for (n = 0; n < pdc_region_cnt; n++) {
379 ret = of_property_read_u32_index(np, "qcom,pdc-ranges",
380 n * 3 + 0,
381 &pdc_region[n].pin_base);
382 if (ret)
383 return ret;
384 ret = of_property_read_u32_index(np, "qcom,pdc-ranges",
385 n * 3 + 1,
386 &pdc_region[n].parent_base);
387 if (ret)
388 return ret;
389 ret = of_property_read_u32_index(np, "qcom,pdc-ranges",
390 n * 3 + 2,
391 &pdc_region[n].cnt);
392 if (ret)
393 return ret;
394
395 for (i = 0; i < pdc_region[n].cnt; i++) {
396 reg_index = (i + pdc_region[n].pin_base) >> 5;
397 irq_index = (i + pdc_region[n].pin_base) & 0x1f;
398 val = pdc_reg_read(IRQ_ENABLE_BANK, reg_index);
399 val &= ~BIT(irq_index);
400 pdc_reg_write(IRQ_ENABLE_BANK, reg_index, val);
401 }
402 }
403
404 return 0;
405 }
406
qcom_pdc_init(struct device_node * node,struct device_node * parent)407 static int qcom_pdc_init(struct device_node *node, struct device_node *parent)
408 {
409 struct irq_domain *parent_domain, *pdc_domain, *pdc_gpio_domain;
410 int ret;
411
412 pdc_base = of_iomap(node, 0);
413 if (!pdc_base) {
414 pr_err("%pOF: unable to map PDC registers\n", node);
415 return -ENXIO;
416 }
417
418 parent_domain = irq_find_host(parent);
419 if (!parent_domain) {
420 pr_err("%pOF: unable to find PDC's parent domain\n", node);
421 ret = -ENXIO;
422 goto fail;
423 }
424
425 ret = pdc_setup_pin_mapping(node);
426 if (ret) {
427 pr_err("%pOF: failed to init PDC pin-hwirq mapping\n", node);
428 goto fail;
429 }
430
431 pdc_domain = irq_domain_create_hierarchy(parent_domain, 0, PDC_MAX_IRQS,
432 of_fwnode_handle(node),
433 &qcom_pdc_ops, NULL);
434 if (!pdc_domain) {
435 pr_err("%pOF: GIC domain add failed\n", node);
436 ret = -ENOMEM;
437 goto fail;
438 }
439
440 pdc_gpio_domain = irq_domain_create_hierarchy(parent_domain,
441 IRQ_DOMAIN_FLAG_QCOM_PDC_WAKEUP,
442 PDC_MAX_GPIO_IRQS,
443 of_fwnode_handle(node),
444 &qcom_pdc_gpio_ops, NULL);
445 if (!pdc_gpio_domain) {
446 pr_err("%pOF: PDC domain add failed for GPIO domain\n", node);
447 ret = -ENOMEM;
448 goto remove;
449 }
450
451 irq_domain_update_bus_token(pdc_gpio_domain, DOMAIN_BUS_WAKEUP);
452
453 return 0;
454
455 remove:
456 irq_domain_remove(pdc_domain);
457 fail:
458 kfree(pdc_region);
459 iounmap(pdc_base);
460 return ret;
461 }
462
463 IRQCHIP_DECLARE(qcom_pdc, "qcom,pdc", qcom_pdc_init);
464