1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2018 Intel Corporation */
3
4 #ifndef _IGC_H_
5 #define _IGC_H_
6
7 #include <linux/kobject.h>
8 #include <linux/pci.h>
9 #include <linux/netdevice.h>
10 #include <linux/vmalloc.h>
11 #include <linux/ethtool.h>
12 #include <linux/sctp.h>
13 #include <linux/ptp_clock_kernel.h>
14 #include <linux/timecounter.h>
15 #include <linux/net_tstamp.h>
16
17 #include "igc_hw.h"
18
19 void igc_ethtool_set_ops(struct net_device *);
20
21 /* Transmit and receive queues */
22 #define IGC_MAX_RX_QUEUES 4
23 #define IGC_MAX_TX_QUEUES 4
24
25 #define MAX_Q_VECTORS 8
26 #define MAX_STD_JUMBO_FRAME_SIZE 9216
27
28 #define MAX_ETYPE_FILTER 8
29 #define IGC_RETA_SIZE 128
30
31 enum igc_mac_filter_type {
32 IGC_MAC_FILTER_TYPE_DST = 0,
33 IGC_MAC_FILTER_TYPE_SRC
34 };
35
36 struct igc_tx_queue_stats {
37 u64 packets;
38 u64 bytes;
39 u64 restart_queue;
40 u64 restart_queue2;
41 };
42
43 struct igc_rx_queue_stats {
44 u64 packets;
45 u64 bytes;
46 u64 drops;
47 u64 csum_err;
48 u64 alloc_failed;
49 };
50
51 struct igc_rx_packet_stats {
52 u64 ipv4_packets; /* IPv4 headers processed */
53 u64 ipv4e_packets; /* IPv4E headers with extensions processed */
54 u64 ipv6_packets; /* IPv6 headers processed */
55 u64 ipv6e_packets; /* IPv6E headers with extensions processed */
56 u64 tcp_packets; /* TCP headers processed */
57 u64 udp_packets; /* UDP headers processed */
58 u64 sctp_packets; /* SCTP headers processed */
59 u64 nfs_packets; /* NFS headers processe */
60 u64 other_packets;
61 };
62
63 struct igc_ring_container {
64 struct igc_ring *ring; /* pointer to linked list of rings */
65 unsigned int total_bytes; /* total bytes processed this int */
66 unsigned int total_packets; /* total packets processed this int */
67 u16 work_limit; /* total work allowed per interrupt */
68 u8 count; /* total number of rings in vector */
69 u8 itr; /* current ITR setting for ring */
70 };
71
72 struct igc_ring {
73 struct igc_q_vector *q_vector; /* backlink to q_vector */
74 struct net_device *netdev; /* back pointer to net_device */
75 struct device *dev; /* device for dma mapping */
76 union { /* array of buffer info structs */
77 struct igc_tx_buffer *tx_buffer_info;
78 struct igc_rx_buffer *rx_buffer_info;
79 };
80 void *desc; /* descriptor ring memory */
81 unsigned long flags; /* ring specific flags */
82 void __iomem *tail; /* pointer to ring tail register */
83 dma_addr_t dma; /* phys address of the ring */
84 unsigned int size; /* length of desc. ring in bytes */
85
86 u16 count; /* number of desc. in the ring */
87 u8 queue_index; /* logical index of the ring*/
88 u8 reg_idx; /* physical index of the ring */
89 bool launchtime_enable; /* true if LaunchTime is enabled */
90 ktime_t last_tx_cycle; /* end of the cycle with a launchtime transmission */
91 ktime_t last_ff_cycle; /* Last cycle with an active first flag */
92
93 u32 start_time;
94 u32 end_time;
95
96 /* everything past this point are written often */
97 u16 next_to_clean;
98 u16 next_to_use;
99 u16 next_to_alloc;
100
101 union {
102 /* TX */
103 struct {
104 struct igc_tx_queue_stats tx_stats;
105 struct u64_stats_sync tx_syncp;
106 struct u64_stats_sync tx_syncp2;
107 };
108 /* RX */
109 struct {
110 struct igc_rx_queue_stats rx_stats;
111 struct igc_rx_packet_stats pkt_stats;
112 struct u64_stats_sync rx_syncp;
113 struct sk_buff *skb;
114 };
115 };
116 } ____cacheline_internodealigned_in_smp;
117
118 /* Board specific private data structure */
119 struct igc_adapter {
120 struct net_device *netdev;
121
122 struct ethtool_eee eee;
123 u16 eee_advert;
124
125 unsigned long state;
126 unsigned int flags;
127 unsigned int num_q_vectors;
128
129 struct msix_entry *msix_entries;
130
131 /* TX */
132 u16 tx_work_limit;
133 u32 tx_timeout_count;
134 int num_tx_queues;
135 struct igc_ring *tx_ring[IGC_MAX_TX_QUEUES];
136
137 /* RX */
138 int num_rx_queues;
139 struct igc_ring *rx_ring[IGC_MAX_RX_QUEUES];
140
141 struct timer_list watchdog_timer;
142 struct timer_list dma_err_timer;
143 struct timer_list phy_info_timer;
144
145 u32 wol;
146 u32 en_mng_pt;
147 u16 link_speed;
148 u16 link_duplex;
149
150 u8 port_num;
151
152 u8 __iomem *io_addr;
153 /* Interrupt Throttle Rate */
154 u32 rx_itr_setting;
155 u32 tx_itr_setting;
156
157 struct work_struct reset_task;
158 struct work_struct watchdog_task;
159 struct work_struct dma_err_task;
160 bool fc_autoneg;
161
162 u8 tx_timeout_factor;
163
164 int msg_enable;
165 u32 max_frame_size;
166 u32 min_frame_size;
167
168 ktime_t base_time;
169 ktime_t cycle_time;
170
171 /* OS defined structs */
172 struct pci_dev *pdev;
173 /* lock for statistics */
174 spinlock_t stats64_lock;
175 struct rtnl_link_stats64 stats64;
176
177 /* structs defined in igc_hw.h */
178 struct igc_hw hw;
179 struct igc_hw_stats stats;
180
181 struct igc_q_vector *q_vector[MAX_Q_VECTORS];
182 u32 eims_enable_mask;
183 u32 eims_other;
184
185 u16 tx_ring_count;
186 u16 rx_ring_count;
187
188 u32 tx_hwtstamp_timeouts;
189 u32 tx_hwtstamp_skipped;
190 u32 rx_hwtstamp_cleared;
191
192 u32 rss_queues;
193 u32 rss_indir_tbl_init;
194
195 /* Any access to elements in nfc_rule_list is protected by the
196 * nfc_rule_lock.
197 */
198 struct mutex nfc_rule_lock;
199 struct list_head nfc_rule_list;
200 unsigned int nfc_rule_count;
201
202 u8 rss_indir_tbl[IGC_RETA_SIZE];
203
204 unsigned long link_check_timeout;
205 struct igc_info ei;
206
207 u32 test_icr;
208
209 struct ptp_clock *ptp_clock;
210 struct ptp_clock_info ptp_caps;
211 struct work_struct ptp_tx_work;
212 struct sk_buff *ptp_tx_skb;
213 struct hwtstamp_config tstamp_config;
214 unsigned long ptp_tx_start;
215 unsigned int ptp_flags;
216 /* System time value lock */
217 spinlock_t tmreg_lock;
218 struct cyclecounter cc;
219 struct timecounter tc;
220 struct timespec64 prev_ptp_time; /* Pre-reset PTP clock */
221 ktime_t ptp_reset_start; /* Reset time in clock mono */
222 };
223
224 void igc_up(struct igc_adapter *adapter);
225 void igc_down(struct igc_adapter *adapter);
226 int igc_open(struct net_device *netdev);
227 int igc_close(struct net_device *netdev);
228 int igc_setup_tx_resources(struct igc_ring *ring);
229 int igc_setup_rx_resources(struct igc_ring *ring);
230 void igc_free_tx_resources(struct igc_ring *ring);
231 void igc_free_rx_resources(struct igc_ring *ring);
232 unsigned int igc_get_max_rss_queues(struct igc_adapter *adapter);
233 void igc_set_flag_queue_pairs(struct igc_adapter *adapter,
234 const u32 max_rss_queues);
235 int igc_reinit_queues(struct igc_adapter *adapter);
236 void igc_write_rss_indir_tbl(struct igc_adapter *adapter);
237 bool igc_has_link(struct igc_adapter *adapter);
238 void igc_reset(struct igc_adapter *adapter);
239 int igc_set_spd_dplx(struct igc_adapter *adapter, u32 spd, u8 dplx);
240 void igc_update_stats(struct igc_adapter *adapter);
241
242 /* igc_dump declarations */
243 void igc_rings_dump(struct igc_adapter *adapter);
244 void igc_regs_dump(struct igc_adapter *adapter);
245
246 extern char igc_driver_name[];
247
248 #define IGC_REGS_LEN 740
249
250 /* flags controlling PTP/1588 function */
251 #define IGC_PTP_ENABLED BIT(0)
252
253 /* Flags definitions */
254 #define IGC_FLAG_HAS_MSI BIT(0)
255 #define IGC_FLAG_QUEUE_PAIRS BIT(3)
256 #define IGC_FLAG_DMAC BIT(4)
257 #define IGC_FLAG_PTP BIT(8)
258 #define IGC_FLAG_WOL_SUPPORTED BIT(8)
259 #define IGC_FLAG_NEED_LINK_UPDATE BIT(9)
260 #define IGC_FLAG_MEDIA_RESET BIT(10)
261 #define IGC_FLAG_MAS_ENABLE BIT(12)
262 #define IGC_FLAG_HAS_MSIX BIT(13)
263 #define IGC_FLAG_EEE BIT(14)
264 #define IGC_FLAG_VLAN_PROMISC BIT(15)
265 #define IGC_FLAG_RX_LEGACY BIT(16)
266 #define IGC_FLAG_TSN_QBV_ENABLED BIT(17)
267
268 #define IGC_FLAG_RSS_FIELD_IPV4_UDP BIT(6)
269 #define IGC_FLAG_RSS_FIELD_IPV6_UDP BIT(7)
270
271 #define IGC_MRQC_ENABLE_RSS_MQ 0x00000002
272 #define IGC_MRQC_RSS_FIELD_IPV4_UDP 0x00400000
273 #define IGC_MRQC_RSS_FIELD_IPV6_UDP 0x00800000
274
275 /* Interrupt defines */
276 #define IGC_START_ITR 648 /* ~6000 ints/sec */
277 #define IGC_4K_ITR 980
278 #define IGC_20K_ITR 196
279 #define IGC_70K_ITR 56
280
281 #define IGC_DEFAULT_ITR 3 /* dynamic */
282 #define IGC_MAX_ITR_USECS 10000
283 #define IGC_MIN_ITR_USECS 10
284 #define NON_Q_VECTORS 1
285 #define MAX_MSIX_ENTRIES 10
286
287 /* TX/RX descriptor defines */
288 #define IGC_DEFAULT_TXD 256
289 #define IGC_DEFAULT_TX_WORK 128
290 #define IGC_MIN_TXD 80
291 #define IGC_MAX_TXD 4096
292
293 #define IGC_DEFAULT_RXD 256
294 #define IGC_MIN_RXD 80
295 #define IGC_MAX_RXD 4096
296
297 /* Supported Rx Buffer Sizes */
298 #define IGC_RXBUFFER_256 256
299 #define IGC_RXBUFFER_2048 2048
300 #define IGC_RXBUFFER_3072 3072
301
302 #define AUTO_ALL_MODES 0
303 #define IGC_RX_HDR_LEN IGC_RXBUFFER_256
304
305 /* Transmit and receive latency (for PTP timestamps) */
306 #define IGC_I225_TX_LATENCY_10 240
307 #define IGC_I225_TX_LATENCY_100 58
308 #define IGC_I225_TX_LATENCY_1000 80
309 #define IGC_I225_TX_LATENCY_2500 1325
310 #define IGC_I225_RX_LATENCY_10 6450
311 #define IGC_I225_RX_LATENCY_100 185
312 #define IGC_I225_RX_LATENCY_1000 300
313 #define IGC_I225_RX_LATENCY_2500 1485
314
315 /* RX and TX descriptor control thresholds.
316 * PTHRESH - MAC will consider prefetch if it has fewer than this number of
317 * descriptors available in its onboard memory.
318 * Setting this to 0 disables RX descriptor prefetch.
319 * HTHRESH - MAC will only prefetch if there are at least this many descriptors
320 * available in host memory.
321 * If PTHRESH is 0, this should also be 0.
322 * WTHRESH - RX descriptor writeback threshold - MAC will delay writing back
323 * descriptors until either it has this many to write back, or the
324 * ITR timer expires.
325 */
326 #define IGC_RX_PTHRESH 8
327 #define IGC_RX_HTHRESH 8
328 #define IGC_TX_PTHRESH 8
329 #define IGC_TX_HTHRESH 1
330 #define IGC_RX_WTHRESH 4
331 #define IGC_TX_WTHRESH 16
332
333 #define IGC_RX_DMA_ATTR \
334 (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING)
335
336 #define IGC_TS_HDR_LEN 16
337
338 #define IGC_SKB_PAD (NET_SKB_PAD + NET_IP_ALIGN)
339
340 #if (PAGE_SIZE < 8192)
341 #define IGC_MAX_FRAME_BUILD_SKB \
342 (SKB_WITH_OVERHEAD(IGC_RXBUFFER_2048) - IGC_SKB_PAD - IGC_TS_HDR_LEN)
343 #else
344 #define IGC_MAX_FRAME_BUILD_SKB (IGC_RXBUFFER_2048 - IGC_TS_HDR_LEN)
345 #endif
346
347 /* How many Rx Buffers do we bundle into one write to the hardware ? */
348 #define IGC_RX_BUFFER_WRITE 16 /* Must be power of 2 */
349
350 /* VLAN info */
351 #define IGC_TX_FLAGS_VLAN_MASK 0xffff0000
352
353 /* igc_test_staterr - tests bits within Rx descriptor status and error fields */
igc_test_staterr(union igc_adv_rx_desc * rx_desc,const u32 stat_err_bits)354 static inline __le32 igc_test_staterr(union igc_adv_rx_desc *rx_desc,
355 const u32 stat_err_bits)
356 {
357 return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits);
358 }
359
360 enum igc_state_t {
361 __IGC_TESTING,
362 __IGC_RESETTING,
363 __IGC_DOWN,
364 __IGC_PTP_TX_IN_PROGRESS,
365 };
366
367 enum igc_tx_flags {
368 /* cmd_type flags */
369 IGC_TX_FLAGS_VLAN = 0x01,
370 IGC_TX_FLAGS_TSO = 0x02,
371 IGC_TX_FLAGS_TSTAMP = 0x04,
372
373 /* olinfo flags */
374 IGC_TX_FLAGS_IPV4 = 0x10,
375 IGC_TX_FLAGS_CSUM = 0x20,
376 };
377
378 enum igc_boards {
379 board_base,
380 };
381
382 /* The largest size we can write to the descriptor is 65535. In order to
383 * maintain a power of two alignment we have to limit ourselves to 32K.
384 */
385 #define IGC_MAX_TXD_PWR 15
386 #define IGC_MAX_DATA_PER_TXD BIT(IGC_MAX_TXD_PWR)
387
388 /* Tx Descriptors needed, worst case */
389 #define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IGC_MAX_DATA_PER_TXD)
390 #define DESC_NEEDED (MAX_SKB_FRAGS + 4)
391
392 /* wrapper around a pointer to a socket buffer,
393 * so a DMA handle can be stored along with the buffer
394 */
395 struct igc_tx_buffer {
396 union igc_adv_tx_desc *next_to_watch;
397 unsigned long time_stamp;
398 struct sk_buff *skb;
399 unsigned int bytecount;
400 u16 gso_segs;
401 __be16 protocol;
402
403 DEFINE_DMA_UNMAP_ADDR(dma);
404 DEFINE_DMA_UNMAP_LEN(len);
405 u32 tx_flags;
406 };
407
408 struct igc_rx_buffer {
409 dma_addr_t dma;
410 struct page *page;
411 #if (BITS_PER_LONG > 32) || (PAGE_SIZE >= 65536)
412 __u32 page_offset;
413 #else
414 __u16 page_offset;
415 #endif
416 __u16 pagecnt_bias;
417 };
418
419 struct igc_q_vector {
420 struct igc_adapter *adapter; /* backlink */
421 void __iomem *itr_register;
422 u32 eims_value; /* EIMS mask value */
423
424 u16 itr_val;
425 u8 set_itr;
426
427 struct igc_ring_container rx, tx;
428
429 struct napi_struct napi;
430
431 struct rcu_head rcu; /* to avoid race with update stats on free */
432 char name[IFNAMSIZ + 9];
433 struct net_device poll_dev;
434
435 /* for dynamic allocation of rings associated with this q_vector */
436 struct igc_ring ring[] ____cacheline_internodealigned_in_smp;
437 };
438
439 enum igc_filter_match_flags {
440 IGC_FILTER_FLAG_ETHER_TYPE = 0x1,
441 IGC_FILTER_FLAG_VLAN_TCI = 0x2,
442 IGC_FILTER_FLAG_SRC_MAC_ADDR = 0x4,
443 IGC_FILTER_FLAG_DST_MAC_ADDR = 0x8,
444 };
445
446 struct igc_nfc_filter {
447 u8 match_flags;
448 u16 etype;
449 u16 vlan_tci;
450 u8 src_addr[ETH_ALEN];
451 u8 dst_addr[ETH_ALEN];
452 };
453
454 struct igc_nfc_rule {
455 struct list_head list;
456 struct igc_nfc_filter filter;
457 u32 location;
458 u16 action;
459 };
460
461 /* IGC supports a total of 32 NFC rules: 16 MAC address based,, 8 VLAN priority
462 * based, and 8 ethertype based.
463 */
464 #define IGC_MAX_RXNFC_RULES 32
465
466 /* igc_desc_unused - calculate if we have unused descriptors */
igc_desc_unused(const struct igc_ring * ring)467 static inline u16 igc_desc_unused(const struct igc_ring *ring)
468 {
469 u16 ntc = ring->next_to_clean;
470 u16 ntu = ring->next_to_use;
471
472 return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1;
473 }
474
igc_get_phy_info(struct igc_hw * hw)475 static inline s32 igc_get_phy_info(struct igc_hw *hw)
476 {
477 if (hw->phy.ops.get_phy_info)
478 return hw->phy.ops.get_phy_info(hw);
479
480 return 0;
481 }
482
igc_reset_phy(struct igc_hw * hw)483 static inline s32 igc_reset_phy(struct igc_hw *hw)
484 {
485 if (hw->phy.ops.reset)
486 return hw->phy.ops.reset(hw);
487
488 return 0;
489 }
490
txring_txq(const struct igc_ring * tx_ring)491 static inline struct netdev_queue *txring_txq(const struct igc_ring *tx_ring)
492 {
493 return netdev_get_tx_queue(tx_ring->netdev, tx_ring->queue_index);
494 }
495
496 enum igc_ring_flags_t {
497 IGC_RING_FLAG_RX_3K_BUFFER,
498 IGC_RING_FLAG_RX_BUILD_SKB_ENABLED,
499 IGC_RING_FLAG_RX_SCTP_CSUM,
500 IGC_RING_FLAG_RX_LB_VLAN_BSWAP,
501 IGC_RING_FLAG_TX_CTX_IDX,
502 IGC_RING_FLAG_TX_DETECT_HANG
503 };
504
505 #define ring_uses_large_buffer(ring) \
506 test_bit(IGC_RING_FLAG_RX_3K_BUFFER, &(ring)->flags)
507
508 #define ring_uses_build_skb(ring) \
509 test_bit(IGC_RING_FLAG_RX_BUILD_SKB_ENABLED, &(ring)->flags)
510
igc_rx_bufsz(struct igc_ring * ring)511 static inline unsigned int igc_rx_bufsz(struct igc_ring *ring)
512 {
513 #if (PAGE_SIZE < 8192)
514 if (ring_uses_large_buffer(ring))
515 return IGC_RXBUFFER_3072;
516
517 if (ring_uses_build_skb(ring))
518 return IGC_MAX_FRAME_BUILD_SKB + IGC_TS_HDR_LEN;
519 #endif
520 return IGC_RXBUFFER_2048;
521 }
522
igc_rx_pg_order(struct igc_ring * ring)523 static inline unsigned int igc_rx_pg_order(struct igc_ring *ring)
524 {
525 #if (PAGE_SIZE < 8192)
526 if (ring_uses_large_buffer(ring))
527 return 1;
528 #endif
529 return 0;
530 }
531
igc_read_phy_reg(struct igc_hw * hw,u32 offset,u16 * data)532 static inline s32 igc_read_phy_reg(struct igc_hw *hw, u32 offset, u16 *data)
533 {
534 if (hw->phy.ops.read_reg)
535 return hw->phy.ops.read_reg(hw, offset, data);
536
537 return -EOPNOTSUPP;
538 }
539
540 void igc_reinit_locked(struct igc_adapter *);
541 struct igc_nfc_rule *igc_get_nfc_rule(struct igc_adapter *adapter,
542 u32 location);
543 int igc_add_nfc_rule(struct igc_adapter *adapter, struct igc_nfc_rule *rule);
544 void igc_del_nfc_rule(struct igc_adapter *adapter, struct igc_nfc_rule *rule);
545
546 void igc_ptp_init(struct igc_adapter *adapter);
547 void igc_ptp_reset(struct igc_adapter *adapter);
548 void igc_ptp_suspend(struct igc_adapter *adapter);
549 void igc_ptp_stop(struct igc_adapter *adapter);
550 void igc_ptp_rx_pktstamp(struct igc_q_vector *q_vector, __le32 *va,
551 struct sk_buff *skb);
552 int igc_ptp_set_ts_config(struct net_device *netdev, struct ifreq *ifr);
553 int igc_ptp_get_ts_config(struct net_device *netdev, struct ifreq *ifr);
554 void igc_ptp_tx_hang(struct igc_adapter *adapter);
555 void igc_ptp_read(struct igc_adapter *adapter, struct timespec64 *ts);
556
557 #define igc_rx_pg_size(_ring) (PAGE_SIZE << igc_rx_pg_order(_ring))
558
559 #define IGC_TXD_DCMD (IGC_ADVTXD_DCMD_EOP | IGC_ADVTXD_DCMD_RS)
560
561 #define IGC_RX_DESC(R, i) \
562 (&(((union igc_adv_rx_desc *)((R)->desc))[i]))
563 #define IGC_TX_DESC(R, i) \
564 (&(((union igc_adv_tx_desc *)((R)->desc))[i]))
565 #define IGC_TX_CTXTDESC(R, i) \
566 (&(((struct igc_adv_tx_context_desc *)((R)->desc))[i]))
567
568 #endif /* _IGC_H_ */
569