• Home
  • Line#
  • Scopes#
  • Navigate#
  • Raw
  • Download
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  *  Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved.
4  */
5 
6 #include <linux/signal.h>
7 #include <linux/slab.h>
8 #include <linux/module.h>
9 #include <linux/netdevice.h>
10 #include <linux/etherdevice.h>
11 #include <linux/mii.h>
12 #include <linux/ethtool.h>
13 #include <linux/usb.h>
14 #include <linux/crc32.h>
15 #include <linux/if_vlan.h>
16 #include <linux/uaccess.h>
17 #include <linux/list.h>
18 #include <linux/ip.h>
19 #include <linux/ipv6.h>
20 #include <net/ip6_checksum.h>
21 #include <uapi/linux/mdio.h>
22 #include <linux/mdio.h>
23 #include <linux/usb/cdc.h>
24 #include <linux/suspend.h>
25 #include <linux/atomic.h>
26 #include <linux/acpi.h>
27 #include <linux/firmware.h>
28 #include <crypto/hash.h>
29 
30 /* Information for net-next */
31 #define NETNEXT_VERSION		"11"
32 
33 /* Information for net */
34 #define NET_VERSION		"11"
35 
36 #define DRIVER_VERSION		"v1." NETNEXT_VERSION "." NET_VERSION
37 #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>"
38 #define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters"
39 #define MODULENAME "r8152"
40 
41 #define R8152_PHY_ID		32
42 
43 #define PLA_IDR			0xc000
44 #define PLA_RCR			0xc010
45 #define PLA_RMS			0xc016
46 #define PLA_RXFIFO_CTRL0	0xc0a0
47 #define PLA_RXFIFO_CTRL1	0xc0a4
48 #define PLA_RXFIFO_CTRL2	0xc0a8
49 #define PLA_DMY_REG0		0xc0b0
50 #define PLA_FMC			0xc0b4
51 #define PLA_CFG_WOL		0xc0b6
52 #define PLA_TEREDO_CFG		0xc0bc
53 #define PLA_TEREDO_WAKE_BASE	0xc0c4
54 #define PLA_MAR			0xcd00
55 #define PLA_BACKUP		0xd000
56 #define PLA_BDC_CR		0xd1a0
57 #define PLA_TEREDO_TIMER	0xd2cc
58 #define PLA_REALWOW_TIMER	0xd2e8
59 #define PLA_UPHY_TIMER		0xd388
60 #define PLA_SUSPEND_FLAG	0xd38a
61 #define PLA_INDICATE_FALG	0xd38c
62 #define PLA_MACDBG_PRE		0xd38c	/* RTL_VER_04 only */
63 #define PLA_MACDBG_POST		0xd38e	/* RTL_VER_04 only */
64 #define PLA_EXTRA_STATUS	0xd398
65 #define PLA_EFUSE_DATA		0xdd00
66 #define PLA_EFUSE_CMD		0xdd02
67 #define PLA_LEDSEL		0xdd90
68 #define PLA_LED_FEATURE		0xdd92
69 #define PLA_PHYAR		0xde00
70 #define PLA_BOOT_CTRL		0xe004
71 #define PLA_LWAKE_CTRL_REG	0xe007
72 #define PLA_GPHY_INTR_IMR	0xe022
73 #define PLA_EEE_CR		0xe040
74 #define PLA_EEEP_CR		0xe080
75 #define PLA_MAC_PWR_CTRL	0xe0c0
76 #define PLA_MAC_PWR_CTRL2	0xe0ca
77 #define PLA_MAC_PWR_CTRL3	0xe0cc
78 #define PLA_MAC_PWR_CTRL4	0xe0ce
79 #define PLA_WDT6_CTRL		0xe428
80 #define PLA_TCR0		0xe610
81 #define PLA_TCR1		0xe612
82 #define PLA_MTPS		0xe615
83 #define PLA_TXFIFO_CTRL		0xe618
84 #define PLA_RSTTALLY		0xe800
85 #define PLA_CR			0xe813
86 #define PLA_CRWECR		0xe81c
87 #define PLA_CONFIG12		0xe81e	/* CONFIG1, CONFIG2 */
88 #define PLA_CONFIG34		0xe820	/* CONFIG3, CONFIG4 */
89 #define PLA_CONFIG5		0xe822
90 #define PLA_PHY_PWR		0xe84c
91 #define PLA_OOB_CTRL		0xe84f
92 #define PLA_CPCR		0xe854
93 #define PLA_MISC_0		0xe858
94 #define PLA_MISC_1		0xe85a
95 #define PLA_OCP_GPHY_BASE	0xe86c
96 #define PLA_TALLYCNT		0xe890
97 #define PLA_SFF_STS_7		0xe8de
98 #define PLA_PHYSTATUS		0xe908
99 #define PLA_CONFIG6		0xe90a /* CONFIG6 */
100 #define PLA_BP_BA		0xfc26
101 #define PLA_BP_0		0xfc28
102 #define PLA_BP_1		0xfc2a
103 #define PLA_BP_2		0xfc2c
104 #define PLA_BP_3		0xfc2e
105 #define PLA_BP_4		0xfc30
106 #define PLA_BP_5		0xfc32
107 #define PLA_BP_6		0xfc34
108 #define PLA_BP_7		0xfc36
109 #define PLA_BP_EN		0xfc38
110 
111 #define USB_USB2PHY		0xb41e
112 #define USB_SSPHYLINK1		0xb426
113 #define USB_SSPHYLINK2		0xb428
114 #define USB_U2P3_CTRL		0xb460
115 #define USB_CSR_DUMMY1		0xb464
116 #define USB_CSR_DUMMY2		0xb466
117 #define USB_DEV_STAT		0xb808
118 #define USB_CONNECT_TIMER	0xcbf8
119 #define USB_MSC_TIMER		0xcbfc
120 #define USB_BURST_SIZE		0xcfc0
121 #define USB_FW_FIX_EN0		0xcfca
122 #define USB_FW_FIX_EN1		0xcfcc
123 #define USB_LPM_CONFIG		0xcfd8
124 #define USB_CSTMR		0xcfef	/* RTL8153A */
125 #define USB_FW_CTRL		0xd334	/* RTL8153B */
126 #define USB_FC_TIMER		0xd340
127 #define USB_USB_CTRL		0xd406
128 #define USB_PHY_CTRL		0xd408
129 #define USB_TX_AGG		0xd40a
130 #define USB_RX_BUF_TH		0xd40c
131 #define USB_USB_TIMER		0xd428
132 #define USB_RX_EARLY_TIMEOUT	0xd42c
133 #define USB_RX_EARLY_SIZE	0xd42e
134 #define USB_PM_CTRL_STATUS	0xd432	/* RTL8153A */
135 #define USB_RX_EXTRA_AGGR_TMR	0xd432	/* RTL8153B */
136 #define USB_TX_DMA		0xd434
137 #define USB_UPT_RXDMA_OWN	0xd437
138 #define USB_TOLERANCE		0xd490
139 #define USB_LPM_CTRL		0xd41a
140 #define USB_BMU_RESET		0xd4b0
141 #define USB_U1U2_TIMER		0xd4da
142 #define USB_FW_TASK		0xd4e8	/* RTL8153B */
143 #define USB_UPS_CTRL		0xd800
144 #define USB_POWER_CUT		0xd80a
145 #define USB_MISC_0		0xd81a
146 #define USB_MISC_1		0xd81f
147 #define USB_AFE_CTRL2		0xd824
148 #define USB_UPS_CFG		0xd842
149 #define USB_UPS_FLAGS		0xd848
150 #define USB_WDT1_CTRL		0xe404
151 #define USB_WDT11_CTRL		0xe43c
152 #define USB_BP_BA		PLA_BP_BA
153 #define USB_BP_0		PLA_BP_0
154 #define USB_BP_1		PLA_BP_1
155 #define USB_BP_2		PLA_BP_2
156 #define USB_BP_3		PLA_BP_3
157 #define USB_BP_4		PLA_BP_4
158 #define USB_BP_5		PLA_BP_5
159 #define USB_BP_6		PLA_BP_6
160 #define USB_BP_7		PLA_BP_7
161 #define USB_BP_EN		PLA_BP_EN	/* RTL8153A */
162 #define USB_BP_8		0xfc38		/* RTL8153B */
163 #define USB_BP_9		0xfc3a
164 #define USB_BP_10		0xfc3c
165 #define USB_BP_11		0xfc3e
166 #define USB_BP_12		0xfc40
167 #define USB_BP_13		0xfc42
168 #define USB_BP_14		0xfc44
169 #define USB_BP_15		0xfc46
170 #define USB_BP2_EN		0xfc48
171 
172 /* OCP Registers */
173 #define OCP_ALDPS_CONFIG	0x2010
174 #define OCP_EEE_CONFIG1		0x2080
175 #define OCP_EEE_CONFIG2		0x2092
176 #define OCP_EEE_CONFIG3		0x2094
177 #define OCP_BASE_MII		0xa400
178 #define OCP_EEE_AR		0xa41a
179 #define OCP_EEE_DATA		0xa41c
180 #define OCP_PHY_STATUS		0xa420
181 #define OCP_NCTL_CFG		0xa42c
182 #define OCP_POWER_CFG		0xa430
183 #define OCP_EEE_CFG		0xa432
184 #define OCP_SRAM_ADDR		0xa436
185 #define OCP_SRAM_DATA		0xa438
186 #define OCP_DOWN_SPEED		0xa442
187 #define OCP_EEE_ABLE		0xa5c4
188 #define OCP_EEE_ADV		0xa5d0
189 #define OCP_EEE_LPABLE		0xa5d2
190 #define OCP_PHY_STATE		0xa708		/* nway state for 8153 */
191 #define OCP_PHY_PATCH_STAT	0xb800
192 #define OCP_PHY_PATCH_CMD	0xb820
193 #define OCP_PHY_LOCK		0xb82e
194 #define OCP_ADC_IOFFSET		0xbcfc
195 #define OCP_ADC_CFG		0xbc06
196 #define OCP_SYSCLK_CFG		0xc416
197 
198 /* SRAM Register */
199 #define SRAM_GREEN_CFG		0x8011
200 #define SRAM_LPF_CFG		0x8012
201 #define SRAM_10M_AMP1		0x8080
202 #define SRAM_10M_AMP2		0x8082
203 #define SRAM_IMPEDANCE		0x8084
204 #define SRAM_PHY_LOCK		0xb82e
205 
206 /* PLA_RCR */
207 #define RCR_AAP			0x00000001
208 #define RCR_APM			0x00000002
209 #define RCR_AM			0x00000004
210 #define RCR_AB			0x00000008
211 #define RCR_ACPT_ALL		(RCR_AAP | RCR_APM | RCR_AM | RCR_AB)
212 
213 /* PLA_RXFIFO_CTRL0 */
214 #define RXFIFO_THR1_NORMAL	0x00080002
215 #define RXFIFO_THR1_OOB		0x01800003
216 
217 /* PLA_RXFIFO_CTRL1 */
218 #define RXFIFO_THR2_FULL	0x00000060
219 #define RXFIFO_THR2_HIGH	0x00000038
220 #define RXFIFO_THR2_OOB		0x0000004a
221 #define RXFIFO_THR2_NORMAL	0x00a0
222 
223 /* PLA_RXFIFO_CTRL2 */
224 #define RXFIFO_THR3_FULL	0x00000078
225 #define RXFIFO_THR3_HIGH	0x00000048
226 #define RXFIFO_THR3_OOB		0x0000005a
227 #define RXFIFO_THR3_NORMAL	0x0110
228 
229 /* PLA_TXFIFO_CTRL */
230 #define TXFIFO_THR_NORMAL	0x00400008
231 #define TXFIFO_THR_NORMAL2	0x01000008
232 
233 /* PLA_DMY_REG0 */
234 #define ECM_ALDPS		0x0002
235 
236 /* PLA_FMC */
237 #define FMC_FCR_MCU_EN		0x0001
238 
239 /* PLA_EEEP_CR */
240 #define EEEP_CR_EEEP_TX		0x0002
241 
242 /* PLA_WDT6_CTRL */
243 #define WDT6_SET_MODE		0x0010
244 
245 /* PLA_TCR0 */
246 #define TCR0_TX_EMPTY		0x0800
247 #define TCR0_AUTO_FIFO		0x0080
248 
249 /* PLA_TCR1 */
250 #define VERSION_MASK		0x7cf0
251 
252 /* PLA_MTPS */
253 #define MTPS_JUMBO		(12 * 1024 / 64)
254 #define MTPS_DEFAULT		(6 * 1024 / 64)
255 
256 /* PLA_RSTTALLY */
257 #define TALLY_RESET		0x0001
258 
259 /* PLA_CR */
260 #define CR_RST			0x10
261 #define CR_RE			0x08
262 #define CR_TE			0x04
263 
264 /* PLA_CRWECR */
265 #define CRWECR_NORAML		0x00
266 #define CRWECR_CONFIG		0xc0
267 
268 /* PLA_OOB_CTRL */
269 #define NOW_IS_OOB		0x80
270 #define TXFIFO_EMPTY		0x20
271 #define RXFIFO_EMPTY		0x10
272 #define LINK_LIST_READY		0x02
273 #define DIS_MCU_CLROOB		0x01
274 #define FIFO_EMPTY		(TXFIFO_EMPTY | RXFIFO_EMPTY)
275 
276 /* PLA_MISC_1 */
277 #define RXDY_GATED_EN		0x0008
278 
279 /* PLA_SFF_STS_7 */
280 #define RE_INIT_LL		0x8000
281 #define MCU_BORW_EN		0x4000
282 
283 /* PLA_CPCR */
284 #define CPCR_RX_VLAN		0x0040
285 
286 /* PLA_CFG_WOL */
287 #define MAGIC_EN		0x0001
288 
289 /* PLA_TEREDO_CFG */
290 #define TEREDO_SEL		0x8000
291 #define TEREDO_WAKE_MASK	0x7f00
292 #define TEREDO_RS_EVENT_MASK	0x00fe
293 #define OOB_TEREDO_EN		0x0001
294 
295 /* PLA_BDC_CR */
296 #define ALDPS_PROXY_MODE	0x0001
297 
298 /* PLA_EFUSE_CMD */
299 #define EFUSE_READ_CMD		BIT(15)
300 #define EFUSE_DATA_BIT16	BIT(7)
301 
302 /* PLA_CONFIG34 */
303 #define LINK_ON_WAKE_EN		0x0010
304 #define LINK_OFF_WAKE_EN	0x0008
305 
306 /* PLA_CONFIG6 */
307 #define LANWAKE_CLR_EN		BIT(0)
308 
309 /* PLA_CONFIG5 */
310 #define BWF_EN			0x0040
311 #define MWF_EN			0x0020
312 #define UWF_EN			0x0010
313 #define LAN_WAKE_EN		0x0002
314 
315 /* PLA_LED_FEATURE */
316 #define LED_MODE_MASK		0x0700
317 
318 /* PLA_PHY_PWR */
319 #define TX_10M_IDLE_EN		0x0080
320 #define PFM_PWM_SWITCH		0x0040
321 #define TEST_IO_OFF		BIT(4)
322 
323 /* PLA_MAC_PWR_CTRL */
324 #define D3_CLK_GATED_EN		0x00004000
325 #define MCU_CLK_RATIO		0x07010f07
326 #define MCU_CLK_RATIO_MASK	0x0f0f0f0f
327 #define ALDPS_SPDWN_RATIO	0x0f87
328 
329 /* PLA_MAC_PWR_CTRL2 */
330 #define EEE_SPDWN_RATIO		0x8007
331 #define MAC_CLK_SPDWN_EN	BIT(15)
332 
333 /* PLA_MAC_PWR_CTRL3 */
334 #define PLA_MCU_SPDWN_EN	BIT(14)
335 #define PKT_AVAIL_SPDWN_EN	0x0100
336 #define SUSPEND_SPDWN_EN	0x0004
337 #define U1U2_SPDWN_EN		0x0002
338 #define L1_SPDWN_EN		0x0001
339 
340 /* PLA_MAC_PWR_CTRL4 */
341 #define PWRSAVE_SPDWN_EN	0x1000
342 #define RXDV_SPDWN_EN		0x0800
343 #define TX10MIDLE_EN		0x0100
344 #define TP100_SPDWN_EN		0x0020
345 #define TP500_SPDWN_EN		0x0010
346 #define TP1000_SPDWN_EN		0x0008
347 #define EEE_SPDWN_EN		0x0001
348 
349 /* PLA_GPHY_INTR_IMR */
350 #define GPHY_STS_MSK		0x0001
351 #define SPEED_DOWN_MSK		0x0002
352 #define SPDWN_RXDV_MSK		0x0004
353 #define SPDWN_LINKCHG_MSK	0x0008
354 
355 /* PLA_PHYAR */
356 #define PHYAR_FLAG		0x80000000
357 
358 /* PLA_EEE_CR */
359 #define EEE_RX_EN		0x0001
360 #define EEE_TX_EN		0x0002
361 
362 /* PLA_BOOT_CTRL */
363 #define AUTOLOAD_DONE		0x0002
364 
365 /* PLA_LWAKE_CTRL_REG */
366 #define LANWAKE_PIN		BIT(7)
367 
368 /* PLA_SUSPEND_FLAG */
369 #define LINK_CHG_EVENT		BIT(0)
370 
371 /* PLA_INDICATE_FALG */
372 #define UPCOMING_RUNTIME_D3	BIT(0)
373 
374 /* PLA_MACDBG_PRE and PLA_MACDBG_POST */
375 #define DEBUG_OE		BIT(0)
376 #define DEBUG_LTSSM		0x0082
377 
378 /* PLA_EXTRA_STATUS */
379 #define CUR_LINK_OK		BIT(15)
380 #define U3P3_CHECK_EN		BIT(7)	/* RTL_VER_05 only */
381 #define LINK_CHANGE_FLAG	BIT(8)
382 #define POLL_LINK_CHG		BIT(0)
383 
384 /* USB_USB2PHY */
385 #define USB2PHY_SUSPEND		0x0001
386 #define USB2PHY_L1		0x0002
387 
388 /* USB_SSPHYLINK1 */
389 #define DELAY_PHY_PWR_CHG	BIT(1)
390 
391 /* USB_SSPHYLINK2 */
392 #define pwd_dn_scale_mask	0x3ffe
393 #define pwd_dn_scale(x)		((x) << 1)
394 
395 /* USB_CSR_DUMMY1 */
396 #define DYNAMIC_BURST		0x0001
397 
398 /* USB_CSR_DUMMY2 */
399 #define EP4_FULL_FC		0x0001
400 
401 /* USB_DEV_STAT */
402 #define STAT_SPEED_MASK		0x0006
403 #define STAT_SPEED_HIGH		0x0000
404 #define STAT_SPEED_FULL		0x0002
405 
406 /* USB_FW_FIX_EN0 */
407 #define FW_FIX_SUSPEND		BIT(14)
408 
409 /* USB_FW_FIX_EN1 */
410 #define FW_IP_RESET_EN		BIT(9)
411 
412 /* USB_LPM_CONFIG */
413 #define LPM_U1U2_EN		BIT(0)
414 
415 /* USB_TX_AGG */
416 #define TX_AGG_MAX_THRESHOLD	0x03
417 
418 /* USB_RX_BUF_TH */
419 #define RX_THR_SUPPER		0x0c350180
420 #define RX_THR_HIGH		0x7a120180
421 #define RX_THR_SLOW		0xffff0180
422 #define RX_THR_B		0x00010001
423 
424 /* USB_TX_DMA */
425 #define TEST_MODE_DISABLE	0x00000001
426 #define TX_SIZE_ADJUST1		0x00000100
427 
428 /* USB_BMU_RESET */
429 #define BMU_RESET_EP_IN		0x01
430 #define BMU_RESET_EP_OUT	0x02
431 
432 /* USB_UPT_RXDMA_OWN */
433 #define OWN_UPDATE		BIT(0)
434 #define OWN_CLEAR		BIT(1)
435 
436 /* USB_FW_TASK */
437 #define FC_PATCH_TASK		BIT(1)
438 
439 /* USB_UPS_CTRL */
440 #define POWER_CUT		0x0100
441 
442 /* USB_PM_CTRL_STATUS */
443 #define RESUME_INDICATE		0x0001
444 
445 /* USB_CSTMR */
446 #define FORCE_SUPER		BIT(0)
447 
448 /* USB_FW_CTRL */
449 #define FLOW_CTRL_PATCH_OPT	BIT(1)
450 
451 /* USB_FC_TIMER */
452 #define CTRL_TIMER_EN		BIT(15)
453 
454 /* USB_USB_CTRL */
455 #define RX_AGG_DISABLE		0x0010
456 #define RX_ZERO_EN		0x0080
457 
458 /* USB_U2P3_CTRL */
459 #define U2P3_ENABLE		0x0001
460 
461 /* USB_POWER_CUT */
462 #define PWR_EN			0x0001
463 #define PHASE2_EN		0x0008
464 #define UPS_EN			BIT(4)
465 #define USP_PREWAKE		BIT(5)
466 
467 /* USB_MISC_0 */
468 #define PCUT_STATUS		0x0001
469 
470 /* USB_RX_EARLY_TIMEOUT */
471 #define COALESCE_SUPER		 85000U
472 #define COALESCE_HIGH		250000U
473 #define COALESCE_SLOW		524280U
474 
475 /* USB_WDT1_CTRL */
476 #define WTD1_EN			BIT(0)
477 
478 /* USB_WDT11_CTRL */
479 #define TIMER11_EN		0x0001
480 
481 /* USB_LPM_CTRL */
482 /* bit 4 ~ 5: fifo empty boundary */
483 #define FIFO_EMPTY_1FB		0x30	/* 0x1fb * 64 = 32448 bytes */
484 /* bit 2 ~ 3: LMP timer */
485 #define LPM_TIMER_MASK		0x0c
486 #define LPM_TIMER_500MS		0x04	/* 500 ms */
487 #define LPM_TIMER_500US		0x0c	/* 500 us */
488 #define ROK_EXIT_LPM		0x02
489 
490 /* USB_AFE_CTRL2 */
491 #define SEN_VAL_MASK		0xf800
492 #define SEN_VAL_NORMAL		0xa000
493 #define SEL_RXIDLE		0x0100
494 
495 /* USB_UPS_CFG */
496 #define SAW_CNT_1MS_MASK	0x0fff
497 
498 /* USB_UPS_FLAGS */
499 #define UPS_FLAGS_R_TUNE		BIT(0)
500 #define UPS_FLAGS_EN_10M_CKDIV		BIT(1)
501 #define UPS_FLAGS_250M_CKDIV		BIT(2)
502 #define UPS_FLAGS_EN_ALDPS		BIT(3)
503 #define UPS_FLAGS_CTAP_SHORT_DIS	BIT(4)
504 #define ups_flags_speed(x)		((x) << 16)
505 #define UPS_FLAGS_EN_EEE		BIT(20)
506 #define UPS_FLAGS_EN_500M_EEE		BIT(21)
507 #define UPS_FLAGS_EN_EEE_CKDIV		BIT(22)
508 #define UPS_FLAGS_EEE_PLLOFF_100	BIT(23)
509 #define UPS_FLAGS_EEE_PLLOFF_GIGA	BIT(24)
510 #define UPS_FLAGS_EEE_CMOD_LV_EN	BIT(25)
511 #define UPS_FLAGS_EN_GREEN		BIT(26)
512 #define UPS_FLAGS_EN_FLOW_CTR		BIT(27)
513 
514 enum spd_duplex {
515 	NWAY_10M_HALF,
516 	NWAY_10M_FULL,
517 	NWAY_100M_HALF,
518 	NWAY_100M_FULL,
519 	NWAY_1000M_FULL,
520 	FORCE_10M_HALF,
521 	FORCE_10M_FULL,
522 	FORCE_100M_HALF,
523 	FORCE_100M_FULL,
524 };
525 
526 /* OCP_ALDPS_CONFIG */
527 #define ENPWRSAVE		0x8000
528 #define ENPDNPS			0x0200
529 #define LINKENA			0x0100
530 #define DIS_SDSAVE		0x0010
531 
532 /* OCP_PHY_STATUS */
533 #define PHY_STAT_MASK		0x0007
534 #define PHY_STAT_EXT_INIT	2
535 #define PHY_STAT_LAN_ON		3
536 #define PHY_STAT_PWRDN		5
537 
538 /* OCP_NCTL_CFG */
539 #define PGA_RETURN_EN		BIT(1)
540 
541 /* OCP_POWER_CFG */
542 #define EEE_CLKDIV_EN		0x8000
543 #define EN_ALDPS		0x0004
544 #define EN_10M_PLLOFF		0x0001
545 
546 /* OCP_EEE_CONFIG1 */
547 #define RG_TXLPI_MSK_HFDUP	0x8000
548 #define RG_MATCLR_EN		0x4000
549 #define EEE_10_CAP		0x2000
550 #define EEE_NWAY_EN		0x1000
551 #define TX_QUIET_EN		0x0200
552 #define RX_QUIET_EN		0x0100
553 #define sd_rise_time_mask	0x0070
554 #define sd_rise_time(x)		(min(x, 7) << 4)	/* bit 4 ~ 6 */
555 #define RG_RXLPI_MSK_HFDUP	0x0008
556 #define SDFALLTIME		0x0007	/* bit 0 ~ 2 */
557 
558 /* OCP_EEE_CONFIG2 */
559 #define RG_LPIHYS_NUM		0x7000	/* bit 12 ~ 15 */
560 #define RG_DACQUIET_EN		0x0400
561 #define RG_LDVQUIET_EN		0x0200
562 #define RG_CKRSEL		0x0020
563 #define RG_EEEPRG_EN		0x0010
564 
565 /* OCP_EEE_CONFIG3 */
566 #define fast_snr_mask		0xff80
567 #define fast_snr(x)		(min(x, 0x1ff) << 7)	/* bit 7 ~ 15 */
568 #define RG_LFS_SEL		0x0060	/* bit 6 ~ 5 */
569 #define MSK_PH			0x0006	/* bit 0 ~ 3 */
570 
571 /* OCP_EEE_AR */
572 /* bit[15:14] function */
573 #define FUN_ADDR		0x0000
574 #define FUN_DATA		0x4000
575 /* bit[4:0] device addr */
576 
577 /* OCP_EEE_CFG */
578 #define CTAP_SHORT_EN		0x0040
579 #define EEE10_EN		0x0010
580 
581 /* OCP_DOWN_SPEED */
582 #define EN_EEE_CMODE		BIT(14)
583 #define EN_EEE_1000		BIT(13)
584 #define EN_EEE_100		BIT(12)
585 #define EN_10M_CLKDIV		BIT(11)
586 #define EN_10M_BGOFF		0x0080
587 
588 /* OCP_PHY_STATE */
589 #define TXDIS_STATE		0x01
590 #define ABD_STATE		0x02
591 
592 /* OCP_PHY_PATCH_STAT */
593 #define PATCH_READY		BIT(6)
594 
595 /* OCP_PHY_PATCH_CMD */
596 #define PATCH_REQUEST		BIT(4)
597 
598 /* OCP_PHY_LOCK */
599 #define PATCH_LOCK		BIT(0)
600 
601 /* OCP_ADC_CFG */
602 #define CKADSEL_L		0x0100
603 #define ADC_EN			0x0080
604 #define EN_EMI_L		0x0040
605 
606 /* OCP_SYSCLK_CFG */
607 #define clk_div_expo(x)		(min(x, 5) << 8)
608 
609 /* SRAM_GREEN_CFG */
610 #define GREEN_ETH_EN		BIT(15)
611 #define R_TUNE_EN		BIT(11)
612 
613 /* SRAM_LPF_CFG */
614 #define LPF_AUTO_TUNE		0x8000
615 
616 /* SRAM_10M_AMP1 */
617 #define GDAC_IB_UPALL		0x0008
618 
619 /* SRAM_10M_AMP2 */
620 #define AMP_DN			0x0200
621 
622 /* SRAM_IMPEDANCE */
623 #define RX_DRIVING_MASK		0x6000
624 
625 /* SRAM_PHY_LOCK */
626 #define PHY_PATCH_LOCK		0x0001
627 
628 /* MAC PASSTHRU */
629 #define AD_MASK			0xfee0
630 #define BND_MASK		0x0004
631 #define BD_MASK			0x0001
632 #define EFUSE			0xcfdb
633 #define PASS_THRU_MASK		0x1
634 
635 #define BP4_SUPER_ONLY		0x1578	/* RTL_VER_04 only */
636 
637 enum rtl_register_content {
638 	_1000bps	= 0x10,
639 	_100bps		= 0x08,
640 	_10bps		= 0x04,
641 	LINK_STATUS	= 0x02,
642 	FULL_DUP	= 0x01,
643 };
644 
645 #define RTL8152_MAX_TX		4
646 #define RTL8152_MAX_RX		10
647 #define INTBUFSIZE		2
648 #define TX_ALIGN		4
649 #define RX_ALIGN		8
650 
651 #define RTL8152_RX_MAX_PENDING	4096
652 #define RTL8152_RXFG_HEADSZ	256
653 
654 #define INTR_LINK		0x0004
655 
656 #define RTL8152_REQT_READ	0xc0
657 #define RTL8152_REQT_WRITE	0x40
658 #define RTL8152_REQ_GET_REGS	0x05
659 #define RTL8152_REQ_SET_REGS	0x05
660 
661 #define BYTE_EN_DWORD		0xff
662 #define BYTE_EN_WORD		0x33
663 #define BYTE_EN_BYTE		0x11
664 #define BYTE_EN_SIX_BYTES	0x3f
665 #define BYTE_EN_START_MASK	0x0f
666 #define BYTE_EN_END_MASK	0xf0
667 
668 #define RTL8153_MAX_PACKET	9216 /* 9K */
669 #define RTL8153_MAX_MTU		(RTL8153_MAX_PACKET - VLAN_ETH_HLEN - \
670 				 ETH_FCS_LEN)
671 #define RTL8152_RMS		(VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)
672 #define RTL8153_RMS		RTL8153_MAX_PACKET
673 #define RTL8152_TX_TIMEOUT	(5 * HZ)
674 #define RTL8152_NAPI_WEIGHT	64
675 #define rx_reserved_size(x)	((x) + VLAN_ETH_HLEN + ETH_FCS_LEN + \
676 				 sizeof(struct rx_desc) + RX_ALIGN)
677 
678 /* rtl8152 flags */
679 enum rtl8152_flags {
680 	RTL8152_UNPLUG = 0,
681 	RTL8152_SET_RX_MODE,
682 	WORK_ENABLE,
683 	RTL8152_LINK_CHG,
684 	SELECTIVE_SUSPEND,
685 	PHY_RESET,
686 	SCHEDULE_TASKLET,
687 	GREEN_ETHERNET,
688 	DELL_TB_RX_AGG_BUG,
689 	LENOVO_MACPASSTHRU,
690 };
691 
692 /* Define these values to match your device */
693 #define VENDOR_ID_REALTEK		0x0bda
694 #define VENDOR_ID_MICROSOFT		0x045e
695 #define VENDOR_ID_SAMSUNG		0x04e8
696 #define VENDOR_ID_LENOVO		0x17ef
697 #define VENDOR_ID_LINKSYS		0x13b1
698 #define VENDOR_ID_NVIDIA		0x0955
699 #define VENDOR_ID_TPLINK		0x2357
700 
701 #define DEVICE_ID_THINKPAD_THUNDERBOLT3_DOCK_GEN2	0x3082
702 #define DEVICE_ID_THINKPAD_USB_C_DOCK_GEN2		0xa387
703 
704 #define MCU_TYPE_PLA			0x0100
705 #define MCU_TYPE_USB			0x0000
706 
707 struct tally_counter {
708 	__le64	tx_packets;
709 	__le64	rx_packets;
710 	__le64	tx_errors;
711 	__le32	rx_errors;
712 	__le16	rx_missed;
713 	__le16	align_errors;
714 	__le32	tx_one_collision;
715 	__le32	tx_multi_collision;
716 	__le64	rx_unicast;
717 	__le64	rx_broadcast;
718 	__le32	rx_multicast;
719 	__le16	tx_aborted;
720 	__le16	tx_underrun;
721 };
722 
723 struct rx_desc {
724 	__le32 opts1;
725 #define RX_LEN_MASK			0x7fff
726 
727 	__le32 opts2;
728 #define RD_UDP_CS			BIT(23)
729 #define RD_TCP_CS			BIT(22)
730 #define RD_IPV6_CS			BIT(20)
731 #define RD_IPV4_CS			BIT(19)
732 
733 	__le32 opts3;
734 #define IPF				BIT(23) /* IP checksum fail */
735 #define UDPF				BIT(22) /* UDP checksum fail */
736 #define TCPF				BIT(21) /* TCP checksum fail */
737 #define RX_VLAN_TAG			BIT(16)
738 
739 	__le32 opts4;
740 	__le32 opts5;
741 	__le32 opts6;
742 };
743 
744 struct tx_desc {
745 	__le32 opts1;
746 #define TX_FS			BIT(31) /* First segment of a packet */
747 #define TX_LS			BIT(30) /* Final segment of a packet */
748 #define GTSENDV4		BIT(28)
749 #define GTSENDV6		BIT(27)
750 #define GTTCPHO_SHIFT		18
751 #define GTTCPHO_MAX		0x7fU
752 #define TX_LEN_MAX		0x3ffffU
753 
754 	__le32 opts2;
755 #define UDP_CS			BIT(31) /* Calculate UDP/IP checksum */
756 #define TCP_CS			BIT(30) /* Calculate TCP/IP checksum */
757 #define IPV4_CS			BIT(29) /* Calculate IPv4 checksum */
758 #define IPV6_CS			BIT(28) /* Calculate IPv6 checksum */
759 #define MSS_SHIFT		17
760 #define MSS_MAX			0x7ffU
761 #define TCPHO_SHIFT		17
762 #define TCPHO_MAX		0x7ffU
763 #define TX_VLAN_TAG		BIT(16)
764 };
765 
766 struct r8152;
767 
768 struct rx_agg {
769 	struct list_head list, info_list;
770 	struct urb *urb;
771 	struct r8152 *context;
772 	struct page *page;
773 	void *buffer;
774 };
775 
776 struct tx_agg {
777 	struct list_head list;
778 	struct urb *urb;
779 	struct r8152 *context;
780 	void *buffer;
781 	void *head;
782 	u32 skb_num;
783 	u32 skb_len;
784 };
785 
786 struct r8152 {
787 	unsigned long flags;
788 	struct usb_device *udev;
789 	struct napi_struct napi;
790 	struct usb_interface *intf;
791 	struct net_device *netdev;
792 	struct urb *intr_urb;
793 	struct tx_agg tx_info[RTL8152_MAX_TX];
794 	struct list_head rx_info, rx_used;
795 	struct list_head rx_done, tx_free;
796 	struct sk_buff_head tx_queue, rx_queue;
797 	spinlock_t rx_lock, tx_lock;
798 	struct delayed_work schedule, hw_phy_work;
799 	struct mii_if_info mii;
800 	struct mutex control;	/* use for hw setting */
801 #ifdef CONFIG_PM_SLEEP
802 	struct notifier_block pm_notifier;
803 #endif
804 	struct tasklet_struct tx_tl;
805 
806 	struct rtl_ops {
807 		void (*init)(struct r8152 *tp);
808 		int (*enable)(struct r8152 *tp);
809 		void (*disable)(struct r8152 *tp);
810 		void (*up)(struct r8152 *tp);
811 		void (*down)(struct r8152 *tp);
812 		void (*unload)(struct r8152 *tp);
813 		int (*eee_get)(struct r8152 *tp, struct ethtool_eee *eee);
814 		int (*eee_set)(struct r8152 *tp, struct ethtool_eee *eee);
815 		bool (*in_nway)(struct r8152 *tp);
816 		void (*hw_phy_cfg)(struct r8152 *tp);
817 		void (*autosuspend_en)(struct r8152 *tp, bool enable);
818 	} rtl_ops;
819 
820 	struct ups_info {
821 		u32 _10m_ckdiv:1;
822 		u32 _250m_ckdiv:1;
823 		u32 aldps:1;
824 		u32 lite_mode:2;
825 		u32 speed_duplex:4;
826 		u32 eee:1;
827 		u32 eee_lite:1;
828 		u32 eee_ckdiv:1;
829 		u32 eee_plloff_100:1;
830 		u32 eee_plloff_giga:1;
831 		u32 eee_cmod_lv:1;
832 		u32 green:1;
833 		u32 flow_control:1;
834 		u32 ctap_short_off:1;
835 	} ups_info;
836 
837 #define RTL_VER_SIZE		32
838 
839 	struct rtl_fw {
840 		const char *fw_name;
841 		const struct firmware *fw;
842 
843 		char version[RTL_VER_SIZE];
844 		int (*pre_fw)(struct r8152 *tp);
845 		int (*post_fw)(struct r8152 *tp);
846 
847 		bool retry;
848 	} rtl_fw;
849 
850 	atomic_t rx_count;
851 
852 	bool eee_en;
853 	int intr_interval;
854 	u32 saved_wolopts;
855 	u32 msg_enable;
856 	u32 tx_qlen;
857 	u32 coalesce;
858 	u32 advertising;
859 	u32 rx_buf_sz;
860 	u32 rx_copybreak;
861 	u32 rx_pending;
862 
863 	u16 ocp_base;
864 	u16 speed;
865 	u16 eee_adv;
866 	u8 *intr_buff;
867 	u8 version;
868 	u8 duplex;
869 	u8 autoneg;
870 };
871 
872 /**
873  * struct fw_block - block type and total length
874  * @type: type of the current block, such as RTL_FW_END, RTL_FW_PLA,
875  *	RTL_FW_USB and so on.
876  * @length: total length of the current block.
877  */
878 struct fw_block {
879 	__le32 type;
880 	__le32 length;
881 } __packed;
882 
883 /**
884  * struct fw_header - header of the firmware file
885  * @checksum: checksum of sha256 which is calculated from the whole file
886  *	except the checksum field of the file. That is, calculate sha256
887  *	from the version field to the end of the file.
888  * @version: version of this firmware.
889  * @blocks: the first firmware block of the file
890  */
891 struct fw_header {
892 	u8 checksum[32];
893 	char version[RTL_VER_SIZE];
894 	struct fw_block blocks[];
895 } __packed;
896 
897 /**
898  * struct fw_mac - a firmware block used by RTL_FW_PLA and RTL_FW_USB.
899  *	The layout of the firmware block is:
900  *	<struct fw_mac> + <info> + <firmware data>.
901  * @fw_offset: offset of the firmware binary data. The start address of
902  *	the data would be the address of struct fw_mac + @fw_offset.
903  * @fw_reg: the register to load the firmware. Depends on chip.
904  * @bp_ba_addr: the register to write break point base address. Depends on
905  *	chip.
906  * @bp_ba_value: break point base address. Depends on chip.
907  * @bp_en_addr: the register to write break point enabled mask. Depends
908  *	on chip.
909  * @bp_en_value: break point enabled mask. Depends on the firmware.
910  * @bp_start: the start register of break points. Depends on chip.
911  * @bp_num: the break point number which needs to be set for this firmware.
912  *	Depends on the firmware.
913  * @bp: break points. Depends on firmware.
914  * @fw_ver_reg: the register to store the fw version.
915  * @fw_ver_data: the firmware version of the current type.
916  * @info: additional information for debugging, and is followed by the
917  *	binary data of firmware.
918  */
919 struct fw_mac {
920 	struct fw_block blk_hdr;
921 	__le16 fw_offset;
922 	__le16 fw_reg;
923 	__le16 bp_ba_addr;
924 	__le16 bp_ba_value;
925 	__le16 bp_en_addr;
926 	__le16 bp_en_value;
927 	__le16 bp_start;
928 	__le16 bp_num;
929 	__le16 bp[16]; /* any value determined by firmware */
930 	__le32 reserved;
931 	__le16 fw_ver_reg;
932 	u8 fw_ver_data;
933 	char info[];
934 } __packed;
935 
936 /**
937  * struct fw_phy_patch_key - a firmware block used by RTL_FW_PHY_START.
938  *	This is used to set patch key when loading the firmware of PHY.
939  * @key_reg: the register to write the patch key.
940  * @key_data: patch key.
941  */
942 struct fw_phy_patch_key {
943 	struct fw_block blk_hdr;
944 	__le16 key_reg;
945 	__le16 key_data;
946 	__le32 reserved;
947 } __packed;
948 
949 /**
950  * struct fw_phy_nc - a firmware block used by RTL_FW_PHY_NC.
951  *	The layout of the firmware block is:
952  *	<struct fw_phy_nc> + <info> + <firmware data>.
953  * @fw_offset: offset of the firmware binary data. The start address of
954  *	the data would be the address of struct fw_phy_nc + @fw_offset.
955  * @fw_reg: the register to load the firmware. Depends on chip.
956  * @ba_reg: the register to write the base address. Depends on chip.
957  * @ba_data: base address. Depends on chip.
958  * @patch_en_addr: the register of enabling patch mode. Depends on chip.
959  * @patch_en_value: patch mode enabled mask. Depends on the firmware.
960  * @mode_reg: the regitster of switching the mode.
961  * @mod_pre: the mode needing to be set before loading the firmware.
962  * @mod_post: the mode to be set when finishing to load the firmware.
963  * @bp_start: the start register of break points. Depends on chip.
964  * @bp_num: the break point number which needs to be set for this firmware.
965  *	Depends on the firmware.
966  * @bp: break points. Depends on firmware.
967  * @info: additional information for debugging, and is followed by the
968  *	binary data of firmware.
969  */
970 struct fw_phy_nc {
971 	struct fw_block blk_hdr;
972 	__le16 fw_offset;
973 	__le16 fw_reg;
974 	__le16 ba_reg;
975 	__le16 ba_data;
976 	__le16 patch_en_addr;
977 	__le16 patch_en_value;
978 	__le16 mode_reg;
979 	__le16 mode_pre;
980 	__le16 mode_post;
981 	__le16 reserved;
982 	__le16 bp_start;
983 	__le16 bp_num;
984 	__le16 bp[4];
985 	char info[];
986 } __packed;
987 
988 enum rtl_fw_type {
989 	RTL_FW_END = 0,
990 	RTL_FW_PLA,
991 	RTL_FW_USB,
992 	RTL_FW_PHY_START,
993 	RTL_FW_PHY_STOP,
994 	RTL_FW_PHY_NC,
995 };
996 
997 enum rtl_version {
998 	RTL_VER_UNKNOWN = 0,
999 	RTL_VER_01,
1000 	RTL_VER_02,
1001 	RTL_VER_03,
1002 	RTL_VER_04,
1003 	RTL_VER_05,
1004 	RTL_VER_06,
1005 	RTL_VER_07,
1006 	RTL_VER_08,
1007 	RTL_VER_09,
1008 	RTL_VER_MAX
1009 };
1010 
1011 enum tx_csum_stat {
1012 	TX_CSUM_SUCCESS = 0,
1013 	TX_CSUM_TSO,
1014 	TX_CSUM_NONE
1015 };
1016 
1017 #define RTL_ADVERTISED_10_HALF			BIT(0)
1018 #define RTL_ADVERTISED_10_FULL			BIT(1)
1019 #define RTL_ADVERTISED_100_HALF			BIT(2)
1020 #define RTL_ADVERTISED_100_FULL			BIT(3)
1021 #define RTL_ADVERTISED_1000_HALF		BIT(4)
1022 #define RTL_ADVERTISED_1000_FULL		BIT(5)
1023 
1024 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
1025  * The RTL chips use a 64 element hash table based on the Ethernet CRC.
1026  */
1027 static const int multicast_filter_limit = 32;
1028 static unsigned int agg_buf_sz = 16384;
1029 
1030 #define RTL_LIMITED_TSO_SIZE	(agg_buf_sz - sizeof(struct tx_desc) - \
1031 				 VLAN_ETH_HLEN - ETH_FCS_LEN)
1032 
1033 static
get_registers(struct r8152 * tp,u16 value,u16 index,u16 size,void * data)1034 int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
1035 {
1036 	int ret;
1037 	void *tmp;
1038 
1039 	tmp = kmalloc(size, GFP_KERNEL);
1040 	if (!tmp)
1041 		return -ENOMEM;
1042 
1043 	ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0),
1044 			      RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
1045 			      value, index, tmp, size, 500);
1046 	if (ret < 0)
1047 		memset(data, 0xff, size);
1048 	else
1049 		memcpy(data, tmp, size);
1050 
1051 	kfree(tmp);
1052 
1053 	return ret;
1054 }
1055 
1056 static
set_registers(struct r8152 * tp,u16 value,u16 index,u16 size,void * data)1057 int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
1058 {
1059 	int ret;
1060 	void *tmp;
1061 
1062 	tmp = kmemdup(data, size, GFP_KERNEL);
1063 	if (!tmp)
1064 		return -ENOMEM;
1065 
1066 	ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0),
1067 			      RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE,
1068 			      value, index, tmp, size, 500);
1069 
1070 	kfree(tmp);
1071 
1072 	return ret;
1073 }
1074 
rtl_set_unplug(struct r8152 * tp)1075 static void rtl_set_unplug(struct r8152 *tp)
1076 {
1077 	if (tp->udev->state == USB_STATE_NOTATTACHED) {
1078 		set_bit(RTL8152_UNPLUG, &tp->flags);
1079 		smp_mb__after_atomic();
1080 	}
1081 }
1082 
generic_ocp_read(struct r8152 * tp,u16 index,u16 size,void * data,u16 type)1083 static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
1084 			    void *data, u16 type)
1085 {
1086 	u16 limit = 64;
1087 	int ret = 0;
1088 
1089 	if (test_bit(RTL8152_UNPLUG, &tp->flags))
1090 		return -ENODEV;
1091 
1092 	/* both size and indix must be 4 bytes align */
1093 	if ((size & 3) || !size || (index & 3) || !data)
1094 		return -EPERM;
1095 
1096 	if ((u32)index + (u32)size > 0xffff)
1097 		return -EPERM;
1098 
1099 	while (size) {
1100 		if (size > limit) {
1101 			ret = get_registers(tp, index, type, limit, data);
1102 			if (ret < 0)
1103 				break;
1104 
1105 			index += limit;
1106 			data += limit;
1107 			size -= limit;
1108 		} else {
1109 			ret = get_registers(tp, index, type, size, data);
1110 			if (ret < 0)
1111 				break;
1112 
1113 			index += size;
1114 			data += size;
1115 			size = 0;
1116 			break;
1117 		}
1118 	}
1119 
1120 	if (ret == -ENODEV)
1121 		rtl_set_unplug(tp);
1122 
1123 	return ret;
1124 }
1125 
generic_ocp_write(struct r8152 * tp,u16 index,u16 byteen,u16 size,void * data,u16 type)1126 static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
1127 			     u16 size, void *data, u16 type)
1128 {
1129 	int ret;
1130 	u16 byteen_start, byteen_end, byen;
1131 	u16 limit = 512;
1132 
1133 	if (test_bit(RTL8152_UNPLUG, &tp->flags))
1134 		return -ENODEV;
1135 
1136 	/* both size and indix must be 4 bytes align */
1137 	if ((size & 3) || !size || (index & 3) || !data)
1138 		return -EPERM;
1139 
1140 	if ((u32)index + (u32)size > 0xffff)
1141 		return -EPERM;
1142 
1143 	byteen_start = byteen & BYTE_EN_START_MASK;
1144 	byteen_end = byteen & BYTE_EN_END_MASK;
1145 
1146 	byen = byteen_start | (byteen_start << 4);
1147 	ret = set_registers(tp, index, type | byen, 4, data);
1148 	if (ret < 0)
1149 		goto error1;
1150 
1151 	index += 4;
1152 	data += 4;
1153 	size -= 4;
1154 
1155 	if (size) {
1156 		size -= 4;
1157 
1158 		while (size) {
1159 			if (size > limit) {
1160 				ret = set_registers(tp, index,
1161 						    type | BYTE_EN_DWORD,
1162 						    limit, data);
1163 				if (ret < 0)
1164 					goto error1;
1165 
1166 				index += limit;
1167 				data += limit;
1168 				size -= limit;
1169 			} else {
1170 				ret = set_registers(tp, index,
1171 						    type | BYTE_EN_DWORD,
1172 						    size, data);
1173 				if (ret < 0)
1174 					goto error1;
1175 
1176 				index += size;
1177 				data += size;
1178 				size = 0;
1179 				break;
1180 			}
1181 		}
1182 
1183 		byen = byteen_end | (byteen_end >> 4);
1184 		ret = set_registers(tp, index, type | byen, 4, data);
1185 		if (ret < 0)
1186 			goto error1;
1187 	}
1188 
1189 error1:
1190 	if (ret == -ENODEV)
1191 		rtl_set_unplug(tp);
1192 
1193 	return ret;
1194 }
1195 
1196 static inline
pla_ocp_read(struct r8152 * tp,u16 index,u16 size,void * data)1197 int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
1198 {
1199 	return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA);
1200 }
1201 
1202 static inline
pla_ocp_write(struct r8152 * tp,u16 index,u16 byteen,u16 size,void * data)1203 int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
1204 {
1205 	return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA);
1206 }
1207 
1208 static inline
usb_ocp_write(struct r8152 * tp,u16 index,u16 byteen,u16 size,void * data)1209 int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
1210 {
1211 	return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB);
1212 }
1213 
ocp_read_dword(struct r8152 * tp,u16 type,u16 index)1214 static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index)
1215 {
1216 	__le32 data;
1217 
1218 	generic_ocp_read(tp, index, sizeof(data), &data, type);
1219 
1220 	return __le32_to_cpu(data);
1221 }
1222 
ocp_write_dword(struct r8152 * tp,u16 type,u16 index,u32 data)1223 static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data)
1224 {
1225 	__le32 tmp = __cpu_to_le32(data);
1226 
1227 	generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type);
1228 }
1229 
ocp_read_word(struct r8152 * tp,u16 type,u16 index)1230 static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index)
1231 {
1232 	u32 data;
1233 	__le32 tmp;
1234 	u16 byen = BYTE_EN_WORD;
1235 	u8 shift = index & 2;
1236 
1237 	index &= ~3;
1238 	byen <<= shift;
1239 
1240 	generic_ocp_read(tp, index, sizeof(tmp), &tmp, type | byen);
1241 
1242 	data = __le32_to_cpu(tmp);
1243 	data >>= (shift * 8);
1244 	data &= 0xffff;
1245 
1246 	return (u16)data;
1247 }
1248 
ocp_write_word(struct r8152 * tp,u16 type,u16 index,u32 data)1249 static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data)
1250 {
1251 	u32 mask = 0xffff;
1252 	__le32 tmp;
1253 	u16 byen = BYTE_EN_WORD;
1254 	u8 shift = index & 2;
1255 
1256 	data &= mask;
1257 
1258 	if (index & 2) {
1259 		byen <<= shift;
1260 		mask <<= (shift * 8);
1261 		data <<= (shift * 8);
1262 		index &= ~3;
1263 	}
1264 
1265 	tmp = __cpu_to_le32(data);
1266 
1267 	generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
1268 }
1269 
ocp_read_byte(struct r8152 * tp,u16 type,u16 index)1270 static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index)
1271 {
1272 	u32 data;
1273 	__le32 tmp;
1274 	u8 shift = index & 3;
1275 
1276 	index &= ~3;
1277 
1278 	generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
1279 
1280 	data = __le32_to_cpu(tmp);
1281 	data >>= (shift * 8);
1282 	data &= 0xff;
1283 
1284 	return (u8)data;
1285 }
1286 
ocp_write_byte(struct r8152 * tp,u16 type,u16 index,u32 data)1287 static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data)
1288 {
1289 	u32 mask = 0xff;
1290 	__le32 tmp;
1291 	u16 byen = BYTE_EN_BYTE;
1292 	u8 shift = index & 3;
1293 
1294 	data &= mask;
1295 
1296 	if (index & 3) {
1297 		byen <<= shift;
1298 		mask <<= (shift * 8);
1299 		data <<= (shift * 8);
1300 		index &= ~3;
1301 	}
1302 
1303 	tmp = __cpu_to_le32(data);
1304 
1305 	generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
1306 }
1307 
ocp_reg_read(struct r8152 * tp,u16 addr)1308 static u16 ocp_reg_read(struct r8152 *tp, u16 addr)
1309 {
1310 	u16 ocp_base, ocp_index;
1311 
1312 	ocp_base = addr & 0xf000;
1313 	if (ocp_base != tp->ocp_base) {
1314 		ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
1315 		tp->ocp_base = ocp_base;
1316 	}
1317 
1318 	ocp_index = (addr & 0x0fff) | 0xb000;
1319 	return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index);
1320 }
1321 
ocp_reg_write(struct r8152 * tp,u16 addr,u16 data)1322 static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data)
1323 {
1324 	u16 ocp_base, ocp_index;
1325 
1326 	ocp_base = addr & 0xf000;
1327 	if (ocp_base != tp->ocp_base) {
1328 		ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
1329 		tp->ocp_base = ocp_base;
1330 	}
1331 
1332 	ocp_index = (addr & 0x0fff) | 0xb000;
1333 	ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data);
1334 }
1335 
r8152_mdio_write(struct r8152 * tp,u32 reg_addr,u32 value)1336 static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value)
1337 {
1338 	ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value);
1339 }
1340 
r8152_mdio_read(struct r8152 * tp,u32 reg_addr)1341 static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr)
1342 {
1343 	return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2);
1344 }
1345 
sram_write(struct r8152 * tp,u16 addr,u16 data)1346 static void sram_write(struct r8152 *tp, u16 addr, u16 data)
1347 {
1348 	ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
1349 	ocp_reg_write(tp, OCP_SRAM_DATA, data);
1350 }
1351 
sram_read(struct r8152 * tp,u16 addr)1352 static u16 sram_read(struct r8152 *tp, u16 addr)
1353 {
1354 	ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
1355 	return ocp_reg_read(tp, OCP_SRAM_DATA);
1356 }
1357 
read_mii_word(struct net_device * netdev,int phy_id,int reg)1358 static int read_mii_word(struct net_device *netdev, int phy_id, int reg)
1359 {
1360 	struct r8152 *tp = netdev_priv(netdev);
1361 	int ret;
1362 
1363 	if (test_bit(RTL8152_UNPLUG, &tp->flags))
1364 		return -ENODEV;
1365 
1366 	if (phy_id != R8152_PHY_ID)
1367 		return -EINVAL;
1368 
1369 	ret = r8152_mdio_read(tp, reg);
1370 
1371 	return ret;
1372 }
1373 
1374 static
write_mii_word(struct net_device * netdev,int phy_id,int reg,int val)1375 void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val)
1376 {
1377 	struct r8152 *tp = netdev_priv(netdev);
1378 
1379 	if (test_bit(RTL8152_UNPLUG, &tp->flags))
1380 		return;
1381 
1382 	if (phy_id != R8152_PHY_ID)
1383 		return;
1384 
1385 	r8152_mdio_write(tp, reg, val);
1386 }
1387 
1388 static int
1389 r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags);
1390 
rtl8152_set_mac_address(struct net_device * netdev,void * p)1391 static int rtl8152_set_mac_address(struct net_device *netdev, void *p)
1392 {
1393 	struct r8152 *tp = netdev_priv(netdev);
1394 	struct sockaddr *addr = p;
1395 	int ret = -EADDRNOTAVAIL;
1396 
1397 	if (!is_valid_ether_addr(addr->sa_data))
1398 		goto out1;
1399 
1400 	ret = usb_autopm_get_interface(tp->intf);
1401 	if (ret < 0)
1402 		goto out1;
1403 
1404 	mutex_lock(&tp->control);
1405 
1406 	memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1407 
1408 	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
1409 	pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data);
1410 	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
1411 
1412 	mutex_unlock(&tp->control);
1413 
1414 	usb_autopm_put_interface(tp->intf);
1415 out1:
1416 	return ret;
1417 }
1418 
1419 /* Devices containing proper chips can support a persistent
1420  * host system provided MAC address.
1421  * Examples of this are Dell TB15 and Dell WD15 docks
1422  */
vendor_mac_passthru_addr_read(struct r8152 * tp,struct sockaddr * sa)1423 static int vendor_mac_passthru_addr_read(struct r8152 *tp, struct sockaddr *sa)
1424 {
1425 	acpi_status status;
1426 	struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
1427 	union acpi_object *obj;
1428 	int ret = -EINVAL;
1429 	u32 ocp_data;
1430 	unsigned char buf[6];
1431 	char *mac_obj_name;
1432 	acpi_object_type mac_obj_type;
1433 	int mac_strlen;
1434 
1435 	if (test_bit(LENOVO_MACPASSTHRU, &tp->flags)) {
1436 		mac_obj_name = "\\MACA";
1437 		mac_obj_type = ACPI_TYPE_STRING;
1438 		mac_strlen = 0x16;
1439 	} else {
1440 		/* test for -AD variant of RTL8153 */
1441 		ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
1442 		if ((ocp_data & AD_MASK) == 0x1000) {
1443 			/* test for MAC address pass-through bit */
1444 			ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, EFUSE);
1445 			if ((ocp_data & PASS_THRU_MASK) != 1) {
1446 				netif_dbg(tp, probe, tp->netdev,
1447 						"No efuse for RTL8153-AD MAC pass through\n");
1448 				return -ENODEV;
1449 			}
1450 		} else {
1451 			/* test for RTL8153-BND and RTL8153-BD */
1452 			ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_1);
1453 			if ((ocp_data & BND_MASK) == 0 && (ocp_data & BD_MASK) == 0) {
1454 				netif_dbg(tp, probe, tp->netdev,
1455 						"Invalid variant for MAC pass through\n");
1456 				return -ENODEV;
1457 			}
1458 		}
1459 
1460 		mac_obj_name = "\\_SB.AMAC";
1461 		mac_obj_type = ACPI_TYPE_BUFFER;
1462 		mac_strlen = 0x17;
1463 	}
1464 
1465 	/* returns _AUXMAC_#AABBCCDDEEFF# */
1466 	status = acpi_evaluate_object(NULL, mac_obj_name, NULL, &buffer);
1467 	obj = (union acpi_object *)buffer.pointer;
1468 	if (!ACPI_SUCCESS(status))
1469 		return -ENODEV;
1470 	if (obj->type != mac_obj_type || obj->string.length != mac_strlen) {
1471 		netif_warn(tp, probe, tp->netdev,
1472 			   "Invalid buffer for pass-thru MAC addr: (%d, %d)\n",
1473 			   obj->type, obj->string.length);
1474 		goto amacout;
1475 	}
1476 
1477 	if (strncmp(obj->string.pointer, "_AUXMAC_#", 9) != 0 ||
1478 	    strncmp(obj->string.pointer + 0x15, "#", 1) != 0) {
1479 		netif_warn(tp, probe, tp->netdev,
1480 			   "Invalid header when reading pass-thru MAC addr\n");
1481 		goto amacout;
1482 	}
1483 	ret = hex2bin(buf, obj->string.pointer + 9, 6);
1484 	if (!(ret == 0 && is_valid_ether_addr(buf))) {
1485 		netif_warn(tp, probe, tp->netdev,
1486 			   "Invalid MAC for pass-thru MAC addr: %d, %pM\n",
1487 			   ret, buf);
1488 		ret = -EINVAL;
1489 		goto amacout;
1490 	}
1491 	memcpy(sa->sa_data, buf, 6);
1492 	netif_info(tp, probe, tp->netdev,
1493 		   "Using pass-thru MAC addr %pM\n", sa->sa_data);
1494 
1495 amacout:
1496 	kfree(obj);
1497 	return ret;
1498 }
1499 
determine_ethernet_addr(struct r8152 * tp,struct sockaddr * sa)1500 static int determine_ethernet_addr(struct r8152 *tp, struct sockaddr *sa)
1501 {
1502 	struct net_device *dev = tp->netdev;
1503 	int ret;
1504 
1505 	sa->sa_family = dev->type;
1506 
1507 	ret = eth_platform_get_mac_address(&tp->udev->dev, sa->sa_data);
1508 	if (ret < 0) {
1509 		if (tp->version == RTL_VER_01) {
1510 			ret = pla_ocp_read(tp, PLA_IDR, 8, sa->sa_data);
1511 		} else {
1512 			/* if device doesn't support MAC pass through this will
1513 			 * be expected to be non-zero
1514 			 */
1515 			ret = vendor_mac_passthru_addr_read(tp, sa);
1516 			if (ret < 0)
1517 				ret = pla_ocp_read(tp, PLA_BACKUP, 8,
1518 						   sa->sa_data);
1519 		}
1520 	}
1521 
1522 	if (ret < 0) {
1523 		netif_err(tp, probe, dev, "Get ether addr fail\n");
1524 	} else if (!is_valid_ether_addr(sa->sa_data)) {
1525 		netif_err(tp, probe, dev, "Invalid ether addr %pM\n",
1526 			  sa->sa_data);
1527 		eth_hw_addr_random(dev);
1528 		ether_addr_copy(sa->sa_data, dev->dev_addr);
1529 		netif_info(tp, probe, dev, "Random ether addr %pM\n",
1530 			   sa->sa_data);
1531 		return 0;
1532 	}
1533 
1534 	return ret;
1535 }
1536 
set_ethernet_addr(struct r8152 * tp)1537 static int set_ethernet_addr(struct r8152 *tp)
1538 {
1539 	struct net_device *dev = tp->netdev;
1540 	struct sockaddr sa;
1541 	int ret;
1542 
1543 	ret = determine_ethernet_addr(tp, &sa);
1544 	if (ret < 0)
1545 		return ret;
1546 
1547 	if (tp->version == RTL_VER_01)
1548 		ether_addr_copy(dev->dev_addr, sa.sa_data);
1549 	else
1550 		ret = rtl8152_set_mac_address(dev, &sa);
1551 
1552 	return ret;
1553 }
1554 
read_bulk_callback(struct urb * urb)1555 static void read_bulk_callback(struct urb *urb)
1556 {
1557 	struct net_device *netdev;
1558 	int status = urb->status;
1559 	struct rx_agg *agg;
1560 	struct r8152 *tp;
1561 	unsigned long flags;
1562 
1563 	agg = urb->context;
1564 	if (!agg)
1565 		return;
1566 
1567 	tp = agg->context;
1568 	if (!tp)
1569 		return;
1570 
1571 	if (test_bit(RTL8152_UNPLUG, &tp->flags))
1572 		return;
1573 
1574 	if (!test_bit(WORK_ENABLE, &tp->flags))
1575 		return;
1576 
1577 	netdev = tp->netdev;
1578 
1579 	/* When link down, the driver would cancel all bulks. */
1580 	/* This avoid the re-submitting bulk */
1581 	if (!netif_carrier_ok(netdev))
1582 		return;
1583 
1584 	usb_mark_last_busy(tp->udev);
1585 
1586 	switch (status) {
1587 	case 0:
1588 		if (urb->actual_length < ETH_ZLEN)
1589 			break;
1590 
1591 		spin_lock_irqsave(&tp->rx_lock, flags);
1592 		list_add_tail(&agg->list, &tp->rx_done);
1593 		spin_unlock_irqrestore(&tp->rx_lock, flags);
1594 		napi_schedule(&tp->napi);
1595 		return;
1596 	case -ESHUTDOWN:
1597 		rtl_set_unplug(tp);
1598 		netif_device_detach(tp->netdev);
1599 		return;
1600 	case -ENOENT:
1601 		return;	/* the urb is in unlink state */
1602 	case -ETIME:
1603 		if (net_ratelimit())
1604 			netdev_warn(netdev, "maybe reset is needed?\n");
1605 		break;
1606 	default:
1607 		if (net_ratelimit())
1608 			netdev_warn(netdev, "Rx status %d\n", status);
1609 		break;
1610 	}
1611 
1612 	r8152_submit_rx(tp, agg, GFP_ATOMIC);
1613 }
1614 
write_bulk_callback(struct urb * urb)1615 static void write_bulk_callback(struct urb *urb)
1616 {
1617 	struct net_device_stats *stats;
1618 	struct net_device *netdev;
1619 	struct tx_agg *agg;
1620 	struct r8152 *tp;
1621 	unsigned long flags;
1622 	int status = urb->status;
1623 
1624 	agg = urb->context;
1625 	if (!agg)
1626 		return;
1627 
1628 	tp = agg->context;
1629 	if (!tp)
1630 		return;
1631 
1632 	netdev = tp->netdev;
1633 	stats = &netdev->stats;
1634 	if (status) {
1635 		if (net_ratelimit())
1636 			netdev_warn(netdev, "Tx status %d\n", status);
1637 		stats->tx_errors += agg->skb_num;
1638 	} else {
1639 		stats->tx_packets += agg->skb_num;
1640 		stats->tx_bytes += agg->skb_len;
1641 	}
1642 
1643 	spin_lock_irqsave(&tp->tx_lock, flags);
1644 	list_add_tail(&agg->list, &tp->tx_free);
1645 	spin_unlock_irqrestore(&tp->tx_lock, flags);
1646 
1647 	usb_autopm_put_interface_async(tp->intf);
1648 
1649 	if (!netif_carrier_ok(netdev))
1650 		return;
1651 
1652 	if (!test_bit(WORK_ENABLE, &tp->flags))
1653 		return;
1654 
1655 	if (test_bit(RTL8152_UNPLUG, &tp->flags))
1656 		return;
1657 
1658 	if (!skb_queue_empty(&tp->tx_queue))
1659 		tasklet_schedule(&tp->tx_tl);
1660 }
1661 
intr_callback(struct urb * urb)1662 static void intr_callback(struct urb *urb)
1663 {
1664 	struct r8152 *tp;
1665 	__le16 *d;
1666 	int status = urb->status;
1667 	int res;
1668 
1669 	tp = urb->context;
1670 	if (!tp)
1671 		return;
1672 
1673 	if (!test_bit(WORK_ENABLE, &tp->flags))
1674 		return;
1675 
1676 	if (test_bit(RTL8152_UNPLUG, &tp->flags))
1677 		return;
1678 
1679 	switch (status) {
1680 	case 0:			/* success */
1681 		break;
1682 	case -ECONNRESET:	/* unlink */
1683 	case -ESHUTDOWN:
1684 		netif_device_detach(tp->netdev);
1685 		fallthrough;
1686 	case -ENOENT:
1687 	case -EPROTO:
1688 		netif_info(tp, intr, tp->netdev,
1689 			   "Stop submitting intr, status %d\n", status);
1690 		return;
1691 	case -EOVERFLOW:
1692 		if (net_ratelimit())
1693 			netif_info(tp, intr, tp->netdev,
1694 				   "intr status -EOVERFLOW\n");
1695 		goto resubmit;
1696 	/* -EPIPE:  should clear the halt */
1697 	default:
1698 		netif_info(tp, intr, tp->netdev, "intr status %d\n", status);
1699 		goto resubmit;
1700 	}
1701 
1702 	d = urb->transfer_buffer;
1703 	if (INTR_LINK & __le16_to_cpu(d[0])) {
1704 		if (!netif_carrier_ok(tp->netdev)) {
1705 			set_bit(RTL8152_LINK_CHG, &tp->flags);
1706 			schedule_delayed_work(&tp->schedule, 0);
1707 		}
1708 	} else {
1709 		if (netif_carrier_ok(tp->netdev)) {
1710 			netif_stop_queue(tp->netdev);
1711 			set_bit(RTL8152_LINK_CHG, &tp->flags);
1712 			schedule_delayed_work(&tp->schedule, 0);
1713 		}
1714 	}
1715 
1716 resubmit:
1717 	res = usb_submit_urb(urb, GFP_ATOMIC);
1718 	if (res == -ENODEV) {
1719 		rtl_set_unplug(tp);
1720 		netif_device_detach(tp->netdev);
1721 	} else if (res) {
1722 		netif_err(tp, intr, tp->netdev,
1723 			  "can't resubmit intr, status %d\n", res);
1724 	}
1725 }
1726 
rx_agg_align(void * data)1727 static inline void *rx_agg_align(void *data)
1728 {
1729 	return (void *)ALIGN((uintptr_t)data, RX_ALIGN);
1730 }
1731 
tx_agg_align(void * data)1732 static inline void *tx_agg_align(void *data)
1733 {
1734 	return (void *)ALIGN((uintptr_t)data, TX_ALIGN);
1735 }
1736 
free_rx_agg(struct r8152 * tp,struct rx_agg * agg)1737 static void free_rx_agg(struct r8152 *tp, struct rx_agg *agg)
1738 {
1739 	list_del(&agg->info_list);
1740 
1741 	usb_free_urb(agg->urb);
1742 	put_page(agg->page);
1743 	kfree(agg);
1744 
1745 	atomic_dec(&tp->rx_count);
1746 }
1747 
alloc_rx_agg(struct r8152 * tp,gfp_t mflags)1748 static struct rx_agg *alloc_rx_agg(struct r8152 *tp, gfp_t mflags)
1749 {
1750 	struct net_device *netdev = tp->netdev;
1751 	int node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
1752 	unsigned int order = get_order(tp->rx_buf_sz);
1753 	struct rx_agg *rx_agg;
1754 	unsigned long flags;
1755 
1756 	rx_agg = kmalloc_node(sizeof(*rx_agg), mflags, node);
1757 	if (!rx_agg)
1758 		return NULL;
1759 
1760 	rx_agg->page = alloc_pages(mflags | __GFP_COMP, order);
1761 	if (!rx_agg->page)
1762 		goto free_rx;
1763 
1764 	rx_agg->buffer = page_address(rx_agg->page);
1765 
1766 	rx_agg->urb = usb_alloc_urb(0, mflags);
1767 	if (!rx_agg->urb)
1768 		goto free_buf;
1769 
1770 	rx_agg->context = tp;
1771 
1772 	INIT_LIST_HEAD(&rx_agg->list);
1773 	INIT_LIST_HEAD(&rx_agg->info_list);
1774 	spin_lock_irqsave(&tp->rx_lock, flags);
1775 	list_add_tail(&rx_agg->info_list, &tp->rx_info);
1776 	spin_unlock_irqrestore(&tp->rx_lock, flags);
1777 
1778 	atomic_inc(&tp->rx_count);
1779 
1780 	return rx_agg;
1781 
1782 free_buf:
1783 	__free_pages(rx_agg->page, order);
1784 free_rx:
1785 	kfree(rx_agg);
1786 	return NULL;
1787 }
1788 
free_all_mem(struct r8152 * tp)1789 static void free_all_mem(struct r8152 *tp)
1790 {
1791 	struct rx_agg *agg, *agg_next;
1792 	unsigned long flags;
1793 	int i;
1794 
1795 	spin_lock_irqsave(&tp->rx_lock, flags);
1796 
1797 	list_for_each_entry_safe(agg, agg_next, &tp->rx_info, info_list)
1798 		free_rx_agg(tp, agg);
1799 
1800 	spin_unlock_irqrestore(&tp->rx_lock, flags);
1801 
1802 	WARN_ON(atomic_read(&tp->rx_count));
1803 
1804 	for (i = 0; i < RTL8152_MAX_TX; i++) {
1805 		usb_free_urb(tp->tx_info[i].urb);
1806 		tp->tx_info[i].urb = NULL;
1807 
1808 		kfree(tp->tx_info[i].buffer);
1809 		tp->tx_info[i].buffer = NULL;
1810 		tp->tx_info[i].head = NULL;
1811 	}
1812 
1813 	usb_free_urb(tp->intr_urb);
1814 	tp->intr_urb = NULL;
1815 
1816 	kfree(tp->intr_buff);
1817 	tp->intr_buff = NULL;
1818 }
1819 
alloc_all_mem(struct r8152 * tp)1820 static int alloc_all_mem(struct r8152 *tp)
1821 {
1822 	struct net_device *netdev = tp->netdev;
1823 	struct usb_interface *intf = tp->intf;
1824 	struct usb_host_interface *alt = intf->cur_altsetting;
1825 	struct usb_host_endpoint *ep_intr = alt->endpoint + 2;
1826 	int node, i;
1827 
1828 	node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
1829 
1830 	spin_lock_init(&tp->rx_lock);
1831 	spin_lock_init(&tp->tx_lock);
1832 	INIT_LIST_HEAD(&tp->rx_info);
1833 	INIT_LIST_HEAD(&tp->tx_free);
1834 	INIT_LIST_HEAD(&tp->rx_done);
1835 	skb_queue_head_init(&tp->tx_queue);
1836 	skb_queue_head_init(&tp->rx_queue);
1837 	atomic_set(&tp->rx_count, 0);
1838 
1839 	for (i = 0; i < RTL8152_MAX_RX; i++) {
1840 		if (!alloc_rx_agg(tp, GFP_KERNEL))
1841 			goto err1;
1842 	}
1843 
1844 	for (i = 0; i < RTL8152_MAX_TX; i++) {
1845 		struct urb *urb;
1846 		u8 *buf;
1847 
1848 		buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
1849 		if (!buf)
1850 			goto err1;
1851 
1852 		if (buf != tx_agg_align(buf)) {
1853 			kfree(buf);
1854 			buf = kmalloc_node(agg_buf_sz + TX_ALIGN, GFP_KERNEL,
1855 					   node);
1856 			if (!buf)
1857 				goto err1;
1858 		}
1859 
1860 		urb = usb_alloc_urb(0, GFP_KERNEL);
1861 		if (!urb) {
1862 			kfree(buf);
1863 			goto err1;
1864 		}
1865 
1866 		INIT_LIST_HEAD(&tp->tx_info[i].list);
1867 		tp->tx_info[i].context = tp;
1868 		tp->tx_info[i].urb = urb;
1869 		tp->tx_info[i].buffer = buf;
1870 		tp->tx_info[i].head = tx_agg_align(buf);
1871 
1872 		list_add_tail(&tp->tx_info[i].list, &tp->tx_free);
1873 	}
1874 
1875 	tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL);
1876 	if (!tp->intr_urb)
1877 		goto err1;
1878 
1879 	tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL);
1880 	if (!tp->intr_buff)
1881 		goto err1;
1882 
1883 	tp->intr_interval = (int)ep_intr->desc.bInterval;
1884 	usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3),
1885 			 tp->intr_buff, INTBUFSIZE, intr_callback,
1886 			 tp, tp->intr_interval);
1887 
1888 	return 0;
1889 
1890 err1:
1891 	free_all_mem(tp);
1892 	return -ENOMEM;
1893 }
1894 
r8152_get_tx_agg(struct r8152 * tp)1895 static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp)
1896 {
1897 	struct tx_agg *agg = NULL;
1898 	unsigned long flags;
1899 
1900 	if (list_empty(&tp->tx_free))
1901 		return NULL;
1902 
1903 	spin_lock_irqsave(&tp->tx_lock, flags);
1904 	if (!list_empty(&tp->tx_free)) {
1905 		struct list_head *cursor;
1906 
1907 		cursor = tp->tx_free.next;
1908 		list_del_init(cursor);
1909 		agg = list_entry(cursor, struct tx_agg, list);
1910 	}
1911 	spin_unlock_irqrestore(&tp->tx_lock, flags);
1912 
1913 	return agg;
1914 }
1915 
1916 /* r8152_csum_workaround()
1917  * The hw limits the value of the transport offset. When the offset is out of
1918  * range, calculate the checksum by sw.
1919  */
r8152_csum_workaround(struct r8152 * tp,struct sk_buff * skb,struct sk_buff_head * list)1920 static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb,
1921 				  struct sk_buff_head *list)
1922 {
1923 	if (skb_shinfo(skb)->gso_size) {
1924 		netdev_features_t features = tp->netdev->features;
1925 		struct sk_buff *segs, *seg, *next;
1926 		struct sk_buff_head seg_list;
1927 
1928 		features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
1929 		segs = skb_gso_segment(skb, features);
1930 		if (IS_ERR(segs) || !segs)
1931 			goto drop;
1932 
1933 		__skb_queue_head_init(&seg_list);
1934 
1935 		skb_list_walk_safe(segs, seg, next) {
1936 			skb_mark_not_on_list(seg);
1937 			__skb_queue_tail(&seg_list, seg);
1938 		}
1939 
1940 		skb_queue_splice(&seg_list, list);
1941 		dev_kfree_skb(skb);
1942 	} else if (skb->ip_summed == CHECKSUM_PARTIAL) {
1943 		if (skb_checksum_help(skb) < 0)
1944 			goto drop;
1945 
1946 		__skb_queue_head(list, skb);
1947 	} else {
1948 		struct net_device_stats *stats;
1949 
1950 drop:
1951 		stats = &tp->netdev->stats;
1952 		stats->tx_dropped++;
1953 		dev_kfree_skb(skb);
1954 	}
1955 }
1956 
rtl_tx_vlan_tag(struct tx_desc * desc,struct sk_buff * skb)1957 static inline void rtl_tx_vlan_tag(struct tx_desc *desc, struct sk_buff *skb)
1958 {
1959 	if (skb_vlan_tag_present(skb)) {
1960 		u32 opts2;
1961 
1962 		opts2 = TX_VLAN_TAG | swab16(skb_vlan_tag_get(skb));
1963 		desc->opts2 |= cpu_to_le32(opts2);
1964 	}
1965 }
1966 
rtl_rx_vlan_tag(struct rx_desc * desc,struct sk_buff * skb)1967 static inline void rtl_rx_vlan_tag(struct rx_desc *desc, struct sk_buff *skb)
1968 {
1969 	u32 opts2 = le32_to_cpu(desc->opts2);
1970 
1971 	if (opts2 & RX_VLAN_TAG)
1972 		__vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
1973 				       swab16(opts2 & 0xffff));
1974 }
1975 
r8152_tx_csum(struct r8152 * tp,struct tx_desc * desc,struct sk_buff * skb,u32 len,u32 transport_offset)1976 static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc,
1977 			 struct sk_buff *skb, u32 len, u32 transport_offset)
1978 {
1979 	u32 mss = skb_shinfo(skb)->gso_size;
1980 	u32 opts1, opts2 = 0;
1981 	int ret = TX_CSUM_SUCCESS;
1982 
1983 	WARN_ON_ONCE(len > TX_LEN_MAX);
1984 
1985 	opts1 = len | TX_FS | TX_LS;
1986 
1987 	if (mss) {
1988 		if (transport_offset > GTTCPHO_MAX) {
1989 			netif_warn(tp, tx_err, tp->netdev,
1990 				   "Invalid transport offset 0x%x for TSO\n",
1991 				   transport_offset);
1992 			ret = TX_CSUM_TSO;
1993 			goto unavailable;
1994 		}
1995 
1996 		switch (vlan_get_protocol(skb)) {
1997 		case htons(ETH_P_IP):
1998 			opts1 |= GTSENDV4;
1999 			break;
2000 
2001 		case htons(ETH_P_IPV6):
2002 			if (skb_cow_head(skb, 0)) {
2003 				ret = TX_CSUM_TSO;
2004 				goto unavailable;
2005 			}
2006 			tcp_v6_gso_csum_prep(skb);
2007 			opts1 |= GTSENDV6;
2008 			break;
2009 
2010 		default:
2011 			WARN_ON_ONCE(1);
2012 			break;
2013 		}
2014 
2015 		opts1 |= transport_offset << GTTCPHO_SHIFT;
2016 		opts2 |= min(mss, MSS_MAX) << MSS_SHIFT;
2017 	} else if (skb->ip_summed == CHECKSUM_PARTIAL) {
2018 		u8 ip_protocol;
2019 
2020 		if (transport_offset > TCPHO_MAX) {
2021 			netif_warn(tp, tx_err, tp->netdev,
2022 				   "Invalid transport offset 0x%x\n",
2023 				   transport_offset);
2024 			ret = TX_CSUM_NONE;
2025 			goto unavailable;
2026 		}
2027 
2028 		switch (vlan_get_protocol(skb)) {
2029 		case htons(ETH_P_IP):
2030 			opts2 |= IPV4_CS;
2031 			ip_protocol = ip_hdr(skb)->protocol;
2032 			break;
2033 
2034 		case htons(ETH_P_IPV6):
2035 			opts2 |= IPV6_CS;
2036 			ip_protocol = ipv6_hdr(skb)->nexthdr;
2037 			break;
2038 
2039 		default:
2040 			ip_protocol = IPPROTO_RAW;
2041 			break;
2042 		}
2043 
2044 		if (ip_protocol == IPPROTO_TCP)
2045 			opts2 |= TCP_CS;
2046 		else if (ip_protocol == IPPROTO_UDP)
2047 			opts2 |= UDP_CS;
2048 		else
2049 			WARN_ON_ONCE(1);
2050 
2051 		opts2 |= transport_offset << TCPHO_SHIFT;
2052 	}
2053 
2054 	desc->opts2 = cpu_to_le32(opts2);
2055 	desc->opts1 = cpu_to_le32(opts1);
2056 
2057 unavailable:
2058 	return ret;
2059 }
2060 
r8152_tx_agg_fill(struct r8152 * tp,struct tx_agg * agg)2061 static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg)
2062 {
2063 	struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
2064 	int remain, ret;
2065 	u8 *tx_data;
2066 
2067 	__skb_queue_head_init(&skb_head);
2068 	spin_lock(&tx_queue->lock);
2069 	skb_queue_splice_init(tx_queue, &skb_head);
2070 	spin_unlock(&tx_queue->lock);
2071 
2072 	tx_data = agg->head;
2073 	agg->skb_num = 0;
2074 	agg->skb_len = 0;
2075 	remain = agg_buf_sz;
2076 
2077 	while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) {
2078 		struct tx_desc *tx_desc;
2079 		struct sk_buff *skb;
2080 		unsigned int len;
2081 		u32 offset;
2082 
2083 		skb = __skb_dequeue(&skb_head);
2084 		if (!skb)
2085 			break;
2086 
2087 		len = skb->len + sizeof(*tx_desc);
2088 
2089 		if (len > remain) {
2090 			__skb_queue_head(&skb_head, skb);
2091 			break;
2092 		}
2093 
2094 		tx_data = tx_agg_align(tx_data);
2095 		tx_desc = (struct tx_desc *)tx_data;
2096 
2097 		offset = (u32)skb_transport_offset(skb);
2098 
2099 		if (r8152_tx_csum(tp, tx_desc, skb, skb->len, offset)) {
2100 			r8152_csum_workaround(tp, skb, &skb_head);
2101 			continue;
2102 		}
2103 
2104 		rtl_tx_vlan_tag(tx_desc, skb);
2105 
2106 		tx_data += sizeof(*tx_desc);
2107 
2108 		len = skb->len;
2109 		if (skb_copy_bits(skb, 0, tx_data, len) < 0) {
2110 			struct net_device_stats *stats = &tp->netdev->stats;
2111 
2112 			stats->tx_dropped++;
2113 			dev_kfree_skb_any(skb);
2114 			tx_data -= sizeof(*tx_desc);
2115 			continue;
2116 		}
2117 
2118 		tx_data += len;
2119 		agg->skb_len += len;
2120 		agg->skb_num += skb_shinfo(skb)->gso_segs ?: 1;
2121 
2122 		dev_kfree_skb_any(skb);
2123 
2124 		remain = agg_buf_sz - (int)(tx_agg_align(tx_data) - agg->head);
2125 
2126 		if (test_bit(DELL_TB_RX_AGG_BUG, &tp->flags))
2127 			break;
2128 	}
2129 
2130 	if (!skb_queue_empty(&skb_head)) {
2131 		spin_lock(&tx_queue->lock);
2132 		skb_queue_splice(&skb_head, tx_queue);
2133 		spin_unlock(&tx_queue->lock);
2134 	}
2135 
2136 	netif_tx_lock(tp->netdev);
2137 
2138 	if (netif_queue_stopped(tp->netdev) &&
2139 	    skb_queue_len(&tp->tx_queue) < tp->tx_qlen)
2140 		netif_wake_queue(tp->netdev);
2141 
2142 	netif_tx_unlock(tp->netdev);
2143 
2144 	ret = usb_autopm_get_interface_async(tp->intf);
2145 	if (ret < 0)
2146 		goto out_tx_fill;
2147 
2148 	usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2),
2149 			  agg->head, (int)(tx_data - (u8 *)agg->head),
2150 			  (usb_complete_t)write_bulk_callback, agg);
2151 
2152 	ret = usb_submit_urb(agg->urb, GFP_ATOMIC);
2153 	if (ret < 0)
2154 		usb_autopm_put_interface_async(tp->intf);
2155 
2156 out_tx_fill:
2157 	return ret;
2158 }
2159 
r8152_rx_csum(struct r8152 * tp,struct rx_desc * rx_desc)2160 static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc)
2161 {
2162 	u8 checksum = CHECKSUM_NONE;
2163 	u32 opts2, opts3;
2164 
2165 	if (!(tp->netdev->features & NETIF_F_RXCSUM))
2166 		goto return_result;
2167 
2168 	opts2 = le32_to_cpu(rx_desc->opts2);
2169 	opts3 = le32_to_cpu(rx_desc->opts3);
2170 
2171 	if (opts2 & RD_IPV4_CS) {
2172 		if (opts3 & IPF)
2173 			checksum = CHECKSUM_NONE;
2174 		else if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
2175 			checksum = CHECKSUM_UNNECESSARY;
2176 		else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
2177 			checksum = CHECKSUM_UNNECESSARY;
2178 	} else if (opts2 & RD_IPV6_CS) {
2179 		if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
2180 			checksum = CHECKSUM_UNNECESSARY;
2181 		else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
2182 			checksum = CHECKSUM_UNNECESSARY;
2183 	}
2184 
2185 return_result:
2186 	return checksum;
2187 }
2188 
rx_count_exceed(struct r8152 * tp)2189 static inline bool rx_count_exceed(struct r8152 *tp)
2190 {
2191 	return atomic_read(&tp->rx_count) > RTL8152_MAX_RX;
2192 }
2193 
agg_offset(struct rx_agg * agg,void * addr)2194 static inline int agg_offset(struct rx_agg *agg, void *addr)
2195 {
2196 	return (int)(addr - agg->buffer);
2197 }
2198 
rtl_get_free_rx(struct r8152 * tp,gfp_t mflags)2199 static struct rx_agg *rtl_get_free_rx(struct r8152 *tp, gfp_t mflags)
2200 {
2201 	struct rx_agg *agg, *agg_next, *agg_free = NULL;
2202 	unsigned long flags;
2203 
2204 	spin_lock_irqsave(&tp->rx_lock, flags);
2205 
2206 	list_for_each_entry_safe(agg, agg_next, &tp->rx_used, list) {
2207 		if (page_count(agg->page) == 1) {
2208 			if (!agg_free) {
2209 				list_del_init(&agg->list);
2210 				agg_free = agg;
2211 				continue;
2212 			}
2213 			if (rx_count_exceed(tp)) {
2214 				list_del_init(&agg->list);
2215 				free_rx_agg(tp, agg);
2216 			}
2217 			break;
2218 		}
2219 	}
2220 
2221 	spin_unlock_irqrestore(&tp->rx_lock, flags);
2222 
2223 	if (!agg_free && atomic_read(&tp->rx_count) < tp->rx_pending)
2224 		agg_free = alloc_rx_agg(tp, mflags);
2225 
2226 	return agg_free;
2227 }
2228 
rx_bottom(struct r8152 * tp,int budget)2229 static int rx_bottom(struct r8152 *tp, int budget)
2230 {
2231 	unsigned long flags;
2232 	struct list_head *cursor, *next, rx_queue;
2233 	int ret = 0, work_done = 0;
2234 	struct napi_struct *napi = &tp->napi;
2235 
2236 	if (!skb_queue_empty(&tp->rx_queue)) {
2237 		while (work_done < budget) {
2238 			struct sk_buff *skb = __skb_dequeue(&tp->rx_queue);
2239 			struct net_device *netdev = tp->netdev;
2240 			struct net_device_stats *stats = &netdev->stats;
2241 			unsigned int pkt_len;
2242 
2243 			if (!skb)
2244 				break;
2245 
2246 			pkt_len = skb->len;
2247 			napi_gro_receive(napi, skb);
2248 			work_done++;
2249 			stats->rx_packets++;
2250 			stats->rx_bytes += pkt_len;
2251 		}
2252 	}
2253 
2254 	if (list_empty(&tp->rx_done))
2255 		goto out1;
2256 
2257 	INIT_LIST_HEAD(&rx_queue);
2258 	spin_lock_irqsave(&tp->rx_lock, flags);
2259 	list_splice_init(&tp->rx_done, &rx_queue);
2260 	spin_unlock_irqrestore(&tp->rx_lock, flags);
2261 
2262 	list_for_each_safe(cursor, next, &rx_queue) {
2263 		struct rx_desc *rx_desc;
2264 		struct rx_agg *agg, *agg_free;
2265 		int len_used = 0;
2266 		struct urb *urb;
2267 		u8 *rx_data;
2268 
2269 		list_del_init(cursor);
2270 
2271 		agg = list_entry(cursor, struct rx_agg, list);
2272 		urb = agg->urb;
2273 		if (urb->actual_length < ETH_ZLEN)
2274 			goto submit;
2275 
2276 		agg_free = rtl_get_free_rx(tp, GFP_ATOMIC);
2277 
2278 		rx_desc = agg->buffer;
2279 		rx_data = agg->buffer;
2280 		len_used += sizeof(struct rx_desc);
2281 
2282 		while (urb->actual_length > len_used) {
2283 			struct net_device *netdev = tp->netdev;
2284 			struct net_device_stats *stats = &netdev->stats;
2285 			unsigned int pkt_len, rx_frag_head_sz;
2286 			struct sk_buff *skb;
2287 
2288 			/* limite the skb numbers for rx_queue */
2289 			if (unlikely(skb_queue_len(&tp->rx_queue) >= 1000))
2290 				break;
2291 
2292 			pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
2293 			if (pkt_len < ETH_ZLEN)
2294 				break;
2295 
2296 			len_used += pkt_len;
2297 			if (urb->actual_length < len_used)
2298 				break;
2299 
2300 			pkt_len -= ETH_FCS_LEN;
2301 			rx_data += sizeof(struct rx_desc);
2302 
2303 			if (!agg_free || tp->rx_copybreak > pkt_len)
2304 				rx_frag_head_sz = pkt_len;
2305 			else
2306 				rx_frag_head_sz = tp->rx_copybreak;
2307 
2308 			skb = napi_alloc_skb(napi, rx_frag_head_sz);
2309 			if (!skb) {
2310 				stats->rx_dropped++;
2311 				goto find_next_rx;
2312 			}
2313 
2314 			skb->ip_summed = r8152_rx_csum(tp, rx_desc);
2315 			memcpy(skb->data, rx_data, rx_frag_head_sz);
2316 			skb_put(skb, rx_frag_head_sz);
2317 			pkt_len -= rx_frag_head_sz;
2318 			rx_data += rx_frag_head_sz;
2319 			if (pkt_len) {
2320 				skb_add_rx_frag(skb, 0, agg->page,
2321 						agg_offset(agg, rx_data),
2322 						pkt_len,
2323 						SKB_DATA_ALIGN(pkt_len));
2324 				get_page(agg->page);
2325 			}
2326 
2327 			skb->protocol = eth_type_trans(skb, netdev);
2328 			rtl_rx_vlan_tag(rx_desc, skb);
2329 			if (work_done < budget) {
2330 				work_done++;
2331 				stats->rx_packets++;
2332 				stats->rx_bytes += skb->len;
2333 				napi_gro_receive(napi, skb);
2334 			} else {
2335 				__skb_queue_tail(&tp->rx_queue, skb);
2336 			}
2337 
2338 find_next_rx:
2339 			rx_data = rx_agg_align(rx_data + pkt_len + ETH_FCS_LEN);
2340 			rx_desc = (struct rx_desc *)rx_data;
2341 			len_used = agg_offset(agg, rx_data);
2342 			len_used += sizeof(struct rx_desc);
2343 		}
2344 
2345 		WARN_ON(!agg_free && page_count(agg->page) > 1);
2346 
2347 		if (agg_free) {
2348 			spin_lock_irqsave(&tp->rx_lock, flags);
2349 			if (page_count(agg->page) == 1) {
2350 				list_add(&agg_free->list, &tp->rx_used);
2351 			} else {
2352 				list_add_tail(&agg->list, &tp->rx_used);
2353 				agg = agg_free;
2354 				urb = agg->urb;
2355 			}
2356 			spin_unlock_irqrestore(&tp->rx_lock, flags);
2357 		}
2358 
2359 submit:
2360 		if (!ret) {
2361 			ret = r8152_submit_rx(tp, agg, GFP_ATOMIC);
2362 		} else {
2363 			urb->actual_length = 0;
2364 			list_add_tail(&agg->list, next);
2365 		}
2366 	}
2367 
2368 	if (!list_empty(&rx_queue)) {
2369 		spin_lock_irqsave(&tp->rx_lock, flags);
2370 		list_splice_tail(&rx_queue, &tp->rx_done);
2371 		spin_unlock_irqrestore(&tp->rx_lock, flags);
2372 	}
2373 
2374 out1:
2375 	return work_done;
2376 }
2377 
tx_bottom(struct r8152 * tp)2378 static void tx_bottom(struct r8152 *tp)
2379 {
2380 	int res;
2381 
2382 	do {
2383 		struct net_device *netdev = tp->netdev;
2384 		struct tx_agg *agg;
2385 
2386 		if (skb_queue_empty(&tp->tx_queue))
2387 			break;
2388 
2389 		agg = r8152_get_tx_agg(tp);
2390 		if (!agg)
2391 			break;
2392 
2393 		res = r8152_tx_agg_fill(tp, agg);
2394 		if (!res)
2395 			continue;
2396 
2397 		if (res == -ENODEV) {
2398 			rtl_set_unplug(tp);
2399 			netif_device_detach(netdev);
2400 		} else {
2401 			struct net_device_stats *stats = &netdev->stats;
2402 			unsigned long flags;
2403 
2404 			netif_warn(tp, tx_err, netdev,
2405 				   "failed tx_urb %d\n", res);
2406 			stats->tx_dropped += agg->skb_num;
2407 
2408 			spin_lock_irqsave(&tp->tx_lock, flags);
2409 			list_add_tail(&agg->list, &tp->tx_free);
2410 			spin_unlock_irqrestore(&tp->tx_lock, flags);
2411 		}
2412 	} while (res == 0);
2413 }
2414 
bottom_half(unsigned long data)2415 static void bottom_half(unsigned long data)
2416 {
2417 	struct r8152 *tp;
2418 
2419 	tp = (struct r8152 *)data;
2420 
2421 	if (test_bit(RTL8152_UNPLUG, &tp->flags))
2422 		return;
2423 
2424 	if (!test_bit(WORK_ENABLE, &tp->flags))
2425 		return;
2426 
2427 	/* When link down, the driver would cancel all bulks. */
2428 	/* This avoid the re-submitting bulk */
2429 	if (!netif_carrier_ok(tp->netdev))
2430 		return;
2431 
2432 	clear_bit(SCHEDULE_TASKLET, &tp->flags);
2433 
2434 	tx_bottom(tp);
2435 }
2436 
r8152_poll(struct napi_struct * napi,int budget)2437 static int r8152_poll(struct napi_struct *napi, int budget)
2438 {
2439 	struct r8152 *tp = container_of(napi, struct r8152, napi);
2440 	int work_done;
2441 
2442 	work_done = rx_bottom(tp, budget);
2443 
2444 	if (work_done < budget) {
2445 		if (!napi_complete_done(napi, work_done))
2446 			goto out;
2447 		if (!list_empty(&tp->rx_done))
2448 			napi_schedule(napi);
2449 	}
2450 
2451 out:
2452 	return work_done;
2453 }
2454 
2455 static
r8152_submit_rx(struct r8152 * tp,struct rx_agg * agg,gfp_t mem_flags)2456 int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags)
2457 {
2458 	int ret;
2459 
2460 	/* The rx would be stopped, so skip submitting */
2461 	if (test_bit(RTL8152_UNPLUG, &tp->flags) ||
2462 	    !test_bit(WORK_ENABLE, &tp->flags) || !netif_carrier_ok(tp->netdev))
2463 		return 0;
2464 
2465 	usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1),
2466 			  agg->buffer, tp->rx_buf_sz,
2467 			  (usb_complete_t)read_bulk_callback, agg);
2468 
2469 	ret = usb_submit_urb(agg->urb, mem_flags);
2470 	if (ret == -ENODEV) {
2471 		rtl_set_unplug(tp);
2472 		netif_device_detach(tp->netdev);
2473 	} else if (ret) {
2474 		struct urb *urb = agg->urb;
2475 		unsigned long flags;
2476 
2477 		urb->actual_length = 0;
2478 		spin_lock_irqsave(&tp->rx_lock, flags);
2479 		list_add_tail(&agg->list, &tp->rx_done);
2480 		spin_unlock_irqrestore(&tp->rx_lock, flags);
2481 
2482 		netif_err(tp, rx_err, tp->netdev,
2483 			  "Couldn't submit rx[%p], ret = %d\n", agg, ret);
2484 
2485 		napi_schedule(&tp->napi);
2486 	}
2487 
2488 	return ret;
2489 }
2490 
rtl_drop_queued_tx(struct r8152 * tp)2491 static void rtl_drop_queued_tx(struct r8152 *tp)
2492 {
2493 	struct net_device_stats *stats = &tp->netdev->stats;
2494 	struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
2495 	struct sk_buff *skb;
2496 
2497 	if (skb_queue_empty(tx_queue))
2498 		return;
2499 
2500 	__skb_queue_head_init(&skb_head);
2501 	spin_lock_bh(&tx_queue->lock);
2502 	skb_queue_splice_init(tx_queue, &skb_head);
2503 	spin_unlock_bh(&tx_queue->lock);
2504 
2505 	while ((skb = __skb_dequeue(&skb_head))) {
2506 		dev_kfree_skb(skb);
2507 		stats->tx_dropped++;
2508 	}
2509 }
2510 
rtl8152_tx_timeout(struct net_device * netdev,unsigned int txqueue)2511 static void rtl8152_tx_timeout(struct net_device *netdev, unsigned int txqueue)
2512 {
2513 	struct r8152 *tp = netdev_priv(netdev);
2514 
2515 	netif_warn(tp, tx_err, netdev, "Tx timeout\n");
2516 
2517 	usb_queue_reset_device(tp->intf);
2518 }
2519 
rtl8152_set_rx_mode(struct net_device * netdev)2520 static void rtl8152_set_rx_mode(struct net_device *netdev)
2521 {
2522 	struct r8152 *tp = netdev_priv(netdev);
2523 
2524 	if (netif_carrier_ok(netdev)) {
2525 		set_bit(RTL8152_SET_RX_MODE, &tp->flags);
2526 		schedule_delayed_work(&tp->schedule, 0);
2527 	}
2528 }
2529 
_rtl8152_set_rx_mode(struct net_device * netdev)2530 static void _rtl8152_set_rx_mode(struct net_device *netdev)
2531 {
2532 	struct r8152 *tp = netdev_priv(netdev);
2533 	u32 mc_filter[2];	/* Multicast hash filter */
2534 	__le32 tmp[2];
2535 	u32 ocp_data;
2536 
2537 	netif_stop_queue(netdev);
2538 	ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2539 	ocp_data &= ~RCR_ACPT_ALL;
2540 	ocp_data |= RCR_AB | RCR_APM;
2541 
2542 	if (netdev->flags & IFF_PROMISC) {
2543 		/* Unconditionally log net taps. */
2544 		netif_notice(tp, link, netdev, "Promiscuous mode enabled\n");
2545 		ocp_data |= RCR_AM | RCR_AAP;
2546 		mc_filter[1] = 0xffffffff;
2547 		mc_filter[0] = 0xffffffff;
2548 	} else if ((netdev_mc_count(netdev) > multicast_filter_limit) ||
2549 		   (netdev->flags & IFF_ALLMULTI)) {
2550 		/* Too many to filter perfectly -- accept all multicasts. */
2551 		ocp_data |= RCR_AM;
2552 		mc_filter[1] = 0xffffffff;
2553 		mc_filter[0] = 0xffffffff;
2554 	} else {
2555 		struct netdev_hw_addr *ha;
2556 
2557 		mc_filter[1] = 0;
2558 		mc_filter[0] = 0;
2559 		netdev_for_each_mc_addr(ha, netdev) {
2560 			int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
2561 
2562 			mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2563 			ocp_data |= RCR_AM;
2564 		}
2565 	}
2566 
2567 	tmp[0] = __cpu_to_le32(swab32(mc_filter[1]));
2568 	tmp[1] = __cpu_to_le32(swab32(mc_filter[0]));
2569 
2570 	pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp);
2571 	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2572 	netif_wake_queue(netdev);
2573 }
2574 
2575 static netdev_features_t
rtl8152_features_check(struct sk_buff * skb,struct net_device * dev,netdev_features_t features)2576 rtl8152_features_check(struct sk_buff *skb, struct net_device *dev,
2577 		       netdev_features_t features)
2578 {
2579 	u32 mss = skb_shinfo(skb)->gso_size;
2580 	int max_offset = mss ? GTTCPHO_MAX : TCPHO_MAX;
2581 	int offset = skb_transport_offset(skb);
2582 
2583 	if ((mss || skb->ip_summed == CHECKSUM_PARTIAL) && offset > max_offset)
2584 		features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
2585 	else if ((skb->len + sizeof(struct tx_desc)) > agg_buf_sz)
2586 		features &= ~NETIF_F_GSO_MASK;
2587 
2588 	return features;
2589 }
2590 
rtl8152_start_xmit(struct sk_buff * skb,struct net_device * netdev)2591 static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb,
2592 				      struct net_device *netdev)
2593 {
2594 	struct r8152 *tp = netdev_priv(netdev);
2595 
2596 	skb_tx_timestamp(skb);
2597 
2598 	skb_queue_tail(&tp->tx_queue, skb);
2599 
2600 	if (!list_empty(&tp->tx_free)) {
2601 		if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
2602 			set_bit(SCHEDULE_TASKLET, &tp->flags);
2603 			schedule_delayed_work(&tp->schedule, 0);
2604 		} else {
2605 			usb_mark_last_busy(tp->udev);
2606 			tasklet_schedule(&tp->tx_tl);
2607 		}
2608 	} else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen) {
2609 		netif_stop_queue(netdev);
2610 	}
2611 
2612 	return NETDEV_TX_OK;
2613 }
2614 
r8152b_reset_packet_filter(struct r8152 * tp)2615 static void r8152b_reset_packet_filter(struct r8152 *tp)
2616 {
2617 	u32	ocp_data;
2618 
2619 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);
2620 	ocp_data &= ~FMC_FCR_MCU_EN;
2621 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
2622 	ocp_data |= FMC_FCR_MCU_EN;
2623 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
2624 }
2625 
rtl8152_nic_reset(struct r8152 * tp)2626 static void rtl8152_nic_reset(struct r8152 *tp)
2627 {
2628 	int	i;
2629 
2630 	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST);
2631 
2632 	for (i = 0; i < 1000; i++) {
2633 		if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST))
2634 			break;
2635 		usleep_range(100, 400);
2636 	}
2637 }
2638 
set_tx_qlen(struct r8152 * tp)2639 static void set_tx_qlen(struct r8152 *tp)
2640 {
2641 	struct net_device *netdev = tp->netdev;
2642 
2643 	tp->tx_qlen = agg_buf_sz / (netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN +
2644 				    sizeof(struct tx_desc));
2645 }
2646 
rtl8152_get_speed(struct r8152 * tp)2647 static inline u8 rtl8152_get_speed(struct r8152 *tp)
2648 {
2649 	return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);
2650 }
2651 
rtl_set_eee_plus(struct r8152 * tp)2652 static void rtl_set_eee_plus(struct r8152 *tp)
2653 {
2654 	u32 ocp_data;
2655 	u8 speed;
2656 
2657 	speed = rtl8152_get_speed(tp);
2658 	if (speed & _10bps) {
2659 		ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
2660 		ocp_data |= EEEP_CR_EEEP_TX;
2661 		ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
2662 	} else {
2663 		ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
2664 		ocp_data &= ~EEEP_CR_EEEP_TX;
2665 		ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
2666 	}
2667 }
2668 
rxdy_gated_en(struct r8152 * tp,bool enable)2669 static void rxdy_gated_en(struct r8152 *tp, bool enable)
2670 {
2671 	u32 ocp_data;
2672 
2673 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
2674 	if (enable)
2675 		ocp_data |= RXDY_GATED_EN;
2676 	else
2677 		ocp_data &= ~RXDY_GATED_EN;
2678 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
2679 }
2680 
rtl_start_rx(struct r8152 * tp)2681 static int rtl_start_rx(struct r8152 *tp)
2682 {
2683 	struct rx_agg *agg, *agg_next;
2684 	struct list_head tmp_list;
2685 	unsigned long flags;
2686 	int ret = 0, i = 0;
2687 
2688 	INIT_LIST_HEAD(&tmp_list);
2689 
2690 	spin_lock_irqsave(&tp->rx_lock, flags);
2691 
2692 	INIT_LIST_HEAD(&tp->rx_done);
2693 	INIT_LIST_HEAD(&tp->rx_used);
2694 
2695 	list_splice_init(&tp->rx_info, &tmp_list);
2696 
2697 	spin_unlock_irqrestore(&tp->rx_lock, flags);
2698 
2699 	list_for_each_entry_safe(agg, agg_next, &tmp_list, info_list) {
2700 		INIT_LIST_HEAD(&agg->list);
2701 
2702 		/* Only RTL8152_MAX_RX rx_agg need to be submitted. */
2703 		if (++i > RTL8152_MAX_RX) {
2704 			spin_lock_irqsave(&tp->rx_lock, flags);
2705 			list_add_tail(&agg->list, &tp->rx_used);
2706 			spin_unlock_irqrestore(&tp->rx_lock, flags);
2707 		} else if (unlikely(ret < 0)) {
2708 			spin_lock_irqsave(&tp->rx_lock, flags);
2709 			list_add_tail(&agg->list, &tp->rx_done);
2710 			spin_unlock_irqrestore(&tp->rx_lock, flags);
2711 		} else {
2712 			ret = r8152_submit_rx(tp, agg, GFP_KERNEL);
2713 		}
2714 	}
2715 
2716 	spin_lock_irqsave(&tp->rx_lock, flags);
2717 	WARN_ON(!list_empty(&tp->rx_info));
2718 	list_splice(&tmp_list, &tp->rx_info);
2719 	spin_unlock_irqrestore(&tp->rx_lock, flags);
2720 
2721 	return ret;
2722 }
2723 
rtl_stop_rx(struct r8152 * tp)2724 static int rtl_stop_rx(struct r8152 *tp)
2725 {
2726 	struct rx_agg *agg, *agg_next;
2727 	struct list_head tmp_list;
2728 	unsigned long flags;
2729 
2730 	INIT_LIST_HEAD(&tmp_list);
2731 
2732 	/* The usb_kill_urb() couldn't be used in atomic.
2733 	 * Therefore, move the list of rx_info to a tmp one.
2734 	 * Then, list_for_each_entry_safe could be used without
2735 	 * spin lock.
2736 	 */
2737 
2738 	spin_lock_irqsave(&tp->rx_lock, flags);
2739 	list_splice_init(&tp->rx_info, &tmp_list);
2740 	spin_unlock_irqrestore(&tp->rx_lock, flags);
2741 
2742 	list_for_each_entry_safe(agg, agg_next, &tmp_list, info_list) {
2743 		/* At least RTL8152_MAX_RX rx_agg have the page_count being
2744 		 * equal to 1, so the other ones could be freed safely.
2745 		 */
2746 		if (page_count(agg->page) > 1)
2747 			free_rx_agg(tp, agg);
2748 		else
2749 			usb_kill_urb(agg->urb);
2750 	}
2751 
2752 	/* Move back the list of temp to the rx_info */
2753 	spin_lock_irqsave(&tp->rx_lock, flags);
2754 	WARN_ON(!list_empty(&tp->rx_info));
2755 	list_splice(&tmp_list, &tp->rx_info);
2756 	spin_unlock_irqrestore(&tp->rx_lock, flags);
2757 
2758 	while (!skb_queue_empty(&tp->rx_queue))
2759 		dev_kfree_skb(__skb_dequeue(&tp->rx_queue));
2760 
2761 	return 0;
2762 }
2763 
r8153b_rx_agg_chg_indicate(struct r8152 * tp)2764 static inline void r8153b_rx_agg_chg_indicate(struct r8152 *tp)
2765 {
2766 	ocp_write_byte(tp, MCU_TYPE_USB, USB_UPT_RXDMA_OWN,
2767 		       OWN_UPDATE | OWN_CLEAR);
2768 }
2769 
rtl_enable(struct r8152 * tp)2770 static int rtl_enable(struct r8152 *tp)
2771 {
2772 	u32 ocp_data;
2773 
2774 	r8152b_reset_packet_filter(tp);
2775 
2776 	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
2777 	ocp_data |= CR_RE | CR_TE;
2778 	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
2779 
2780 	switch (tp->version) {
2781 	case RTL_VER_08:
2782 	case RTL_VER_09:
2783 		r8153b_rx_agg_chg_indicate(tp);
2784 		break;
2785 	default:
2786 		break;
2787 	}
2788 
2789 	rxdy_gated_en(tp, false);
2790 
2791 	return 0;
2792 }
2793 
rtl8152_enable(struct r8152 * tp)2794 static int rtl8152_enable(struct r8152 *tp)
2795 {
2796 	if (test_bit(RTL8152_UNPLUG, &tp->flags))
2797 		return -ENODEV;
2798 
2799 	set_tx_qlen(tp);
2800 	rtl_set_eee_plus(tp);
2801 
2802 	return rtl_enable(tp);
2803 }
2804 
r8153_set_rx_early_timeout(struct r8152 * tp)2805 static void r8153_set_rx_early_timeout(struct r8152 *tp)
2806 {
2807 	u32 ocp_data = tp->coalesce / 8;
2808 
2809 	switch (tp->version) {
2810 	case RTL_VER_03:
2811 	case RTL_VER_04:
2812 	case RTL_VER_05:
2813 	case RTL_VER_06:
2814 		ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT,
2815 			       ocp_data);
2816 		break;
2817 
2818 	case RTL_VER_08:
2819 	case RTL_VER_09:
2820 		/* The RTL8153B uses USB_RX_EXTRA_AGGR_TMR for rx timeout
2821 		 * primarily. For USB_RX_EARLY_TIMEOUT, we fix it to 128ns.
2822 		 */
2823 		ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT,
2824 			       128 / 8);
2825 		ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EXTRA_AGGR_TMR,
2826 			       ocp_data);
2827 		break;
2828 
2829 	default:
2830 		break;
2831 	}
2832 }
2833 
r8153_set_rx_early_size(struct r8152 * tp)2834 static void r8153_set_rx_early_size(struct r8152 *tp)
2835 {
2836 	u32 ocp_data = tp->rx_buf_sz - rx_reserved_size(tp->netdev->mtu);
2837 
2838 	switch (tp->version) {
2839 	case RTL_VER_03:
2840 	case RTL_VER_04:
2841 	case RTL_VER_05:
2842 	case RTL_VER_06:
2843 		ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,
2844 			       ocp_data / 4);
2845 		break;
2846 	case RTL_VER_08:
2847 	case RTL_VER_09:
2848 		ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,
2849 			       ocp_data / 8);
2850 		break;
2851 	default:
2852 		WARN_ON_ONCE(1);
2853 		break;
2854 	}
2855 }
2856 
rtl8153_enable(struct r8152 * tp)2857 static int rtl8153_enable(struct r8152 *tp)
2858 {
2859 	if (test_bit(RTL8152_UNPLUG, &tp->flags))
2860 		return -ENODEV;
2861 
2862 	set_tx_qlen(tp);
2863 	rtl_set_eee_plus(tp);
2864 	r8153_set_rx_early_timeout(tp);
2865 	r8153_set_rx_early_size(tp);
2866 
2867 	if (tp->version == RTL_VER_09) {
2868 		u32 ocp_data;
2869 
2870 		ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
2871 		ocp_data &= ~FC_PATCH_TASK;
2872 		ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
2873 		usleep_range(1000, 2000);
2874 		ocp_data |= FC_PATCH_TASK;
2875 		ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
2876 	}
2877 
2878 	return rtl_enable(tp);
2879 }
2880 
rtl_disable(struct r8152 * tp)2881 static void rtl_disable(struct r8152 *tp)
2882 {
2883 	u32 ocp_data;
2884 	int i;
2885 
2886 	if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
2887 		rtl_drop_queued_tx(tp);
2888 		return;
2889 	}
2890 
2891 	ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2892 	ocp_data &= ~RCR_ACPT_ALL;
2893 	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2894 
2895 	rtl_drop_queued_tx(tp);
2896 
2897 	for (i = 0; i < RTL8152_MAX_TX; i++)
2898 		usb_kill_urb(tp->tx_info[i].urb);
2899 
2900 	rxdy_gated_en(tp, true);
2901 
2902 	for (i = 0; i < 1000; i++) {
2903 		ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2904 		if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY)
2905 			break;
2906 		usleep_range(1000, 2000);
2907 	}
2908 
2909 	for (i = 0; i < 1000; i++) {
2910 		if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY)
2911 			break;
2912 		usleep_range(1000, 2000);
2913 	}
2914 
2915 	rtl_stop_rx(tp);
2916 
2917 	rtl8152_nic_reset(tp);
2918 }
2919 
r8152_power_cut_en(struct r8152 * tp,bool enable)2920 static void r8152_power_cut_en(struct r8152 *tp, bool enable)
2921 {
2922 	u32 ocp_data;
2923 
2924 	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
2925 	if (enable)
2926 		ocp_data |= POWER_CUT;
2927 	else
2928 		ocp_data &= ~POWER_CUT;
2929 	ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
2930 
2931 	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
2932 	ocp_data &= ~RESUME_INDICATE;
2933 	ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
2934 }
2935 
rtl_rx_vlan_en(struct r8152 * tp,bool enable)2936 static void rtl_rx_vlan_en(struct r8152 *tp, bool enable)
2937 {
2938 	u32 ocp_data;
2939 
2940 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
2941 	if (enable)
2942 		ocp_data |= CPCR_RX_VLAN;
2943 	else
2944 		ocp_data &= ~CPCR_RX_VLAN;
2945 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
2946 }
2947 
rtl8152_set_features(struct net_device * dev,netdev_features_t features)2948 static int rtl8152_set_features(struct net_device *dev,
2949 				netdev_features_t features)
2950 {
2951 	netdev_features_t changed = features ^ dev->features;
2952 	struct r8152 *tp = netdev_priv(dev);
2953 	int ret;
2954 
2955 	ret = usb_autopm_get_interface(tp->intf);
2956 	if (ret < 0)
2957 		goto out;
2958 
2959 	mutex_lock(&tp->control);
2960 
2961 	if (changed & NETIF_F_HW_VLAN_CTAG_RX) {
2962 		if (features & NETIF_F_HW_VLAN_CTAG_RX)
2963 			rtl_rx_vlan_en(tp, true);
2964 		else
2965 			rtl_rx_vlan_en(tp, false);
2966 	}
2967 
2968 	mutex_unlock(&tp->control);
2969 
2970 	usb_autopm_put_interface(tp->intf);
2971 
2972 out:
2973 	return ret;
2974 }
2975 
2976 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
2977 
__rtl_get_wol(struct r8152 * tp)2978 static u32 __rtl_get_wol(struct r8152 *tp)
2979 {
2980 	u32 ocp_data;
2981 	u32 wolopts = 0;
2982 
2983 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2984 	if (ocp_data & LINK_ON_WAKE_EN)
2985 		wolopts |= WAKE_PHY;
2986 
2987 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2988 	if (ocp_data & UWF_EN)
2989 		wolopts |= WAKE_UCAST;
2990 	if (ocp_data & BWF_EN)
2991 		wolopts |= WAKE_BCAST;
2992 	if (ocp_data & MWF_EN)
2993 		wolopts |= WAKE_MCAST;
2994 
2995 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
2996 	if (ocp_data & MAGIC_EN)
2997 		wolopts |= WAKE_MAGIC;
2998 
2999 	return wolopts;
3000 }
3001 
__rtl_set_wol(struct r8152 * tp,u32 wolopts)3002 static void __rtl_set_wol(struct r8152 *tp, u32 wolopts)
3003 {
3004 	u32 ocp_data;
3005 
3006 	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
3007 
3008 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
3009 	ocp_data &= ~LINK_ON_WAKE_EN;
3010 	if (wolopts & WAKE_PHY)
3011 		ocp_data |= LINK_ON_WAKE_EN;
3012 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
3013 
3014 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
3015 	ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN);
3016 	if (wolopts & WAKE_UCAST)
3017 		ocp_data |= UWF_EN;
3018 	if (wolopts & WAKE_BCAST)
3019 		ocp_data |= BWF_EN;
3020 	if (wolopts & WAKE_MCAST)
3021 		ocp_data |= MWF_EN;
3022 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data);
3023 
3024 	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
3025 
3026 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
3027 	ocp_data &= ~MAGIC_EN;
3028 	if (wolopts & WAKE_MAGIC)
3029 		ocp_data |= MAGIC_EN;
3030 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data);
3031 
3032 	if (wolopts & WAKE_ANY)
3033 		device_set_wakeup_enable(&tp->udev->dev, true);
3034 	else
3035 		device_set_wakeup_enable(&tp->udev->dev, false);
3036 }
3037 
r8153_u1u2en(struct r8152 * tp,bool enable)3038 static void r8153_u1u2en(struct r8152 *tp, bool enable)
3039 {
3040 	u8 u1u2[8];
3041 
3042 	if (enable)
3043 		memset(u1u2, 0xff, sizeof(u1u2));
3044 	else
3045 		memset(u1u2, 0x00, sizeof(u1u2));
3046 
3047 	usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2);
3048 }
3049 
r8153b_u1u2en(struct r8152 * tp,bool enable)3050 static void r8153b_u1u2en(struct r8152 *tp, bool enable)
3051 {
3052 	u32 ocp_data;
3053 
3054 	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG);
3055 	if (enable)
3056 		ocp_data |= LPM_U1U2_EN;
3057 	else
3058 		ocp_data &= ~LPM_U1U2_EN;
3059 
3060 	ocp_write_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG, ocp_data);
3061 }
3062 
r8153_u2p3en(struct r8152 * tp,bool enable)3063 static void r8153_u2p3en(struct r8152 *tp, bool enable)
3064 {
3065 	u32 ocp_data;
3066 
3067 	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
3068 	if (enable)
3069 		ocp_data |= U2P3_ENABLE;
3070 	else
3071 		ocp_data &= ~U2P3_ENABLE;
3072 	ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);
3073 }
3074 
r8153b_ups_flags(struct r8152 * tp)3075 static void r8153b_ups_flags(struct r8152 *tp)
3076 {
3077 	u32 ups_flags = 0;
3078 
3079 	if (tp->ups_info.green)
3080 		ups_flags |= UPS_FLAGS_EN_GREEN;
3081 
3082 	if (tp->ups_info.aldps)
3083 		ups_flags |= UPS_FLAGS_EN_ALDPS;
3084 
3085 	if (tp->ups_info.eee)
3086 		ups_flags |= UPS_FLAGS_EN_EEE;
3087 
3088 	if (tp->ups_info.flow_control)
3089 		ups_flags |= UPS_FLAGS_EN_FLOW_CTR;
3090 
3091 	if (tp->ups_info.eee_ckdiv)
3092 		ups_flags |= UPS_FLAGS_EN_EEE_CKDIV;
3093 
3094 	if (tp->ups_info.eee_cmod_lv)
3095 		ups_flags |= UPS_FLAGS_EEE_CMOD_LV_EN;
3096 
3097 	if (tp->ups_info._10m_ckdiv)
3098 		ups_flags |= UPS_FLAGS_EN_10M_CKDIV;
3099 
3100 	if (tp->ups_info.eee_plloff_100)
3101 		ups_flags |= UPS_FLAGS_EEE_PLLOFF_100;
3102 
3103 	if (tp->ups_info.eee_plloff_giga)
3104 		ups_flags |= UPS_FLAGS_EEE_PLLOFF_GIGA;
3105 
3106 	if (tp->ups_info._250m_ckdiv)
3107 		ups_flags |= UPS_FLAGS_250M_CKDIV;
3108 
3109 	if (tp->ups_info.ctap_short_off)
3110 		ups_flags |= UPS_FLAGS_CTAP_SHORT_DIS;
3111 
3112 	switch (tp->ups_info.speed_duplex) {
3113 	case NWAY_10M_HALF:
3114 		ups_flags |= ups_flags_speed(1);
3115 		break;
3116 	case NWAY_10M_FULL:
3117 		ups_flags |= ups_flags_speed(2);
3118 		break;
3119 	case NWAY_100M_HALF:
3120 		ups_flags |= ups_flags_speed(3);
3121 		break;
3122 	case NWAY_100M_FULL:
3123 		ups_flags |= ups_flags_speed(4);
3124 		break;
3125 	case NWAY_1000M_FULL:
3126 		ups_flags |= ups_flags_speed(5);
3127 		break;
3128 	case FORCE_10M_HALF:
3129 		ups_flags |= ups_flags_speed(6);
3130 		break;
3131 	case FORCE_10M_FULL:
3132 		ups_flags |= ups_flags_speed(7);
3133 		break;
3134 	case FORCE_100M_HALF:
3135 		ups_flags |= ups_flags_speed(8);
3136 		break;
3137 	case FORCE_100M_FULL:
3138 		ups_flags |= ups_flags_speed(9);
3139 		break;
3140 	default:
3141 		break;
3142 	}
3143 
3144 	ocp_write_dword(tp, MCU_TYPE_USB, USB_UPS_FLAGS, ups_flags);
3145 }
3146 
r8153b_green_en(struct r8152 * tp,bool enable)3147 static void r8153b_green_en(struct r8152 *tp, bool enable)
3148 {
3149 	u16 data;
3150 
3151 	if (enable) {
3152 		sram_write(tp, 0x8045, 0);	/* 10M abiq&ldvbias */
3153 		sram_write(tp, 0x804d, 0x1222);	/* 100M short abiq&ldvbias */
3154 		sram_write(tp, 0x805d, 0x0022);	/* 1000M short abiq&ldvbias */
3155 	} else {
3156 		sram_write(tp, 0x8045, 0x2444);	/* 10M abiq&ldvbias */
3157 		sram_write(tp, 0x804d, 0x2444);	/* 100M short abiq&ldvbias */
3158 		sram_write(tp, 0x805d, 0x2444);	/* 1000M short abiq&ldvbias */
3159 	}
3160 
3161 	data = sram_read(tp, SRAM_GREEN_CFG);
3162 	data |= GREEN_ETH_EN;
3163 	sram_write(tp, SRAM_GREEN_CFG, data);
3164 
3165 	tp->ups_info.green = enable;
3166 }
3167 
r8153_phy_status(struct r8152 * tp,u16 desired)3168 static u16 r8153_phy_status(struct r8152 *tp, u16 desired)
3169 {
3170 	u16 data;
3171 	int i;
3172 
3173 	for (i = 0; i < 500; i++) {
3174 		data = ocp_reg_read(tp, OCP_PHY_STATUS);
3175 		data &= PHY_STAT_MASK;
3176 		if (desired) {
3177 			if (data == desired)
3178 				break;
3179 		} else if (data == PHY_STAT_LAN_ON || data == PHY_STAT_PWRDN ||
3180 			   data == PHY_STAT_EXT_INIT) {
3181 			break;
3182 		}
3183 
3184 		msleep(20);
3185 		if (test_bit(RTL8152_UNPLUG, &tp->flags))
3186 			break;
3187 	}
3188 
3189 	return data;
3190 }
3191 
r8153b_ups_en(struct r8152 * tp,bool enable)3192 static void r8153b_ups_en(struct r8152 *tp, bool enable)
3193 {
3194 	u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_POWER_CUT);
3195 
3196 	if (enable) {
3197 		r8153b_ups_flags(tp);
3198 
3199 		ocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN;
3200 		ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3201 
3202 		ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, 0xcfff);
3203 		ocp_data |= BIT(0);
3204 		ocp_write_byte(tp, MCU_TYPE_USB, 0xcfff, ocp_data);
3205 	} else {
3206 		u16 data;
3207 
3208 		ocp_data &= ~(UPS_EN | USP_PREWAKE);
3209 		ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3210 
3211 		ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, 0xcfff);
3212 		ocp_data &= ~BIT(0);
3213 		ocp_write_byte(tp, MCU_TYPE_USB, 0xcfff, ocp_data);
3214 
3215 		ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
3216 		ocp_data &= ~PCUT_STATUS;
3217 		ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
3218 
3219 		data = r8153_phy_status(tp, 0);
3220 
3221 		switch (data) {
3222 		case PHY_STAT_PWRDN:
3223 		case PHY_STAT_EXT_INIT:
3224 			r8153b_green_en(tp,
3225 					test_bit(GREEN_ETHERNET, &tp->flags));
3226 
3227 			data = r8152_mdio_read(tp, MII_BMCR);
3228 			data &= ~BMCR_PDOWN;
3229 			data |= BMCR_RESET;
3230 			r8152_mdio_write(tp, MII_BMCR, data);
3231 
3232 			data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
3233 			fallthrough;
3234 
3235 		default:
3236 			if (data != PHY_STAT_LAN_ON)
3237 				netif_warn(tp, link, tp->netdev,
3238 					   "PHY not ready");
3239 			break;
3240 		}
3241 	}
3242 }
3243 
r8153_power_cut_en(struct r8152 * tp,bool enable)3244 static void r8153_power_cut_en(struct r8152 *tp, bool enable)
3245 {
3246 	u32 ocp_data;
3247 
3248 	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
3249 	if (enable)
3250 		ocp_data |= PWR_EN | PHASE2_EN;
3251 	else
3252 		ocp_data &= ~(PWR_EN | PHASE2_EN);
3253 	ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3254 
3255 	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
3256 	ocp_data &= ~PCUT_STATUS;
3257 	ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
3258 }
3259 
r8153b_power_cut_en(struct r8152 * tp,bool enable)3260 static void r8153b_power_cut_en(struct r8152 *tp, bool enable)
3261 {
3262 	u32 ocp_data;
3263 
3264 	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
3265 	if (enable)
3266 		ocp_data |= PWR_EN | PHASE2_EN;
3267 	else
3268 		ocp_data &= ~PWR_EN;
3269 	ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3270 
3271 	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
3272 	ocp_data &= ~PCUT_STATUS;
3273 	ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
3274 }
3275 
r8153_queue_wake(struct r8152 * tp,bool enable)3276 static void r8153_queue_wake(struct r8152 *tp, bool enable)
3277 {
3278 	u32 ocp_data;
3279 
3280 	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_INDICATE_FALG);
3281 	if (enable)
3282 		ocp_data |= UPCOMING_RUNTIME_D3;
3283 	else
3284 		ocp_data &= ~UPCOMING_RUNTIME_D3;
3285 	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_INDICATE_FALG, ocp_data);
3286 
3287 	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_SUSPEND_FLAG);
3288 	ocp_data &= ~LINK_CHG_EVENT;
3289 	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_SUSPEND_FLAG, ocp_data);
3290 
3291 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
3292 	ocp_data &= ~LINK_CHANGE_FLAG;
3293 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
3294 }
3295 
rtl_can_wakeup(struct r8152 * tp)3296 static bool rtl_can_wakeup(struct r8152 *tp)
3297 {
3298 	struct usb_device *udev = tp->udev;
3299 
3300 	return (udev->actconfig->desc.bmAttributes & USB_CONFIG_ATT_WAKEUP);
3301 }
3302 
rtl_runtime_suspend_enable(struct r8152 * tp,bool enable)3303 static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable)
3304 {
3305 	if (enable) {
3306 		u32 ocp_data;
3307 
3308 		__rtl_set_wol(tp, WAKE_ANY);
3309 
3310 		ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
3311 
3312 		ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
3313 		ocp_data |= LINK_OFF_WAKE_EN;
3314 		ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
3315 
3316 		ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
3317 	} else {
3318 		u32 ocp_data;
3319 
3320 		__rtl_set_wol(tp, tp->saved_wolopts);
3321 
3322 		ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
3323 
3324 		ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
3325 		ocp_data &= ~LINK_OFF_WAKE_EN;
3326 		ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
3327 
3328 		ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
3329 	}
3330 }
3331 
rtl8153_runtime_enable(struct r8152 * tp,bool enable)3332 static void rtl8153_runtime_enable(struct r8152 *tp, bool enable)
3333 {
3334 	if (enable) {
3335 		r8153_u1u2en(tp, false);
3336 		r8153_u2p3en(tp, false);
3337 		rtl_runtime_suspend_enable(tp, true);
3338 	} else {
3339 		rtl_runtime_suspend_enable(tp, false);
3340 
3341 		switch (tp->version) {
3342 		case RTL_VER_03:
3343 		case RTL_VER_04:
3344 			break;
3345 		case RTL_VER_05:
3346 		case RTL_VER_06:
3347 		default:
3348 			r8153_u2p3en(tp, true);
3349 			break;
3350 		}
3351 
3352 		r8153_u1u2en(tp, true);
3353 	}
3354 }
3355 
rtl8153b_runtime_enable(struct r8152 * tp,bool enable)3356 static void rtl8153b_runtime_enable(struct r8152 *tp, bool enable)
3357 {
3358 	if (enable) {
3359 		r8153_queue_wake(tp, true);
3360 		r8153b_u1u2en(tp, false);
3361 		r8153_u2p3en(tp, false);
3362 		rtl_runtime_suspend_enable(tp, true);
3363 		r8153b_ups_en(tp, true);
3364 	} else {
3365 		r8153b_ups_en(tp, false);
3366 		r8153_queue_wake(tp, false);
3367 		rtl_runtime_suspend_enable(tp, false);
3368 		if (tp->udev->speed != USB_SPEED_HIGH)
3369 			r8153b_u1u2en(tp, true);
3370 	}
3371 }
3372 
r8153_teredo_off(struct r8152 * tp)3373 static void r8153_teredo_off(struct r8152 *tp)
3374 {
3375 	u32 ocp_data;
3376 
3377 	switch (tp->version) {
3378 	case RTL_VER_01:
3379 	case RTL_VER_02:
3380 	case RTL_VER_03:
3381 	case RTL_VER_04:
3382 	case RTL_VER_05:
3383 	case RTL_VER_06:
3384 	case RTL_VER_07:
3385 		ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
3386 		ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK |
3387 			      OOB_TEREDO_EN);
3388 		ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
3389 		break;
3390 
3391 	case RTL_VER_08:
3392 	case RTL_VER_09:
3393 		/* The bit 0 ~ 7 are relative with teredo settings. They are
3394 		 * W1C (write 1 to clear), so set all 1 to disable it.
3395 		 */
3396 		ocp_write_byte(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, 0xff);
3397 		break;
3398 
3399 	default:
3400 		break;
3401 	}
3402 
3403 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE);
3404 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0);
3405 	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0);
3406 }
3407 
rtl_reset_bmu(struct r8152 * tp)3408 static void rtl_reset_bmu(struct r8152 *tp)
3409 {
3410 	u32 ocp_data;
3411 
3412 	ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_BMU_RESET);
3413 	ocp_data &= ~(BMU_RESET_EP_IN | BMU_RESET_EP_OUT);
3414 	ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
3415 	ocp_data |= BMU_RESET_EP_IN | BMU_RESET_EP_OUT;
3416 	ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
3417 }
3418 
3419 /* Clear the bp to stop the firmware before loading a new one */
rtl_clear_bp(struct r8152 * tp,u16 type)3420 static void rtl_clear_bp(struct r8152 *tp, u16 type)
3421 {
3422 	switch (tp->version) {
3423 	case RTL_VER_01:
3424 	case RTL_VER_02:
3425 	case RTL_VER_07:
3426 		break;
3427 	case RTL_VER_03:
3428 	case RTL_VER_04:
3429 	case RTL_VER_05:
3430 	case RTL_VER_06:
3431 		ocp_write_byte(tp, type, PLA_BP_EN, 0);
3432 		break;
3433 	case RTL_VER_08:
3434 	case RTL_VER_09:
3435 	default:
3436 		if (type == MCU_TYPE_USB) {
3437 			ocp_write_word(tp, MCU_TYPE_USB, USB_BP2_EN, 0);
3438 
3439 			ocp_write_word(tp, MCU_TYPE_USB, USB_BP_8, 0);
3440 			ocp_write_word(tp, MCU_TYPE_USB, USB_BP_9, 0);
3441 			ocp_write_word(tp, MCU_TYPE_USB, USB_BP_10, 0);
3442 			ocp_write_word(tp, MCU_TYPE_USB, USB_BP_11, 0);
3443 			ocp_write_word(tp, MCU_TYPE_USB, USB_BP_12, 0);
3444 			ocp_write_word(tp, MCU_TYPE_USB, USB_BP_13, 0);
3445 			ocp_write_word(tp, MCU_TYPE_USB, USB_BP_14, 0);
3446 			ocp_write_word(tp, MCU_TYPE_USB, USB_BP_15, 0);
3447 		} else {
3448 			ocp_write_byte(tp, MCU_TYPE_PLA, PLA_BP_EN, 0);
3449 		}
3450 		break;
3451 	}
3452 
3453 	ocp_write_word(tp, type, PLA_BP_0, 0);
3454 	ocp_write_word(tp, type, PLA_BP_1, 0);
3455 	ocp_write_word(tp, type, PLA_BP_2, 0);
3456 	ocp_write_word(tp, type, PLA_BP_3, 0);
3457 	ocp_write_word(tp, type, PLA_BP_4, 0);
3458 	ocp_write_word(tp, type, PLA_BP_5, 0);
3459 	ocp_write_word(tp, type, PLA_BP_6, 0);
3460 	ocp_write_word(tp, type, PLA_BP_7, 0);
3461 
3462 	/* wait 3 ms to make sure the firmware is stopped */
3463 	usleep_range(3000, 6000);
3464 	ocp_write_word(tp, type, PLA_BP_BA, 0);
3465 }
3466 
r8153_patch_request(struct r8152 * tp,bool request)3467 static int r8153_patch_request(struct r8152 *tp, bool request)
3468 {
3469 	u16 data;
3470 	int i;
3471 
3472 	data = ocp_reg_read(tp, OCP_PHY_PATCH_CMD);
3473 	if (request)
3474 		data |= PATCH_REQUEST;
3475 	else
3476 		data &= ~PATCH_REQUEST;
3477 	ocp_reg_write(tp, OCP_PHY_PATCH_CMD, data);
3478 
3479 	for (i = 0; request && i < 5000; i++) {
3480 		usleep_range(1000, 2000);
3481 		if (ocp_reg_read(tp, OCP_PHY_PATCH_STAT) & PATCH_READY)
3482 			break;
3483 	}
3484 
3485 	if (request && !(ocp_reg_read(tp, OCP_PHY_PATCH_STAT) & PATCH_READY)) {
3486 		netif_err(tp, drv, tp->netdev, "patch request fail\n");
3487 		r8153_patch_request(tp, false);
3488 		return -ETIME;
3489 	} else {
3490 		return 0;
3491 	}
3492 }
3493 
r8153_pre_ram_code(struct r8152 * tp,u16 key_addr,u16 patch_key)3494 static int r8153_pre_ram_code(struct r8152 *tp, u16 key_addr, u16 patch_key)
3495 {
3496 	if (r8153_patch_request(tp, true)) {
3497 		dev_err(&tp->intf->dev, "patch request fail\n");
3498 		return -ETIME;
3499 	}
3500 
3501 	sram_write(tp, key_addr, patch_key);
3502 	sram_write(tp, SRAM_PHY_LOCK, PHY_PATCH_LOCK);
3503 
3504 	return 0;
3505 }
3506 
r8153_post_ram_code(struct r8152 * tp,u16 key_addr)3507 static int r8153_post_ram_code(struct r8152 *tp, u16 key_addr)
3508 {
3509 	u16 data;
3510 
3511 	sram_write(tp, 0x0000, 0x0000);
3512 
3513 	data = ocp_reg_read(tp, OCP_PHY_LOCK);
3514 	data &= ~PATCH_LOCK;
3515 	ocp_reg_write(tp, OCP_PHY_LOCK, data);
3516 
3517 	sram_write(tp, key_addr, 0x0000);
3518 
3519 	r8153_patch_request(tp, false);
3520 
3521 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, tp->ocp_base);
3522 
3523 	return 0;
3524 }
3525 
rtl8152_is_fw_phy_nc_ok(struct r8152 * tp,struct fw_phy_nc * phy)3526 static bool rtl8152_is_fw_phy_nc_ok(struct r8152 *tp, struct fw_phy_nc *phy)
3527 {
3528 	u32 length;
3529 	u16 fw_offset, fw_reg, ba_reg, patch_en_addr, mode_reg, bp_start;
3530 	bool rc = false;
3531 
3532 	switch (tp->version) {
3533 	case RTL_VER_04:
3534 	case RTL_VER_05:
3535 	case RTL_VER_06:
3536 		fw_reg = 0xa014;
3537 		ba_reg = 0xa012;
3538 		patch_en_addr = 0xa01a;
3539 		mode_reg = 0xb820;
3540 		bp_start = 0xa000;
3541 		break;
3542 	default:
3543 		goto out;
3544 	}
3545 
3546 	fw_offset = __le16_to_cpu(phy->fw_offset);
3547 	if (fw_offset < sizeof(*phy)) {
3548 		dev_err(&tp->intf->dev, "fw_offset too small\n");
3549 		goto out;
3550 	}
3551 
3552 	length = __le32_to_cpu(phy->blk_hdr.length);
3553 	if (length < fw_offset) {
3554 		dev_err(&tp->intf->dev, "invalid fw_offset\n");
3555 		goto out;
3556 	}
3557 
3558 	length -= __le16_to_cpu(phy->fw_offset);
3559 	if (!length || (length & 1)) {
3560 		dev_err(&tp->intf->dev, "invalid block length\n");
3561 		goto out;
3562 	}
3563 
3564 	if (__le16_to_cpu(phy->fw_reg) != fw_reg) {
3565 		dev_err(&tp->intf->dev, "invalid register to load firmware\n");
3566 		goto out;
3567 	}
3568 
3569 	if (__le16_to_cpu(phy->ba_reg) != ba_reg) {
3570 		dev_err(&tp->intf->dev, "invalid base address register\n");
3571 		goto out;
3572 	}
3573 
3574 	if (__le16_to_cpu(phy->patch_en_addr) != patch_en_addr) {
3575 		dev_err(&tp->intf->dev,
3576 			"invalid patch mode enabled register\n");
3577 		goto out;
3578 	}
3579 
3580 	if (__le16_to_cpu(phy->mode_reg) != mode_reg) {
3581 		dev_err(&tp->intf->dev,
3582 			"invalid register to switch the mode\n");
3583 		goto out;
3584 	}
3585 
3586 	if (__le16_to_cpu(phy->bp_start) != bp_start) {
3587 		dev_err(&tp->intf->dev,
3588 			"invalid start register of break point\n");
3589 		goto out;
3590 	}
3591 
3592 	if (__le16_to_cpu(phy->bp_num) > 4) {
3593 		dev_err(&tp->intf->dev, "invalid break point number\n");
3594 		goto out;
3595 	}
3596 
3597 	rc = true;
3598 out:
3599 	return rc;
3600 }
3601 
rtl8152_is_fw_mac_ok(struct r8152 * tp,struct fw_mac * mac)3602 static bool rtl8152_is_fw_mac_ok(struct r8152 *tp, struct fw_mac *mac)
3603 {
3604 	u16 fw_reg, bp_ba_addr, bp_en_addr, bp_start, fw_offset;
3605 	bool rc = false;
3606 	u32 length, type;
3607 	int i, max_bp;
3608 
3609 	type = __le32_to_cpu(mac->blk_hdr.type);
3610 	if (type == RTL_FW_PLA) {
3611 		switch (tp->version) {
3612 		case RTL_VER_01:
3613 		case RTL_VER_02:
3614 		case RTL_VER_07:
3615 			fw_reg = 0xf800;
3616 			bp_ba_addr = PLA_BP_BA;
3617 			bp_en_addr = 0;
3618 			bp_start = PLA_BP_0;
3619 			max_bp = 8;
3620 			break;
3621 		case RTL_VER_03:
3622 		case RTL_VER_04:
3623 		case RTL_VER_05:
3624 		case RTL_VER_06:
3625 		case RTL_VER_08:
3626 		case RTL_VER_09:
3627 			fw_reg = 0xf800;
3628 			bp_ba_addr = PLA_BP_BA;
3629 			bp_en_addr = PLA_BP_EN;
3630 			bp_start = PLA_BP_0;
3631 			max_bp = 8;
3632 			break;
3633 		default:
3634 			goto out;
3635 		}
3636 	} else if (type == RTL_FW_USB) {
3637 		switch (tp->version) {
3638 		case RTL_VER_03:
3639 		case RTL_VER_04:
3640 		case RTL_VER_05:
3641 		case RTL_VER_06:
3642 			fw_reg = 0xf800;
3643 			bp_ba_addr = USB_BP_BA;
3644 			bp_en_addr = USB_BP_EN;
3645 			bp_start = USB_BP_0;
3646 			max_bp = 8;
3647 			break;
3648 		case RTL_VER_08:
3649 		case RTL_VER_09:
3650 			fw_reg = 0xe600;
3651 			bp_ba_addr = USB_BP_BA;
3652 			bp_en_addr = USB_BP2_EN;
3653 			bp_start = USB_BP_0;
3654 			max_bp = 16;
3655 			break;
3656 		case RTL_VER_01:
3657 		case RTL_VER_02:
3658 		case RTL_VER_07:
3659 		default:
3660 			goto out;
3661 		}
3662 	} else {
3663 		goto out;
3664 	}
3665 
3666 	fw_offset = __le16_to_cpu(mac->fw_offset);
3667 	if (fw_offset < sizeof(*mac)) {
3668 		dev_err(&tp->intf->dev, "fw_offset too small\n");
3669 		goto out;
3670 	}
3671 
3672 	length = __le32_to_cpu(mac->blk_hdr.length);
3673 	if (length < fw_offset) {
3674 		dev_err(&tp->intf->dev, "invalid fw_offset\n");
3675 		goto out;
3676 	}
3677 
3678 	length -= fw_offset;
3679 	if (length < 4 || (length & 3)) {
3680 		dev_err(&tp->intf->dev, "invalid block length\n");
3681 		goto out;
3682 	}
3683 
3684 	if (__le16_to_cpu(mac->fw_reg) != fw_reg) {
3685 		dev_err(&tp->intf->dev, "invalid register to load firmware\n");
3686 		goto out;
3687 	}
3688 
3689 	if (__le16_to_cpu(mac->bp_ba_addr) != bp_ba_addr) {
3690 		dev_err(&tp->intf->dev, "invalid base address register\n");
3691 		goto out;
3692 	}
3693 
3694 	if (__le16_to_cpu(mac->bp_en_addr) != bp_en_addr) {
3695 		dev_err(&tp->intf->dev, "invalid enabled mask register\n");
3696 		goto out;
3697 	}
3698 
3699 	if (__le16_to_cpu(mac->bp_start) != bp_start) {
3700 		dev_err(&tp->intf->dev,
3701 			"invalid start register of break point\n");
3702 		goto out;
3703 	}
3704 
3705 	if (__le16_to_cpu(mac->bp_num) > max_bp) {
3706 		dev_err(&tp->intf->dev, "invalid break point number\n");
3707 		goto out;
3708 	}
3709 
3710 	for (i = __le16_to_cpu(mac->bp_num); i < max_bp; i++) {
3711 		if (mac->bp[i]) {
3712 			dev_err(&tp->intf->dev, "unused bp%u is not zero\n", i);
3713 			goto out;
3714 		}
3715 	}
3716 
3717 	rc = true;
3718 out:
3719 	return rc;
3720 }
3721 
3722 /* Verify the checksum for the firmware file. It is calculated from the version
3723  * field to the end of the file. Compare the result with the checksum field to
3724  * make sure the file is correct.
3725  */
rtl8152_fw_verify_checksum(struct r8152 * tp,struct fw_header * fw_hdr,size_t size)3726 static long rtl8152_fw_verify_checksum(struct r8152 *tp,
3727 				       struct fw_header *fw_hdr, size_t size)
3728 {
3729 	unsigned char checksum[sizeof(fw_hdr->checksum)];
3730 	struct crypto_shash *alg;
3731 	struct shash_desc *sdesc;
3732 	size_t len;
3733 	long rc;
3734 
3735 	alg = crypto_alloc_shash("sha256", 0, 0);
3736 	if (IS_ERR(alg)) {
3737 		rc = PTR_ERR(alg);
3738 		goto out;
3739 	}
3740 
3741 	if (crypto_shash_digestsize(alg) != sizeof(fw_hdr->checksum)) {
3742 		rc = -EFAULT;
3743 		dev_err(&tp->intf->dev, "digestsize incorrect (%u)\n",
3744 			crypto_shash_digestsize(alg));
3745 		goto free_shash;
3746 	}
3747 
3748 	len = sizeof(*sdesc) + crypto_shash_descsize(alg);
3749 	sdesc = kmalloc(len, GFP_KERNEL);
3750 	if (!sdesc) {
3751 		rc = -ENOMEM;
3752 		goto free_shash;
3753 	}
3754 	sdesc->tfm = alg;
3755 
3756 	len = size - sizeof(fw_hdr->checksum);
3757 	rc = crypto_shash_digest(sdesc, fw_hdr->version, len, checksum);
3758 	kfree(sdesc);
3759 	if (rc)
3760 		goto free_shash;
3761 
3762 	if (memcmp(fw_hdr->checksum, checksum, sizeof(fw_hdr->checksum))) {
3763 		dev_err(&tp->intf->dev, "checksum fail\n");
3764 		rc = -EFAULT;
3765 	}
3766 
3767 free_shash:
3768 	crypto_free_shash(alg);
3769 out:
3770 	return rc;
3771 }
3772 
rtl8152_check_firmware(struct r8152 * tp,struct rtl_fw * rtl_fw)3773 static long rtl8152_check_firmware(struct r8152 *tp, struct rtl_fw *rtl_fw)
3774 {
3775 	const struct firmware *fw = rtl_fw->fw;
3776 	struct fw_header *fw_hdr = (struct fw_header *)fw->data;
3777 	struct fw_mac *pla = NULL, *usb = NULL;
3778 	struct fw_phy_patch_key *start = NULL;
3779 	struct fw_phy_nc *phy_nc = NULL;
3780 	struct fw_block *stop = NULL;
3781 	long ret = -EFAULT;
3782 	int i;
3783 
3784 	if (fw->size < sizeof(*fw_hdr)) {
3785 		dev_err(&tp->intf->dev, "file too small\n");
3786 		goto fail;
3787 	}
3788 
3789 	ret = rtl8152_fw_verify_checksum(tp, fw_hdr, fw->size);
3790 	if (ret)
3791 		goto fail;
3792 
3793 	ret = -EFAULT;
3794 
3795 	for (i = sizeof(*fw_hdr); i < fw->size;) {
3796 		struct fw_block *block = (struct fw_block *)&fw->data[i];
3797 		u32 type;
3798 
3799 		if ((i + sizeof(*block)) > fw->size)
3800 			goto fail;
3801 
3802 		type = __le32_to_cpu(block->type);
3803 		switch (type) {
3804 		case RTL_FW_END:
3805 			if (__le32_to_cpu(block->length) != sizeof(*block))
3806 				goto fail;
3807 			goto fw_end;
3808 		case RTL_FW_PLA:
3809 			if (pla) {
3810 				dev_err(&tp->intf->dev,
3811 					"multiple PLA firmware encountered");
3812 				goto fail;
3813 			}
3814 
3815 			pla = (struct fw_mac *)block;
3816 			if (!rtl8152_is_fw_mac_ok(tp, pla)) {
3817 				dev_err(&tp->intf->dev,
3818 					"check PLA firmware failed\n");
3819 				goto fail;
3820 			}
3821 			break;
3822 		case RTL_FW_USB:
3823 			if (usb) {
3824 				dev_err(&tp->intf->dev,
3825 					"multiple USB firmware encountered");
3826 				goto fail;
3827 			}
3828 
3829 			usb = (struct fw_mac *)block;
3830 			if (!rtl8152_is_fw_mac_ok(tp, usb)) {
3831 				dev_err(&tp->intf->dev,
3832 					"check USB firmware failed\n");
3833 				goto fail;
3834 			}
3835 			break;
3836 		case RTL_FW_PHY_START:
3837 			if (start || phy_nc || stop) {
3838 				dev_err(&tp->intf->dev,
3839 					"check PHY_START fail\n");
3840 				goto fail;
3841 			}
3842 
3843 			if (__le32_to_cpu(block->length) != sizeof(*start)) {
3844 				dev_err(&tp->intf->dev,
3845 					"Invalid length for PHY_START\n");
3846 				goto fail;
3847 			}
3848 
3849 			start = (struct fw_phy_patch_key *)block;
3850 			break;
3851 		case RTL_FW_PHY_STOP:
3852 			if (stop || !start) {
3853 				dev_err(&tp->intf->dev,
3854 					"Check PHY_STOP fail\n");
3855 				goto fail;
3856 			}
3857 
3858 			if (__le32_to_cpu(block->length) != sizeof(*block)) {
3859 				dev_err(&tp->intf->dev,
3860 					"Invalid length for PHY_STOP\n");
3861 				goto fail;
3862 			}
3863 
3864 			stop = block;
3865 			break;
3866 		case RTL_FW_PHY_NC:
3867 			if (!start || stop) {
3868 				dev_err(&tp->intf->dev,
3869 					"check PHY_NC fail\n");
3870 				goto fail;
3871 			}
3872 
3873 			if (phy_nc) {
3874 				dev_err(&tp->intf->dev,
3875 					"multiple PHY NC encountered\n");
3876 				goto fail;
3877 			}
3878 
3879 			phy_nc = (struct fw_phy_nc *)block;
3880 			if (!rtl8152_is_fw_phy_nc_ok(tp, phy_nc)) {
3881 				dev_err(&tp->intf->dev,
3882 					"check PHY NC firmware failed\n");
3883 				goto fail;
3884 			}
3885 
3886 			break;
3887 		default:
3888 			dev_warn(&tp->intf->dev, "Unknown type %u is found\n",
3889 				 type);
3890 			break;
3891 		}
3892 
3893 		/* next block */
3894 		i += ALIGN(__le32_to_cpu(block->length), 8);
3895 	}
3896 
3897 fw_end:
3898 	if ((phy_nc || start) && !stop) {
3899 		dev_err(&tp->intf->dev, "without PHY_STOP\n");
3900 		goto fail;
3901 	}
3902 
3903 	return 0;
3904 fail:
3905 	return ret;
3906 }
3907 
rtl8152_fw_phy_nc_apply(struct r8152 * tp,struct fw_phy_nc * phy)3908 static void rtl8152_fw_phy_nc_apply(struct r8152 *tp, struct fw_phy_nc *phy)
3909 {
3910 	u16 mode_reg, bp_index;
3911 	u32 length, i, num;
3912 	__le16 *data;
3913 
3914 	mode_reg = __le16_to_cpu(phy->mode_reg);
3915 	sram_write(tp, mode_reg, __le16_to_cpu(phy->mode_pre));
3916 	sram_write(tp, __le16_to_cpu(phy->ba_reg),
3917 		   __le16_to_cpu(phy->ba_data));
3918 
3919 	length = __le32_to_cpu(phy->blk_hdr.length);
3920 	length -= __le16_to_cpu(phy->fw_offset);
3921 	num = length / 2;
3922 	data = (__le16 *)((u8 *)phy + __le16_to_cpu(phy->fw_offset));
3923 
3924 	ocp_reg_write(tp, OCP_SRAM_ADDR, __le16_to_cpu(phy->fw_reg));
3925 	for (i = 0; i < num; i++)
3926 		ocp_reg_write(tp, OCP_SRAM_DATA, __le16_to_cpu(data[i]));
3927 
3928 	sram_write(tp, __le16_to_cpu(phy->patch_en_addr),
3929 		   __le16_to_cpu(phy->patch_en_value));
3930 
3931 	bp_index = __le16_to_cpu(phy->bp_start);
3932 	num = __le16_to_cpu(phy->bp_num);
3933 	for (i = 0; i < num; i++) {
3934 		sram_write(tp, bp_index, __le16_to_cpu(phy->bp[i]));
3935 		bp_index += 2;
3936 	}
3937 
3938 	sram_write(tp, mode_reg, __le16_to_cpu(phy->mode_post));
3939 
3940 	dev_dbg(&tp->intf->dev, "successfully applied %s\n", phy->info);
3941 }
3942 
rtl8152_fw_mac_apply(struct r8152 * tp,struct fw_mac * mac)3943 static void rtl8152_fw_mac_apply(struct r8152 *tp, struct fw_mac *mac)
3944 {
3945 	u16 bp_en_addr, bp_index, type, bp_num, fw_ver_reg;
3946 	u32 length;
3947 	u8 *data;
3948 	int i;
3949 
3950 	switch (__le32_to_cpu(mac->blk_hdr.type)) {
3951 	case RTL_FW_PLA:
3952 		type = MCU_TYPE_PLA;
3953 		break;
3954 	case RTL_FW_USB:
3955 		type = MCU_TYPE_USB;
3956 		break;
3957 	default:
3958 		return;
3959 	}
3960 
3961 	rtl_clear_bp(tp, type);
3962 
3963 	/* Enable backup/restore of MACDBG. This is required after clearing PLA
3964 	 * break points and before applying the PLA firmware.
3965 	 */
3966 	if (tp->version == RTL_VER_04 && type == MCU_TYPE_PLA &&
3967 	    !(ocp_read_word(tp, MCU_TYPE_PLA, PLA_MACDBG_POST) & DEBUG_OE)) {
3968 		ocp_write_word(tp, MCU_TYPE_PLA, PLA_MACDBG_PRE, DEBUG_LTSSM);
3969 		ocp_write_word(tp, MCU_TYPE_PLA, PLA_MACDBG_POST, DEBUG_LTSSM);
3970 	}
3971 
3972 	length = __le32_to_cpu(mac->blk_hdr.length);
3973 	length -= __le16_to_cpu(mac->fw_offset);
3974 
3975 	data = (u8 *)mac;
3976 	data += __le16_to_cpu(mac->fw_offset);
3977 
3978 	generic_ocp_write(tp, __le16_to_cpu(mac->fw_reg), 0xff, length, data,
3979 			  type);
3980 
3981 	ocp_write_word(tp, type, __le16_to_cpu(mac->bp_ba_addr),
3982 		       __le16_to_cpu(mac->bp_ba_value));
3983 
3984 	bp_index = __le16_to_cpu(mac->bp_start);
3985 	bp_num = __le16_to_cpu(mac->bp_num);
3986 	for (i = 0; i < bp_num; i++) {
3987 		ocp_write_word(tp, type, bp_index, __le16_to_cpu(mac->bp[i]));
3988 		bp_index += 2;
3989 	}
3990 
3991 	bp_en_addr = __le16_to_cpu(mac->bp_en_addr);
3992 	if (bp_en_addr)
3993 		ocp_write_word(tp, type, bp_en_addr,
3994 			       __le16_to_cpu(mac->bp_en_value));
3995 
3996 	fw_ver_reg = __le16_to_cpu(mac->fw_ver_reg);
3997 	if (fw_ver_reg)
3998 		ocp_write_byte(tp, MCU_TYPE_USB, fw_ver_reg,
3999 			       mac->fw_ver_data);
4000 
4001 	dev_dbg(&tp->intf->dev, "successfully applied %s\n", mac->info);
4002 }
4003 
rtl8152_apply_firmware(struct r8152 * tp)4004 static void rtl8152_apply_firmware(struct r8152 *tp)
4005 {
4006 	struct rtl_fw *rtl_fw = &tp->rtl_fw;
4007 	const struct firmware *fw;
4008 	struct fw_header *fw_hdr;
4009 	struct fw_phy_patch_key *key;
4010 	u16 key_addr = 0;
4011 	int i;
4012 
4013 	if (IS_ERR_OR_NULL(rtl_fw->fw))
4014 		return;
4015 
4016 	fw = rtl_fw->fw;
4017 	fw_hdr = (struct fw_header *)fw->data;
4018 
4019 	if (rtl_fw->pre_fw)
4020 		rtl_fw->pre_fw(tp);
4021 
4022 	for (i = offsetof(struct fw_header, blocks); i < fw->size;) {
4023 		struct fw_block *block = (struct fw_block *)&fw->data[i];
4024 
4025 		switch (__le32_to_cpu(block->type)) {
4026 		case RTL_FW_END:
4027 			goto post_fw;
4028 		case RTL_FW_PLA:
4029 		case RTL_FW_USB:
4030 			rtl8152_fw_mac_apply(tp, (struct fw_mac *)block);
4031 			break;
4032 		case RTL_FW_PHY_START:
4033 			key = (struct fw_phy_patch_key *)block;
4034 			key_addr = __le16_to_cpu(key->key_reg);
4035 			r8153_pre_ram_code(tp, key_addr,
4036 					   __le16_to_cpu(key->key_data));
4037 			break;
4038 		case RTL_FW_PHY_STOP:
4039 			WARN_ON(!key_addr);
4040 			r8153_post_ram_code(tp, key_addr);
4041 			break;
4042 		case RTL_FW_PHY_NC:
4043 			rtl8152_fw_phy_nc_apply(tp, (struct fw_phy_nc *)block);
4044 			break;
4045 		default:
4046 			break;
4047 		}
4048 
4049 		i += ALIGN(__le32_to_cpu(block->length), 8);
4050 	}
4051 
4052 post_fw:
4053 	if (rtl_fw->post_fw)
4054 		rtl_fw->post_fw(tp);
4055 
4056 	strscpy(rtl_fw->version, fw_hdr->version, RTL_VER_SIZE);
4057 	dev_info(&tp->intf->dev, "load %s successfully\n", rtl_fw->version);
4058 }
4059 
rtl8152_release_firmware(struct r8152 * tp)4060 static void rtl8152_release_firmware(struct r8152 *tp)
4061 {
4062 	struct rtl_fw *rtl_fw = &tp->rtl_fw;
4063 
4064 	if (!IS_ERR_OR_NULL(rtl_fw->fw)) {
4065 		release_firmware(rtl_fw->fw);
4066 		rtl_fw->fw = NULL;
4067 	}
4068 }
4069 
rtl8152_request_firmware(struct r8152 * tp)4070 static int rtl8152_request_firmware(struct r8152 *tp)
4071 {
4072 	struct rtl_fw *rtl_fw = &tp->rtl_fw;
4073 	long rc;
4074 
4075 	if (rtl_fw->fw || !rtl_fw->fw_name) {
4076 		dev_info(&tp->intf->dev, "skip request firmware\n");
4077 		rc = 0;
4078 		goto result;
4079 	}
4080 
4081 	rc = request_firmware(&rtl_fw->fw, rtl_fw->fw_name, &tp->intf->dev);
4082 	if (rc < 0)
4083 		goto result;
4084 
4085 	rc = rtl8152_check_firmware(tp, rtl_fw);
4086 	if (rc < 0)
4087 		release_firmware(rtl_fw->fw);
4088 
4089 result:
4090 	if (rc) {
4091 		rtl_fw->fw = ERR_PTR(rc);
4092 
4093 		dev_warn(&tp->intf->dev,
4094 			 "unable to load firmware patch %s (%ld)\n",
4095 			 rtl_fw->fw_name, rc);
4096 	}
4097 
4098 	return rc;
4099 }
4100 
r8152_aldps_en(struct r8152 * tp,bool enable)4101 static void r8152_aldps_en(struct r8152 *tp, bool enable)
4102 {
4103 	if (enable) {
4104 		ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS |
4105 						    LINKENA | DIS_SDSAVE);
4106 	} else {
4107 		ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA |
4108 						    DIS_SDSAVE);
4109 		msleep(20);
4110 	}
4111 }
4112 
r8152_mmd_indirect(struct r8152 * tp,u16 dev,u16 reg)4113 static inline void r8152_mmd_indirect(struct r8152 *tp, u16 dev, u16 reg)
4114 {
4115 	ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | dev);
4116 	ocp_reg_write(tp, OCP_EEE_DATA, reg);
4117 	ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | dev);
4118 }
4119 
r8152_mmd_read(struct r8152 * tp,u16 dev,u16 reg)4120 static u16 r8152_mmd_read(struct r8152 *tp, u16 dev, u16 reg)
4121 {
4122 	u16 data;
4123 
4124 	r8152_mmd_indirect(tp, dev, reg);
4125 	data = ocp_reg_read(tp, OCP_EEE_DATA);
4126 	ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
4127 
4128 	return data;
4129 }
4130 
r8152_mmd_write(struct r8152 * tp,u16 dev,u16 reg,u16 data)4131 static void r8152_mmd_write(struct r8152 *tp, u16 dev, u16 reg, u16 data)
4132 {
4133 	r8152_mmd_indirect(tp, dev, reg);
4134 	ocp_reg_write(tp, OCP_EEE_DATA, data);
4135 	ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
4136 }
4137 
r8152_eee_en(struct r8152 * tp,bool enable)4138 static void r8152_eee_en(struct r8152 *tp, bool enable)
4139 {
4140 	u16 config1, config2, config3;
4141 	u32 ocp_data;
4142 
4143 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
4144 	config1 = ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask;
4145 	config2 = ocp_reg_read(tp, OCP_EEE_CONFIG2);
4146 	config3 = ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask;
4147 
4148 	if (enable) {
4149 		ocp_data |= EEE_RX_EN | EEE_TX_EN;
4150 		config1 |= EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN;
4151 		config1 |= sd_rise_time(1);
4152 		config2 |= RG_DACQUIET_EN | RG_LDVQUIET_EN;
4153 		config3 |= fast_snr(42);
4154 	} else {
4155 		ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
4156 		config1 &= ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN |
4157 			     RX_QUIET_EN);
4158 		config1 |= sd_rise_time(7);
4159 		config2 &= ~(RG_DACQUIET_EN | RG_LDVQUIET_EN);
4160 		config3 |= fast_snr(511);
4161 	}
4162 
4163 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
4164 	ocp_reg_write(tp, OCP_EEE_CONFIG1, config1);
4165 	ocp_reg_write(tp, OCP_EEE_CONFIG2, config2);
4166 	ocp_reg_write(tp, OCP_EEE_CONFIG3, config3);
4167 }
4168 
r8153_eee_en(struct r8152 * tp,bool enable)4169 static void r8153_eee_en(struct r8152 *tp, bool enable)
4170 {
4171 	u32 ocp_data;
4172 	u16 config;
4173 
4174 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
4175 	config = ocp_reg_read(tp, OCP_EEE_CFG);
4176 
4177 	if (enable) {
4178 		ocp_data |= EEE_RX_EN | EEE_TX_EN;
4179 		config |= EEE10_EN;
4180 	} else {
4181 		ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
4182 		config &= ~EEE10_EN;
4183 	}
4184 
4185 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
4186 	ocp_reg_write(tp, OCP_EEE_CFG, config);
4187 
4188 	tp->ups_info.eee = enable;
4189 }
4190 
rtl_eee_enable(struct r8152 * tp,bool enable)4191 static void rtl_eee_enable(struct r8152 *tp, bool enable)
4192 {
4193 	switch (tp->version) {
4194 	case RTL_VER_01:
4195 	case RTL_VER_02:
4196 	case RTL_VER_07:
4197 		if (enable) {
4198 			r8152_eee_en(tp, true);
4199 			r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV,
4200 					tp->eee_adv);
4201 		} else {
4202 			r8152_eee_en(tp, false);
4203 			r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0);
4204 		}
4205 		break;
4206 	case RTL_VER_03:
4207 	case RTL_VER_04:
4208 	case RTL_VER_05:
4209 	case RTL_VER_06:
4210 	case RTL_VER_08:
4211 	case RTL_VER_09:
4212 		if (enable) {
4213 			r8153_eee_en(tp, true);
4214 			ocp_reg_write(tp, OCP_EEE_ADV, tp->eee_adv);
4215 		} else {
4216 			r8153_eee_en(tp, false);
4217 			ocp_reg_write(tp, OCP_EEE_ADV, 0);
4218 		}
4219 		break;
4220 	default:
4221 		break;
4222 	}
4223 }
4224 
r8152b_enable_fc(struct r8152 * tp)4225 static void r8152b_enable_fc(struct r8152 *tp)
4226 {
4227 	u16 anar;
4228 
4229 	anar = r8152_mdio_read(tp, MII_ADVERTISE);
4230 	anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4231 	r8152_mdio_write(tp, MII_ADVERTISE, anar);
4232 
4233 	tp->ups_info.flow_control = true;
4234 }
4235 
rtl8152_disable(struct r8152 * tp)4236 static void rtl8152_disable(struct r8152 *tp)
4237 {
4238 	r8152_aldps_en(tp, false);
4239 	rtl_disable(tp);
4240 	r8152_aldps_en(tp, true);
4241 }
4242 
r8152b_hw_phy_cfg(struct r8152 * tp)4243 static void r8152b_hw_phy_cfg(struct r8152 *tp)
4244 {
4245 	rtl8152_apply_firmware(tp);
4246 	rtl_eee_enable(tp, tp->eee_en);
4247 	r8152_aldps_en(tp, true);
4248 	r8152b_enable_fc(tp);
4249 
4250 	set_bit(PHY_RESET, &tp->flags);
4251 }
4252 
wait_oob_link_list_ready(struct r8152 * tp)4253 static void wait_oob_link_list_ready(struct r8152 *tp)
4254 {
4255 	u32 ocp_data;
4256 	int i;
4257 
4258 	for (i = 0; i < 1000; i++) {
4259 		ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
4260 		if (ocp_data & LINK_LIST_READY)
4261 			break;
4262 		usleep_range(1000, 2000);
4263 	}
4264 }
4265 
r8152b_exit_oob(struct r8152 * tp)4266 static void r8152b_exit_oob(struct r8152 *tp)
4267 {
4268 	u32 ocp_data;
4269 
4270 	ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
4271 	ocp_data &= ~RCR_ACPT_ALL;
4272 	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
4273 
4274 	rxdy_gated_en(tp, true);
4275 	r8153_teredo_off(tp);
4276 	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
4277 	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00);
4278 
4279 	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
4280 	ocp_data &= ~NOW_IS_OOB;
4281 	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
4282 
4283 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
4284 	ocp_data &= ~MCU_BORW_EN;
4285 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
4286 
4287 	wait_oob_link_list_ready(tp);
4288 
4289 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
4290 	ocp_data |= RE_INIT_LL;
4291 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
4292 
4293 	wait_oob_link_list_ready(tp);
4294 
4295 	rtl8152_nic_reset(tp);
4296 
4297 	/* rx share fifo credit full threshold */
4298 	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
4299 
4300 	if (tp->udev->speed == USB_SPEED_FULL ||
4301 	    tp->udev->speed == USB_SPEED_LOW) {
4302 		/* rx share fifo credit near full threshold */
4303 		ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
4304 				RXFIFO_THR2_FULL);
4305 		ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
4306 				RXFIFO_THR3_FULL);
4307 	} else {
4308 		/* rx share fifo credit near full threshold */
4309 		ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
4310 				RXFIFO_THR2_HIGH);
4311 		ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
4312 				RXFIFO_THR3_HIGH);
4313 	}
4314 
4315 	/* TX share fifo free credit full threshold */
4316 	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL);
4317 
4318 	ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD);
4319 	ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH);
4320 	ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA,
4321 			TEST_MODE_DISABLE | TX_SIZE_ADJUST1);
4322 
4323 	rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
4324 
4325 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
4326 
4327 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
4328 	ocp_data |= TCR0_AUTO_FIFO;
4329 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
4330 }
4331 
r8152b_enter_oob(struct r8152 * tp)4332 static void r8152b_enter_oob(struct r8152 *tp)
4333 {
4334 	u32 ocp_data;
4335 
4336 	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
4337 	ocp_data &= ~NOW_IS_OOB;
4338 	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
4339 
4340 	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
4341 	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
4342 	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
4343 
4344 	rtl_disable(tp);
4345 
4346 	wait_oob_link_list_ready(tp);
4347 
4348 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
4349 	ocp_data |= RE_INIT_LL;
4350 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
4351 
4352 	wait_oob_link_list_ready(tp);
4353 
4354 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
4355 
4356 	rtl_rx_vlan_en(tp, true);
4357 
4358 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BDC_CR);
4359 	ocp_data |= ALDPS_PROXY_MODE;
4360 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_BDC_CR, ocp_data);
4361 
4362 	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
4363 	ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
4364 	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
4365 
4366 	rxdy_gated_en(tp, false);
4367 
4368 	ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
4369 	ocp_data |= RCR_APM | RCR_AM | RCR_AB;
4370 	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
4371 }
4372 
r8153_pre_firmware_1(struct r8152 * tp)4373 static int r8153_pre_firmware_1(struct r8152 *tp)
4374 {
4375 	int i;
4376 
4377 	/* Wait till the WTD timer is ready. It would take at most 104 ms. */
4378 	for (i = 0; i < 104; i++) {
4379 		u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_WDT1_CTRL);
4380 
4381 		if (!(ocp_data & WTD1_EN))
4382 			break;
4383 		usleep_range(1000, 2000);
4384 	}
4385 
4386 	return 0;
4387 }
4388 
r8153_post_firmware_1(struct r8152 * tp)4389 static int r8153_post_firmware_1(struct r8152 *tp)
4390 {
4391 	/* set USB_BP_4 to support USB_SPEED_SUPER only */
4392 	if (ocp_read_byte(tp, MCU_TYPE_USB, USB_CSTMR) & FORCE_SUPER)
4393 		ocp_write_word(tp, MCU_TYPE_USB, USB_BP_4, BP4_SUPER_ONLY);
4394 
4395 	/* reset UPHY timer to 36 ms */
4396 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_UPHY_TIMER, 36000 / 16);
4397 
4398 	return 0;
4399 }
4400 
r8153_pre_firmware_2(struct r8152 * tp)4401 static int r8153_pre_firmware_2(struct r8152 *tp)
4402 {
4403 	u32 ocp_data;
4404 
4405 	r8153_pre_firmware_1(tp);
4406 
4407 	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0);
4408 	ocp_data &= ~FW_FIX_SUSPEND;
4409 	ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0, ocp_data);
4410 
4411 	return 0;
4412 }
4413 
r8153_post_firmware_2(struct r8152 * tp)4414 static int r8153_post_firmware_2(struct r8152 *tp)
4415 {
4416 	u32 ocp_data;
4417 
4418 	/* enable bp0 if support USB_SPEED_SUPER only */
4419 	if (ocp_read_byte(tp, MCU_TYPE_USB, USB_CSTMR) & FORCE_SUPER) {
4420 		ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BP_EN);
4421 		ocp_data |= BIT(0);
4422 		ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_EN, ocp_data);
4423 	}
4424 
4425 	/* reset UPHY timer to 36 ms */
4426 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_UPHY_TIMER, 36000 / 16);
4427 
4428 	/* enable U3P3 check, set the counter to 4 */
4429 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, U3P3_CHECK_EN | 4);
4430 
4431 	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0);
4432 	ocp_data |= FW_FIX_SUSPEND;
4433 	ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0, ocp_data);
4434 
4435 	ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
4436 	ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
4437 	ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
4438 
4439 	return 0;
4440 }
4441 
r8153_post_firmware_3(struct r8152 * tp)4442 static int r8153_post_firmware_3(struct r8152 *tp)
4443 {
4444 	u32 ocp_data;
4445 
4446 	ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
4447 	ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
4448 	ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
4449 
4450 	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1);
4451 	ocp_data |= FW_IP_RESET_EN;
4452 	ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1, ocp_data);
4453 
4454 	return 0;
4455 }
4456 
r8153b_pre_firmware_1(struct r8152 * tp)4457 static int r8153b_pre_firmware_1(struct r8152 *tp)
4458 {
4459 	/* enable fc timer and set timer to 1 second. */
4460 	ocp_write_word(tp, MCU_TYPE_USB, USB_FC_TIMER,
4461 		       CTRL_TIMER_EN | (1000 / 8));
4462 
4463 	return 0;
4464 }
4465 
r8153b_post_firmware_1(struct r8152 * tp)4466 static int r8153b_post_firmware_1(struct r8152 *tp)
4467 {
4468 	u32 ocp_data;
4469 
4470 	/* enable bp0 for RTL8153-BND */
4471 	ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_1);
4472 	if (ocp_data & BND_MASK) {
4473 		ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BP_EN);
4474 		ocp_data |= BIT(0);
4475 		ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_EN, ocp_data);
4476 	}
4477 
4478 	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_CTRL);
4479 	ocp_data |= FLOW_CTRL_PATCH_OPT;
4480 	ocp_write_word(tp, MCU_TYPE_USB, USB_FW_CTRL, ocp_data);
4481 
4482 	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
4483 	ocp_data |= FC_PATCH_TASK;
4484 	ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
4485 
4486 	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1);
4487 	ocp_data |= FW_IP_RESET_EN;
4488 	ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1, ocp_data);
4489 
4490 	return 0;
4491 }
4492 
r8153_aldps_en(struct r8152 * tp,bool enable)4493 static void r8153_aldps_en(struct r8152 *tp, bool enable)
4494 {
4495 	u16 data;
4496 
4497 	data = ocp_reg_read(tp, OCP_POWER_CFG);
4498 	if (enable) {
4499 		data |= EN_ALDPS;
4500 		ocp_reg_write(tp, OCP_POWER_CFG, data);
4501 	} else {
4502 		int i;
4503 
4504 		data &= ~EN_ALDPS;
4505 		ocp_reg_write(tp, OCP_POWER_CFG, data);
4506 		for (i = 0; i < 20; i++) {
4507 			usleep_range(1000, 2000);
4508 			if (ocp_read_word(tp, MCU_TYPE_PLA, 0xe000) & 0x0100)
4509 				break;
4510 		}
4511 	}
4512 
4513 	tp->ups_info.aldps = enable;
4514 }
4515 
r8153_hw_phy_cfg(struct r8152 * tp)4516 static void r8153_hw_phy_cfg(struct r8152 *tp)
4517 {
4518 	u32 ocp_data;
4519 	u16 data;
4520 
4521 	/* disable ALDPS before updating the PHY parameters */
4522 	r8153_aldps_en(tp, false);
4523 
4524 	/* disable EEE before updating the PHY parameters */
4525 	rtl_eee_enable(tp, false);
4526 
4527 	rtl8152_apply_firmware(tp);
4528 
4529 	if (tp->version == RTL_VER_03) {
4530 		data = ocp_reg_read(tp, OCP_EEE_CFG);
4531 		data &= ~CTAP_SHORT_EN;
4532 		ocp_reg_write(tp, OCP_EEE_CFG, data);
4533 	}
4534 
4535 	data = ocp_reg_read(tp, OCP_POWER_CFG);
4536 	data |= EEE_CLKDIV_EN;
4537 	ocp_reg_write(tp, OCP_POWER_CFG, data);
4538 
4539 	data = ocp_reg_read(tp, OCP_DOWN_SPEED);
4540 	data |= EN_10M_BGOFF;
4541 	ocp_reg_write(tp, OCP_DOWN_SPEED, data);
4542 	data = ocp_reg_read(tp, OCP_POWER_CFG);
4543 	data |= EN_10M_PLLOFF;
4544 	ocp_reg_write(tp, OCP_POWER_CFG, data);
4545 	sram_write(tp, SRAM_IMPEDANCE, 0x0b13);
4546 
4547 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
4548 	ocp_data |= PFM_PWM_SWITCH;
4549 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
4550 
4551 	/* Enable LPF corner auto tune */
4552 	sram_write(tp, SRAM_LPF_CFG, 0xf70f);
4553 
4554 	/* Adjust 10M Amplitude */
4555 	sram_write(tp, SRAM_10M_AMP1, 0x00af);
4556 	sram_write(tp, SRAM_10M_AMP2, 0x0208);
4557 
4558 	if (tp->eee_en)
4559 		rtl_eee_enable(tp, true);
4560 
4561 	r8153_aldps_en(tp, true);
4562 	r8152b_enable_fc(tp);
4563 
4564 	switch (tp->version) {
4565 	case RTL_VER_03:
4566 	case RTL_VER_04:
4567 		break;
4568 	case RTL_VER_05:
4569 	case RTL_VER_06:
4570 	default:
4571 		r8153_u2p3en(tp, true);
4572 		break;
4573 	}
4574 
4575 	set_bit(PHY_RESET, &tp->flags);
4576 }
4577 
r8152_efuse_read(struct r8152 * tp,u8 addr)4578 static u32 r8152_efuse_read(struct r8152 *tp, u8 addr)
4579 {
4580 	u32 ocp_data;
4581 
4582 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD, EFUSE_READ_CMD | addr);
4583 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD);
4584 	ocp_data = (ocp_data & EFUSE_DATA_BIT16) << 9;	/* data of bit16 */
4585 	ocp_data |= ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_DATA);
4586 
4587 	return ocp_data;
4588 }
4589 
r8153b_hw_phy_cfg(struct r8152 * tp)4590 static void r8153b_hw_phy_cfg(struct r8152 *tp)
4591 {
4592 	u32 ocp_data;
4593 	u16 data;
4594 
4595 	/* disable ALDPS before updating the PHY parameters */
4596 	r8153_aldps_en(tp, false);
4597 
4598 	/* disable EEE before updating the PHY parameters */
4599 	rtl_eee_enable(tp, false);
4600 
4601 	rtl8152_apply_firmware(tp);
4602 
4603 	r8153b_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags));
4604 
4605 	data = sram_read(tp, SRAM_GREEN_CFG);
4606 	data |= R_TUNE_EN;
4607 	sram_write(tp, SRAM_GREEN_CFG, data);
4608 	data = ocp_reg_read(tp, OCP_NCTL_CFG);
4609 	data |= PGA_RETURN_EN;
4610 	ocp_reg_write(tp, OCP_NCTL_CFG, data);
4611 
4612 	/* ADC Bias Calibration:
4613 	 * read efuse offset 0x7d to get a 17-bit data. Remove the dummy/fake
4614 	 * bit (bit3) to rebuild the real 16-bit data. Write the data to the
4615 	 * ADC ioffset.
4616 	 */
4617 	ocp_data = r8152_efuse_read(tp, 0x7d);
4618 	data = (u16)(((ocp_data & 0x1fff0) >> 1) | (ocp_data & 0x7));
4619 	if (data != 0xffff)
4620 		ocp_reg_write(tp, OCP_ADC_IOFFSET, data);
4621 
4622 	/* ups mode tx-link-pulse timing adjustment:
4623 	 * rg_saw_cnt = OCP reg 0xC426 Bit[13:0]
4624 	 * swr_cnt_1ms_ini = 16000000 / rg_saw_cnt
4625 	 */
4626 	ocp_data = ocp_reg_read(tp, 0xc426);
4627 	ocp_data &= 0x3fff;
4628 	if (ocp_data) {
4629 		u32 swr_cnt_1ms_ini;
4630 
4631 		swr_cnt_1ms_ini = (16000000 / ocp_data) & SAW_CNT_1MS_MASK;
4632 		ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CFG);
4633 		ocp_data = (ocp_data & ~SAW_CNT_1MS_MASK) | swr_cnt_1ms_ini;
4634 		ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CFG, ocp_data);
4635 	}
4636 
4637 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
4638 	ocp_data |= PFM_PWM_SWITCH;
4639 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
4640 
4641 	/* Advnace EEE */
4642 	if (!r8153_patch_request(tp, true)) {
4643 		data = ocp_reg_read(tp, OCP_POWER_CFG);
4644 		data |= EEE_CLKDIV_EN;
4645 		ocp_reg_write(tp, OCP_POWER_CFG, data);
4646 		tp->ups_info.eee_ckdiv = true;
4647 
4648 		data = ocp_reg_read(tp, OCP_DOWN_SPEED);
4649 		data |= EN_EEE_CMODE | EN_EEE_1000 | EN_10M_CLKDIV;
4650 		ocp_reg_write(tp, OCP_DOWN_SPEED, data);
4651 		tp->ups_info.eee_cmod_lv = true;
4652 		tp->ups_info._10m_ckdiv = true;
4653 		tp->ups_info.eee_plloff_giga = true;
4654 
4655 		ocp_reg_write(tp, OCP_SYSCLK_CFG, 0);
4656 		ocp_reg_write(tp, OCP_SYSCLK_CFG, clk_div_expo(5));
4657 		tp->ups_info._250m_ckdiv = true;
4658 
4659 		r8153_patch_request(tp, false);
4660 	}
4661 
4662 	if (tp->eee_en)
4663 		rtl_eee_enable(tp, true);
4664 
4665 	r8153_aldps_en(tp, true);
4666 	r8152b_enable_fc(tp);
4667 
4668 	set_bit(PHY_RESET, &tp->flags);
4669 }
4670 
r8153_first_init(struct r8152 * tp)4671 static void r8153_first_init(struct r8152 *tp)
4672 {
4673 	u32 ocp_data;
4674 
4675 	rxdy_gated_en(tp, true);
4676 	r8153_teredo_off(tp);
4677 
4678 	ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
4679 	ocp_data &= ~RCR_ACPT_ALL;
4680 	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
4681 
4682 	rtl8152_nic_reset(tp);
4683 	rtl_reset_bmu(tp);
4684 
4685 	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
4686 	ocp_data &= ~NOW_IS_OOB;
4687 	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
4688 
4689 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
4690 	ocp_data &= ~MCU_BORW_EN;
4691 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
4692 
4693 	wait_oob_link_list_ready(tp);
4694 
4695 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
4696 	ocp_data |= RE_INIT_LL;
4697 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
4698 
4699 	wait_oob_link_list_ready(tp);
4700 
4701 	rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
4702 
4703 	ocp_data = tp->netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
4704 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data);
4705 	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO);
4706 
4707 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
4708 	ocp_data |= TCR0_AUTO_FIFO;
4709 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
4710 
4711 	rtl8152_nic_reset(tp);
4712 
4713 	/* rx share fifo credit full threshold */
4714 	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
4715 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);
4716 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);
4717 	/* TX share fifo free credit full threshold */
4718 	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
4719 }
4720 
r8153_enter_oob(struct r8152 * tp)4721 static void r8153_enter_oob(struct r8152 *tp)
4722 {
4723 	u32 ocp_data;
4724 
4725 	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
4726 	ocp_data &= ~NOW_IS_OOB;
4727 	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
4728 
4729 	rtl_disable(tp);
4730 	rtl_reset_bmu(tp);
4731 
4732 	wait_oob_link_list_ready(tp);
4733 
4734 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
4735 	ocp_data |= RE_INIT_LL;
4736 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
4737 
4738 	wait_oob_link_list_ready(tp);
4739 
4740 	ocp_data = tp->netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
4741 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data);
4742 
4743 	switch (tp->version) {
4744 	case RTL_VER_03:
4745 	case RTL_VER_04:
4746 	case RTL_VER_05:
4747 	case RTL_VER_06:
4748 		ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
4749 		ocp_data &= ~TEREDO_WAKE_MASK;
4750 		ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
4751 		break;
4752 
4753 	case RTL_VER_08:
4754 	case RTL_VER_09:
4755 		/* Clear teredo wake event. bit[15:8] is the teredo wakeup
4756 		 * type. Set it to zero. bits[7:0] are the W1C bits about
4757 		 * the events. Set them to all 1 to clear them.
4758 		 */
4759 		ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_WAKE_BASE, 0x00ff);
4760 		break;
4761 
4762 	default:
4763 		break;
4764 	}
4765 
4766 	rtl_rx_vlan_en(tp, true);
4767 
4768 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BDC_CR);
4769 	ocp_data |= ALDPS_PROXY_MODE;
4770 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_BDC_CR, ocp_data);
4771 
4772 	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
4773 	ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
4774 	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
4775 
4776 	rxdy_gated_en(tp, false);
4777 
4778 	ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
4779 	ocp_data |= RCR_APM | RCR_AM | RCR_AB;
4780 	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
4781 }
4782 
rtl8153_disable(struct r8152 * tp)4783 static void rtl8153_disable(struct r8152 *tp)
4784 {
4785 	r8153_aldps_en(tp, false);
4786 	rtl_disable(tp);
4787 	rtl_reset_bmu(tp);
4788 	r8153_aldps_en(tp, true);
4789 }
4790 
rtl8152_set_speed(struct r8152 * tp,u8 autoneg,u32 speed,u8 duplex,u32 advertising)4791 static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u32 speed, u8 duplex,
4792 			     u32 advertising)
4793 {
4794 	u16 bmcr;
4795 	int ret = 0;
4796 
4797 	if (autoneg == AUTONEG_DISABLE) {
4798 		if (duplex != DUPLEX_HALF && duplex != DUPLEX_FULL)
4799 			return -EINVAL;
4800 
4801 		switch (speed) {
4802 		case SPEED_10:
4803 			bmcr = BMCR_SPEED10;
4804 			if (duplex == DUPLEX_FULL) {
4805 				bmcr |= BMCR_FULLDPLX;
4806 				tp->ups_info.speed_duplex = FORCE_10M_FULL;
4807 			} else {
4808 				tp->ups_info.speed_duplex = FORCE_10M_HALF;
4809 			}
4810 			break;
4811 		case SPEED_100:
4812 			bmcr = BMCR_SPEED100;
4813 			if (duplex == DUPLEX_FULL) {
4814 				bmcr |= BMCR_FULLDPLX;
4815 				tp->ups_info.speed_duplex = FORCE_100M_FULL;
4816 			} else {
4817 				tp->ups_info.speed_duplex = FORCE_100M_HALF;
4818 			}
4819 			break;
4820 		case SPEED_1000:
4821 			if (tp->mii.supports_gmii) {
4822 				bmcr = BMCR_SPEED1000 | BMCR_FULLDPLX;
4823 				tp->ups_info.speed_duplex = NWAY_1000M_FULL;
4824 				break;
4825 			}
4826 			fallthrough;
4827 		default:
4828 			ret = -EINVAL;
4829 			goto out;
4830 		}
4831 
4832 		if (duplex == DUPLEX_FULL)
4833 			tp->mii.full_duplex = 1;
4834 		else
4835 			tp->mii.full_duplex = 0;
4836 
4837 		tp->mii.force_media = 1;
4838 	} else {
4839 		u16 anar, tmp1;
4840 		u32 support;
4841 
4842 		support = RTL_ADVERTISED_10_HALF | RTL_ADVERTISED_10_FULL |
4843 			  RTL_ADVERTISED_100_HALF | RTL_ADVERTISED_100_FULL;
4844 
4845 		if (tp->mii.supports_gmii)
4846 			support |= RTL_ADVERTISED_1000_FULL;
4847 
4848 		if (!(advertising & support))
4849 			return -EINVAL;
4850 
4851 		anar = r8152_mdio_read(tp, MII_ADVERTISE);
4852 		tmp1 = anar & ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
4853 				ADVERTISE_100HALF | ADVERTISE_100FULL);
4854 		if (advertising & RTL_ADVERTISED_10_HALF) {
4855 			tmp1 |= ADVERTISE_10HALF;
4856 			tp->ups_info.speed_duplex = NWAY_10M_HALF;
4857 		}
4858 		if (advertising & RTL_ADVERTISED_10_FULL) {
4859 			tmp1 |= ADVERTISE_10FULL;
4860 			tp->ups_info.speed_duplex = NWAY_10M_FULL;
4861 		}
4862 
4863 		if (advertising & RTL_ADVERTISED_100_HALF) {
4864 			tmp1 |= ADVERTISE_100HALF;
4865 			tp->ups_info.speed_duplex = NWAY_100M_HALF;
4866 		}
4867 		if (advertising & RTL_ADVERTISED_100_FULL) {
4868 			tmp1 |= ADVERTISE_100FULL;
4869 			tp->ups_info.speed_duplex = NWAY_100M_FULL;
4870 		}
4871 
4872 		if (anar != tmp1) {
4873 			r8152_mdio_write(tp, MII_ADVERTISE, tmp1);
4874 			tp->mii.advertising = tmp1;
4875 		}
4876 
4877 		if (tp->mii.supports_gmii) {
4878 			u16 gbcr;
4879 
4880 			gbcr = r8152_mdio_read(tp, MII_CTRL1000);
4881 			tmp1 = gbcr & ~(ADVERTISE_1000FULL |
4882 					ADVERTISE_1000HALF);
4883 
4884 			if (advertising & RTL_ADVERTISED_1000_FULL) {
4885 				tmp1 |= ADVERTISE_1000FULL;
4886 				tp->ups_info.speed_duplex = NWAY_1000M_FULL;
4887 			}
4888 
4889 			if (gbcr != tmp1)
4890 				r8152_mdio_write(tp, MII_CTRL1000, tmp1);
4891 		}
4892 
4893 		bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
4894 
4895 		tp->mii.force_media = 0;
4896 	}
4897 
4898 	if (test_and_clear_bit(PHY_RESET, &tp->flags))
4899 		bmcr |= BMCR_RESET;
4900 
4901 	r8152_mdio_write(tp, MII_BMCR, bmcr);
4902 
4903 	if (bmcr & BMCR_RESET) {
4904 		int i;
4905 
4906 		for (i = 0; i < 50; i++) {
4907 			msleep(20);
4908 			if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
4909 				break;
4910 		}
4911 	}
4912 
4913 out:
4914 	return ret;
4915 }
4916 
rtl8152_up(struct r8152 * tp)4917 static void rtl8152_up(struct r8152 *tp)
4918 {
4919 	if (test_bit(RTL8152_UNPLUG, &tp->flags))
4920 		return;
4921 
4922 	r8152_aldps_en(tp, false);
4923 	r8152b_exit_oob(tp);
4924 	r8152_aldps_en(tp, true);
4925 }
4926 
rtl8152_down(struct r8152 * tp)4927 static void rtl8152_down(struct r8152 *tp)
4928 {
4929 	if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
4930 		rtl_drop_queued_tx(tp);
4931 		return;
4932 	}
4933 
4934 	r8152_power_cut_en(tp, false);
4935 	r8152_aldps_en(tp, false);
4936 	r8152b_enter_oob(tp);
4937 	r8152_aldps_en(tp, true);
4938 }
4939 
rtl8153_up(struct r8152 * tp)4940 static void rtl8153_up(struct r8152 *tp)
4941 {
4942 	u32 ocp_data;
4943 
4944 	if (test_bit(RTL8152_UNPLUG, &tp->flags))
4945 		return;
4946 
4947 	r8153_u1u2en(tp, false);
4948 	r8153_u2p3en(tp, false);
4949 	r8153_aldps_en(tp, false);
4950 	r8153_first_init(tp);
4951 
4952 	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6);
4953 	ocp_data |= LANWAKE_CLR_EN;
4954 	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6, ocp_data);
4955 
4956 	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG);
4957 	ocp_data &= ~LANWAKE_PIN;
4958 	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG, ocp_data);
4959 
4960 	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK1);
4961 	ocp_data &= ~DELAY_PHY_PWR_CHG;
4962 	ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK1, ocp_data);
4963 
4964 	r8153_aldps_en(tp, true);
4965 
4966 	switch (tp->version) {
4967 	case RTL_VER_03:
4968 	case RTL_VER_04:
4969 		break;
4970 	case RTL_VER_05:
4971 	case RTL_VER_06:
4972 	default:
4973 		r8153_u2p3en(tp, true);
4974 		break;
4975 	}
4976 
4977 	r8153_u1u2en(tp, true);
4978 }
4979 
rtl8153_down(struct r8152 * tp)4980 static void rtl8153_down(struct r8152 *tp)
4981 {
4982 	u32 ocp_data;
4983 
4984 	if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
4985 		rtl_drop_queued_tx(tp);
4986 		return;
4987 	}
4988 
4989 	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6);
4990 	ocp_data &= ~LANWAKE_CLR_EN;
4991 	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6, ocp_data);
4992 
4993 	r8153_u1u2en(tp, false);
4994 	r8153_u2p3en(tp, false);
4995 	r8153_power_cut_en(tp, false);
4996 	r8153_aldps_en(tp, false);
4997 	r8153_enter_oob(tp);
4998 	r8153_aldps_en(tp, true);
4999 }
5000 
rtl8153b_up(struct r8152 * tp)5001 static void rtl8153b_up(struct r8152 *tp)
5002 {
5003 	u32 ocp_data;
5004 
5005 	if (test_bit(RTL8152_UNPLUG, &tp->flags))
5006 		return;
5007 
5008 	r8153b_u1u2en(tp, false);
5009 	r8153_u2p3en(tp, false);
5010 	r8153_aldps_en(tp, false);
5011 
5012 	r8153_first_init(tp);
5013 	ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_B);
5014 
5015 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
5016 	ocp_data &= ~PLA_MCU_SPDWN_EN;
5017 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
5018 
5019 	r8153_aldps_en(tp, true);
5020 
5021 	if (tp->udev->speed != USB_SPEED_HIGH)
5022 		r8153b_u1u2en(tp, true);
5023 }
5024 
rtl8153b_down(struct r8152 * tp)5025 static void rtl8153b_down(struct r8152 *tp)
5026 {
5027 	u32 ocp_data;
5028 
5029 	if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
5030 		rtl_drop_queued_tx(tp);
5031 		return;
5032 	}
5033 
5034 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
5035 	ocp_data |= PLA_MCU_SPDWN_EN;
5036 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
5037 
5038 	r8153b_u1u2en(tp, false);
5039 	r8153_u2p3en(tp, false);
5040 	r8153b_power_cut_en(tp, false);
5041 	r8153_aldps_en(tp, false);
5042 	r8153_enter_oob(tp);
5043 	r8153_aldps_en(tp, true);
5044 }
5045 
rtl8152_in_nway(struct r8152 * tp)5046 static bool rtl8152_in_nway(struct r8152 *tp)
5047 {
5048 	u16 nway_state;
5049 
5050 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, 0x2000);
5051 	tp->ocp_base = 0x2000;
5052 	ocp_write_byte(tp, MCU_TYPE_PLA, 0xb014, 0x4c);		/* phy state */
5053 	nway_state = ocp_read_word(tp, MCU_TYPE_PLA, 0xb01a);
5054 
5055 	/* bit 15: TXDIS_STATE, bit 14: ABD_STATE */
5056 	if (nway_state & 0xc000)
5057 		return false;
5058 	else
5059 		return true;
5060 }
5061 
rtl8153_in_nway(struct r8152 * tp)5062 static bool rtl8153_in_nway(struct r8152 *tp)
5063 {
5064 	u16 phy_state = ocp_reg_read(tp, OCP_PHY_STATE) & 0xff;
5065 
5066 	if (phy_state == TXDIS_STATE || phy_state == ABD_STATE)
5067 		return false;
5068 	else
5069 		return true;
5070 }
5071 
set_carrier(struct r8152 * tp)5072 static void set_carrier(struct r8152 *tp)
5073 {
5074 	struct net_device *netdev = tp->netdev;
5075 	struct napi_struct *napi = &tp->napi;
5076 	u8 speed;
5077 
5078 	speed = rtl8152_get_speed(tp);
5079 
5080 	if (speed & LINK_STATUS) {
5081 		if (!netif_carrier_ok(netdev)) {
5082 			tp->rtl_ops.enable(tp);
5083 			netif_stop_queue(netdev);
5084 			napi_disable(napi);
5085 			netif_carrier_on(netdev);
5086 			rtl_start_rx(tp);
5087 			clear_bit(RTL8152_SET_RX_MODE, &tp->flags);
5088 			_rtl8152_set_rx_mode(netdev);
5089 			napi_enable(&tp->napi);
5090 			netif_wake_queue(netdev);
5091 			netif_info(tp, link, netdev, "carrier on\n");
5092 		} else if (netif_queue_stopped(netdev) &&
5093 			   skb_queue_len(&tp->tx_queue) < tp->tx_qlen) {
5094 			netif_wake_queue(netdev);
5095 		}
5096 	} else {
5097 		if (netif_carrier_ok(netdev)) {
5098 			netif_carrier_off(netdev);
5099 			tasklet_disable(&tp->tx_tl);
5100 			napi_disable(napi);
5101 			tp->rtl_ops.disable(tp);
5102 			napi_enable(napi);
5103 			tasklet_enable(&tp->tx_tl);
5104 			netif_info(tp, link, netdev, "carrier off\n");
5105 		}
5106 	}
5107 }
5108 
rtl_work_func_t(struct work_struct * work)5109 static void rtl_work_func_t(struct work_struct *work)
5110 {
5111 	struct r8152 *tp = container_of(work, struct r8152, schedule.work);
5112 
5113 	/* If the device is unplugged or !netif_running(), the workqueue
5114 	 * doesn't need to wake the device, and could return directly.
5115 	 */
5116 	if (test_bit(RTL8152_UNPLUG, &tp->flags) || !netif_running(tp->netdev))
5117 		return;
5118 
5119 	if (usb_autopm_get_interface(tp->intf) < 0)
5120 		return;
5121 
5122 	if (!test_bit(WORK_ENABLE, &tp->flags))
5123 		goto out1;
5124 
5125 	if (!mutex_trylock(&tp->control)) {
5126 		schedule_delayed_work(&tp->schedule, 0);
5127 		goto out1;
5128 	}
5129 
5130 	if (test_and_clear_bit(RTL8152_LINK_CHG, &tp->flags))
5131 		set_carrier(tp);
5132 
5133 	if (test_and_clear_bit(RTL8152_SET_RX_MODE, &tp->flags))
5134 		_rtl8152_set_rx_mode(tp->netdev);
5135 
5136 	/* don't schedule tasket before linking */
5137 	if (test_and_clear_bit(SCHEDULE_TASKLET, &tp->flags) &&
5138 	    netif_carrier_ok(tp->netdev))
5139 		tasklet_schedule(&tp->tx_tl);
5140 
5141 	mutex_unlock(&tp->control);
5142 
5143 out1:
5144 	usb_autopm_put_interface(tp->intf);
5145 }
5146 
rtl_hw_phy_work_func_t(struct work_struct * work)5147 static void rtl_hw_phy_work_func_t(struct work_struct *work)
5148 {
5149 	struct r8152 *tp = container_of(work, struct r8152, hw_phy_work.work);
5150 
5151 	if (test_bit(RTL8152_UNPLUG, &tp->flags))
5152 		return;
5153 
5154 	if (usb_autopm_get_interface(tp->intf) < 0)
5155 		return;
5156 
5157 	mutex_lock(&tp->control);
5158 
5159 	if (rtl8152_request_firmware(tp) == -ENODEV && tp->rtl_fw.retry) {
5160 		tp->rtl_fw.retry = false;
5161 		tp->rtl_fw.fw = NULL;
5162 
5163 		/* Delay execution in case request_firmware() is not ready yet.
5164 		 */
5165 		queue_delayed_work(system_long_wq, &tp->hw_phy_work, HZ * 10);
5166 		goto ignore_once;
5167 	}
5168 
5169 	tp->rtl_ops.hw_phy_cfg(tp);
5170 
5171 	rtl8152_set_speed(tp, tp->autoneg, tp->speed, tp->duplex,
5172 			  tp->advertising);
5173 
5174 ignore_once:
5175 	mutex_unlock(&tp->control);
5176 
5177 	usb_autopm_put_interface(tp->intf);
5178 }
5179 
5180 #ifdef CONFIG_PM_SLEEP
rtl_notifier(struct notifier_block * nb,unsigned long action,void * data)5181 static int rtl_notifier(struct notifier_block *nb, unsigned long action,
5182 			void *data)
5183 {
5184 	struct r8152 *tp = container_of(nb, struct r8152, pm_notifier);
5185 
5186 	switch (action) {
5187 	case PM_HIBERNATION_PREPARE:
5188 	case PM_SUSPEND_PREPARE:
5189 		usb_autopm_get_interface(tp->intf);
5190 		break;
5191 
5192 	case PM_POST_HIBERNATION:
5193 	case PM_POST_SUSPEND:
5194 		usb_autopm_put_interface(tp->intf);
5195 		break;
5196 
5197 	case PM_POST_RESTORE:
5198 	case PM_RESTORE_PREPARE:
5199 	default:
5200 		break;
5201 	}
5202 
5203 	return NOTIFY_DONE;
5204 }
5205 #endif
5206 
rtl8152_open(struct net_device * netdev)5207 static int rtl8152_open(struct net_device *netdev)
5208 {
5209 	struct r8152 *tp = netdev_priv(netdev);
5210 	int res = 0;
5211 
5212 	if (work_busy(&tp->hw_phy_work.work) & WORK_BUSY_PENDING) {
5213 		cancel_delayed_work_sync(&tp->hw_phy_work);
5214 		rtl_hw_phy_work_func_t(&tp->hw_phy_work.work);
5215 	}
5216 
5217 	res = alloc_all_mem(tp);
5218 	if (res)
5219 		goto out;
5220 
5221 	res = usb_autopm_get_interface(tp->intf);
5222 	if (res < 0)
5223 		goto out_free;
5224 
5225 	mutex_lock(&tp->control);
5226 
5227 	tp->rtl_ops.up(tp);
5228 
5229 	netif_carrier_off(netdev);
5230 	netif_start_queue(netdev);
5231 	set_bit(WORK_ENABLE, &tp->flags);
5232 
5233 	res = usb_submit_urb(tp->intr_urb, GFP_KERNEL);
5234 	if (res) {
5235 		if (res == -ENODEV)
5236 			netif_device_detach(tp->netdev);
5237 		netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n",
5238 			   res);
5239 		goto out_unlock;
5240 	}
5241 	napi_enable(&tp->napi);
5242 	tasklet_enable(&tp->tx_tl);
5243 
5244 	mutex_unlock(&tp->control);
5245 
5246 	usb_autopm_put_interface(tp->intf);
5247 #ifdef CONFIG_PM_SLEEP
5248 	tp->pm_notifier.notifier_call = rtl_notifier;
5249 	register_pm_notifier(&tp->pm_notifier);
5250 #endif
5251 	return 0;
5252 
5253 out_unlock:
5254 	mutex_unlock(&tp->control);
5255 	usb_autopm_put_interface(tp->intf);
5256 out_free:
5257 	free_all_mem(tp);
5258 out:
5259 	return res;
5260 }
5261 
rtl8152_close(struct net_device * netdev)5262 static int rtl8152_close(struct net_device *netdev)
5263 {
5264 	struct r8152 *tp = netdev_priv(netdev);
5265 	int res = 0;
5266 
5267 #ifdef CONFIG_PM_SLEEP
5268 	unregister_pm_notifier(&tp->pm_notifier);
5269 #endif
5270 	tasklet_disable(&tp->tx_tl);
5271 	clear_bit(WORK_ENABLE, &tp->flags);
5272 	usb_kill_urb(tp->intr_urb);
5273 	cancel_delayed_work_sync(&tp->schedule);
5274 	napi_disable(&tp->napi);
5275 	netif_stop_queue(netdev);
5276 
5277 	res = usb_autopm_get_interface(tp->intf);
5278 	if (res < 0 || test_bit(RTL8152_UNPLUG, &tp->flags)) {
5279 		rtl_drop_queued_tx(tp);
5280 		rtl_stop_rx(tp);
5281 	} else {
5282 		mutex_lock(&tp->control);
5283 
5284 		tp->rtl_ops.down(tp);
5285 
5286 		mutex_unlock(&tp->control);
5287 	}
5288 
5289 	if (!res)
5290 		usb_autopm_put_interface(tp->intf);
5291 
5292 	free_all_mem(tp);
5293 
5294 	return res;
5295 }
5296 
rtl_tally_reset(struct r8152 * tp)5297 static void rtl_tally_reset(struct r8152 *tp)
5298 {
5299 	u32 ocp_data;
5300 
5301 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY);
5302 	ocp_data |= TALLY_RESET;
5303 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data);
5304 }
5305 
r8152b_init(struct r8152 * tp)5306 static void r8152b_init(struct r8152 *tp)
5307 {
5308 	u32 ocp_data;
5309 	u16 data;
5310 
5311 	if (test_bit(RTL8152_UNPLUG, &tp->flags))
5312 		return;
5313 
5314 	data = r8152_mdio_read(tp, MII_BMCR);
5315 	if (data & BMCR_PDOWN) {
5316 		data &= ~BMCR_PDOWN;
5317 		r8152_mdio_write(tp, MII_BMCR, data);
5318 	}
5319 
5320 	r8152_aldps_en(tp, false);
5321 
5322 	if (tp->version == RTL_VER_01) {
5323 		ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
5324 		ocp_data &= ~LED_MODE_MASK;
5325 		ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
5326 	}
5327 
5328 	r8152_power_cut_en(tp, false);
5329 
5330 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
5331 	ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH;
5332 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
5333 	ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL);
5334 	ocp_data &= ~MCU_CLK_RATIO_MASK;
5335 	ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN;
5336 	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data);
5337 	ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK |
5338 		   SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK;
5339 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data);
5340 
5341 	rtl_tally_reset(tp);
5342 
5343 	/* enable rx aggregation */
5344 	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
5345 	ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
5346 	ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
5347 }
5348 
r8153_init(struct r8152 * tp)5349 static void r8153_init(struct r8152 *tp)
5350 {
5351 	u32 ocp_data;
5352 	u16 data;
5353 	int i;
5354 
5355 	if (test_bit(RTL8152_UNPLUG, &tp->flags))
5356 		return;
5357 
5358 	r8153_u1u2en(tp, false);
5359 
5360 	for (i = 0; i < 500; i++) {
5361 		if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
5362 		    AUTOLOAD_DONE)
5363 			break;
5364 
5365 		msleep(20);
5366 		if (test_bit(RTL8152_UNPLUG, &tp->flags))
5367 			break;
5368 	}
5369 
5370 	data = r8153_phy_status(tp, 0);
5371 
5372 	if (tp->version == RTL_VER_03 || tp->version == RTL_VER_04 ||
5373 	    tp->version == RTL_VER_05)
5374 		ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L);
5375 
5376 	data = r8152_mdio_read(tp, MII_BMCR);
5377 	if (data & BMCR_PDOWN) {
5378 		data &= ~BMCR_PDOWN;
5379 		r8152_mdio_write(tp, MII_BMCR, data);
5380 	}
5381 
5382 	data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
5383 
5384 	r8153_u2p3en(tp, false);
5385 
5386 	if (tp->version == RTL_VER_04) {
5387 		ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2);
5388 		ocp_data &= ~pwd_dn_scale_mask;
5389 		ocp_data |= pwd_dn_scale(96);
5390 		ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2, ocp_data);
5391 
5392 		ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
5393 		ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
5394 		ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
5395 	} else if (tp->version == RTL_VER_05) {
5396 		ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0);
5397 		ocp_data &= ~ECM_ALDPS;
5398 		ocp_write_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0, ocp_data);
5399 
5400 		ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
5401 		if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
5402 			ocp_data &= ~DYNAMIC_BURST;
5403 		else
5404 			ocp_data |= DYNAMIC_BURST;
5405 		ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
5406 	} else if (tp->version == RTL_VER_06) {
5407 		ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
5408 		if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
5409 			ocp_data &= ~DYNAMIC_BURST;
5410 		else
5411 			ocp_data |= DYNAMIC_BURST;
5412 		ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
5413 
5414 		r8153_queue_wake(tp, false);
5415 
5416 		ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
5417 		if (rtl8152_get_speed(tp) & LINK_STATUS)
5418 			ocp_data |= CUR_LINK_OK;
5419 		else
5420 			ocp_data &= ~CUR_LINK_OK;
5421 		ocp_data |= POLL_LINK_CHG;
5422 		ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
5423 	}
5424 
5425 	ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2);
5426 	ocp_data |= EP4_FULL_FC;
5427 	ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2, ocp_data);
5428 
5429 	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL);
5430 	ocp_data &= ~TIMER11_EN;
5431 	ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data);
5432 
5433 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
5434 	ocp_data &= ~LED_MODE_MASK;
5435 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
5436 
5437 	ocp_data = FIFO_EMPTY_1FB | ROK_EXIT_LPM;
5438 	if (tp->version == RTL_VER_04 && tp->udev->speed < USB_SPEED_SUPER)
5439 		ocp_data |= LPM_TIMER_500MS;
5440 	else
5441 		ocp_data |= LPM_TIMER_500US;
5442 	ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data);
5443 
5444 	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2);
5445 	ocp_data &= ~SEN_VAL_MASK;
5446 	ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE;
5447 	ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data);
5448 
5449 	ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001);
5450 
5451 	/* MAC clock speed down */
5452 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, 0);
5453 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, 0);
5454 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, 0);
5455 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, 0);
5456 
5457 	r8153_power_cut_en(tp, false);
5458 	rtl_runtime_suspend_enable(tp, false);
5459 	r8153_u1u2en(tp, true);
5460 	usb_enable_lpm(tp->udev);
5461 
5462 	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6);
5463 	ocp_data |= LANWAKE_CLR_EN;
5464 	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6, ocp_data);
5465 
5466 	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG);
5467 	ocp_data &= ~LANWAKE_PIN;
5468 	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG, ocp_data);
5469 
5470 	/* rx aggregation */
5471 	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
5472 	ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
5473 	if (test_bit(DELL_TB_RX_AGG_BUG, &tp->flags))
5474 		ocp_data |= RX_AGG_DISABLE;
5475 
5476 	ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
5477 
5478 	rtl_tally_reset(tp);
5479 
5480 	switch (tp->udev->speed) {
5481 	case USB_SPEED_SUPER:
5482 	case USB_SPEED_SUPER_PLUS:
5483 		tp->coalesce = COALESCE_SUPER;
5484 		break;
5485 	case USB_SPEED_HIGH:
5486 		tp->coalesce = COALESCE_HIGH;
5487 		break;
5488 	default:
5489 		tp->coalesce = COALESCE_SLOW;
5490 		break;
5491 	}
5492 }
5493 
r8153b_init(struct r8152 * tp)5494 static void r8153b_init(struct r8152 *tp)
5495 {
5496 	u32 ocp_data;
5497 	u16 data;
5498 	int i;
5499 
5500 	if (test_bit(RTL8152_UNPLUG, &tp->flags))
5501 		return;
5502 
5503 	r8153b_u1u2en(tp, false);
5504 
5505 	for (i = 0; i < 500; i++) {
5506 		if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
5507 		    AUTOLOAD_DONE)
5508 			break;
5509 
5510 		msleep(20);
5511 		if (test_bit(RTL8152_UNPLUG, &tp->flags))
5512 			break;
5513 	}
5514 
5515 	data = r8153_phy_status(tp, 0);
5516 
5517 	data = r8152_mdio_read(tp, MII_BMCR);
5518 	if (data & BMCR_PDOWN) {
5519 		data &= ~BMCR_PDOWN;
5520 		r8152_mdio_write(tp, MII_BMCR, data);
5521 	}
5522 
5523 	data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
5524 
5525 	r8153_u2p3en(tp, false);
5526 
5527 	/* MSC timer = 0xfff * 8ms = 32760 ms */
5528 	ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff);
5529 
5530 	/* U1/U2/L1 idle timer. 500 us */
5531 	ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500);
5532 
5533 	r8153b_power_cut_en(tp, false);
5534 	r8153b_ups_en(tp, false);
5535 	r8153_queue_wake(tp, false);
5536 	rtl_runtime_suspend_enable(tp, false);
5537 
5538 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
5539 	if (rtl8152_get_speed(tp) & LINK_STATUS)
5540 		ocp_data |= CUR_LINK_OK;
5541 	else
5542 		ocp_data &= ~CUR_LINK_OK;
5543 	ocp_data |= POLL_LINK_CHG;
5544 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
5545 
5546 	if (tp->udev->speed != USB_SPEED_HIGH)
5547 		r8153b_u1u2en(tp, true);
5548 	usb_enable_lpm(tp->udev);
5549 
5550 	/* MAC clock speed down */
5551 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2);
5552 	ocp_data |= MAC_CLK_SPDWN_EN;
5553 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data);
5554 
5555 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
5556 	ocp_data &= ~PLA_MCU_SPDWN_EN;
5557 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
5558 
5559 	if (tp->version == RTL_VER_09) {
5560 		/* Disable Test IO for 32QFN */
5561 		if (ocp_read_byte(tp, MCU_TYPE_PLA, 0xdc00) & BIT(5)) {
5562 			ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
5563 			ocp_data |= TEST_IO_OFF;
5564 			ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
5565 		}
5566 	}
5567 
5568 	set_bit(GREEN_ETHERNET, &tp->flags);
5569 
5570 	/* rx aggregation */
5571 	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
5572 	ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
5573 	ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
5574 
5575 	rtl_tally_reset(tp);
5576 
5577 	tp->coalesce = 15000;	/* 15 us */
5578 }
5579 
rtl8152_pre_reset(struct usb_interface * intf)5580 static int rtl8152_pre_reset(struct usb_interface *intf)
5581 {
5582 	struct r8152 *tp = usb_get_intfdata(intf);
5583 	struct net_device *netdev;
5584 
5585 	if (!tp)
5586 		return 0;
5587 
5588 	netdev = tp->netdev;
5589 	if (!netif_running(netdev))
5590 		return 0;
5591 
5592 	netif_stop_queue(netdev);
5593 	tasklet_disable(&tp->tx_tl);
5594 	clear_bit(WORK_ENABLE, &tp->flags);
5595 	usb_kill_urb(tp->intr_urb);
5596 	cancel_delayed_work_sync(&tp->schedule);
5597 	napi_disable(&tp->napi);
5598 	if (netif_carrier_ok(netdev)) {
5599 		mutex_lock(&tp->control);
5600 		tp->rtl_ops.disable(tp);
5601 		mutex_unlock(&tp->control);
5602 	}
5603 
5604 	return 0;
5605 }
5606 
rtl8152_post_reset(struct usb_interface * intf)5607 static int rtl8152_post_reset(struct usb_interface *intf)
5608 {
5609 	struct r8152 *tp = usb_get_intfdata(intf);
5610 	struct net_device *netdev;
5611 	struct sockaddr sa;
5612 
5613 	if (!tp)
5614 		return 0;
5615 
5616 	/* reset the MAC adddress in case of policy change */
5617 	if (determine_ethernet_addr(tp, &sa) >= 0) {
5618 		rtnl_lock();
5619 		dev_set_mac_address (tp->netdev, &sa, NULL);
5620 		rtnl_unlock();
5621 	}
5622 
5623 	netdev = tp->netdev;
5624 	if (!netif_running(netdev))
5625 		return 0;
5626 
5627 	set_bit(WORK_ENABLE, &tp->flags);
5628 	if (netif_carrier_ok(netdev)) {
5629 		mutex_lock(&tp->control);
5630 		tp->rtl_ops.enable(tp);
5631 		rtl_start_rx(tp);
5632 		_rtl8152_set_rx_mode(netdev);
5633 		mutex_unlock(&tp->control);
5634 	}
5635 
5636 	napi_enable(&tp->napi);
5637 	tasklet_enable(&tp->tx_tl);
5638 	netif_wake_queue(netdev);
5639 	usb_submit_urb(tp->intr_urb, GFP_KERNEL);
5640 
5641 	if (!list_empty(&tp->rx_done))
5642 		napi_schedule(&tp->napi);
5643 
5644 	return 0;
5645 }
5646 
delay_autosuspend(struct r8152 * tp)5647 static bool delay_autosuspend(struct r8152 *tp)
5648 {
5649 	bool sw_linking = !!netif_carrier_ok(tp->netdev);
5650 	bool hw_linking = !!(rtl8152_get_speed(tp) & LINK_STATUS);
5651 
5652 	/* This means a linking change occurs and the driver doesn't detect it,
5653 	 * yet. If the driver has disabled tx/rx and hw is linking on, the
5654 	 * device wouldn't wake up by receiving any packet.
5655 	 */
5656 	if (work_busy(&tp->schedule.work) || sw_linking != hw_linking)
5657 		return true;
5658 
5659 	/* If the linking down is occurred by nway, the device may miss the
5660 	 * linking change event. And it wouldn't wake when linking on.
5661 	 */
5662 	if (!sw_linking && tp->rtl_ops.in_nway(tp))
5663 		return true;
5664 	else if (!skb_queue_empty(&tp->tx_queue))
5665 		return true;
5666 	else
5667 		return false;
5668 }
5669 
rtl8152_runtime_resume(struct r8152 * tp)5670 static int rtl8152_runtime_resume(struct r8152 *tp)
5671 {
5672 	struct net_device *netdev = tp->netdev;
5673 
5674 	if (netif_running(netdev) && netdev->flags & IFF_UP) {
5675 		struct napi_struct *napi = &tp->napi;
5676 
5677 		tp->rtl_ops.autosuspend_en(tp, false);
5678 		napi_disable(napi);
5679 		set_bit(WORK_ENABLE, &tp->flags);
5680 
5681 		if (netif_carrier_ok(netdev)) {
5682 			if (rtl8152_get_speed(tp) & LINK_STATUS) {
5683 				rtl_start_rx(tp);
5684 			} else {
5685 				netif_carrier_off(netdev);
5686 				tp->rtl_ops.disable(tp);
5687 				netif_info(tp, link, netdev, "linking down\n");
5688 			}
5689 		}
5690 
5691 		napi_enable(napi);
5692 		clear_bit(SELECTIVE_SUSPEND, &tp->flags);
5693 		smp_mb__after_atomic();
5694 
5695 		if (!list_empty(&tp->rx_done))
5696 			napi_schedule(&tp->napi);
5697 
5698 		usb_submit_urb(tp->intr_urb, GFP_NOIO);
5699 	} else {
5700 		if (netdev->flags & IFF_UP)
5701 			tp->rtl_ops.autosuspend_en(tp, false);
5702 
5703 		clear_bit(SELECTIVE_SUSPEND, &tp->flags);
5704 	}
5705 
5706 	return 0;
5707 }
5708 
rtl8152_system_resume(struct r8152 * tp)5709 static int rtl8152_system_resume(struct r8152 *tp)
5710 {
5711 	struct net_device *netdev = tp->netdev;
5712 
5713 	netif_device_attach(netdev);
5714 
5715 	if (netif_running(netdev) && (netdev->flags & IFF_UP)) {
5716 		tp->rtl_ops.up(tp);
5717 		netif_carrier_off(netdev);
5718 		set_bit(WORK_ENABLE, &tp->flags);
5719 		usb_submit_urb(tp->intr_urb, GFP_NOIO);
5720 	}
5721 
5722 	return 0;
5723 }
5724 
rtl8152_runtime_suspend(struct r8152 * tp)5725 static int rtl8152_runtime_suspend(struct r8152 *tp)
5726 {
5727 	struct net_device *netdev = tp->netdev;
5728 	int ret = 0;
5729 
5730 	set_bit(SELECTIVE_SUSPEND, &tp->flags);
5731 	smp_mb__after_atomic();
5732 
5733 	if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
5734 		u32 rcr = 0;
5735 
5736 		if (netif_carrier_ok(netdev)) {
5737 			u32 ocp_data;
5738 
5739 			rcr = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
5740 			ocp_data = rcr & ~RCR_ACPT_ALL;
5741 			ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
5742 			rxdy_gated_en(tp, true);
5743 			ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA,
5744 						 PLA_OOB_CTRL);
5745 			if (!(ocp_data & RXFIFO_EMPTY)) {
5746 				rxdy_gated_en(tp, false);
5747 				ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr);
5748 				clear_bit(SELECTIVE_SUSPEND, &tp->flags);
5749 				smp_mb__after_atomic();
5750 				ret = -EBUSY;
5751 				goto out1;
5752 			}
5753 		}
5754 
5755 		clear_bit(WORK_ENABLE, &tp->flags);
5756 		usb_kill_urb(tp->intr_urb);
5757 
5758 		tp->rtl_ops.autosuspend_en(tp, true);
5759 
5760 		if (netif_carrier_ok(netdev)) {
5761 			struct napi_struct *napi = &tp->napi;
5762 
5763 			napi_disable(napi);
5764 			rtl_stop_rx(tp);
5765 			rxdy_gated_en(tp, false);
5766 			ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr);
5767 			napi_enable(napi);
5768 		}
5769 
5770 		if (delay_autosuspend(tp)) {
5771 			rtl8152_runtime_resume(tp);
5772 			ret = -EBUSY;
5773 		}
5774 	}
5775 
5776 out1:
5777 	return ret;
5778 }
5779 
rtl8152_system_suspend(struct r8152 * tp)5780 static int rtl8152_system_suspend(struct r8152 *tp)
5781 {
5782 	struct net_device *netdev = tp->netdev;
5783 
5784 	netif_device_detach(netdev);
5785 
5786 	if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
5787 		struct napi_struct *napi = &tp->napi;
5788 
5789 		clear_bit(WORK_ENABLE, &tp->flags);
5790 		usb_kill_urb(tp->intr_urb);
5791 		tasklet_disable(&tp->tx_tl);
5792 		napi_disable(napi);
5793 		cancel_delayed_work_sync(&tp->schedule);
5794 		tp->rtl_ops.down(tp);
5795 		napi_enable(napi);
5796 		tasklet_enable(&tp->tx_tl);
5797 	}
5798 
5799 	return 0;
5800 }
5801 
rtl8152_suspend(struct usb_interface * intf,pm_message_t message)5802 static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message)
5803 {
5804 	struct r8152 *tp = usb_get_intfdata(intf);
5805 	int ret;
5806 
5807 	mutex_lock(&tp->control);
5808 
5809 	if (PMSG_IS_AUTO(message))
5810 		ret = rtl8152_runtime_suspend(tp);
5811 	else
5812 		ret = rtl8152_system_suspend(tp);
5813 
5814 	mutex_unlock(&tp->control);
5815 
5816 	return ret;
5817 }
5818 
rtl8152_resume(struct usb_interface * intf)5819 static int rtl8152_resume(struct usb_interface *intf)
5820 {
5821 	struct r8152 *tp = usb_get_intfdata(intf);
5822 	int ret;
5823 
5824 	mutex_lock(&tp->control);
5825 
5826 	if (test_bit(SELECTIVE_SUSPEND, &tp->flags))
5827 		ret = rtl8152_runtime_resume(tp);
5828 	else
5829 		ret = rtl8152_system_resume(tp);
5830 
5831 	mutex_unlock(&tp->control);
5832 
5833 	return ret;
5834 }
5835 
rtl8152_reset_resume(struct usb_interface * intf)5836 static int rtl8152_reset_resume(struct usb_interface *intf)
5837 {
5838 	struct r8152 *tp = usb_get_intfdata(intf);
5839 
5840 	clear_bit(SELECTIVE_SUSPEND, &tp->flags);
5841 	tp->rtl_ops.init(tp);
5842 	queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0);
5843 	set_ethernet_addr(tp);
5844 	return rtl8152_resume(intf);
5845 }
5846 
rtl8152_get_wol(struct net_device * dev,struct ethtool_wolinfo * wol)5847 static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
5848 {
5849 	struct r8152 *tp = netdev_priv(dev);
5850 
5851 	if (usb_autopm_get_interface(tp->intf) < 0)
5852 		return;
5853 
5854 	if (!rtl_can_wakeup(tp)) {
5855 		wol->supported = 0;
5856 		wol->wolopts = 0;
5857 	} else {
5858 		mutex_lock(&tp->control);
5859 		wol->supported = WAKE_ANY;
5860 		wol->wolopts = __rtl_get_wol(tp);
5861 		mutex_unlock(&tp->control);
5862 	}
5863 
5864 	usb_autopm_put_interface(tp->intf);
5865 }
5866 
rtl8152_set_wol(struct net_device * dev,struct ethtool_wolinfo * wol)5867 static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
5868 {
5869 	struct r8152 *tp = netdev_priv(dev);
5870 	int ret;
5871 
5872 	if (!rtl_can_wakeup(tp))
5873 		return -EOPNOTSUPP;
5874 
5875 	if (wol->wolopts & ~WAKE_ANY)
5876 		return -EINVAL;
5877 
5878 	ret = usb_autopm_get_interface(tp->intf);
5879 	if (ret < 0)
5880 		goto out_set_wol;
5881 
5882 	mutex_lock(&tp->control);
5883 
5884 	__rtl_set_wol(tp, wol->wolopts);
5885 	tp->saved_wolopts = wol->wolopts & WAKE_ANY;
5886 
5887 	mutex_unlock(&tp->control);
5888 
5889 	usb_autopm_put_interface(tp->intf);
5890 
5891 out_set_wol:
5892 	return ret;
5893 }
5894 
rtl8152_get_msglevel(struct net_device * dev)5895 static u32 rtl8152_get_msglevel(struct net_device *dev)
5896 {
5897 	struct r8152 *tp = netdev_priv(dev);
5898 
5899 	return tp->msg_enable;
5900 }
5901 
rtl8152_set_msglevel(struct net_device * dev,u32 value)5902 static void rtl8152_set_msglevel(struct net_device *dev, u32 value)
5903 {
5904 	struct r8152 *tp = netdev_priv(dev);
5905 
5906 	tp->msg_enable = value;
5907 }
5908 
rtl8152_get_drvinfo(struct net_device * netdev,struct ethtool_drvinfo * info)5909 static void rtl8152_get_drvinfo(struct net_device *netdev,
5910 				struct ethtool_drvinfo *info)
5911 {
5912 	struct r8152 *tp = netdev_priv(netdev);
5913 
5914 	strlcpy(info->driver, MODULENAME, sizeof(info->driver));
5915 	strlcpy(info->version, DRIVER_VERSION, sizeof(info->version));
5916 	usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info));
5917 	if (!IS_ERR_OR_NULL(tp->rtl_fw.fw))
5918 		strlcpy(info->fw_version, tp->rtl_fw.version,
5919 			sizeof(info->fw_version));
5920 }
5921 
5922 static
rtl8152_get_link_ksettings(struct net_device * netdev,struct ethtool_link_ksettings * cmd)5923 int rtl8152_get_link_ksettings(struct net_device *netdev,
5924 			       struct ethtool_link_ksettings *cmd)
5925 {
5926 	struct r8152 *tp = netdev_priv(netdev);
5927 	int ret;
5928 
5929 	if (!tp->mii.mdio_read)
5930 		return -EOPNOTSUPP;
5931 
5932 	ret = usb_autopm_get_interface(tp->intf);
5933 	if (ret < 0)
5934 		goto out;
5935 
5936 	mutex_lock(&tp->control);
5937 
5938 	mii_ethtool_get_link_ksettings(&tp->mii, cmd);
5939 
5940 	mutex_unlock(&tp->control);
5941 
5942 	usb_autopm_put_interface(tp->intf);
5943 
5944 out:
5945 	return ret;
5946 }
5947 
rtl8152_set_link_ksettings(struct net_device * dev,const struct ethtool_link_ksettings * cmd)5948 static int rtl8152_set_link_ksettings(struct net_device *dev,
5949 				      const struct ethtool_link_ksettings *cmd)
5950 {
5951 	struct r8152 *tp = netdev_priv(dev);
5952 	u32 advertising = 0;
5953 	int ret;
5954 
5955 	ret = usb_autopm_get_interface(tp->intf);
5956 	if (ret < 0)
5957 		goto out;
5958 
5959 	if (test_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT,
5960 		     cmd->link_modes.advertising))
5961 		advertising |= RTL_ADVERTISED_10_HALF;
5962 
5963 	if (test_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT,
5964 		     cmd->link_modes.advertising))
5965 		advertising |= RTL_ADVERTISED_10_FULL;
5966 
5967 	if (test_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT,
5968 		     cmd->link_modes.advertising))
5969 		advertising |= RTL_ADVERTISED_100_HALF;
5970 
5971 	if (test_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT,
5972 		     cmd->link_modes.advertising))
5973 		advertising |= RTL_ADVERTISED_100_FULL;
5974 
5975 	if (test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
5976 		     cmd->link_modes.advertising))
5977 		advertising |= RTL_ADVERTISED_1000_HALF;
5978 
5979 	if (test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
5980 		     cmd->link_modes.advertising))
5981 		advertising |= RTL_ADVERTISED_1000_FULL;
5982 
5983 	mutex_lock(&tp->control);
5984 
5985 	ret = rtl8152_set_speed(tp, cmd->base.autoneg, cmd->base.speed,
5986 				cmd->base.duplex, advertising);
5987 	if (!ret) {
5988 		tp->autoneg = cmd->base.autoneg;
5989 		tp->speed = cmd->base.speed;
5990 		tp->duplex = cmd->base.duplex;
5991 		tp->advertising = advertising;
5992 	}
5993 
5994 	mutex_unlock(&tp->control);
5995 
5996 	usb_autopm_put_interface(tp->intf);
5997 
5998 out:
5999 	return ret;
6000 }
6001 
6002 static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = {
6003 	"tx_packets",
6004 	"rx_packets",
6005 	"tx_errors",
6006 	"rx_errors",
6007 	"rx_missed",
6008 	"align_errors",
6009 	"tx_single_collisions",
6010 	"tx_multi_collisions",
6011 	"rx_unicast",
6012 	"rx_broadcast",
6013 	"rx_multicast",
6014 	"tx_aborted",
6015 	"tx_underrun",
6016 };
6017 
rtl8152_get_sset_count(struct net_device * dev,int sset)6018 static int rtl8152_get_sset_count(struct net_device *dev, int sset)
6019 {
6020 	switch (sset) {
6021 	case ETH_SS_STATS:
6022 		return ARRAY_SIZE(rtl8152_gstrings);
6023 	default:
6024 		return -EOPNOTSUPP;
6025 	}
6026 }
6027 
rtl8152_get_ethtool_stats(struct net_device * dev,struct ethtool_stats * stats,u64 * data)6028 static void rtl8152_get_ethtool_stats(struct net_device *dev,
6029 				      struct ethtool_stats *stats, u64 *data)
6030 {
6031 	struct r8152 *tp = netdev_priv(dev);
6032 	struct tally_counter tally;
6033 
6034 	if (usb_autopm_get_interface(tp->intf) < 0)
6035 		return;
6036 
6037 	generic_ocp_read(tp, PLA_TALLYCNT, sizeof(tally), &tally, MCU_TYPE_PLA);
6038 
6039 	usb_autopm_put_interface(tp->intf);
6040 
6041 	data[0] = le64_to_cpu(tally.tx_packets);
6042 	data[1] = le64_to_cpu(tally.rx_packets);
6043 	data[2] = le64_to_cpu(tally.tx_errors);
6044 	data[3] = le32_to_cpu(tally.rx_errors);
6045 	data[4] = le16_to_cpu(tally.rx_missed);
6046 	data[5] = le16_to_cpu(tally.align_errors);
6047 	data[6] = le32_to_cpu(tally.tx_one_collision);
6048 	data[7] = le32_to_cpu(tally.tx_multi_collision);
6049 	data[8] = le64_to_cpu(tally.rx_unicast);
6050 	data[9] = le64_to_cpu(tally.rx_broadcast);
6051 	data[10] = le32_to_cpu(tally.rx_multicast);
6052 	data[11] = le16_to_cpu(tally.tx_aborted);
6053 	data[12] = le16_to_cpu(tally.tx_underrun);
6054 }
6055 
rtl8152_get_strings(struct net_device * dev,u32 stringset,u8 * data)6056 static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data)
6057 {
6058 	switch (stringset) {
6059 	case ETH_SS_STATS:
6060 		memcpy(data, rtl8152_gstrings, sizeof(rtl8152_gstrings));
6061 		break;
6062 	}
6063 }
6064 
r8152_get_eee(struct r8152 * tp,struct ethtool_eee * eee)6065 static int r8152_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
6066 {
6067 	u32 lp, adv, supported = 0;
6068 	u16 val;
6069 
6070 	val = r8152_mmd_read(tp, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
6071 	supported = mmd_eee_cap_to_ethtool_sup_t(val);
6072 
6073 	val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
6074 	adv = mmd_eee_adv_to_ethtool_adv_t(val);
6075 
6076 	val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE);
6077 	lp = mmd_eee_adv_to_ethtool_adv_t(val);
6078 
6079 	eee->eee_enabled = tp->eee_en;
6080 	eee->eee_active = !!(supported & adv & lp);
6081 	eee->supported = supported;
6082 	eee->advertised = tp->eee_adv;
6083 	eee->lp_advertised = lp;
6084 
6085 	return 0;
6086 }
6087 
r8152_set_eee(struct r8152 * tp,struct ethtool_eee * eee)6088 static int r8152_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
6089 {
6090 	u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
6091 
6092 	tp->eee_en = eee->eee_enabled;
6093 	tp->eee_adv = val;
6094 
6095 	rtl_eee_enable(tp, tp->eee_en);
6096 
6097 	return 0;
6098 }
6099 
r8153_get_eee(struct r8152 * tp,struct ethtool_eee * eee)6100 static int r8153_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
6101 {
6102 	u32 lp, adv, supported = 0;
6103 	u16 val;
6104 
6105 	val = ocp_reg_read(tp, OCP_EEE_ABLE);
6106 	supported = mmd_eee_cap_to_ethtool_sup_t(val);
6107 
6108 	val = ocp_reg_read(tp, OCP_EEE_ADV);
6109 	adv = mmd_eee_adv_to_ethtool_adv_t(val);
6110 
6111 	val = ocp_reg_read(tp, OCP_EEE_LPABLE);
6112 	lp = mmd_eee_adv_to_ethtool_adv_t(val);
6113 
6114 	eee->eee_enabled = tp->eee_en;
6115 	eee->eee_active = !!(supported & adv & lp);
6116 	eee->supported = supported;
6117 	eee->advertised = tp->eee_adv;
6118 	eee->lp_advertised = lp;
6119 
6120 	return 0;
6121 }
6122 
6123 static int
rtl_ethtool_get_eee(struct net_device * net,struct ethtool_eee * edata)6124 rtl_ethtool_get_eee(struct net_device *net, struct ethtool_eee *edata)
6125 {
6126 	struct r8152 *tp = netdev_priv(net);
6127 	int ret;
6128 
6129 	ret = usb_autopm_get_interface(tp->intf);
6130 	if (ret < 0)
6131 		goto out;
6132 
6133 	mutex_lock(&tp->control);
6134 
6135 	ret = tp->rtl_ops.eee_get(tp, edata);
6136 
6137 	mutex_unlock(&tp->control);
6138 
6139 	usb_autopm_put_interface(tp->intf);
6140 
6141 out:
6142 	return ret;
6143 }
6144 
6145 static int
rtl_ethtool_set_eee(struct net_device * net,struct ethtool_eee * edata)6146 rtl_ethtool_set_eee(struct net_device *net, struct ethtool_eee *edata)
6147 {
6148 	struct r8152 *tp = netdev_priv(net);
6149 	int ret;
6150 
6151 	ret = usb_autopm_get_interface(tp->intf);
6152 	if (ret < 0)
6153 		goto out;
6154 
6155 	mutex_lock(&tp->control);
6156 
6157 	ret = tp->rtl_ops.eee_set(tp, edata);
6158 	if (!ret)
6159 		ret = mii_nway_restart(&tp->mii);
6160 
6161 	mutex_unlock(&tp->control);
6162 
6163 	usb_autopm_put_interface(tp->intf);
6164 
6165 out:
6166 	return ret;
6167 }
6168 
rtl8152_nway_reset(struct net_device * dev)6169 static int rtl8152_nway_reset(struct net_device *dev)
6170 {
6171 	struct r8152 *tp = netdev_priv(dev);
6172 	int ret;
6173 
6174 	ret = usb_autopm_get_interface(tp->intf);
6175 	if (ret < 0)
6176 		goto out;
6177 
6178 	mutex_lock(&tp->control);
6179 
6180 	ret = mii_nway_restart(&tp->mii);
6181 
6182 	mutex_unlock(&tp->control);
6183 
6184 	usb_autopm_put_interface(tp->intf);
6185 
6186 out:
6187 	return ret;
6188 }
6189 
rtl8152_get_coalesce(struct net_device * netdev,struct ethtool_coalesce * coalesce)6190 static int rtl8152_get_coalesce(struct net_device *netdev,
6191 				struct ethtool_coalesce *coalesce)
6192 {
6193 	struct r8152 *tp = netdev_priv(netdev);
6194 
6195 	switch (tp->version) {
6196 	case RTL_VER_01:
6197 	case RTL_VER_02:
6198 	case RTL_VER_07:
6199 		return -EOPNOTSUPP;
6200 	default:
6201 		break;
6202 	}
6203 
6204 	coalesce->rx_coalesce_usecs = tp->coalesce;
6205 
6206 	return 0;
6207 }
6208 
rtl8152_set_coalesce(struct net_device * netdev,struct ethtool_coalesce * coalesce)6209 static int rtl8152_set_coalesce(struct net_device *netdev,
6210 				struct ethtool_coalesce *coalesce)
6211 {
6212 	struct r8152 *tp = netdev_priv(netdev);
6213 	int ret;
6214 
6215 	switch (tp->version) {
6216 	case RTL_VER_01:
6217 	case RTL_VER_02:
6218 	case RTL_VER_07:
6219 		return -EOPNOTSUPP;
6220 	default:
6221 		break;
6222 	}
6223 
6224 	if (coalesce->rx_coalesce_usecs > COALESCE_SLOW)
6225 		return -EINVAL;
6226 
6227 	ret = usb_autopm_get_interface(tp->intf);
6228 	if (ret < 0)
6229 		return ret;
6230 
6231 	mutex_lock(&tp->control);
6232 
6233 	if (tp->coalesce != coalesce->rx_coalesce_usecs) {
6234 		tp->coalesce = coalesce->rx_coalesce_usecs;
6235 
6236 		if (netif_running(netdev) && netif_carrier_ok(netdev)) {
6237 			netif_stop_queue(netdev);
6238 			napi_disable(&tp->napi);
6239 			tp->rtl_ops.disable(tp);
6240 			tp->rtl_ops.enable(tp);
6241 			rtl_start_rx(tp);
6242 			clear_bit(RTL8152_SET_RX_MODE, &tp->flags);
6243 			_rtl8152_set_rx_mode(netdev);
6244 			napi_enable(&tp->napi);
6245 			netif_wake_queue(netdev);
6246 		}
6247 	}
6248 
6249 	mutex_unlock(&tp->control);
6250 
6251 	usb_autopm_put_interface(tp->intf);
6252 
6253 	return ret;
6254 }
6255 
rtl8152_get_tunable(struct net_device * netdev,const struct ethtool_tunable * tunable,void * d)6256 static int rtl8152_get_tunable(struct net_device *netdev,
6257 			       const struct ethtool_tunable *tunable, void *d)
6258 {
6259 	struct r8152 *tp = netdev_priv(netdev);
6260 
6261 	switch (tunable->id) {
6262 	case ETHTOOL_RX_COPYBREAK:
6263 		*(u32 *)d = tp->rx_copybreak;
6264 		break;
6265 	default:
6266 		return -EOPNOTSUPP;
6267 	}
6268 
6269 	return 0;
6270 }
6271 
rtl8152_set_tunable(struct net_device * netdev,const struct ethtool_tunable * tunable,const void * d)6272 static int rtl8152_set_tunable(struct net_device *netdev,
6273 			       const struct ethtool_tunable *tunable,
6274 			       const void *d)
6275 {
6276 	struct r8152 *tp = netdev_priv(netdev);
6277 	u32 val;
6278 
6279 	switch (tunable->id) {
6280 	case ETHTOOL_RX_COPYBREAK:
6281 		val = *(u32 *)d;
6282 		if (val < ETH_ZLEN) {
6283 			netif_err(tp, rx_err, netdev,
6284 				  "Invalid rx copy break value\n");
6285 			return -EINVAL;
6286 		}
6287 
6288 		if (tp->rx_copybreak != val) {
6289 			if (netdev->flags & IFF_UP) {
6290 				mutex_lock(&tp->control);
6291 				napi_disable(&tp->napi);
6292 				tp->rx_copybreak = val;
6293 				napi_enable(&tp->napi);
6294 				mutex_unlock(&tp->control);
6295 			} else {
6296 				tp->rx_copybreak = val;
6297 			}
6298 		}
6299 		break;
6300 	default:
6301 		return -EOPNOTSUPP;
6302 	}
6303 
6304 	return 0;
6305 }
6306 
rtl8152_get_ringparam(struct net_device * netdev,struct ethtool_ringparam * ring)6307 static void rtl8152_get_ringparam(struct net_device *netdev,
6308 				  struct ethtool_ringparam *ring)
6309 {
6310 	struct r8152 *tp = netdev_priv(netdev);
6311 
6312 	ring->rx_max_pending = RTL8152_RX_MAX_PENDING;
6313 	ring->rx_pending = tp->rx_pending;
6314 }
6315 
rtl8152_set_ringparam(struct net_device * netdev,struct ethtool_ringparam * ring)6316 static int rtl8152_set_ringparam(struct net_device *netdev,
6317 				 struct ethtool_ringparam *ring)
6318 {
6319 	struct r8152 *tp = netdev_priv(netdev);
6320 
6321 	if (ring->rx_pending < (RTL8152_MAX_RX * 2))
6322 		return -EINVAL;
6323 
6324 	if (tp->rx_pending != ring->rx_pending) {
6325 		if (netdev->flags & IFF_UP) {
6326 			mutex_lock(&tp->control);
6327 			napi_disable(&tp->napi);
6328 			tp->rx_pending = ring->rx_pending;
6329 			napi_enable(&tp->napi);
6330 			mutex_unlock(&tp->control);
6331 		} else {
6332 			tp->rx_pending = ring->rx_pending;
6333 		}
6334 	}
6335 
6336 	return 0;
6337 }
6338 
6339 static const struct ethtool_ops ops = {
6340 	.supported_coalesce_params = ETHTOOL_COALESCE_USECS,
6341 	.get_drvinfo = rtl8152_get_drvinfo,
6342 	.get_link = ethtool_op_get_link,
6343 	.nway_reset = rtl8152_nway_reset,
6344 	.get_msglevel = rtl8152_get_msglevel,
6345 	.set_msglevel = rtl8152_set_msglevel,
6346 	.get_wol = rtl8152_get_wol,
6347 	.set_wol = rtl8152_set_wol,
6348 	.get_strings = rtl8152_get_strings,
6349 	.get_sset_count = rtl8152_get_sset_count,
6350 	.get_ethtool_stats = rtl8152_get_ethtool_stats,
6351 	.get_coalesce = rtl8152_get_coalesce,
6352 	.set_coalesce = rtl8152_set_coalesce,
6353 	.get_eee = rtl_ethtool_get_eee,
6354 	.set_eee = rtl_ethtool_set_eee,
6355 	.get_link_ksettings = rtl8152_get_link_ksettings,
6356 	.set_link_ksettings = rtl8152_set_link_ksettings,
6357 	.get_tunable = rtl8152_get_tunable,
6358 	.set_tunable = rtl8152_set_tunable,
6359 	.get_ringparam = rtl8152_get_ringparam,
6360 	.set_ringparam = rtl8152_set_ringparam,
6361 };
6362 
rtl8152_ioctl(struct net_device * netdev,struct ifreq * rq,int cmd)6363 static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
6364 {
6365 	struct r8152 *tp = netdev_priv(netdev);
6366 	struct mii_ioctl_data *data = if_mii(rq);
6367 	int res;
6368 
6369 	if (test_bit(RTL8152_UNPLUG, &tp->flags))
6370 		return -ENODEV;
6371 
6372 	res = usb_autopm_get_interface(tp->intf);
6373 	if (res < 0)
6374 		goto out;
6375 
6376 	switch (cmd) {
6377 	case SIOCGMIIPHY:
6378 		data->phy_id = R8152_PHY_ID; /* Internal PHY */
6379 		break;
6380 
6381 	case SIOCGMIIREG:
6382 		mutex_lock(&tp->control);
6383 		data->val_out = r8152_mdio_read(tp, data->reg_num);
6384 		mutex_unlock(&tp->control);
6385 		break;
6386 
6387 	case SIOCSMIIREG:
6388 		if (!capable(CAP_NET_ADMIN)) {
6389 			res = -EPERM;
6390 			break;
6391 		}
6392 		mutex_lock(&tp->control);
6393 		r8152_mdio_write(tp, data->reg_num, data->val_in);
6394 		mutex_unlock(&tp->control);
6395 		break;
6396 
6397 	default:
6398 		res = -EOPNOTSUPP;
6399 	}
6400 
6401 	usb_autopm_put_interface(tp->intf);
6402 
6403 out:
6404 	return res;
6405 }
6406 
rtl8152_change_mtu(struct net_device * dev,int new_mtu)6407 static int rtl8152_change_mtu(struct net_device *dev, int new_mtu)
6408 {
6409 	struct r8152 *tp = netdev_priv(dev);
6410 	int ret;
6411 
6412 	switch (tp->version) {
6413 	case RTL_VER_01:
6414 	case RTL_VER_02:
6415 	case RTL_VER_07:
6416 		dev->mtu = new_mtu;
6417 		return 0;
6418 	default:
6419 		break;
6420 	}
6421 
6422 	ret = usb_autopm_get_interface(tp->intf);
6423 	if (ret < 0)
6424 		return ret;
6425 
6426 	mutex_lock(&tp->control);
6427 
6428 	dev->mtu = new_mtu;
6429 
6430 	if (netif_running(dev)) {
6431 		u32 rms = new_mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
6432 
6433 		ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, rms);
6434 
6435 		if (netif_carrier_ok(dev))
6436 			r8153_set_rx_early_size(tp);
6437 	}
6438 
6439 	mutex_unlock(&tp->control);
6440 
6441 	usb_autopm_put_interface(tp->intf);
6442 
6443 	return ret;
6444 }
6445 
6446 static const struct net_device_ops rtl8152_netdev_ops = {
6447 	.ndo_open		= rtl8152_open,
6448 	.ndo_stop		= rtl8152_close,
6449 	.ndo_do_ioctl		= rtl8152_ioctl,
6450 	.ndo_start_xmit		= rtl8152_start_xmit,
6451 	.ndo_tx_timeout		= rtl8152_tx_timeout,
6452 	.ndo_set_features	= rtl8152_set_features,
6453 	.ndo_set_rx_mode	= rtl8152_set_rx_mode,
6454 	.ndo_set_mac_address	= rtl8152_set_mac_address,
6455 	.ndo_change_mtu		= rtl8152_change_mtu,
6456 	.ndo_validate_addr	= eth_validate_addr,
6457 	.ndo_features_check	= rtl8152_features_check,
6458 };
6459 
rtl8152_unload(struct r8152 * tp)6460 static void rtl8152_unload(struct r8152 *tp)
6461 {
6462 	if (test_bit(RTL8152_UNPLUG, &tp->flags))
6463 		return;
6464 
6465 	if (tp->version != RTL_VER_01)
6466 		r8152_power_cut_en(tp, true);
6467 }
6468 
rtl8153_unload(struct r8152 * tp)6469 static void rtl8153_unload(struct r8152 *tp)
6470 {
6471 	if (test_bit(RTL8152_UNPLUG, &tp->flags))
6472 		return;
6473 
6474 	r8153_power_cut_en(tp, false);
6475 }
6476 
rtl8153b_unload(struct r8152 * tp)6477 static void rtl8153b_unload(struct r8152 *tp)
6478 {
6479 	if (test_bit(RTL8152_UNPLUG, &tp->flags))
6480 		return;
6481 
6482 	r8153b_power_cut_en(tp, false);
6483 }
6484 
rtl_ops_init(struct r8152 * tp)6485 static int rtl_ops_init(struct r8152 *tp)
6486 {
6487 	struct rtl_ops *ops = &tp->rtl_ops;
6488 	int ret = 0;
6489 
6490 	switch (tp->version) {
6491 	case RTL_VER_01:
6492 	case RTL_VER_02:
6493 	case RTL_VER_07:
6494 		ops->init		= r8152b_init;
6495 		ops->enable		= rtl8152_enable;
6496 		ops->disable		= rtl8152_disable;
6497 		ops->up			= rtl8152_up;
6498 		ops->down		= rtl8152_down;
6499 		ops->unload		= rtl8152_unload;
6500 		ops->eee_get		= r8152_get_eee;
6501 		ops->eee_set		= r8152_set_eee;
6502 		ops->in_nway		= rtl8152_in_nway;
6503 		ops->hw_phy_cfg		= r8152b_hw_phy_cfg;
6504 		ops->autosuspend_en	= rtl_runtime_suspend_enable;
6505 		tp->rx_buf_sz		= 16 * 1024;
6506 		tp->eee_en		= true;
6507 		tp->eee_adv		= MDIO_EEE_100TX;
6508 		break;
6509 
6510 	case RTL_VER_03:
6511 	case RTL_VER_04:
6512 	case RTL_VER_05:
6513 	case RTL_VER_06:
6514 		ops->init		= r8153_init;
6515 		ops->enable		= rtl8153_enable;
6516 		ops->disable		= rtl8153_disable;
6517 		ops->up			= rtl8153_up;
6518 		ops->down		= rtl8153_down;
6519 		ops->unload		= rtl8153_unload;
6520 		ops->eee_get		= r8153_get_eee;
6521 		ops->eee_set		= r8152_set_eee;
6522 		ops->in_nway		= rtl8153_in_nway;
6523 		ops->hw_phy_cfg		= r8153_hw_phy_cfg;
6524 		ops->autosuspend_en	= rtl8153_runtime_enable;
6525 		if (tp->udev->speed < USB_SPEED_SUPER)
6526 			tp->rx_buf_sz	= 16 * 1024;
6527 		else
6528 			tp->rx_buf_sz	= 32 * 1024;
6529 		tp->eee_en		= true;
6530 		tp->eee_adv		= MDIO_EEE_1000T | MDIO_EEE_100TX;
6531 		break;
6532 
6533 	case RTL_VER_08:
6534 	case RTL_VER_09:
6535 		ops->init		= r8153b_init;
6536 		ops->enable		= rtl8153_enable;
6537 		ops->disable		= rtl8153_disable;
6538 		ops->up			= rtl8153b_up;
6539 		ops->down		= rtl8153b_down;
6540 		ops->unload		= rtl8153b_unload;
6541 		ops->eee_get		= r8153_get_eee;
6542 		ops->eee_set		= r8152_set_eee;
6543 		ops->in_nway		= rtl8153_in_nway;
6544 		ops->hw_phy_cfg		= r8153b_hw_phy_cfg;
6545 		ops->autosuspend_en	= rtl8153b_runtime_enable;
6546 		tp->rx_buf_sz		= 32 * 1024;
6547 		tp->eee_en		= true;
6548 		tp->eee_adv		= MDIO_EEE_1000T | MDIO_EEE_100TX;
6549 		break;
6550 
6551 	default:
6552 		ret = -ENODEV;
6553 		netif_err(tp, probe, tp->netdev, "Unknown Device\n");
6554 		break;
6555 	}
6556 
6557 	return ret;
6558 }
6559 
6560 #define FIRMWARE_8153A_2	"rtl_nic/rtl8153a-2.fw"
6561 #define FIRMWARE_8153A_3	"rtl_nic/rtl8153a-3.fw"
6562 #define FIRMWARE_8153A_4	"rtl_nic/rtl8153a-4.fw"
6563 #define FIRMWARE_8153B_2	"rtl_nic/rtl8153b-2.fw"
6564 
6565 MODULE_FIRMWARE(FIRMWARE_8153A_2);
6566 MODULE_FIRMWARE(FIRMWARE_8153A_3);
6567 MODULE_FIRMWARE(FIRMWARE_8153A_4);
6568 MODULE_FIRMWARE(FIRMWARE_8153B_2);
6569 
rtl_fw_init(struct r8152 * tp)6570 static int rtl_fw_init(struct r8152 *tp)
6571 {
6572 	struct rtl_fw *rtl_fw = &tp->rtl_fw;
6573 
6574 	switch (tp->version) {
6575 	case RTL_VER_04:
6576 		rtl_fw->fw_name		= FIRMWARE_8153A_2;
6577 		rtl_fw->pre_fw		= r8153_pre_firmware_1;
6578 		rtl_fw->post_fw		= r8153_post_firmware_1;
6579 		break;
6580 	case RTL_VER_05:
6581 		rtl_fw->fw_name		= FIRMWARE_8153A_3;
6582 		rtl_fw->pre_fw		= r8153_pre_firmware_2;
6583 		rtl_fw->post_fw		= r8153_post_firmware_2;
6584 		break;
6585 	case RTL_VER_06:
6586 		rtl_fw->fw_name		= FIRMWARE_8153A_4;
6587 		rtl_fw->post_fw		= r8153_post_firmware_3;
6588 		break;
6589 	case RTL_VER_09:
6590 		rtl_fw->fw_name		= FIRMWARE_8153B_2;
6591 		rtl_fw->pre_fw		= r8153b_pre_firmware_1;
6592 		rtl_fw->post_fw		= r8153b_post_firmware_1;
6593 		break;
6594 	default:
6595 		break;
6596 	}
6597 
6598 	return 0;
6599 }
6600 
rtl_get_version(struct usb_interface * intf)6601 static u8 rtl_get_version(struct usb_interface *intf)
6602 {
6603 	struct usb_device *udev = interface_to_usbdev(intf);
6604 	u32 ocp_data = 0;
6605 	__le32 *tmp;
6606 	u8 version;
6607 	int ret;
6608 
6609 	tmp = kmalloc(sizeof(*tmp), GFP_KERNEL);
6610 	if (!tmp)
6611 		return 0;
6612 
6613 	ret = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
6614 			      RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
6615 			      PLA_TCR0, MCU_TYPE_PLA, tmp, sizeof(*tmp), 500);
6616 	if (ret > 0)
6617 		ocp_data = (__le32_to_cpu(*tmp) >> 16) & VERSION_MASK;
6618 
6619 	kfree(tmp);
6620 
6621 	switch (ocp_data) {
6622 	case 0x4c00:
6623 		version = RTL_VER_01;
6624 		break;
6625 	case 0x4c10:
6626 		version = RTL_VER_02;
6627 		break;
6628 	case 0x5c00:
6629 		version = RTL_VER_03;
6630 		break;
6631 	case 0x5c10:
6632 		version = RTL_VER_04;
6633 		break;
6634 	case 0x5c20:
6635 		version = RTL_VER_05;
6636 		break;
6637 	case 0x5c30:
6638 		version = RTL_VER_06;
6639 		break;
6640 	case 0x4800:
6641 		version = RTL_VER_07;
6642 		break;
6643 	case 0x6000:
6644 		version = RTL_VER_08;
6645 		break;
6646 	case 0x6010:
6647 		version = RTL_VER_09;
6648 		break;
6649 	default:
6650 		version = RTL_VER_UNKNOWN;
6651 		dev_info(&intf->dev, "Unknown version 0x%04x\n", ocp_data);
6652 		break;
6653 	}
6654 
6655 	dev_dbg(&intf->dev, "Detected version 0x%04x\n", version);
6656 
6657 	return version;
6658 }
6659 
rtl8152_probe(struct usb_interface * intf,const struct usb_device_id * id)6660 static int rtl8152_probe(struct usb_interface *intf,
6661 			 const struct usb_device_id *id)
6662 {
6663 	struct usb_device *udev = interface_to_usbdev(intf);
6664 	u8 version = rtl_get_version(intf);
6665 	struct r8152 *tp;
6666 	struct net_device *netdev;
6667 	int ret;
6668 
6669 	if (version == RTL_VER_UNKNOWN)
6670 		return -ENODEV;
6671 
6672 	if (udev->actconfig->desc.bConfigurationValue != 1) {
6673 		usb_driver_set_configuration(udev, 1);
6674 		return -ENODEV;
6675 	}
6676 
6677 	if (intf->cur_altsetting->desc.bNumEndpoints < 3)
6678 		return -ENODEV;
6679 
6680 	usb_reset_device(udev);
6681 	netdev = alloc_etherdev(sizeof(struct r8152));
6682 	if (!netdev) {
6683 		dev_err(&intf->dev, "Out of memory\n");
6684 		return -ENOMEM;
6685 	}
6686 
6687 	SET_NETDEV_DEV(netdev, &intf->dev);
6688 	tp = netdev_priv(netdev);
6689 	tp->msg_enable = 0x7FFF;
6690 
6691 	tp->udev = udev;
6692 	tp->netdev = netdev;
6693 	tp->intf = intf;
6694 	tp->version = version;
6695 
6696 	switch (version) {
6697 	case RTL_VER_01:
6698 	case RTL_VER_02:
6699 	case RTL_VER_07:
6700 		tp->mii.supports_gmii = 0;
6701 		break;
6702 	default:
6703 		tp->mii.supports_gmii = 1;
6704 		break;
6705 	}
6706 
6707 	ret = rtl_ops_init(tp);
6708 	if (ret)
6709 		goto out;
6710 
6711 	rtl_fw_init(tp);
6712 
6713 	mutex_init(&tp->control);
6714 	INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t);
6715 	INIT_DELAYED_WORK(&tp->hw_phy_work, rtl_hw_phy_work_func_t);
6716 	tasklet_init(&tp->tx_tl, bottom_half, (unsigned long)tp);
6717 	tasklet_disable(&tp->tx_tl);
6718 
6719 	netdev->netdev_ops = &rtl8152_netdev_ops;
6720 	netdev->watchdog_timeo = RTL8152_TX_TIMEOUT;
6721 
6722 	netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
6723 			    NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM |
6724 			    NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_RX |
6725 			    NETIF_F_HW_VLAN_CTAG_TX;
6726 	netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
6727 			      NETIF_F_TSO | NETIF_F_FRAGLIST |
6728 			      NETIF_F_IPV6_CSUM | NETIF_F_TSO6 |
6729 			      NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX;
6730 	netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
6731 				NETIF_F_HIGHDMA | NETIF_F_FRAGLIST |
6732 				NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
6733 
6734 	if (tp->version == RTL_VER_01) {
6735 		netdev->features &= ~NETIF_F_RXCSUM;
6736 		netdev->hw_features &= ~NETIF_F_RXCSUM;
6737 	}
6738 
6739 	if (le16_to_cpu(udev->descriptor.idVendor) == VENDOR_ID_LENOVO) {
6740 		switch (le16_to_cpu(udev->descriptor.idProduct)) {
6741 		case DEVICE_ID_THINKPAD_THUNDERBOLT3_DOCK_GEN2:
6742 		case DEVICE_ID_THINKPAD_USB_C_DOCK_GEN2:
6743 			set_bit(LENOVO_MACPASSTHRU, &tp->flags);
6744 		}
6745 	}
6746 
6747 	if (le16_to_cpu(udev->descriptor.bcdDevice) == 0x3011 && udev->serial &&
6748 	    (!strcmp(udev->serial, "000001000000") ||
6749 	     !strcmp(udev->serial, "000002000000"))) {
6750 		dev_info(&udev->dev, "Dell TB16 Dock, disable RX aggregation");
6751 		set_bit(DELL_TB_RX_AGG_BUG, &tp->flags);
6752 	}
6753 
6754 	netdev->ethtool_ops = &ops;
6755 	netif_set_gso_max_size(netdev, RTL_LIMITED_TSO_SIZE);
6756 
6757 	/* MTU range: 68 - 1500 or 9194 */
6758 	netdev->min_mtu = ETH_MIN_MTU;
6759 	switch (tp->version) {
6760 	case RTL_VER_01:
6761 	case RTL_VER_02:
6762 		netdev->max_mtu = ETH_DATA_LEN;
6763 		break;
6764 	default:
6765 		netdev->max_mtu = RTL8153_MAX_MTU;
6766 		break;
6767 	}
6768 
6769 	tp->mii.dev = netdev;
6770 	tp->mii.mdio_read = read_mii_word;
6771 	tp->mii.mdio_write = write_mii_word;
6772 	tp->mii.phy_id_mask = 0x3f;
6773 	tp->mii.reg_num_mask = 0x1f;
6774 	tp->mii.phy_id = R8152_PHY_ID;
6775 
6776 	tp->autoneg = AUTONEG_ENABLE;
6777 	tp->speed = SPEED_100;
6778 	tp->advertising = RTL_ADVERTISED_10_HALF | RTL_ADVERTISED_10_FULL |
6779 			  RTL_ADVERTISED_100_HALF | RTL_ADVERTISED_100_FULL;
6780 	if (tp->mii.supports_gmii) {
6781 		tp->speed = SPEED_1000;
6782 		tp->advertising |= RTL_ADVERTISED_1000_FULL;
6783 	}
6784 	tp->duplex = DUPLEX_FULL;
6785 
6786 	tp->rx_copybreak = RTL8152_RXFG_HEADSZ;
6787 	tp->rx_pending = 10 * RTL8152_MAX_RX;
6788 
6789 	intf->needs_remote_wakeup = 1;
6790 
6791 	if (!rtl_can_wakeup(tp))
6792 		__rtl_set_wol(tp, 0);
6793 	else
6794 		tp->saved_wolopts = __rtl_get_wol(tp);
6795 
6796 	tp->rtl_ops.init(tp);
6797 #if IS_BUILTIN(CONFIG_USB_RTL8152)
6798 	/* Retry in case request_firmware() is not ready yet. */
6799 	tp->rtl_fw.retry = true;
6800 #endif
6801 	queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0);
6802 	set_ethernet_addr(tp);
6803 
6804 	usb_set_intfdata(intf, tp);
6805 	netif_napi_add(netdev, &tp->napi, r8152_poll, RTL8152_NAPI_WEIGHT);
6806 
6807 	ret = register_netdev(netdev);
6808 	if (ret != 0) {
6809 		netif_err(tp, probe, netdev, "couldn't register the device\n");
6810 		goto out1;
6811 	}
6812 
6813 	if (tp->saved_wolopts)
6814 		device_set_wakeup_enable(&udev->dev, true);
6815 	else
6816 		device_set_wakeup_enable(&udev->dev, false);
6817 
6818 	netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION);
6819 
6820 	return 0;
6821 
6822 out1:
6823 	tasklet_kill(&tp->tx_tl);
6824 	usb_set_intfdata(intf, NULL);
6825 out:
6826 	free_netdev(netdev);
6827 	return ret;
6828 }
6829 
rtl8152_disconnect(struct usb_interface * intf)6830 static void rtl8152_disconnect(struct usb_interface *intf)
6831 {
6832 	struct r8152 *tp = usb_get_intfdata(intf);
6833 
6834 	usb_set_intfdata(intf, NULL);
6835 	if (tp) {
6836 		rtl_set_unplug(tp);
6837 
6838 		unregister_netdev(tp->netdev);
6839 		tasklet_kill(&tp->tx_tl);
6840 		cancel_delayed_work_sync(&tp->hw_phy_work);
6841 		tp->rtl_ops.unload(tp);
6842 		rtl8152_release_firmware(tp);
6843 		free_netdev(tp->netdev);
6844 	}
6845 }
6846 
6847 #define REALTEK_USB_DEVICE(vend, prod)	\
6848 	.match_flags = USB_DEVICE_ID_MATCH_DEVICE | \
6849 		       USB_DEVICE_ID_MATCH_INT_CLASS, \
6850 	.idVendor = (vend), \
6851 	.idProduct = (prod), \
6852 	.bInterfaceClass = USB_CLASS_VENDOR_SPEC \
6853 }, \
6854 { \
6855 	.match_flags = USB_DEVICE_ID_MATCH_INT_INFO | \
6856 		       USB_DEVICE_ID_MATCH_DEVICE, \
6857 	.idVendor = (vend), \
6858 	.idProduct = (prod), \
6859 	.bInterfaceClass = USB_CLASS_COMM, \
6860 	.bInterfaceSubClass = USB_CDC_SUBCLASS_ETHERNET, \
6861 	.bInterfaceProtocol = USB_CDC_PROTO_NONE
6862 
6863 /* table of devices that work with this driver */
6864 static const struct usb_device_id rtl8152_table[] = {
6865 	{REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8050)},
6866 	{REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8152)},
6867 	{REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8153)},
6868 	{REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07ab)},
6869 	{REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07c6)},
6870 	{REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x0927)},
6871 	{REALTEK_USB_DEVICE(VENDOR_ID_SAMSUNG, 0xa101)},
6872 	{REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x304f)},
6873 	{REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x3054)},
6874 	{REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x3062)},
6875 	{REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x3069)},
6876 	{REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x3082)},
6877 	{REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x7205)},
6878 	{REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x720c)},
6879 	{REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x7214)},
6880 	{REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x721e)},
6881 	{REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0xa387)},
6882 	{REALTEK_USB_DEVICE(VENDOR_ID_LINKSYS, 0x0041)},
6883 	{REALTEK_USB_DEVICE(VENDOR_ID_NVIDIA,  0x09ff)},
6884 	{REALTEK_USB_DEVICE(VENDOR_ID_TPLINK,  0x0601)},
6885 	{}
6886 };
6887 
6888 MODULE_DEVICE_TABLE(usb, rtl8152_table);
6889 
6890 static struct usb_driver rtl8152_driver = {
6891 	.name =		MODULENAME,
6892 	.id_table =	rtl8152_table,
6893 	.probe =	rtl8152_probe,
6894 	.disconnect =	rtl8152_disconnect,
6895 	.suspend =	rtl8152_suspend,
6896 	.resume =	rtl8152_resume,
6897 	.reset_resume =	rtl8152_reset_resume,
6898 	.pre_reset =	rtl8152_pre_reset,
6899 	.post_reset =	rtl8152_post_reset,
6900 	.supports_autosuspend = 1,
6901 	.disable_hub_initiated_lpm = 1,
6902 };
6903 
6904 module_usb_driver(rtl8152_driver);
6905 
6906 MODULE_AUTHOR(DRIVER_AUTHOR);
6907 MODULE_DESCRIPTION(DRIVER_DESC);
6908 MODULE_LICENSE("GPL");
6909 MODULE_VERSION(DRIVER_VERSION);
6910