1 /******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
8 * Copyright(c) 2018 - 2021 Intel Corporation
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of version 2 of the GNU General Public License as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
18 *
19 * BSD LICENSE
20 *
21 * Copyright(c) 2018 - 2020 Intel Corporation
22 * All rights reserved.
23 *
24 * Redistribution and use in source and binary forms, with or without
25 * modification, are permitted provided that the following conditions
26 * are met:
27 *
28 * * Redistributions of source code must retain the above copyright
29 * notice, this list of conditions and the following disclaimer.
30 * * Redistributions in binary form must reproduce the above copyright
31 * notice, this list of conditions and the following disclaimer in
32 * the documentation and/or other materials provided with the
33 * distribution.
34 * * Neither the name Intel Corporation nor the names of its
35 * contributors may be used to endorse or promote products derived
36 * from this software without specific prior written permission.
37 *
38 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
39 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
40 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
41 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
42 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
43 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
44 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
45 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
46 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
47 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
48 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
49 *
50 *****************************************************************************/
51
52 #include "iwl-trans.h"
53 #include "iwl-fh.h"
54 #include "iwl-context-info-gen3.h"
55 #include "internal.h"
56 #include "iwl-prph.h"
57
58 static void
iwl_pcie_ctxt_info_dbg_enable(struct iwl_trans * trans,struct iwl_prph_scratch_hwm_cfg * dbg_cfg,u32 * control_flags)59 iwl_pcie_ctxt_info_dbg_enable(struct iwl_trans *trans,
60 struct iwl_prph_scratch_hwm_cfg *dbg_cfg,
61 u32 *control_flags)
62 {
63 enum iwl_fw_ini_allocation_id alloc_id = IWL_FW_INI_ALLOCATION_ID_DBGC1;
64 struct iwl_fw_ini_allocation_tlv *fw_mon_cfg;
65 u32 dbg_flags = 0;
66
67 if (!iwl_trans_dbg_ini_valid(trans)) {
68 struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon;
69
70 iwl_pcie_alloc_fw_monitor(trans, 0);
71
72 if (fw_mon->size) {
73 dbg_flags |= IWL_PRPH_SCRATCH_EDBG_DEST_DRAM;
74
75 IWL_DEBUG_FW(trans,
76 "WRT: Applying DRAM buffer destination\n");
77
78 dbg_cfg->hwm_base_addr = cpu_to_le64(fw_mon->physical);
79 dbg_cfg->hwm_size = cpu_to_le32(fw_mon->size);
80 }
81
82 goto out;
83 }
84
85 fw_mon_cfg = &trans->dbg.fw_mon_cfg[alloc_id];
86
87 switch (le32_to_cpu(fw_mon_cfg->buf_location)) {
88 case IWL_FW_INI_LOCATION_SRAM_PATH:
89 dbg_flags |= IWL_PRPH_SCRATCH_EDBG_DEST_INTERNAL;
90 IWL_DEBUG_FW(trans,
91 "WRT: Applying SMEM buffer destination\n");
92 break;
93
94 case IWL_FW_INI_LOCATION_NPK_PATH:
95 dbg_flags |= IWL_PRPH_SCRATCH_EDBG_DEST_TB22DTF;
96 IWL_DEBUG_FW(trans,
97 "WRT: Applying NPK buffer destination\n");
98 break;
99
100 case IWL_FW_INI_LOCATION_DRAM_PATH:
101 if (trans->dbg.fw_mon_ini[alloc_id].num_frags) {
102 struct iwl_dram_data *frag =
103 &trans->dbg.fw_mon_ini[alloc_id].frags[0];
104 dbg_flags |= IWL_PRPH_SCRATCH_EDBG_DEST_DRAM;
105 dbg_cfg->hwm_base_addr = cpu_to_le64(frag->physical);
106 dbg_cfg->hwm_size = cpu_to_le32(frag->size);
107 IWL_DEBUG_FW(trans,
108 "WRT: Applying DRAM destination (alloc_id=%u, num_frags=%u)\n",
109 alloc_id,
110 trans->dbg.fw_mon_ini[alloc_id].num_frags);
111 }
112 break;
113 default:
114 IWL_ERR(trans, "WRT: Invalid buffer destination\n");
115 }
116 out:
117 if (dbg_flags)
118 *control_flags |= IWL_PRPH_SCRATCH_EARLY_DEBUG_EN | dbg_flags;
119 }
120
iwl_pcie_ctxt_info_gen3_init(struct iwl_trans * trans,const struct fw_img * fw)121 int iwl_pcie_ctxt_info_gen3_init(struct iwl_trans *trans,
122 const struct fw_img *fw)
123 {
124 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
125 struct iwl_context_info_gen3 *ctxt_info_gen3;
126 struct iwl_prph_scratch *prph_scratch;
127 struct iwl_prph_scratch_ctrl_cfg *prph_sc_ctrl;
128 struct iwl_prph_info *prph_info;
129 u32 control_flags = 0;
130 int ret;
131 int cmdq_size = max_t(u32, IWL_CMD_QUEUE_SIZE,
132 trans->cfg->min_txq_size);
133
134 switch (trans_pcie->rx_buf_size) {
135 case IWL_AMSDU_DEF:
136 return -EINVAL;
137 case IWL_AMSDU_2K:
138 break;
139 case IWL_AMSDU_4K:
140 control_flags |= IWL_PRPH_SCRATCH_RB_SIZE_4K;
141 break;
142 case IWL_AMSDU_8K:
143 control_flags |= IWL_PRPH_SCRATCH_RB_SIZE_4K;
144 /* if firmware supports the ext size, tell it */
145 control_flags |= IWL_PRPH_SCRATCH_RB_SIZE_EXT_8K;
146 break;
147 case IWL_AMSDU_12K:
148 control_flags |= IWL_PRPH_SCRATCH_RB_SIZE_4K;
149 /* if firmware supports the ext size, tell it */
150 control_flags |= IWL_PRPH_SCRATCH_RB_SIZE_EXT_12K;
151 break;
152 }
153
154 /* Allocate prph scratch */
155 prph_scratch = dma_alloc_coherent(trans->dev, sizeof(*prph_scratch),
156 &trans_pcie->prph_scratch_dma_addr,
157 GFP_KERNEL);
158 if (!prph_scratch)
159 return -ENOMEM;
160
161 prph_sc_ctrl = &prph_scratch->ctrl_cfg;
162
163 prph_sc_ctrl->version.version = 0;
164 prph_sc_ctrl->version.mac_id =
165 cpu_to_le16((u16)iwl_read32(trans, CSR_HW_REV));
166 prph_sc_ctrl->version.size = cpu_to_le16(sizeof(*prph_scratch) / 4);
167
168 control_flags |= IWL_PRPH_SCRATCH_MTR_MODE;
169 control_flags |= IWL_PRPH_MTR_FORMAT_256B & IWL_PRPH_SCRATCH_MTR_FORMAT;
170
171 /* initialize RX default queue */
172 prph_sc_ctrl->rbd_cfg.free_rbd_addr =
173 cpu_to_le64(trans_pcie->rxq->bd_dma);
174
175 iwl_pcie_ctxt_info_dbg_enable(trans, &prph_sc_ctrl->hwm_cfg,
176 &control_flags);
177 prph_sc_ctrl->control.control_flags = cpu_to_le32(control_flags);
178
179 /* allocate ucode sections in dram and set addresses */
180 ret = iwl_pcie_init_fw_sec(trans, fw, &prph_scratch->dram);
181 if (ret)
182 goto err_free_prph_scratch;
183
184
185 /* Allocate prph information
186 * currently we don't assign to the prph info anything, but it would get
187 * assigned later */
188 prph_info = dma_alloc_coherent(trans->dev, sizeof(*prph_info),
189 &trans_pcie->prph_info_dma_addr,
190 GFP_KERNEL);
191 if (!prph_info) {
192 ret = -ENOMEM;
193 goto err_free_prph_scratch;
194 }
195
196 /* Allocate context info */
197 ctxt_info_gen3 = dma_alloc_coherent(trans->dev,
198 sizeof(*ctxt_info_gen3),
199 &trans_pcie->ctxt_info_dma_addr,
200 GFP_KERNEL);
201 if (!ctxt_info_gen3) {
202 ret = -ENOMEM;
203 goto err_free_prph_info;
204 }
205
206 ctxt_info_gen3->prph_info_base_addr =
207 cpu_to_le64(trans_pcie->prph_info_dma_addr);
208 ctxt_info_gen3->prph_scratch_base_addr =
209 cpu_to_le64(trans_pcie->prph_scratch_dma_addr);
210 ctxt_info_gen3->prph_scratch_size =
211 cpu_to_le32(sizeof(*prph_scratch));
212 ctxt_info_gen3->cr_head_idx_arr_base_addr =
213 cpu_to_le64(trans_pcie->rxq->rb_stts_dma);
214 ctxt_info_gen3->tr_tail_idx_arr_base_addr =
215 cpu_to_le64(trans_pcie->rxq->tr_tail_dma);
216 ctxt_info_gen3->cr_tail_idx_arr_base_addr =
217 cpu_to_le64(trans_pcie->rxq->cr_tail_dma);
218 ctxt_info_gen3->cr_idx_arr_size =
219 cpu_to_le16(IWL_NUM_OF_COMPLETION_RINGS);
220 ctxt_info_gen3->tr_idx_arr_size =
221 cpu_to_le16(IWL_NUM_OF_TRANSFER_RINGS);
222 ctxt_info_gen3->mtr_base_addr =
223 cpu_to_le64(trans->txqs.txq[trans->txqs.cmd.q_id]->dma_addr);
224 ctxt_info_gen3->mcr_base_addr =
225 cpu_to_le64(trans_pcie->rxq->used_bd_dma);
226 ctxt_info_gen3->mtr_size =
227 cpu_to_le16(TFD_QUEUE_CB_SIZE(cmdq_size));
228 ctxt_info_gen3->mcr_size =
229 cpu_to_le16(RX_QUEUE_CB_SIZE(trans->cfg->num_rbds));
230
231 trans_pcie->ctxt_info_gen3 = ctxt_info_gen3;
232 trans_pcie->prph_info = prph_info;
233 trans_pcie->prph_scratch = prph_scratch;
234
235 /* Allocate IML */
236 trans_pcie->iml = dma_alloc_coherent(trans->dev, trans->iml_len,
237 &trans_pcie->iml_dma_addr,
238 GFP_KERNEL);
239 if (!trans_pcie->iml) {
240 ret = -ENOMEM;
241 goto err_free_ctxt_info;
242 }
243
244 memcpy(trans_pcie->iml, trans->iml, trans->iml_len);
245
246 iwl_enable_fw_load_int_ctx_info(trans);
247
248 /* kick FW self load */
249 iwl_write64(trans, CSR_CTXT_INFO_ADDR,
250 trans_pcie->ctxt_info_dma_addr);
251 iwl_write64(trans, CSR_IML_DATA_ADDR,
252 trans_pcie->iml_dma_addr);
253 iwl_write32(trans, CSR_IML_SIZE_ADDR, trans->iml_len);
254
255 iwl_set_bit(trans, CSR_CTXT_INFO_BOOT_CTRL,
256 CSR_AUTO_FUNC_BOOT_ENA);
257
258 return 0;
259
260 err_free_ctxt_info:
261 dma_free_coherent(trans->dev, sizeof(*trans_pcie->ctxt_info_gen3),
262 trans_pcie->ctxt_info_gen3,
263 trans_pcie->ctxt_info_dma_addr);
264 trans_pcie->ctxt_info_gen3 = NULL;
265 err_free_prph_info:
266 dma_free_coherent(trans->dev,
267 sizeof(*prph_info),
268 prph_info,
269 trans_pcie->prph_info_dma_addr);
270
271 err_free_prph_scratch:
272 dma_free_coherent(trans->dev,
273 sizeof(*prph_scratch),
274 prph_scratch,
275 trans_pcie->prph_scratch_dma_addr);
276 return ret;
277
278 }
279
iwl_pcie_ctxt_info_gen3_free(struct iwl_trans * trans)280 void iwl_pcie_ctxt_info_gen3_free(struct iwl_trans *trans)
281 {
282 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
283
284 if (!trans_pcie->ctxt_info_gen3)
285 return;
286
287 dma_free_coherent(trans->dev, sizeof(*trans_pcie->ctxt_info_gen3),
288 trans_pcie->ctxt_info_gen3,
289 trans_pcie->ctxt_info_dma_addr);
290 trans_pcie->ctxt_info_dma_addr = 0;
291 trans_pcie->ctxt_info_gen3 = NULL;
292
293 dma_free_coherent(trans->dev, trans->iml_len, trans_pcie->iml,
294 trans_pcie->iml_dma_addr);
295 trans_pcie->iml_dma_addr = 0;
296 trans_pcie->iml = NULL;
297
298 iwl_pcie_ctxt_info_free_fw_img(trans);
299
300 dma_free_coherent(trans->dev, sizeof(*trans_pcie->prph_scratch),
301 trans_pcie->prph_scratch,
302 trans_pcie->prph_scratch_dma_addr);
303 trans_pcie->prph_scratch_dma_addr = 0;
304 trans_pcie->prph_scratch = NULL;
305
306 dma_free_coherent(trans->dev, sizeof(*trans_pcie->prph_info),
307 trans_pcie->prph_info,
308 trans_pcie->prph_info_dma_addr);
309 trans_pcie->prph_info_dma_addr = 0;
310 trans_pcie->prph_info = NULL;
311 }
312
iwl_trans_pcie_ctx_info_gen3_set_pnvm(struct iwl_trans * trans,const void * data,u32 len)313 int iwl_trans_pcie_ctx_info_gen3_set_pnvm(struct iwl_trans *trans,
314 const void *data, u32 len)
315 {
316 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
317 struct iwl_prph_scratch_ctrl_cfg *prph_sc_ctrl =
318 &trans_pcie->prph_scratch->ctrl_cfg;
319 int ret;
320
321 if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_AX210)
322 return 0;
323
324 /* only allocate the DRAM if not allocated yet */
325 if (!trans->pnvm_loaded) {
326 if (WARN_ON(prph_sc_ctrl->pnvm_cfg.pnvm_size))
327 return -EBUSY;
328
329 ret = iwl_pcie_ctxt_info_alloc_dma(trans, data, len,
330 &trans_pcie->pnvm_dram);
331 if (ret < 0) {
332 IWL_DEBUG_FW(trans, "Failed to allocate PNVM DMA %d.\n",
333 ret);
334 return ret;
335 }
336 }
337
338 prph_sc_ctrl->pnvm_cfg.pnvm_base_addr =
339 cpu_to_le64(trans_pcie->pnvm_dram.physical);
340 prph_sc_ctrl->pnvm_cfg.pnvm_size =
341 cpu_to_le32(trans_pcie->pnvm_dram.size);
342
343 return 0;
344 }
345