1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Loongson PCI Host Controller Driver
4 *
5 * Copyright (C) 2020 Jiaxun Yang <jiaxun.yang@flygoat.com>
6 */
7
8 #include <linux/of_device.h>
9 #include <linux/of_pci.h>
10 #include <linux/pci.h>
11 #include <linux/pci_ids.h>
12
13 #include "../pci.h"
14
15 /* Device IDs */
16 #define DEV_LS2K_PCIE_PORT0 0x1a05
17 #define DEV_LS7A_PCIE_PORT0 0x7a09
18 #define DEV_LS7A_PCIE_PORT1 0x7a19
19 #define DEV_LS7A_PCIE_PORT2 0x7a29
20 #define DEV_LS7A_PCIE_PORT3 0x7a39
21 #define DEV_LS7A_PCIE_PORT4 0x7a49
22 #define DEV_LS7A_PCIE_PORT5 0x7a59
23 #define DEV_LS7A_PCIE_PORT6 0x7a69
24
25 #define DEV_LS2K_APB 0x7a02
26 #define DEV_LS7A_CONF 0x7a10
27 #define DEV_LS7A_LPC 0x7a0c
28
29 #define FLAG_CFG0 BIT(0)
30 #define FLAG_CFG1 BIT(1)
31 #define FLAG_DEV_FIX BIT(2)
32
33 struct loongson_pci {
34 void __iomem *cfg0_base;
35 void __iomem *cfg1_base;
36 struct platform_device *pdev;
37 u32 flags;
38 };
39
40 /* Fixup wrong class code in PCIe bridges */
bridge_class_quirk(struct pci_dev * dev)41 static void bridge_class_quirk(struct pci_dev *dev)
42 {
43 dev->class = PCI_CLASS_BRIDGE_PCI << 8;
44 }
45 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
46 DEV_LS7A_PCIE_PORT0, bridge_class_quirk);
47 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
48 DEV_LS7A_PCIE_PORT1, bridge_class_quirk);
49 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
50 DEV_LS7A_PCIE_PORT2, bridge_class_quirk);
51
system_bus_quirk(struct pci_dev * pdev)52 static void system_bus_quirk(struct pci_dev *pdev)
53 {
54 /*
55 * The address space consumed by these devices is outside the
56 * resources of the host bridge.
57 */
58 pdev->mmio_always_on = 1;
59 pdev->non_compliant_bars = 1;
60 }
61 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
62 DEV_LS2K_APB, system_bus_quirk);
63 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
64 DEV_LS7A_CONF, system_bus_quirk);
65 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
66 DEV_LS7A_LPC, system_bus_quirk);
67
loongson_mrrs_quirk(struct pci_dev * pdev)68 static void loongson_mrrs_quirk(struct pci_dev *pdev)
69 {
70 /*
71 * Some Loongson PCIe ports have h/w limitations of maximum read
72 * request size. They can't handle anything larger than this. So
73 * force this limit on any devices attached under these ports.
74 */
75 struct pci_host_bridge *bridge = pci_find_host_bridge(pdev->bus);
76
77 bridge->no_inc_mrrs = 1;
78 }
79 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
80 DEV_LS2K_PCIE_PORT0, loongson_mrrs_quirk);
81 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
82 DEV_LS7A_PCIE_PORT0, loongson_mrrs_quirk);
83 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
84 DEV_LS7A_PCIE_PORT1, loongson_mrrs_quirk);
85 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
86 DEV_LS7A_PCIE_PORT2, loongson_mrrs_quirk);
87 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
88 DEV_LS7A_PCIE_PORT3, loongson_mrrs_quirk);
89 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
90 DEV_LS7A_PCIE_PORT4, loongson_mrrs_quirk);
91 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
92 DEV_LS7A_PCIE_PORT5, loongson_mrrs_quirk);
93 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
94 DEV_LS7A_PCIE_PORT6, loongson_mrrs_quirk);
95
cfg1_map(struct loongson_pci * priv,int bus,unsigned int devfn,int where)96 static void __iomem *cfg1_map(struct loongson_pci *priv, int bus,
97 unsigned int devfn, int where)
98 {
99 unsigned long addroff = 0x0;
100
101 if (bus != 0)
102 addroff |= BIT(28); /* Type 1 Access */
103 addroff |= (where & 0xff) | ((where & 0xf00) << 16);
104 addroff |= (bus << 16) | (devfn << 8);
105 return priv->cfg1_base + addroff;
106 }
107
cfg0_map(struct loongson_pci * priv,int bus,unsigned int devfn,int where)108 static void __iomem *cfg0_map(struct loongson_pci *priv, int bus,
109 unsigned int devfn, int where)
110 {
111 unsigned long addroff = 0x0;
112
113 if (bus != 0)
114 addroff |= BIT(24); /* Type 1 Access */
115 addroff |= (bus << 16) | (devfn << 8) | where;
116 return priv->cfg0_base + addroff;
117 }
118
pci_loongson_map_bus(struct pci_bus * bus,unsigned int devfn,int where)119 static void __iomem *pci_loongson_map_bus(struct pci_bus *bus, unsigned int devfn,
120 int where)
121 {
122 unsigned char busnum = bus->number;
123 struct pci_host_bridge *bridge = pci_find_host_bridge(bus);
124 struct loongson_pci *priv = pci_host_bridge_priv(bridge);
125
126 /*
127 * Do not read more than one device on the bus other than
128 * the host bus. For our hardware the root bus is always bus 0.
129 */
130 if (priv->flags & FLAG_DEV_FIX && busnum != 0 &&
131 PCI_SLOT(devfn) > 0)
132 return NULL;
133
134 /* CFG0 can only access standard space */
135 if (where < PCI_CFG_SPACE_SIZE && priv->cfg0_base)
136 return cfg0_map(priv, busnum, devfn, where);
137
138 /* CFG1 can access extended space */
139 if (where < PCI_CFG_SPACE_EXP_SIZE && priv->cfg1_base)
140 return cfg1_map(priv, busnum, devfn, where);
141
142 return NULL;
143 }
144
loongson_map_irq(const struct pci_dev * dev,u8 slot,u8 pin)145 static int loongson_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
146 {
147 int irq;
148 u8 val;
149
150 irq = of_irq_parse_and_map_pci(dev, slot, pin);
151 if (irq > 0)
152 return irq;
153
154 /* Care i8259 legacy systems */
155 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &val);
156 /* i8259 only have 15 IRQs */
157 if (val > 15)
158 return 0;
159
160 return val;
161 }
162
163 /* H/w only accept 32-bit PCI operations */
164 static struct pci_ops loongson_pci_ops = {
165 .map_bus = pci_loongson_map_bus,
166 .read = pci_generic_config_read32,
167 .write = pci_generic_config_write32,
168 };
169
170 static const struct of_device_id loongson_pci_of_match[] = {
171 { .compatible = "loongson,ls2k-pci",
172 .data = (void *)(FLAG_CFG0 | FLAG_CFG1 | FLAG_DEV_FIX), },
173 { .compatible = "loongson,ls7a-pci",
174 .data = (void *)(FLAG_CFG0 | FLAG_CFG1 | FLAG_DEV_FIX), },
175 { .compatible = "loongson,rs780e-pci",
176 .data = (void *)(FLAG_CFG0), },
177 {}
178 };
179
loongson_pci_probe(struct platform_device * pdev)180 static int loongson_pci_probe(struct platform_device *pdev)
181 {
182 struct loongson_pci *priv;
183 struct device *dev = &pdev->dev;
184 struct device_node *node = dev->of_node;
185 struct pci_host_bridge *bridge;
186 struct resource *regs;
187
188 if (!node)
189 return -ENODEV;
190
191 bridge = devm_pci_alloc_host_bridge(dev, sizeof(*priv));
192 if (!bridge)
193 return -ENODEV;
194
195 priv = pci_host_bridge_priv(bridge);
196 priv->pdev = pdev;
197 priv->flags = (unsigned long)of_device_get_match_data(dev);
198
199 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
200 if (!regs) {
201 dev_err(dev, "missing mem resources for cfg0\n");
202 return -EINVAL;
203 }
204
205 priv->cfg0_base = devm_pci_remap_cfg_resource(dev, regs);
206 if (IS_ERR(priv->cfg0_base))
207 return PTR_ERR(priv->cfg0_base);
208
209 /* CFG1 is optional */
210 if (priv->flags & FLAG_CFG1) {
211 regs = platform_get_resource(pdev, IORESOURCE_MEM, 1);
212 if (!regs)
213 dev_info(dev, "missing mem resource for cfg1\n");
214 else {
215 priv->cfg1_base = devm_pci_remap_cfg_resource(dev, regs);
216 if (IS_ERR(priv->cfg1_base))
217 priv->cfg1_base = NULL;
218 }
219 }
220
221 bridge->sysdata = priv;
222 bridge->ops = &loongson_pci_ops;
223 bridge->map_irq = loongson_map_irq;
224
225 return pci_host_probe(bridge);
226 }
227
228 static struct platform_driver loongson_pci_driver = {
229 .driver = {
230 .name = "loongson-pci",
231 .of_match_table = loongson_pci_of_match,
232 },
233 .probe = loongson_pci_probe,
234 };
235 builtin_platform_driver(loongson_pci_driver);
236