1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Rockchip USB2.0 PHY with Innosilicon IP block driver
4 *
5 * Copyright (C) 2016 Fuzhou Rockchip Electronics Co., Ltd
6 */
7
8 #include <linux/clk.h>
9 #include <linux/clk-provider.h>
10 #include <linux/delay.h>
11 #include <linux/extcon-provider.h>
12 #include <linux/interrupt.h>
13 #include <linux/io.h>
14 #include <linux/gpio/consumer.h>
15 #include <linux/jiffies.h>
16 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/mutex.h>
19 #include <linux/of.h>
20 #include <linux/of_address.h>
21 #include <linux/of_irq.h>
22 #include <linux/of_platform.h>
23 #include <linux/phy/phy.h>
24 #include <linux/platform_device.h>
25 #include <linux/power_supply.h>
26 #include <linux/regmap.h>
27 #include <linux/mfd/syscon.h>
28 #include <linux/usb/of.h>
29 #include <linux/usb/otg.h>
30
31 #define BIT_WRITEABLE_SHIFT 16
32 #define SCHEDULE_DELAY (60 * HZ)
33 #define OTG_SCHEDULE_DELAY (2 * HZ)
34
35 enum rockchip_usb2phy_port_id {
36 USB2PHY_PORT_OTG,
37 USB2PHY_PORT_HOST,
38 USB2PHY_NUM_PORTS,
39 };
40
41 enum rockchip_usb2phy_host_state {
42 PHY_STATE_HS_ONLINE = 0,
43 PHY_STATE_DISCONNECT = 1,
44 PHY_STATE_CONNECT = 2,
45 PHY_STATE_FS_LS_ONLINE = 4,
46 };
47
48 /**
49 * enum usb_chg_state - Different states involved in USB charger detection.
50 * @USB_CHG_STATE_UNDEFINED: USB charger is not connected or detection
51 * process is not yet started.
52 * @USB_CHG_STATE_WAIT_FOR_DCD: Waiting for Data pins contact.
53 * @USB_CHG_STATE_DCD_DONE: Data pin contact is detected.
54 * @USB_CHG_STATE_PRIMARY_DONE: Primary detection is completed (Detects
55 * between SDP and DCP/CDP).
56 * @USB_CHG_STATE_SECONDARY_DONE: Secondary detection is completed (Detects
57 * between DCP and CDP).
58 * @USB_CHG_STATE_DETECTED: USB charger type is determined.
59 */
60 enum usb_chg_state {
61 USB_CHG_STATE_UNDEFINED = 0,
62 USB_CHG_STATE_WAIT_FOR_DCD,
63 USB_CHG_STATE_DCD_DONE,
64 USB_CHG_STATE_PRIMARY_DONE,
65 USB_CHG_STATE_SECONDARY_DONE,
66 USB_CHG_STATE_DETECTED,
67 };
68
69 static const unsigned int rockchip_usb2phy_extcon_cable[] = {
70 EXTCON_USB,
71 EXTCON_USB_HOST,
72 EXTCON_CHG_USB_SDP,
73 EXTCON_CHG_USB_CDP,
74 EXTCON_CHG_USB_DCP,
75 EXTCON_CHG_USB_SLOW,
76 EXTCON_NONE,
77 };
78
79 struct usb2phy_reg {
80 unsigned int offset;
81 unsigned int bitend;
82 unsigned int bitstart;
83 unsigned int disable;
84 unsigned int enable;
85 };
86
87 /**
88 * struct rockchip_chg_det_reg - usb charger detect registers
89 * @cp_det: charging port detected successfully.
90 * @dcp_det: dedicated charging port detected successfully.
91 * @dp_det: assert data pin connect successfully.
92 * @idm_sink_en: open dm sink curren.
93 * @idp_sink_en: open dp sink current.
94 * @idp_src_en: open dm source current.
95 * @rdm_pdwn_en: open dm pull down resistor.
96 * @vdm_src_en: open dm voltage source.
97 * @vdp_src_en: open dp voltage source.
98 * @opmode: utmi operational mode.
99 */
100 struct rockchip_chg_det_reg {
101 struct usb2phy_reg cp_det;
102 struct usb2phy_reg dcp_det;
103 struct usb2phy_reg dp_det;
104 struct usb2phy_reg idm_sink_en;
105 struct usb2phy_reg idp_sink_en;
106 struct usb2phy_reg idp_src_en;
107 struct usb2phy_reg rdm_pdwn_en;
108 struct usb2phy_reg vdm_src_en;
109 struct usb2phy_reg vdp_src_en;
110 struct usb2phy_reg opmode;
111 };
112
113 /**
114 * struct rockchip_usb2phy_port_cfg - usb-phy port configuration.
115 * @phy_sus: phy suspend register.
116 * @bvalid_det_en: vbus valid rise detection enable register.
117 * @bvalid_det_st: vbus valid rise detection status register.
118 * @bvalid_det_clr: vbus valid rise detection clear register.
119 * @ls_det_en: linestate detection enable register.
120 * @ls_det_st: linestate detection state register.
121 * @ls_det_clr: linestate detection clear register.
122 * @utmi_avalid: utmi vbus avalid status register.
123 * @utmi_bvalid: utmi vbus bvalid status register.
124 * @utmi_ls: utmi linestate state register.
125 * @utmi_hstdet: utmi host disconnect register.
126 */
127 struct rockchip_usb2phy_port_cfg {
128 struct usb2phy_reg phy_sus;
129 struct usb2phy_reg bvalid_det_en;
130 struct usb2phy_reg bvalid_det_st;
131 struct usb2phy_reg bvalid_det_clr;
132 struct usb2phy_reg ls_det_en;
133 struct usb2phy_reg ls_det_st;
134 struct usb2phy_reg ls_det_clr;
135 struct usb2phy_reg utmi_avalid;
136 struct usb2phy_reg utmi_bvalid;
137 struct usb2phy_reg utmi_ls;
138 struct usb2phy_reg utmi_hstdet;
139 };
140
141 /**
142 * struct rockchip_usb2phy_cfg - usb-phy configuration.
143 * @reg: the address offset of grf for usb-phy config.
144 * @num_ports: specify how many ports that the phy has.
145 * @clkout_ctl: keep on/turn off output clk of phy.
146 * @port_cfgs: usb-phy port configurations.
147 * @chg_det: charger detection registers.
148 */
149 struct rockchip_usb2phy_cfg {
150 unsigned int reg;
151 unsigned int num_ports;
152 struct usb2phy_reg clkout_ctl;
153 const struct rockchip_usb2phy_port_cfg port_cfgs[USB2PHY_NUM_PORTS];
154 const struct rockchip_chg_det_reg chg_det;
155 };
156
157 /**
158 * struct rockchip_usb2phy_port - usb-phy port data.
159 * @phy: generic phy.
160 * @port_id: flag for otg port or host port.
161 * @suspended: phy suspended flag.
162 * @vbus_attached: otg device vbus status.
163 * @bvalid_irq: IRQ number assigned for vbus valid rise detection.
164 * @ls_irq: IRQ number assigned for linestate detection.
165 * @otg_mux_irq: IRQ number which multiplex otg-id/otg-bvalid/linestate
166 * irqs to one irq in otg-port.
167 * @mutex: for register updating in sm_work.
168 * @chg_work: charge detect work.
169 * @otg_sm_work: OTG state machine work.
170 * @sm_work: HOST state machine work.
171 * @port_cfg: port register configuration, assigned by driver data.
172 * @event_nb: hold event notification callback.
173 * @state: define OTG enumeration states before device reset.
174 * @mode: the dr_mode of the controller.
175 */
176 struct rockchip_usb2phy_port {
177 struct phy *phy;
178 unsigned int port_id;
179 bool suspended;
180 bool vbus_attached;
181 int bvalid_irq;
182 int ls_irq;
183 int otg_mux_irq;
184 struct mutex mutex;
185 struct delayed_work chg_work;
186 struct delayed_work otg_sm_work;
187 struct delayed_work sm_work;
188 const struct rockchip_usb2phy_port_cfg *port_cfg;
189 struct notifier_block event_nb;
190 enum usb_otg_state state;
191 enum usb_dr_mode mode;
192 };
193
194 /**
195 * struct rockchip_usb2phy - usb2.0 phy driver data.
196 * @dev: pointer to device.
197 * @grf: General Register Files regmap.
198 * @usbgrf: USB General Register Files regmap.
199 * @clk: clock struct of phy input clk.
200 * @clk480m: clock struct of phy output clk.
201 * @clk480m_hw: clock struct of phy output clk management.
202 * @chg_state: states involved in USB charger detection.
203 * @chg_type: USB charger types.
204 * @dcd_retries: The retry count used to track Data contact
205 * detection process.
206 * @edev: extcon device for notification registration
207 * @phy_cfg: phy register configuration, assigned by driver data.
208 * @ports: phy port instance.
209 */
210 struct rockchip_usb2phy {
211 struct device *dev;
212 struct regmap *grf;
213 struct regmap *usbgrf;
214 struct clk *clk;
215 struct clk *clk480m;
216 struct clk_hw clk480m_hw;
217 enum usb_chg_state chg_state;
218 enum power_supply_type chg_type;
219 u8 dcd_retries;
220 struct extcon_dev *edev;
221 const struct rockchip_usb2phy_cfg *phy_cfg;
222 struct rockchip_usb2phy_port ports[USB2PHY_NUM_PORTS];
223 };
224
get_reg_base(struct rockchip_usb2phy * rphy)225 static inline struct regmap *get_reg_base(struct rockchip_usb2phy *rphy)
226 {
227 return rphy->usbgrf == NULL ? rphy->grf : rphy->usbgrf;
228 }
229
property_enable(struct regmap * base,const struct usb2phy_reg * reg,bool en)230 static inline int property_enable(struct regmap *base,
231 const struct usb2phy_reg *reg, bool en)
232 {
233 unsigned int val, mask, tmp;
234
235 tmp = en ? reg->enable : reg->disable;
236 mask = GENMASK(reg->bitend, reg->bitstart);
237 val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT);
238
239 return regmap_write(base, reg->offset, val);
240 }
241
property_enabled(struct regmap * base,const struct usb2phy_reg * reg)242 static inline bool property_enabled(struct regmap *base,
243 const struct usb2phy_reg *reg)
244 {
245 int ret;
246 unsigned int tmp, orig;
247 unsigned int mask = GENMASK(reg->bitend, reg->bitstart);
248
249 ret = regmap_read(base, reg->offset, &orig);
250 if (ret)
251 return false;
252
253 tmp = (orig & mask) >> reg->bitstart;
254 return tmp == reg->enable;
255 }
256
rockchip_usb2phy_clk480m_prepare(struct clk_hw * hw)257 static int rockchip_usb2phy_clk480m_prepare(struct clk_hw *hw)
258 {
259 struct rockchip_usb2phy *rphy =
260 container_of(hw, struct rockchip_usb2phy, clk480m_hw);
261 struct regmap *base = get_reg_base(rphy);
262 int ret;
263
264 /* turn on 480m clk output if it is off */
265 if (!property_enabled(base, &rphy->phy_cfg->clkout_ctl)) {
266 ret = property_enable(base, &rphy->phy_cfg->clkout_ctl, true);
267 if (ret)
268 return ret;
269
270 /* waiting for the clk become stable */
271 usleep_range(1200, 1300);
272 }
273
274 return 0;
275 }
276
rockchip_usb2phy_clk480m_unprepare(struct clk_hw * hw)277 static void rockchip_usb2phy_clk480m_unprepare(struct clk_hw *hw)
278 {
279 struct rockchip_usb2phy *rphy =
280 container_of(hw, struct rockchip_usb2phy, clk480m_hw);
281 struct regmap *base = get_reg_base(rphy);
282
283 /* turn off 480m clk output */
284 property_enable(base, &rphy->phy_cfg->clkout_ctl, false);
285 }
286
rockchip_usb2phy_clk480m_prepared(struct clk_hw * hw)287 static int rockchip_usb2phy_clk480m_prepared(struct clk_hw *hw)
288 {
289 struct rockchip_usb2phy *rphy =
290 container_of(hw, struct rockchip_usb2phy, clk480m_hw);
291 struct regmap *base = get_reg_base(rphy);
292
293 return property_enabled(base, &rphy->phy_cfg->clkout_ctl);
294 }
295
296 static unsigned long
rockchip_usb2phy_clk480m_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)297 rockchip_usb2phy_clk480m_recalc_rate(struct clk_hw *hw,
298 unsigned long parent_rate)
299 {
300 return 480000000;
301 }
302
303 static const struct clk_ops rockchip_usb2phy_clkout_ops = {
304 .prepare = rockchip_usb2phy_clk480m_prepare,
305 .unprepare = rockchip_usb2phy_clk480m_unprepare,
306 .is_prepared = rockchip_usb2phy_clk480m_prepared,
307 .recalc_rate = rockchip_usb2phy_clk480m_recalc_rate,
308 };
309
rockchip_usb2phy_clk480m_unregister(void * data)310 static void rockchip_usb2phy_clk480m_unregister(void *data)
311 {
312 struct rockchip_usb2phy *rphy = data;
313
314 of_clk_del_provider(rphy->dev->of_node);
315 clk_unregister(rphy->clk480m);
316 }
317
318 static int
rockchip_usb2phy_clk480m_register(struct rockchip_usb2phy * rphy)319 rockchip_usb2phy_clk480m_register(struct rockchip_usb2phy *rphy)
320 {
321 struct device_node *node = rphy->dev->of_node;
322 struct clk_init_data init;
323 const char *clk_name;
324 int ret;
325
326 init.flags = 0;
327 init.name = "clk_usbphy_480m";
328 init.ops = &rockchip_usb2phy_clkout_ops;
329
330 /* optional override of the clockname */
331 of_property_read_string(node, "clock-output-names", &init.name);
332
333 if (rphy->clk) {
334 clk_name = __clk_get_name(rphy->clk);
335 init.parent_names = &clk_name;
336 init.num_parents = 1;
337 } else {
338 init.parent_names = NULL;
339 init.num_parents = 0;
340 }
341
342 rphy->clk480m_hw.init = &init;
343
344 /* register the clock */
345 rphy->clk480m = clk_register(rphy->dev, &rphy->clk480m_hw);
346 if (IS_ERR(rphy->clk480m)) {
347 ret = PTR_ERR(rphy->clk480m);
348 goto err_ret;
349 }
350
351 ret = of_clk_add_provider(node, of_clk_src_simple_get, rphy->clk480m);
352 if (ret < 0)
353 goto err_clk_provider;
354
355 ret = devm_add_action(rphy->dev, rockchip_usb2phy_clk480m_unregister,
356 rphy);
357 if (ret < 0)
358 goto err_unreg_action;
359
360 return 0;
361
362 err_unreg_action:
363 of_clk_del_provider(node);
364 err_clk_provider:
365 clk_unregister(rphy->clk480m);
366 err_ret:
367 return ret;
368 }
369
rockchip_usb2phy_extcon_register(struct rockchip_usb2phy * rphy)370 static int rockchip_usb2phy_extcon_register(struct rockchip_usb2phy *rphy)
371 {
372 int ret;
373 struct device_node *node = rphy->dev->of_node;
374 struct extcon_dev *edev;
375
376 if (of_property_read_bool(node, "extcon")) {
377 edev = extcon_get_edev_by_phandle(rphy->dev, 0);
378 if (IS_ERR(edev)) {
379 if (PTR_ERR(edev) != -EPROBE_DEFER)
380 dev_err(rphy->dev, "Invalid or missing extcon\n");
381 return PTR_ERR(edev);
382 }
383 } else {
384 /* Initialize extcon device */
385 edev = devm_extcon_dev_allocate(rphy->dev,
386 rockchip_usb2phy_extcon_cable);
387
388 if (IS_ERR(edev))
389 return -ENOMEM;
390
391 ret = devm_extcon_dev_register(rphy->dev, edev);
392 if (ret) {
393 dev_err(rphy->dev, "failed to register extcon device\n");
394 return ret;
395 }
396 }
397
398 rphy->edev = edev;
399
400 return 0;
401 }
402
rockchip_usb2phy_init(struct phy * phy)403 static int rockchip_usb2phy_init(struct phy *phy)
404 {
405 struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
406 struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent);
407 int ret = 0;
408
409 mutex_lock(&rport->mutex);
410
411 if (rport->port_id == USB2PHY_PORT_OTG) {
412 if (rport->mode != USB_DR_MODE_HOST &&
413 rport->mode != USB_DR_MODE_UNKNOWN) {
414 /* clear bvalid status and enable bvalid detect irq */
415 ret = property_enable(rphy->grf,
416 &rport->port_cfg->bvalid_det_clr,
417 true);
418 if (ret)
419 goto out;
420
421 ret = property_enable(rphy->grf,
422 &rport->port_cfg->bvalid_det_en,
423 true);
424 if (ret)
425 goto out;
426
427 schedule_delayed_work(&rport->otg_sm_work,
428 OTG_SCHEDULE_DELAY * 3);
429 } else {
430 /* If OTG works in host only mode, do nothing. */
431 dev_dbg(&rport->phy->dev, "mode %d\n", rport->mode);
432 }
433 } else if (rport->port_id == USB2PHY_PORT_HOST) {
434 /* clear linestate and enable linestate detect irq */
435 ret = property_enable(rphy->grf,
436 &rport->port_cfg->ls_det_clr, true);
437 if (ret)
438 goto out;
439
440 ret = property_enable(rphy->grf,
441 &rport->port_cfg->ls_det_en, true);
442 if (ret)
443 goto out;
444
445 schedule_delayed_work(&rport->sm_work, SCHEDULE_DELAY);
446 }
447
448 out:
449 mutex_unlock(&rport->mutex);
450 return ret;
451 }
452
rockchip_usb2phy_power_on(struct phy * phy)453 static int rockchip_usb2phy_power_on(struct phy *phy)
454 {
455 struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
456 struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent);
457 struct regmap *base = get_reg_base(rphy);
458 int ret;
459
460 dev_dbg(&rport->phy->dev, "port power on\n");
461
462 if (!rport->suspended)
463 return 0;
464
465 ret = clk_prepare_enable(rphy->clk480m);
466 if (ret)
467 return ret;
468
469 ret = property_enable(base, &rport->port_cfg->phy_sus, false);
470 if (ret) {
471 clk_disable_unprepare(rphy->clk480m);
472 return ret;
473 }
474
475 /* waiting for the utmi_clk to become stable */
476 usleep_range(1500, 2000);
477
478 rport->suspended = false;
479 return 0;
480 }
481
rockchip_usb2phy_power_off(struct phy * phy)482 static int rockchip_usb2phy_power_off(struct phy *phy)
483 {
484 struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
485 struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent);
486 struct regmap *base = get_reg_base(rphy);
487 int ret;
488
489 dev_dbg(&rport->phy->dev, "port power off\n");
490
491 if (rport->suspended)
492 return 0;
493
494 ret = property_enable(base, &rport->port_cfg->phy_sus, true);
495 if (ret)
496 return ret;
497
498 rport->suspended = true;
499 clk_disable_unprepare(rphy->clk480m);
500
501 return 0;
502 }
503
rockchip_usb2phy_exit(struct phy * phy)504 static int rockchip_usb2phy_exit(struct phy *phy)
505 {
506 struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
507
508 if (rport->port_id == USB2PHY_PORT_OTG &&
509 rport->mode != USB_DR_MODE_HOST &&
510 rport->mode != USB_DR_MODE_UNKNOWN) {
511 cancel_delayed_work_sync(&rport->otg_sm_work);
512 cancel_delayed_work_sync(&rport->chg_work);
513 } else if (rport->port_id == USB2PHY_PORT_HOST)
514 cancel_delayed_work_sync(&rport->sm_work);
515
516 return 0;
517 }
518
519 static const struct phy_ops rockchip_usb2phy_ops = {
520 .init = rockchip_usb2phy_init,
521 .exit = rockchip_usb2phy_exit,
522 .power_on = rockchip_usb2phy_power_on,
523 .power_off = rockchip_usb2phy_power_off,
524 .owner = THIS_MODULE,
525 };
526
rockchip_usb2phy_otg_sm_work(struct work_struct * work)527 static void rockchip_usb2phy_otg_sm_work(struct work_struct *work)
528 {
529 struct rockchip_usb2phy_port *rport =
530 container_of(work, struct rockchip_usb2phy_port,
531 otg_sm_work.work);
532 struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
533 static unsigned int cable;
534 unsigned long delay;
535 bool vbus_attach, sch_work, notify_charger;
536
537 vbus_attach = property_enabled(rphy->grf,
538 &rport->port_cfg->utmi_bvalid);
539
540 sch_work = false;
541 notify_charger = false;
542 delay = OTG_SCHEDULE_DELAY;
543 dev_dbg(&rport->phy->dev, "%s otg sm work\n",
544 usb_otg_state_string(rport->state));
545
546 switch (rport->state) {
547 case OTG_STATE_UNDEFINED:
548 rport->state = OTG_STATE_B_IDLE;
549 if (!vbus_attach)
550 rockchip_usb2phy_power_off(rport->phy);
551 fallthrough;
552 case OTG_STATE_B_IDLE:
553 if (extcon_get_state(rphy->edev, EXTCON_USB_HOST) > 0) {
554 dev_dbg(&rport->phy->dev, "usb otg host connect\n");
555 rport->state = OTG_STATE_A_HOST;
556 rockchip_usb2phy_power_on(rport->phy);
557 return;
558 } else if (vbus_attach) {
559 dev_dbg(&rport->phy->dev, "vbus_attach\n");
560 switch (rphy->chg_state) {
561 case USB_CHG_STATE_UNDEFINED:
562 schedule_delayed_work(&rport->chg_work, 0);
563 return;
564 case USB_CHG_STATE_DETECTED:
565 switch (rphy->chg_type) {
566 case POWER_SUPPLY_TYPE_USB:
567 dev_dbg(&rport->phy->dev, "sdp cable is connected\n");
568 rockchip_usb2phy_power_on(rport->phy);
569 rport->state = OTG_STATE_B_PERIPHERAL;
570 notify_charger = true;
571 sch_work = true;
572 cable = EXTCON_CHG_USB_SDP;
573 break;
574 case POWER_SUPPLY_TYPE_USB_DCP:
575 dev_dbg(&rport->phy->dev, "dcp cable is connected\n");
576 rockchip_usb2phy_power_off(rport->phy);
577 notify_charger = true;
578 sch_work = true;
579 cable = EXTCON_CHG_USB_DCP;
580 break;
581 case POWER_SUPPLY_TYPE_USB_CDP:
582 dev_dbg(&rport->phy->dev, "cdp cable is connected\n");
583 rockchip_usb2phy_power_on(rport->phy);
584 rport->state = OTG_STATE_B_PERIPHERAL;
585 notify_charger = true;
586 sch_work = true;
587 cable = EXTCON_CHG_USB_CDP;
588 break;
589 default:
590 break;
591 }
592 break;
593 default:
594 break;
595 }
596 } else {
597 notify_charger = true;
598 rphy->chg_state = USB_CHG_STATE_UNDEFINED;
599 rphy->chg_type = POWER_SUPPLY_TYPE_UNKNOWN;
600 }
601
602 if (rport->vbus_attached != vbus_attach) {
603 rport->vbus_attached = vbus_attach;
604
605 if (notify_charger && rphy->edev) {
606 extcon_set_state_sync(rphy->edev,
607 cable, vbus_attach);
608 if (cable == EXTCON_CHG_USB_SDP)
609 extcon_set_state_sync(rphy->edev,
610 EXTCON_USB,
611 vbus_attach);
612 }
613 }
614 break;
615 case OTG_STATE_B_PERIPHERAL:
616 if (!vbus_attach) {
617 dev_dbg(&rport->phy->dev, "usb disconnect\n");
618 rphy->chg_state = USB_CHG_STATE_UNDEFINED;
619 rphy->chg_type = POWER_SUPPLY_TYPE_UNKNOWN;
620 rport->state = OTG_STATE_B_IDLE;
621 delay = 0;
622 rockchip_usb2phy_power_off(rport->phy);
623 }
624 sch_work = true;
625 break;
626 case OTG_STATE_A_HOST:
627 if (extcon_get_state(rphy->edev, EXTCON_USB_HOST) == 0) {
628 dev_dbg(&rport->phy->dev, "usb otg host disconnect\n");
629 rport->state = OTG_STATE_B_IDLE;
630 rockchip_usb2phy_power_off(rport->phy);
631 }
632 break;
633 default:
634 break;
635 }
636
637 if (sch_work)
638 schedule_delayed_work(&rport->otg_sm_work, delay);
639 }
640
chg_to_string(enum power_supply_type chg_type)641 static const char *chg_to_string(enum power_supply_type chg_type)
642 {
643 switch (chg_type) {
644 case POWER_SUPPLY_TYPE_USB:
645 return "USB_SDP_CHARGER";
646 case POWER_SUPPLY_TYPE_USB_DCP:
647 return "USB_DCP_CHARGER";
648 case POWER_SUPPLY_TYPE_USB_CDP:
649 return "USB_CDP_CHARGER";
650 default:
651 return "INVALID_CHARGER";
652 }
653 }
654
rockchip_chg_enable_dcd(struct rockchip_usb2phy * rphy,bool en)655 static void rockchip_chg_enable_dcd(struct rockchip_usb2phy *rphy,
656 bool en)
657 {
658 struct regmap *base = get_reg_base(rphy);
659
660 property_enable(base, &rphy->phy_cfg->chg_det.rdm_pdwn_en, en);
661 property_enable(base, &rphy->phy_cfg->chg_det.idp_src_en, en);
662 }
663
rockchip_chg_enable_primary_det(struct rockchip_usb2phy * rphy,bool en)664 static void rockchip_chg_enable_primary_det(struct rockchip_usb2phy *rphy,
665 bool en)
666 {
667 struct regmap *base = get_reg_base(rphy);
668
669 property_enable(base, &rphy->phy_cfg->chg_det.vdp_src_en, en);
670 property_enable(base, &rphy->phy_cfg->chg_det.idm_sink_en, en);
671 }
672
rockchip_chg_enable_secondary_det(struct rockchip_usb2phy * rphy,bool en)673 static void rockchip_chg_enable_secondary_det(struct rockchip_usb2phy *rphy,
674 bool en)
675 {
676 struct regmap *base = get_reg_base(rphy);
677
678 property_enable(base, &rphy->phy_cfg->chg_det.vdm_src_en, en);
679 property_enable(base, &rphy->phy_cfg->chg_det.idp_sink_en, en);
680 }
681
682 #define CHG_DCD_POLL_TIME (100 * HZ / 1000)
683 #define CHG_DCD_MAX_RETRIES 6
684 #define CHG_PRIMARY_DET_TIME (40 * HZ / 1000)
685 #define CHG_SECONDARY_DET_TIME (40 * HZ / 1000)
rockchip_chg_detect_work(struct work_struct * work)686 static void rockchip_chg_detect_work(struct work_struct *work)
687 {
688 struct rockchip_usb2phy_port *rport =
689 container_of(work, struct rockchip_usb2phy_port, chg_work.work);
690 struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
691 struct regmap *base = get_reg_base(rphy);
692 bool is_dcd, tmout, vout;
693 unsigned long delay;
694
695 dev_dbg(&rport->phy->dev, "chg detection work state = %d\n",
696 rphy->chg_state);
697 switch (rphy->chg_state) {
698 case USB_CHG_STATE_UNDEFINED:
699 if (!rport->suspended)
700 rockchip_usb2phy_power_off(rport->phy);
701 /* put the controller in non-driving mode */
702 property_enable(base, &rphy->phy_cfg->chg_det.opmode, false);
703 /* Start DCD processing stage 1 */
704 rockchip_chg_enable_dcd(rphy, true);
705 rphy->chg_state = USB_CHG_STATE_WAIT_FOR_DCD;
706 rphy->dcd_retries = 0;
707 delay = CHG_DCD_POLL_TIME;
708 break;
709 case USB_CHG_STATE_WAIT_FOR_DCD:
710 /* get data contact detection status */
711 is_dcd = property_enabled(rphy->grf,
712 &rphy->phy_cfg->chg_det.dp_det);
713 tmout = ++rphy->dcd_retries == CHG_DCD_MAX_RETRIES;
714 /* stage 2 */
715 if (is_dcd || tmout) {
716 /* stage 4 */
717 /* Turn off DCD circuitry */
718 rockchip_chg_enable_dcd(rphy, false);
719 /* Voltage Source on DP, Probe on DM */
720 rockchip_chg_enable_primary_det(rphy, true);
721 delay = CHG_PRIMARY_DET_TIME;
722 rphy->chg_state = USB_CHG_STATE_DCD_DONE;
723 } else {
724 /* stage 3 */
725 delay = CHG_DCD_POLL_TIME;
726 }
727 break;
728 case USB_CHG_STATE_DCD_DONE:
729 vout = property_enabled(rphy->grf,
730 &rphy->phy_cfg->chg_det.cp_det);
731 rockchip_chg_enable_primary_det(rphy, false);
732 if (vout) {
733 /* Voltage Source on DM, Probe on DP */
734 rockchip_chg_enable_secondary_det(rphy, true);
735 delay = CHG_SECONDARY_DET_TIME;
736 rphy->chg_state = USB_CHG_STATE_PRIMARY_DONE;
737 } else {
738 if (rphy->dcd_retries == CHG_DCD_MAX_RETRIES) {
739 /* floating charger found */
740 rphy->chg_type = POWER_SUPPLY_TYPE_USB_DCP;
741 rphy->chg_state = USB_CHG_STATE_DETECTED;
742 delay = 0;
743 } else {
744 rphy->chg_type = POWER_SUPPLY_TYPE_USB;
745 rphy->chg_state = USB_CHG_STATE_DETECTED;
746 delay = 0;
747 }
748 }
749 break;
750 case USB_CHG_STATE_PRIMARY_DONE:
751 vout = property_enabled(rphy->grf,
752 &rphy->phy_cfg->chg_det.dcp_det);
753 /* Turn off voltage source */
754 rockchip_chg_enable_secondary_det(rphy, false);
755 if (vout)
756 rphy->chg_type = POWER_SUPPLY_TYPE_USB_DCP;
757 else
758 rphy->chg_type = POWER_SUPPLY_TYPE_USB_CDP;
759 fallthrough;
760 case USB_CHG_STATE_SECONDARY_DONE:
761 rphy->chg_state = USB_CHG_STATE_DETECTED;
762 delay = 0;
763 fallthrough;
764 case USB_CHG_STATE_DETECTED:
765 /* put the controller in normal mode */
766 property_enable(base, &rphy->phy_cfg->chg_det.opmode, true);
767 rockchip_usb2phy_otg_sm_work(&rport->otg_sm_work.work);
768 dev_dbg(&rport->phy->dev, "charger = %s\n",
769 chg_to_string(rphy->chg_type));
770 return;
771 default:
772 return;
773 }
774
775 schedule_delayed_work(&rport->chg_work, delay);
776 }
777
778 /*
779 * The function manage host-phy port state and suspend/resume phy port
780 * to save power.
781 *
782 * we rely on utmi_linestate and utmi_hostdisconnect to identify whether
783 * devices is disconnect or not. Besides, we do not need care it is FS/LS
784 * disconnected or HS disconnected, actually, we just only need get the
785 * device is disconnected at last through rearm the delayed work,
786 * to suspend the phy port in _PHY_STATE_DISCONNECT_ case.
787 *
788 * NOTE: It may invoke *phy_powr_off or *phy_power_on which will invoke
789 * some clk related APIs, so do not invoke it from interrupt context directly.
790 */
rockchip_usb2phy_sm_work(struct work_struct * work)791 static void rockchip_usb2phy_sm_work(struct work_struct *work)
792 {
793 struct rockchip_usb2phy_port *rport =
794 container_of(work, struct rockchip_usb2phy_port, sm_work.work);
795 struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
796 unsigned int sh = rport->port_cfg->utmi_hstdet.bitend -
797 rport->port_cfg->utmi_hstdet.bitstart + 1;
798 unsigned int ul, uhd, state;
799 unsigned int ul_mask, uhd_mask;
800 int ret;
801
802 mutex_lock(&rport->mutex);
803
804 ret = regmap_read(rphy->grf, rport->port_cfg->utmi_ls.offset, &ul);
805 if (ret < 0)
806 goto next_schedule;
807
808 ret = regmap_read(rphy->grf, rport->port_cfg->utmi_hstdet.offset, &uhd);
809 if (ret < 0)
810 goto next_schedule;
811
812 uhd_mask = GENMASK(rport->port_cfg->utmi_hstdet.bitend,
813 rport->port_cfg->utmi_hstdet.bitstart);
814 ul_mask = GENMASK(rport->port_cfg->utmi_ls.bitend,
815 rport->port_cfg->utmi_ls.bitstart);
816
817 /* stitch on utmi_ls and utmi_hstdet as phy state */
818 state = ((uhd & uhd_mask) >> rport->port_cfg->utmi_hstdet.bitstart) |
819 (((ul & ul_mask) >> rport->port_cfg->utmi_ls.bitstart) << sh);
820
821 switch (state) {
822 case PHY_STATE_HS_ONLINE:
823 dev_dbg(&rport->phy->dev, "HS online\n");
824 break;
825 case PHY_STATE_FS_LS_ONLINE:
826 /*
827 * For FS/LS device, the online state share with connect state
828 * from utmi_ls and utmi_hstdet register, so we distinguish
829 * them via suspended flag.
830 *
831 * Plus, there are two cases, one is D- Line pull-up, and D+
832 * line pull-down, the state is 4; another is D+ line pull-up,
833 * and D- line pull-down, the state is 2.
834 */
835 if (!rport->suspended) {
836 /* D- line pull-up, D+ line pull-down */
837 dev_dbg(&rport->phy->dev, "FS/LS online\n");
838 break;
839 }
840 fallthrough;
841 case PHY_STATE_CONNECT:
842 if (rport->suspended) {
843 dev_dbg(&rport->phy->dev, "Connected\n");
844 rockchip_usb2phy_power_on(rport->phy);
845 rport->suspended = false;
846 } else {
847 /* D+ line pull-up, D- line pull-down */
848 dev_dbg(&rport->phy->dev, "FS/LS online\n");
849 }
850 break;
851 case PHY_STATE_DISCONNECT:
852 if (!rport->suspended) {
853 dev_dbg(&rport->phy->dev, "Disconnected\n");
854 rockchip_usb2phy_power_off(rport->phy);
855 rport->suspended = true;
856 }
857
858 /*
859 * activate the linestate detection to get the next device
860 * plug-in irq.
861 */
862 property_enable(rphy->grf, &rport->port_cfg->ls_det_clr, true);
863 property_enable(rphy->grf, &rport->port_cfg->ls_det_en, true);
864
865 /*
866 * we don't need to rearm the delayed work when the phy port
867 * is suspended.
868 */
869 mutex_unlock(&rport->mutex);
870 return;
871 default:
872 dev_dbg(&rport->phy->dev, "unknown phy state\n");
873 break;
874 }
875
876 next_schedule:
877 mutex_unlock(&rport->mutex);
878 schedule_delayed_work(&rport->sm_work, SCHEDULE_DELAY);
879 }
880
rockchip_usb2phy_linestate_irq(int irq,void * data)881 static irqreturn_t rockchip_usb2phy_linestate_irq(int irq, void *data)
882 {
883 struct rockchip_usb2phy_port *rport = data;
884 struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
885
886 if (!property_enabled(rphy->grf, &rport->port_cfg->ls_det_st))
887 return IRQ_NONE;
888
889 mutex_lock(&rport->mutex);
890
891 /* disable linestate detect irq and clear its status */
892 property_enable(rphy->grf, &rport->port_cfg->ls_det_en, false);
893 property_enable(rphy->grf, &rport->port_cfg->ls_det_clr, true);
894
895 mutex_unlock(&rport->mutex);
896
897 /*
898 * In this case for host phy port, a new device is plugged in,
899 * meanwhile, if the phy port is suspended, we need rearm the work to
900 * resume it and mange its states; otherwise, we do nothing about that.
901 */
902 if (rport->suspended && rport->port_id == USB2PHY_PORT_HOST)
903 rockchip_usb2phy_sm_work(&rport->sm_work.work);
904
905 return IRQ_HANDLED;
906 }
907
rockchip_usb2phy_bvalid_irq(int irq,void * data)908 static irqreturn_t rockchip_usb2phy_bvalid_irq(int irq, void *data)
909 {
910 struct rockchip_usb2phy_port *rport = data;
911 struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
912
913 if (!property_enabled(rphy->grf, &rport->port_cfg->bvalid_det_st))
914 return IRQ_NONE;
915
916 mutex_lock(&rport->mutex);
917
918 /* clear bvalid detect irq pending status */
919 property_enable(rphy->grf, &rport->port_cfg->bvalid_det_clr, true);
920
921 mutex_unlock(&rport->mutex);
922
923 rockchip_usb2phy_otg_sm_work(&rport->otg_sm_work.work);
924
925 return IRQ_HANDLED;
926 }
927
rockchip_usb2phy_otg_mux_irq(int irq,void * data)928 static irqreturn_t rockchip_usb2phy_otg_mux_irq(int irq, void *data)
929 {
930 struct rockchip_usb2phy_port *rport = data;
931 struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
932
933 if (property_enabled(rphy->grf, &rport->port_cfg->bvalid_det_st))
934 return rockchip_usb2phy_bvalid_irq(irq, data);
935 else
936 return IRQ_NONE;
937 }
938
rockchip_usb2phy_host_port_init(struct rockchip_usb2phy * rphy,struct rockchip_usb2phy_port * rport,struct device_node * child_np)939 static int rockchip_usb2phy_host_port_init(struct rockchip_usb2phy *rphy,
940 struct rockchip_usb2phy_port *rport,
941 struct device_node *child_np)
942 {
943 int ret;
944
945 rport->port_id = USB2PHY_PORT_HOST;
946 rport->port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_HOST];
947 rport->suspended = true;
948
949 mutex_init(&rport->mutex);
950 INIT_DELAYED_WORK(&rport->sm_work, rockchip_usb2phy_sm_work);
951
952 rport->ls_irq = of_irq_get_byname(child_np, "linestate");
953 if (rport->ls_irq < 0) {
954 dev_err(rphy->dev, "no linestate irq provided\n");
955 return rport->ls_irq;
956 }
957
958 ret = devm_request_threaded_irq(rphy->dev, rport->ls_irq, NULL,
959 rockchip_usb2phy_linestate_irq,
960 IRQF_ONESHOT,
961 "rockchip_usb2phy", rport);
962 if (ret) {
963 dev_err(rphy->dev, "failed to request linestate irq handle\n");
964 return ret;
965 }
966
967 return 0;
968 }
969
rockchip_otg_event(struct notifier_block * nb,unsigned long event,void * ptr)970 static int rockchip_otg_event(struct notifier_block *nb,
971 unsigned long event, void *ptr)
972 {
973 struct rockchip_usb2phy_port *rport =
974 container_of(nb, struct rockchip_usb2phy_port, event_nb);
975
976 schedule_delayed_work(&rport->otg_sm_work, OTG_SCHEDULE_DELAY);
977
978 return NOTIFY_DONE;
979 }
980
rockchip_usb2phy_otg_port_init(struct rockchip_usb2phy * rphy,struct rockchip_usb2phy_port * rport,struct device_node * child_np)981 static int rockchip_usb2phy_otg_port_init(struct rockchip_usb2phy *rphy,
982 struct rockchip_usb2phy_port *rport,
983 struct device_node *child_np)
984 {
985 int ret;
986
987 rport->port_id = USB2PHY_PORT_OTG;
988 rport->port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG];
989 rport->state = OTG_STATE_UNDEFINED;
990
991 /*
992 * set suspended flag to true, but actually don't
993 * put phy in suspend mode, it aims to enable usb
994 * phy and clock in power_on() called by usb controller
995 * driver during probe.
996 */
997 rport->suspended = true;
998 rport->vbus_attached = false;
999
1000 mutex_init(&rport->mutex);
1001
1002 rport->mode = of_usb_get_dr_mode_by_phy(child_np, -1);
1003 if (rport->mode == USB_DR_MODE_HOST ||
1004 rport->mode == USB_DR_MODE_UNKNOWN) {
1005 ret = 0;
1006 goto out;
1007 }
1008
1009 INIT_DELAYED_WORK(&rport->chg_work, rockchip_chg_detect_work);
1010 INIT_DELAYED_WORK(&rport->otg_sm_work, rockchip_usb2phy_otg_sm_work);
1011
1012 /*
1013 * Some SoCs use one interrupt with otg-id/otg-bvalid/linestate
1014 * interrupts muxed together, so probe the otg-mux interrupt first,
1015 * if not found, then look for the regular interrupts one by one.
1016 */
1017 rport->otg_mux_irq = of_irq_get_byname(child_np, "otg-mux");
1018 if (rport->otg_mux_irq > 0) {
1019 ret = devm_request_threaded_irq(rphy->dev, rport->otg_mux_irq,
1020 NULL,
1021 rockchip_usb2phy_otg_mux_irq,
1022 IRQF_ONESHOT,
1023 "rockchip_usb2phy_otg",
1024 rport);
1025 if (ret) {
1026 dev_err(rphy->dev,
1027 "failed to request otg-mux irq handle\n");
1028 goto out;
1029 }
1030 } else {
1031 rport->bvalid_irq = of_irq_get_byname(child_np, "otg-bvalid");
1032 if (rport->bvalid_irq < 0) {
1033 dev_err(rphy->dev, "no vbus valid irq provided\n");
1034 ret = rport->bvalid_irq;
1035 goto out;
1036 }
1037
1038 ret = devm_request_threaded_irq(rphy->dev, rport->bvalid_irq,
1039 NULL,
1040 rockchip_usb2phy_bvalid_irq,
1041 IRQF_ONESHOT,
1042 "rockchip_usb2phy_bvalid",
1043 rport);
1044 if (ret) {
1045 dev_err(rphy->dev,
1046 "failed to request otg-bvalid irq handle\n");
1047 goto out;
1048 }
1049 }
1050
1051 if (!IS_ERR(rphy->edev)) {
1052 rport->event_nb.notifier_call = rockchip_otg_event;
1053
1054 ret = devm_extcon_register_notifier(rphy->dev, rphy->edev,
1055 EXTCON_USB_HOST, &rport->event_nb);
1056 if (ret)
1057 dev_err(rphy->dev, "register USB HOST notifier failed\n");
1058 }
1059
1060 out:
1061 return ret;
1062 }
1063
rockchip_usb2phy_probe(struct platform_device * pdev)1064 static int rockchip_usb2phy_probe(struct platform_device *pdev)
1065 {
1066 struct device *dev = &pdev->dev;
1067 struct device_node *np = dev->of_node;
1068 struct device_node *child_np;
1069 struct phy_provider *provider;
1070 struct rockchip_usb2phy *rphy;
1071 const struct rockchip_usb2phy_cfg *phy_cfgs;
1072 const struct of_device_id *match;
1073 unsigned int reg;
1074 int index, ret;
1075
1076 rphy = devm_kzalloc(dev, sizeof(*rphy), GFP_KERNEL);
1077 if (!rphy)
1078 return -ENOMEM;
1079
1080 match = of_match_device(dev->driver->of_match_table, dev);
1081 if (!match || !match->data) {
1082 dev_err(dev, "phy configs are not assigned!\n");
1083 return -EINVAL;
1084 }
1085
1086 if (!dev->parent || !dev->parent->of_node)
1087 return -EINVAL;
1088
1089 rphy->grf = syscon_node_to_regmap(dev->parent->of_node);
1090 if (IS_ERR(rphy->grf))
1091 return PTR_ERR(rphy->grf);
1092
1093 if (of_device_is_compatible(np, "rockchip,rv1108-usb2phy")) {
1094 rphy->usbgrf =
1095 syscon_regmap_lookup_by_phandle(dev->of_node,
1096 "rockchip,usbgrf");
1097 if (IS_ERR(rphy->usbgrf))
1098 return PTR_ERR(rphy->usbgrf);
1099 } else {
1100 rphy->usbgrf = NULL;
1101 }
1102
1103 if (of_property_read_u32(np, "reg", ®)) {
1104 dev_err(dev, "the reg property is not assigned in %pOFn node\n",
1105 np);
1106 return -EINVAL;
1107 }
1108
1109 rphy->dev = dev;
1110 phy_cfgs = match->data;
1111 rphy->chg_state = USB_CHG_STATE_UNDEFINED;
1112 rphy->chg_type = POWER_SUPPLY_TYPE_UNKNOWN;
1113 platform_set_drvdata(pdev, rphy);
1114
1115 ret = rockchip_usb2phy_extcon_register(rphy);
1116 if (ret)
1117 return ret;
1118
1119 /* find out a proper config which can be matched with dt. */
1120 index = 0;
1121 while (phy_cfgs[index].reg) {
1122 if (phy_cfgs[index].reg == reg) {
1123 rphy->phy_cfg = &phy_cfgs[index];
1124 break;
1125 }
1126
1127 ++index;
1128 }
1129
1130 if (!rphy->phy_cfg) {
1131 dev_err(dev, "no phy-config can be matched with %pOFn node\n",
1132 np);
1133 return -EINVAL;
1134 }
1135
1136 rphy->clk = of_clk_get_by_name(np, "phyclk");
1137 if (!IS_ERR(rphy->clk)) {
1138 clk_prepare_enable(rphy->clk);
1139 } else {
1140 dev_info(&pdev->dev, "no phyclk specified\n");
1141 rphy->clk = NULL;
1142 }
1143
1144 ret = rockchip_usb2phy_clk480m_register(rphy);
1145 if (ret) {
1146 dev_err(dev, "failed to register 480m output clock\n");
1147 goto disable_clks;
1148 }
1149
1150 index = 0;
1151 for_each_available_child_of_node(np, child_np) {
1152 struct rockchip_usb2phy_port *rport = &rphy->ports[index];
1153 struct phy *phy;
1154
1155 /* This driver aims to support both otg-port and host-port */
1156 if (!of_node_name_eq(child_np, "host-port") &&
1157 !of_node_name_eq(child_np, "otg-port"))
1158 goto next_child;
1159
1160 phy = devm_phy_create(dev, child_np, &rockchip_usb2phy_ops);
1161 if (IS_ERR(phy)) {
1162 dev_err(dev, "failed to create phy\n");
1163 ret = PTR_ERR(phy);
1164 goto put_child;
1165 }
1166
1167 rport->phy = phy;
1168 phy_set_drvdata(rport->phy, rport);
1169
1170 /* initialize otg/host port separately */
1171 if (of_node_name_eq(child_np, "host-port")) {
1172 ret = rockchip_usb2phy_host_port_init(rphy, rport,
1173 child_np);
1174 if (ret)
1175 goto put_child;
1176 } else {
1177 ret = rockchip_usb2phy_otg_port_init(rphy, rport,
1178 child_np);
1179 if (ret)
1180 goto put_child;
1181 }
1182
1183 next_child:
1184 /* to prevent out of boundary */
1185 if (++index >= rphy->phy_cfg->num_ports)
1186 break;
1187 }
1188
1189 provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
1190 return PTR_ERR_OR_ZERO(provider);
1191
1192 put_child:
1193 of_node_put(child_np);
1194 disable_clks:
1195 if (rphy->clk) {
1196 clk_disable_unprepare(rphy->clk);
1197 clk_put(rphy->clk);
1198 }
1199 return ret;
1200 }
1201
1202 static const struct rockchip_usb2phy_cfg rk3228_phy_cfgs[] = {
1203 {
1204 .reg = 0x760,
1205 .num_ports = 2,
1206 .clkout_ctl = { 0x0768, 4, 4, 1, 0 },
1207 .port_cfgs = {
1208 [USB2PHY_PORT_OTG] = {
1209 .phy_sus = { 0x0760, 15, 0, 0, 0x1d1 },
1210 .bvalid_det_en = { 0x0680, 3, 3, 0, 1 },
1211 .bvalid_det_st = { 0x0690, 3, 3, 0, 1 },
1212 .bvalid_det_clr = { 0x06a0, 3, 3, 0, 1 },
1213 .ls_det_en = { 0x0680, 2, 2, 0, 1 },
1214 .ls_det_st = { 0x0690, 2, 2, 0, 1 },
1215 .ls_det_clr = { 0x06a0, 2, 2, 0, 1 },
1216 .utmi_bvalid = { 0x0480, 4, 4, 0, 1 },
1217 .utmi_ls = { 0x0480, 3, 2, 0, 1 },
1218 },
1219 [USB2PHY_PORT_HOST] = {
1220 .phy_sus = { 0x0764, 15, 0, 0, 0x1d1 },
1221 .ls_det_en = { 0x0680, 4, 4, 0, 1 },
1222 .ls_det_st = { 0x0690, 4, 4, 0, 1 },
1223 .ls_det_clr = { 0x06a0, 4, 4, 0, 1 }
1224 }
1225 },
1226 .chg_det = {
1227 .opmode = { 0x0760, 3, 0, 5, 1 },
1228 .cp_det = { 0x0884, 4, 4, 0, 1 },
1229 .dcp_det = { 0x0884, 3, 3, 0, 1 },
1230 .dp_det = { 0x0884, 5, 5, 0, 1 },
1231 .idm_sink_en = { 0x0768, 8, 8, 0, 1 },
1232 .idp_sink_en = { 0x0768, 7, 7, 0, 1 },
1233 .idp_src_en = { 0x0768, 9, 9, 0, 1 },
1234 .rdm_pdwn_en = { 0x0768, 10, 10, 0, 1 },
1235 .vdm_src_en = { 0x0768, 12, 12, 0, 1 },
1236 .vdp_src_en = { 0x0768, 11, 11, 0, 1 },
1237 },
1238 },
1239 {
1240 .reg = 0x800,
1241 .num_ports = 2,
1242 .clkout_ctl = { 0x0808, 4, 4, 1, 0 },
1243 .port_cfgs = {
1244 [USB2PHY_PORT_OTG] = {
1245 .phy_sus = { 0x800, 15, 0, 0, 0x1d1 },
1246 .ls_det_en = { 0x0684, 0, 0, 0, 1 },
1247 .ls_det_st = { 0x0694, 0, 0, 0, 1 },
1248 .ls_det_clr = { 0x06a4, 0, 0, 0, 1 }
1249 },
1250 [USB2PHY_PORT_HOST] = {
1251 .phy_sus = { 0x804, 15, 0, 0, 0x1d1 },
1252 .ls_det_en = { 0x0684, 1, 1, 0, 1 },
1253 .ls_det_st = { 0x0694, 1, 1, 0, 1 },
1254 .ls_det_clr = { 0x06a4, 1, 1, 0, 1 }
1255 }
1256 },
1257 },
1258 { /* sentinel */ }
1259 };
1260
1261 static const struct rockchip_usb2phy_cfg rk3328_phy_cfgs[] = {
1262 {
1263 .reg = 0x100,
1264 .num_ports = 2,
1265 .clkout_ctl = { 0x108, 4, 4, 1, 0 },
1266 .port_cfgs = {
1267 [USB2PHY_PORT_OTG] = {
1268 .phy_sus = { 0x0100, 15, 0, 0, 0x1d1 },
1269 .bvalid_det_en = { 0x0110, 2, 2, 0, 1 },
1270 .bvalid_det_st = { 0x0114, 2, 2, 0, 1 },
1271 .bvalid_det_clr = { 0x0118, 2, 2, 0, 1 },
1272 .ls_det_en = { 0x0110, 0, 0, 0, 1 },
1273 .ls_det_st = { 0x0114, 0, 0, 0, 1 },
1274 .ls_det_clr = { 0x0118, 0, 0, 0, 1 },
1275 .utmi_avalid = { 0x0120, 10, 10, 0, 1 },
1276 .utmi_bvalid = { 0x0120, 9, 9, 0, 1 },
1277 .utmi_ls = { 0x0120, 5, 4, 0, 1 },
1278 },
1279 [USB2PHY_PORT_HOST] = {
1280 .phy_sus = { 0x104, 15, 0, 0, 0x1d1 },
1281 .ls_det_en = { 0x110, 1, 1, 0, 1 },
1282 .ls_det_st = { 0x114, 1, 1, 0, 1 },
1283 .ls_det_clr = { 0x118, 1, 1, 0, 1 },
1284 .utmi_ls = { 0x120, 17, 16, 0, 1 },
1285 .utmi_hstdet = { 0x120, 19, 19, 0, 1 }
1286 }
1287 },
1288 .chg_det = {
1289 .opmode = { 0x0100, 3, 0, 5, 1 },
1290 .cp_det = { 0x0120, 24, 24, 0, 1 },
1291 .dcp_det = { 0x0120, 23, 23, 0, 1 },
1292 .dp_det = { 0x0120, 25, 25, 0, 1 },
1293 .idm_sink_en = { 0x0108, 8, 8, 0, 1 },
1294 .idp_sink_en = { 0x0108, 7, 7, 0, 1 },
1295 .idp_src_en = { 0x0108, 9, 9, 0, 1 },
1296 .rdm_pdwn_en = { 0x0108, 10, 10, 0, 1 },
1297 .vdm_src_en = { 0x0108, 12, 12, 0, 1 },
1298 .vdp_src_en = { 0x0108, 11, 11, 0, 1 },
1299 },
1300 },
1301 { /* sentinel */ }
1302 };
1303
1304 static const struct rockchip_usb2phy_cfg rk3366_phy_cfgs[] = {
1305 {
1306 .reg = 0x700,
1307 .num_ports = 2,
1308 .clkout_ctl = { 0x0724, 15, 15, 1, 0 },
1309 .port_cfgs = {
1310 [USB2PHY_PORT_HOST] = {
1311 .phy_sus = { 0x0728, 15, 0, 0, 0x1d1 },
1312 .ls_det_en = { 0x0680, 4, 4, 0, 1 },
1313 .ls_det_st = { 0x0690, 4, 4, 0, 1 },
1314 .ls_det_clr = { 0x06a0, 4, 4, 0, 1 },
1315 .utmi_ls = { 0x049c, 14, 13, 0, 1 },
1316 .utmi_hstdet = { 0x049c, 12, 12, 0, 1 }
1317 }
1318 },
1319 },
1320 { /* sentinel */ }
1321 };
1322
1323 static const struct rockchip_usb2phy_cfg rk3399_phy_cfgs[] = {
1324 {
1325 .reg = 0xe450,
1326 .num_ports = 2,
1327 .clkout_ctl = { 0xe450, 4, 4, 1, 0 },
1328 .port_cfgs = {
1329 [USB2PHY_PORT_OTG] = {
1330 .phy_sus = { 0xe454, 1, 0, 2, 1 },
1331 .bvalid_det_en = { 0xe3c0, 3, 3, 0, 1 },
1332 .bvalid_det_st = { 0xe3e0, 3, 3, 0, 1 },
1333 .bvalid_det_clr = { 0xe3d0, 3, 3, 0, 1 },
1334 .utmi_avalid = { 0xe2ac, 7, 7, 0, 1 },
1335 .utmi_bvalid = { 0xe2ac, 12, 12, 0, 1 },
1336 },
1337 [USB2PHY_PORT_HOST] = {
1338 .phy_sus = { 0xe458, 1, 0, 0x2, 0x1 },
1339 .ls_det_en = { 0xe3c0, 6, 6, 0, 1 },
1340 .ls_det_st = { 0xe3e0, 6, 6, 0, 1 },
1341 .ls_det_clr = { 0xe3d0, 6, 6, 0, 1 },
1342 .utmi_ls = { 0xe2ac, 22, 21, 0, 1 },
1343 .utmi_hstdet = { 0xe2ac, 23, 23, 0, 1 }
1344 }
1345 },
1346 .chg_det = {
1347 .opmode = { 0xe454, 3, 0, 5, 1 },
1348 .cp_det = { 0xe2ac, 2, 2, 0, 1 },
1349 .dcp_det = { 0xe2ac, 1, 1, 0, 1 },
1350 .dp_det = { 0xe2ac, 0, 0, 0, 1 },
1351 .idm_sink_en = { 0xe450, 8, 8, 0, 1 },
1352 .idp_sink_en = { 0xe450, 7, 7, 0, 1 },
1353 .idp_src_en = { 0xe450, 9, 9, 0, 1 },
1354 .rdm_pdwn_en = { 0xe450, 10, 10, 0, 1 },
1355 .vdm_src_en = { 0xe450, 12, 12, 0, 1 },
1356 .vdp_src_en = { 0xe450, 11, 11, 0, 1 },
1357 },
1358 },
1359 {
1360 .reg = 0xe460,
1361 .num_ports = 2,
1362 .clkout_ctl = { 0xe460, 4, 4, 1, 0 },
1363 .port_cfgs = {
1364 [USB2PHY_PORT_OTG] = {
1365 .phy_sus = { 0xe464, 1, 0, 2, 1 },
1366 .bvalid_det_en = { 0xe3c0, 8, 8, 0, 1 },
1367 .bvalid_det_st = { 0xe3e0, 8, 8, 0, 1 },
1368 .bvalid_det_clr = { 0xe3d0, 8, 8, 0, 1 },
1369 .utmi_avalid = { 0xe2ac, 10, 10, 0, 1 },
1370 .utmi_bvalid = { 0xe2ac, 16, 16, 0, 1 },
1371 },
1372 [USB2PHY_PORT_HOST] = {
1373 .phy_sus = { 0xe468, 1, 0, 0x2, 0x1 },
1374 .ls_det_en = { 0xe3c0, 11, 11, 0, 1 },
1375 .ls_det_st = { 0xe3e0, 11, 11, 0, 1 },
1376 .ls_det_clr = { 0xe3d0, 11, 11, 0, 1 },
1377 .utmi_ls = { 0xe2ac, 26, 25, 0, 1 },
1378 .utmi_hstdet = { 0xe2ac, 27, 27, 0, 1 }
1379 }
1380 },
1381 },
1382 { /* sentinel */ }
1383 };
1384
1385 static const struct rockchip_usb2phy_cfg rv1108_phy_cfgs[] = {
1386 {
1387 .reg = 0x100,
1388 .num_ports = 2,
1389 .clkout_ctl = { 0x108, 4, 4, 1, 0 },
1390 .port_cfgs = {
1391 [USB2PHY_PORT_OTG] = {
1392 .phy_sus = { 0x0100, 15, 0, 0, 0x1d1 },
1393 .bvalid_det_en = { 0x0680, 3, 3, 0, 1 },
1394 .bvalid_det_st = { 0x0690, 3, 3, 0, 1 },
1395 .bvalid_det_clr = { 0x06a0, 3, 3, 0, 1 },
1396 .ls_det_en = { 0x0680, 2, 2, 0, 1 },
1397 .ls_det_st = { 0x0690, 2, 2, 0, 1 },
1398 .ls_det_clr = { 0x06a0, 2, 2, 0, 1 },
1399 .utmi_bvalid = { 0x0804, 10, 10, 0, 1 },
1400 .utmi_ls = { 0x0804, 13, 12, 0, 1 },
1401 },
1402 [USB2PHY_PORT_HOST] = {
1403 .phy_sus = { 0x0104, 15, 0, 0, 0x1d1 },
1404 .ls_det_en = { 0x0680, 4, 4, 0, 1 },
1405 .ls_det_st = { 0x0690, 4, 4, 0, 1 },
1406 .ls_det_clr = { 0x06a0, 4, 4, 0, 1 },
1407 .utmi_ls = { 0x0804, 9, 8, 0, 1 },
1408 .utmi_hstdet = { 0x0804, 7, 7, 0, 1 }
1409 }
1410 },
1411 .chg_det = {
1412 .opmode = { 0x0100, 3, 0, 5, 1 },
1413 .cp_det = { 0x0804, 1, 1, 0, 1 },
1414 .dcp_det = { 0x0804, 0, 0, 0, 1 },
1415 .dp_det = { 0x0804, 2, 2, 0, 1 },
1416 .idm_sink_en = { 0x0108, 8, 8, 0, 1 },
1417 .idp_sink_en = { 0x0108, 7, 7, 0, 1 },
1418 .idp_src_en = { 0x0108, 9, 9, 0, 1 },
1419 .rdm_pdwn_en = { 0x0108, 10, 10, 0, 1 },
1420 .vdm_src_en = { 0x0108, 12, 12, 0, 1 },
1421 .vdp_src_en = { 0x0108, 11, 11, 0, 1 },
1422 },
1423 },
1424 { /* sentinel */ }
1425 };
1426
1427 static const struct of_device_id rockchip_usb2phy_dt_match[] = {
1428 { .compatible = "rockchip,px30-usb2phy", .data = &rk3328_phy_cfgs },
1429 { .compatible = "rockchip,rk3228-usb2phy", .data = &rk3228_phy_cfgs },
1430 { .compatible = "rockchip,rk3328-usb2phy", .data = &rk3328_phy_cfgs },
1431 { .compatible = "rockchip,rk3366-usb2phy", .data = &rk3366_phy_cfgs },
1432 { .compatible = "rockchip,rk3399-usb2phy", .data = &rk3399_phy_cfgs },
1433 { .compatible = "rockchip,rv1108-usb2phy", .data = &rv1108_phy_cfgs },
1434 {}
1435 };
1436 MODULE_DEVICE_TABLE(of, rockchip_usb2phy_dt_match);
1437
1438 static struct platform_driver rockchip_usb2phy_driver = {
1439 .probe = rockchip_usb2phy_probe,
1440 .driver = {
1441 .name = "rockchip-usb2phy",
1442 .of_match_table = rockchip_usb2phy_dt_match,
1443 },
1444 };
1445 module_platform_driver(rockchip_usb2phy_driver);
1446
1447 MODULE_AUTHOR("Frank Wang <frank.wang@rock-chips.com>");
1448 MODULE_DESCRIPTION("Rockchip USB2.0 PHY driver");
1449 MODULE_LICENSE("GPL v2");
1450