1 // SPDX-License-Identifier: GPL-2.0+
2 //
3 // Copyright (C) 2011-2012 Freescale Semiconductor, Inc.
4
5 #include <linux/init.h>
6 #include <linux/io.h>
7 #include <linux/kernel.h>
8 #include <linux/module.h>
9 #include <linux/of.h>
10 #include <linux/platform_device.h>
11 #include <linux/pm_wakeirq.h>
12 #include <linux/rtc.h>
13 #include <linux/clk.h>
14 #include <linux/mfd/syscon.h>
15 #include <linux/regmap.h>
16
17 #define SNVS_LPREGISTER_OFFSET 0x34
18
19 /* These register offsets are relative to LP (Low Power) range */
20 #define SNVS_LPCR 0x04
21 #define SNVS_LPSR 0x18
22 #define SNVS_LPSRTCMR 0x1c
23 #define SNVS_LPSRTCLR 0x20
24 #define SNVS_LPTAR 0x24
25 #define SNVS_LPPGDR 0x30
26
27 #define SNVS_LPCR_SRTC_ENV (1 << 0)
28 #define SNVS_LPCR_LPTA_EN (1 << 1)
29 #define SNVS_LPCR_LPWUI_EN (1 << 3)
30 #define SNVS_LPSR_LPTA (1 << 0)
31
32 #define SNVS_LPPGDR_INIT 0x41736166
33 #define CNTR_TO_SECS_SH 15
34
35 /* The maximum RTC clock cycles that are allowed to pass between two
36 * consecutive clock counter register reads. If the values are corrupted a
37 * bigger difference is expected. The RTC frequency is 32kHz. With 320 cycles
38 * we end at 10ms which should be enough for most cases. If it once takes
39 * longer than expected we do a retry.
40 */
41 #define MAX_RTC_READ_DIFF_CYCLES 320
42
43 struct snvs_rtc_data {
44 struct rtc_device *rtc;
45 struct regmap *regmap;
46 int offset;
47 int irq;
48 struct clk *clk;
49 };
50
51 /* Read 64 bit timer register, which could be in inconsistent state */
rtc_read_lpsrt(struct snvs_rtc_data * data)52 static u64 rtc_read_lpsrt(struct snvs_rtc_data *data)
53 {
54 u32 msb, lsb;
55
56 regmap_read(data->regmap, data->offset + SNVS_LPSRTCMR, &msb);
57 regmap_read(data->regmap, data->offset + SNVS_LPSRTCLR, &lsb);
58 return (u64)msb << 32 | lsb;
59 }
60
61 /* Read the secure real time counter, taking care to deal with the cases of the
62 * counter updating while being read.
63 */
rtc_read_lp_counter(struct snvs_rtc_data * data)64 static u32 rtc_read_lp_counter(struct snvs_rtc_data *data)
65 {
66 u64 read1, read2;
67 s64 diff;
68 unsigned int timeout = 100;
69
70 /* As expected, the registers might update between the read of the LSB
71 * reg and the MSB reg. It's also possible that one register might be
72 * in partially modified state as well.
73 */
74 read1 = rtc_read_lpsrt(data);
75 do {
76 read2 = read1;
77 read1 = rtc_read_lpsrt(data);
78 diff = read1 - read2;
79 } while (((diff < 0) || (diff > MAX_RTC_READ_DIFF_CYCLES)) && --timeout);
80 if (!timeout)
81 dev_err(&data->rtc->dev, "Timeout trying to get valid LPSRT Counter read\n");
82
83 /* Convert 47-bit counter to 32-bit raw second count */
84 return (u32) (read1 >> CNTR_TO_SECS_SH);
85 }
86
87 /* Just read the lsb from the counter, dealing with inconsistent state */
rtc_read_lp_counter_lsb(struct snvs_rtc_data * data,u32 * lsb)88 static int rtc_read_lp_counter_lsb(struct snvs_rtc_data *data, u32 *lsb)
89 {
90 u32 count1, count2;
91 s32 diff;
92 unsigned int timeout = 100;
93
94 regmap_read(data->regmap, data->offset + SNVS_LPSRTCLR, &count1);
95 do {
96 count2 = count1;
97 regmap_read(data->regmap, data->offset + SNVS_LPSRTCLR, &count1);
98 diff = count1 - count2;
99 } while (((diff < 0) || (diff > MAX_RTC_READ_DIFF_CYCLES)) && --timeout);
100 if (!timeout) {
101 dev_err(&data->rtc->dev, "Timeout trying to get valid LPSRT Counter read\n");
102 return -ETIMEDOUT;
103 }
104
105 *lsb = count1;
106 return 0;
107 }
108
rtc_write_sync_lp(struct snvs_rtc_data * data)109 static int rtc_write_sync_lp(struct snvs_rtc_data *data)
110 {
111 u32 count1, count2;
112 u32 elapsed;
113 unsigned int timeout = 1000;
114 int ret;
115
116 ret = rtc_read_lp_counter_lsb(data, &count1);
117 if (ret)
118 return ret;
119
120 /* Wait for 3 CKIL cycles, about 61.0-91.5 µs */
121 do {
122 ret = rtc_read_lp_counter_lsb(data, &count2);
123 if (ret)
124 return ret;
125 elapsed = count2 - count1; /* wrap around _is_ handled! */
126 } while (elapsed < 3 && --timeout);
127 if (!timeout) {
128 dev_err(&data->rtc->dev, "Timeout waiting for LPSRT Counter to change\n");
129 return -ETIMEDOUT;
130 }
131 return 0;
132 }
133
snvs_rtc_enable(struct snvs_rtc_data * data,bool enable)134 static int snvs_rtc_enable(struct snvs_rtc_data *data, bool enable)
135 {
136 int timeout = 1000;
137 u32 lpcr;
138
139 regmap_update_bits(data->regmap, data->offset + SNVS_LPCR, SNVS_LPCR_SRTC_ENV,
140 enable ? SNVS_LPCR_SRTC_ENV : 0);
141
142 while (--timeout) {
143 regmap_read(data->regmap, data->offset + SNVS_LPCR, &lpcr);
144
145 if (enable) {
146 if (lpcr & SNVS_LPCR_SRTC_ENV)
147 break;
148 } else {
149 if (!(lpcr & SNVS_LPCR_SRTC_ENV))
150 break;
151 }
152 }
153
154 if (!timeout)
155 return -ETIMEDOUT;
156
157 return 0;
158 }
159
snvs_rtc_read_time(struct device * dev,struct rtc_time * tm)160 static int snvs_rtc_read_time(struct device *dev, struct rtc_time *tm)
161 {
162 struct snvs_rtc_data *data = dev_get_drvdata(dev);
163 unsigned long time;
164 int ret;
165
166 if (data->clk) {
167 ret = clk_enable(data->clk);
168 if (ret)
169 return ret;
170 }
171
172 time = rtc_read_lp_counter(data);
173 rtc_time64_to_tm(time, tm);
174
175 if (data->clk)
176 clk_disable(data->clk);
177
178 return 0;
179 }
180
snvs_rtc_set_time(struct device * dev,struct rtc_time * tm)181 static int snvs_rtc_set_time(struct device *dev, struct rtc_time *tm)
182 {
183 struct snvs_rtc_data *data = dev_get_drvdata(dev);
184 unsigned long time = rtc_tm_to_time64(tm);
185 int ret;
186
187 if (data->clk) {
188 ret = clk_enable(data->clk);
189 if (ret)
190 return ret;
191 }
192
193 /* Disable RTC first */
194 ret = snvs_rtc_enable(data, false);
195 if (ret)
196 return ret;
197
198 /* Write 32-bit time to 47-bit timer, leaving 15 LSBs blank */
199 regmap_write(data->regmap, data->offset + SNVS_LPSRTCLR, time << CNTR_TO_SECS_SH);
200 regmap_write(data->regmap, data->offset + SNVS_LPSRTCMR, time >> (32 - CNTR_TO_SECS_SH));
201
202 /* Enable RTC again */
203 ret = snvs_rtc_enable(data, true);
204
205 if (data->clk)
206 clk_disable(data->clk);
207
208 return ret;
209 }
210
snvs_rtc_read_alarm(struct device * dev,struct rtc_wkalrm * alrm)211 static int snvs_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
212 {
213 struct snvs_rtc_data *data = dev_get_drvdata(dev);
214 u32 lptar, lpsr;
215 int ret;
216
217 if (data->clk) {
218 ret = clk_enable(data->clk);
219 if (ret)
220 return ret;
221 }
222
223 regmap_read(data->regmap, data->offset + SNVS_LPTAR, &lptar);
224 rtc_time64_to_tm(lptar, &alrm->time);
225
226 regmap_read(data->regmap, data->offset + SNVS_LPSR, &lpsr);
227 alrm->pending = (lpsr & SNVS_LPSR_LPTA) ? 1 : 0;
228
229 if (data->clk)
230 clk_disable(data->clk);
231
232 return 0;
233 }
234
snvs_rtc_alarm_irq_enable(struct device * dev,unsigned int enable)235 static int snvs_rtc_alarm_irq_enable(struct device *dev, unsigned int enable)
236 {
237 struct snvs_rtc_data *data = dev_get_drvdata(dev);
238 int ret;
239
240 if (data->clk) {
241 ret = clk_enable(data->clk);
242 if (ret)
243 return ret;
244 }
245
246 regmap_update_bits(data->regmap, data->offset + SNVS_LPCR,
247 (SNVS_LPCR_LPTA_EN | SNVS_LPCR_LPWUI_EN),
248 enable ? (SNVS_LPCR_LPTA_EN | SNVS_LPCR_LPWUI_EN) : 0);
249
250 ret = rtc_write_sync_lp(data);
251
252 if (data->clk)
253 clk_disable(data->clk);
254
255 return ret;
256 }
257
snvs_rtc_set_alarm(struct device * dev,struct rtc_wkalrm * alrm)258 static int snvs_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
259 {
260 struct snvs_rtc_data *data = dev_get_drvdata(dev);
261 unsigned long time = rtc_tm_to_time64(&alrm->time);
262 int ret;
263
264 if (data->clk) {
265 ret = clk_enable(data->clk);
266 if (ret)
267 return ret;
268 }
269
270 regmap_update_bits(data->regmap, data->offset + SNVS_LPCR, SNVS_LPCR_LPTA_EN, 0);
271 ret = rtc_write_sync_lp(data);
272 if (ret)
273 return ret;
274 regmap_write(data->regmap, data->offset + SNVS_LPTAR, time);
275
276 /* Clear alarm interrupt status bit */
277 regmap_write(data->regmap, data->offset + SNVS_LPSR, SNVS_LPSR_LPTA);
278
279 if (data->clk)
280 clk_disable(data->clk);
281
282 return snvs_rtc_alarm_irq_enable(dev, alrm->enabled);
283 }
284
285 static const struct rtc_class_ops snvs_rtc_ops = {
286 .read_time = snvs_rtc_read_time,
287 .set_time = snvs_rtc_set_time,
288 .read_alarm = snvs_rtc_read_alarm,
289 .set_alarm = snvs_rtc_set_alarm,
290 .alarm_irq_enable = snvs_rtc_alarm_irq_enable,
291 };
292
snvs_rtc_irq_handler(int irq,void * dev_id)293 static irqreturn_t snvs_rtc_irq_handler(int irq, void *dev_id)
294 {
295 struct device *dev = dev_id;
296 struct snvs_rtc_data *data = dev_get_drvdata(dev);
297 u32 lpsr;
298 u32 events = 0;
299
300 if (data->clk)
301 clk_enable(data->clk);
302
303 regmap_read(data->regmap, data->offset + SNVS_LPSR, &lpsr);
304
305 if (lpsr & SNVS_LPSR_LPTA) {
306 events |= (RTC_AF | RTC_IRQF);
307
308 /* RTC alarm should be one-shot */
309 snvs_rtc_alarm_irq_enable(dev, 0);
310
311 rtc_update_irq(data->rtc, 1, events);
312 }
313
314 /* clear interrupt status */
315 regmap_write(data->regmap, data->offset + SNVS_LPSR, lpsr);
316
317 if (data->clk)
318 clk_disable(data->clk);
319
320 return events ? IRQ_HANDLED : IRQ_NONE;
321 }
322
323 static const struct regmap_config snvs_rtc_config = {
324 .reg_bits = 32,
325 .val_bits = 32,
326 .reg_stride = 4,
327 };
328
snvs_rtc_action(void * data)329 static void snvs_rtc_action(void *data)
330 {
331 if (data)
332 clk_disable_unprepare(data);
333 }
334
snvs_rtc_probe(struct platform_device * pdev)335 static int snvs_rtc_probe(struct platform_device *pdev)
336 {
337 struct snvs_rtc_data *data;
338 int ret;
339 void __iomem *mmio;
340
341 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
342 if (!data)
343 return -ENOMEM;
344
345 data->rtc = devm_rtc_allocate_device(&pdev->dev);
346 if (IS_ERR(data->rtc))
347 return PTR_ERR(data->rtc);
348
349 data->regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, "regmap");
350
351 if (IS_ERR(data->regmap)) {
352 dev_warn(&pdev->dev, "snvs rtc: you use old dts file, please update it\n");
353
354 mmio = devm_platform_ioremap_resource(pdev, 0);
355 if (IS_ERR(mmio))
356 return PTR_ERR(mmio);
357
358 data->regmap = devm_regmap_init_mmio(&pdev->dev, mmio, &snvs_rtc_config);
359 } else {
360 data->offset = SNVS_LPREGISTER_OFFSET;
361 of_property_read_u32(pdev->dev.of_node, "offset", &data->offset);
362 }
363
364 if (IS_ERR(data->regmap)) {
365 dev_err(&pdev->dev, "Can't find snvs syscon\n");
366 return -ENODEV;
367 }
368
369 data->irq = platform_get_irq(pdev, 0);
370 if (data->irq < 0)
371 return data->irq;
372
373 data->clk = devm_clk_get(&pdev->dev, "snvs-rtc");
374 if (IS_ERR(data->clk)) {
375 data->clk = NULL;
376 } else {
377 ret = clk_prepare_enable(data->clk);
378 if (ret) {
379 dev_err(&pdev->dev,
380 "Could not prepare or enable the snvs clock\n");
381 return ret;
382 }
383 }
384
385 ret = devm_add_action_or_reset(&pdev->dev, snvs_rtc_action, data->clk);
386 if (ret)
387 return ret;
388
389 platform_set_drvdata(pdev, data);
390
391 /* Initialize glitch detect */
392 regmap_write(data->regmap, data->offset + SNVS_LPPGDR, SNVS_LPPGDR_INIT);
393
394 /* Clear interrupt status */
395 regmap_write(data->regmap, data->offset + SNVS_LPSR, 0xffffffff);
396
397 /* Enable RTC */
398 ret = snvs_rtc_enable(data, true);
399 if (ret) {
400 dev_err(&pdev->dev, "failed to enable rtc %d\n", ret);
401 return ret;
402 }
403
404 device_init_wakeup(&pdev->dev, true);
405 ret = dev_pm_set_wake_irq(&pdev->dev, data->irq);
406 if (ret)
407 dev_err(&pdev->dev, "failed to enable irq wake\n");
408
409 ret = devm_request_irq(&pdev->dev, data->irq, snvs_rtc_irq_handler,
410 IRQF_SHARED, "rtc alarm", &pdev->dev);
411 if (ret) {
412 dev_err(&pdev->dev, "failed to request irq %d: %d\n",
413 data->irq, ret);
414 return ret;
415 }
416
417 data->rtc->ops = &snvs_rtc_ops;
418 data->rtc->range_max = U32_MAX;
419
420 return rtc_register_device(data->rtc);
421 }
422
snvs_rtc_suspend_noirq(struct device * dev)423 static int __maybe_unused snvs_rtc_suspend_noirq(struct device *dev)
424 {
425 struct snvs_rtc_data *data = dev_get_drvdata(dev);
426
427 if (data->clk)
428 clk_disable(data->clk);
429
430 return 0;
431 }
432
snvs_rtc_resume_noirq(struct device * dev)433 static int __maybe_unused snvs_rtc_resume_noirq(struct device *dev)
434 {
435 struct snvs_rtc_data *data = dev_get_drvdata(dev);
436
437 if (data->clk)
438 return clk_enable(data->clk);
439
440 return 0;
441 }
442
443 static const struct dev_pm_ops snvs_rtc_pm_ops = {
444 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(snvs_rtc_suspend_noirq, snvs_rtc_resume_noirq)
445 };
446
447 static const struct of_device_id snvs_dt_ids[] = {
448 { .compatible = "fsl,sec-v4.0-mon-rtc-lp", },
449 { /* sentinel */ }
450 };
451 MODULE_DEVICE_TABLE(of, snvs_dt_ids);
452
453 static struct platform_driver snvs_rtc_driver = {
454 .driver = {
455 .name = "snvs_rtc",
456 .pm = &snvs_rtc_pm_ops,
457 .of_match_table = snvs_dt_ids,
458 },
459 .probe = snvs_rtc_probe,
460 };
461 module_platform_driver(snvs_rtc_driver);
462
463 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
464 MODULE_DESCRIPTION("Freescale SNVS RTC Driver");
465 MODULE_LICENSE("GPL");
466