1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Probe module for 8250/16550-type PCI serial ports.
4 *
5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 *
7 * Copyright (C) 2001 Russell King, All Rights Reserved.
8 */
9 #undef DEBUG
10 #include <linux/module.h>
11 #include <linux/pci.h>
12 #include <linux/string.h>
13 #include <linux/kernel.h>
14 #include <linux/slab.h>
15 #include <linux/delay.h>
16 #include <linux/tty.h>
17 #include <linux/serial_reg.h>
18 #include <linux/serial_core.h>
19 #include <linux/8250_pci.h>
20 #include <linux/bitops.h>
21
22 #include <asm/byteorder.h>
23 #include <asm/io.h>
24
25 #include "8250.h"
26
27 /*
28 * init function returns:
29 * > 0 - number of ports
30 * = 0 - use board->num_ports
31 * < 0 - error
32 */
33 struct pci_serial_quirk {
34 u32 vendor;
35 u32 device;
36 u32 subvendor;
37 u32 subdevice;
38 int (*probe)(struct pci_dev *dev);
39 int (*init)(struct pci_dev *dev);
40 int (*setup)(struct serial_private *,
41 const struct pciserial_board *,
42 struct uart_8250_port *, int);
43 void (*exit)(struct pci_dev *dev);
44 };
45
46 struct f815xxa_data {
47 spinlock_t lock;
48 int idx;
49 };
50
51 struct serial_private {
52 struct pci_dev *dev;
53 unsigned int nr;
54 struct pci_serial_quirk *quirk;
55 const struct pciserial_board *board;
56 int line[];
57 };
58
59 #define PCI_DEVICE_ID_HPE_PCI_SERIAL 0x37e
60
61 static const struct pci_device_id pci_use_msi[] = {
62 { PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
63 0xA000, 0x1000) },
64 { PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
65 0xA000, 0x1000) },
66 { PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
67 0xA000, 0x1000) },
68 { PCI_DEVICE_SUB(PCI_VENDOR_ID_HP_3PAR, PCI_DEVICE_ID_HPE_PCI_SERIAL,
69 PCI_ANY_ID, PCI_ANY_ID) },
70 { }
71 };
72
73 static int pci_default_setup(struct serial_private*,
74 const struct pciserial_board*, struct uart_8250_port *, int);
75
moan_device(const char * str,struct pci_dev * dev)76 static void moan_device(const char *str, struct pci_dev *dev)
77 {
78 pci_err(dev, "%s\n"
79 "Please send the output of lspci -vv, this\n"
80 "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
81 "manufacturer and name of serial board or\n"
82 "modem board to <linux-serial@vger.kernel.org>.\n",
83 str, dev->vendor, dev->device,
84 dev->subsystem_vendor, dev->subsystem_device);
85 }
86
87 static int
setup_port(struct serial_private * priv,struct uart_8250_port * port,u8 bar,unsigned int offset,int regshift)88 setup_port(struct serial_private *priv, struct uart_8250_port *port,
89 u8 bar, unsigned int offset, int regshift)
90 {
91 struct pci_dev *dev = priv->dev;
92
93 if (bar >= PCI_STD_NUM_BARS)
94 return -EINVAL;
95
96 if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
97 if (!pcim_iomap(dev, bar, 0) && !pcim_iomap_table(dev))
98 return -ENOMEM;
99
100 port->port.iotype = UPIO_MEM;
101 port->port.iobase = 0;
102 port->port.mapbase = pci_resource_start(dev, bar) + offset;
103 port->port.membase = pcim_iomap_table(dev)[bar] + offset;
104 port->port.regshift = regshift;
105 } else {
106 port->port.iotype = UPIO_PORT;
107 port->port.iobase = pci_resource_start(dev, bar) + offset;
108 port->port.mapbase = 0;
109 port->port.membase = NULL;
110 port->port.regshift = 0;
111 }
112 return 0;
113 }
114
115 /*
116 * ADDI-DATA GmbH communication cards <info@addi-data.com>
117 */
addidata_apci7800_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)118 static int addidata_apci7800_setup(struct serial_private *priv,
119 const struct pciserial_board *board,
120 struct uart_8250_port *port, int idx)
121 {
122 unsigned int bar = 0, offset = board->first_offset;
123 bar = FL_GET_BASE(board->flags);
124
125 if (idx < 2) {
126 offset += idx * board->uart_offset;
127 } else if ((idx >= 2) && (idx < 4)) {
128 bar += 1;
129 offset += ((idx - 2) * board->uart_offset);
130 } else if ((idx >= 4) && (idx < 6)) {
131 bar += 2;
132 offset += ((idx - 4) * board->uart_offset);
133 } else if (idx >= 6) {
134 bar += 3;
135 offset += ((idx - 6) * board->uart_offset);
136 }
137
138 return setup_port(priv, port, bar, offset, board->reg_shift);
139 }
140
141 /*
142 * AFAVLAB uses a different mixture of BARs and offsets
143 * Not that ugly ;) -- HW
144 */
145 static int
afavlab_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)146 afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
147 struct uart_8250_port *port, int idx)
148 {
149 unsigned int bar, offset = board->first_offset;
150
151 bar = FL_GET_BASE(board->flags);
152 if (idx < 4)
153 bar += idx;
154 else {
155 bar = 4;
156 offset += (idx - 4) * board->uart_offset;
157 }
158
159 return setup_port(priv, port, bar, offset, board->reg_shift);
160 }
161
162 /*
163 * HP's Remote Management Console. The Diva chip came in several
164 * different versions. N-class, L2000 and A500 have two Diva chips, each
165 * with 3 UARTs (the third UART on the second chip is unused). Superdome
166 * and Keystone have one Diva chip with 3 UARTs. Some later machines have
167 * one Diva chip, but it has been expanded to 5 UARTs.
168 */
pci_hp_diva_init(struct pci_dev * dev)169 static int pci_hp_diva_init(struct pci_dev *dev)
170 {
171 int rc = 0;
172
173 switch (dev->subsystem_device) {
174 case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
175 case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
176 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
177 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
178 rc = 3;
179 break;
180 case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
181 rc = 2;
182 break;
183 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
184 rc = 4;
185 break;
186 case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
187 case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
188 rc = 1;
189 break;
190 }
191
192 return rc;
193 }
194
195 /*
196 * HP's Diva chip puts the 4th/5th serial port further out, and
197 * some serial ports are supposed to be hidden on certain models.
198 */
199 static int
pci_hp_diva_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)200 pci_hp_diva_setup(struct serial_private *priv,
201 const struct pciserial_board *board,
202 struct uart_8250_port *port, int idx)
203 {
204 unsigned int offset = board->first_offset;
205 unsigned int bar = FL_GET_BASE(board->flags);
206
207 switch (priv->dev->subsystem_device) {
208 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
209 if (idx == 3)
210 idx++;
211 break;
212 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
213 if (idx > 0)
214 idx++;
215 if (idx > 2)
216 idx++;
217 break;
218 }
219 if (idx > 2)
220 offset = 0x18;
221
222 offset += idx * board->uart_offset;
223
224 return setup_port(priv, port, bar, offset, board->reg_shift);
225 }
226
227 /*
228 * Added for EKF Intel i960 serial boards
229 */
pci_inteli960ni_init(struct pci_dev * dev)230 static int pci_inteli960ni_init(struct pci_dev *dev)
231 {
232 u32 oldval;
233
234 if (!(dev->subsystem_device & 0x1000))
235 return -ENODEV;
236
237 /* is firmware started? */
238 pci_read_config_dword(dev, 0x44, &oldval);
239 if (oldval == 0x00001000L) { /* RESET value */
240 pci_dbg(dev, "Local i960 firmware missing\n");
241 return -ENODEV;
242 }
243 return 0;
244 }
245
246 /*
247 * Some PCI serial cards using the PLX 9050 PCI interface chip require
248 * that the card interrupt be explicitly enabled or disabled. This
249 * seems to be mainly needed on card using the PLX which also use I/O
250 * mapped memory.
251 */
pci_plx9050_init(struct pci_dev * dev)252 static int pci_plx9050_init(struct pci_dev *dev)
253 {
254 u8 irq_config;
255 void __iomem *p;
256
257 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
258 moan_device("no memory in bar 0", dev);
259 return 0;
260 }
261
262 irq_config = 0x41;
263 if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
264 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
265 irq_config = 0x43;
266
267 if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
268 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
269 /*
270 * As the megawolf cards have the int pins active
271 * high, and have 2 UART chips, both ints must be
272 * enabled on the 9050. Also, the UARTS are set in
273 * 16450 mode by default, so we have to enable the
274 * 16C950 'enhanced' mode so that we can use the
275 * deep FIFOs
276 */
277 irq_config = 0x5b;
278 /*
279 * enable/disable interrupts
280 */
281 p = ioremap(pci_resource_start(dev, 0), 0x80);
282 if (p == NULL)
283 return -ENOMEM;
284 writel(irq_config, p + 0x4c);
285
286 /*
287 * Read the register back to ensure that it took effect.
288 */
289 readl(p + 0x4c);
290 iounmap(p);
291
292 return 0;
293 }
294
pci_plx9050_exit(struct pci_dev * dev)295 static void pci_plx9050_exit(struct pci_dev *dev)
296 {
297 u8 __iomem *p;
298
299 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
300 return;
301
302 /*
303 * disable interrupts
304 */
305 p = ioremap(pci_resource_start(dev, 0), 0x80);
306 if (p != NULL) {
307 writel(0, p + 0x4c);
308
309 /*
310 * Read the register back to ensure that it took effect.
311 */
312 readl(p + 0x4c);
313 iounmap(p);
314 }
315 }
316
317 #define NI8420_INT_ENABLE_REG 0x38
318 #define NI8420_INT_ENABLE_BIT 0x2000
319
pci_ni8420_exit(struct pci_dev * dev)320 static void pci_ni8420_exit(struct pci_dev *dev)
321 {
322 void __iomem *p;
323 unsigned int bar = 0;
324
325 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
326 moan_device("no memory in bar", dev);
327 return;
328 }
329
330 p = pci_ioremap_bar(dev, bar);
331 if (p == NULL)
332 return;
333
334 /* Disable the CPU Interrupt */
335 writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
336 p + NI8420_INT_ENABLE_REG);
337 iounmap(p);
338 }
339
340
341 /* MITE registers */
342 #define MITE_IOWBSR1 0xc4
343 #define MITE_IOWCR1 0xf4
344 #define MITE_LCIMR1 0x08
345 #define MITE_LCIMR2 0x10
346
347 #define MITE_LCIMR2_CLR_CPU_IE (1 << 30)
348
pci_ni8430_exit(struct pci_dev * dev)349 static void pci_ni8430_exit(struct pci_dev *dev)
350 {
351 void __iomem *p;
352 unsigned int bar = 0;
353
354 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
355 moan_device("no memory in bar", dev);
356 return;
357 }
358
359 p = pci_ioremap_bar(dev, bar);
360 if (p == NULL)
361 return;
362
363 /* Disable the CPU Interrupt */
364 writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
365 iounmap(p);
366 }
367
368 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
369 static int
sbs_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)370 sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
371 struct uart_8250_port *port, int idx)
372 {
373 unsigned int bar, offset = board->first_offset;
374
375 bar = 0;
376
377 if (idx < 4) {
378 /* first four channels map to 0, 0x100, 0x200, 0x300 */
379 offset += idx * board->uart_offset;
380 } else if (idx < 8) {
381 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
382 offset += idx * board->uart_offset + 0xC00;
383 } else /* we have only 8 ports on PMC-OCTALPRO */
384 return 1;
385
386 return setup_port(priv, port, bar, offset, board->reg_shift);
387 }
388
389 /*
390 * This does initialization for PMC OCTALPRO cards:
391 * maps the device memory, resets the UARTs (needed, bc
392 * if the module is removed and inserted again, the card
393 * is in the sleep mode) and enables global interrupt.
394 */
395
396 /* global control register offset for SBS PMC-OctalPro */
397 #define OCT_REG_CR_OFF 0x500
398
sbs_init(struct pci_dev * dev)399 static int sbs_init(struct pci_dev *dev)
400 {
401 u8 __iomem *p;
402
403 p = pci_ioremap_bar(dev, 0);
404
405 if (p == NULL)
406 return -ENOMEM;
407 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
408 writeb(0x10, p + OCT_REG_CR_OFF);
409 udelay(50);
410 writeb(0x0, p + OCT_REG_CR_OFF);
411
412 /* Set bit-2 (INTENABLE) of Control Register */
413 writeb(0x4, p + OCT_REG_CR_OFF);
414 iounmap(p);
415
416 return 0;
417 }
418
419 /*
420 * Disables the global interrupt of PMC-OctalPro
421 */
422
sbs_exit(struct pci_dev * dev)423 static void sbs_exit(struct pci_dev *dev)
424 {
425 u8 __iomem *p;
426
427 p = pci_ioremap_bar(dev, 0);
428 /* FIXME: What if resource_len < OCT_REG_CR_OFF */
429 if (p != NULL)
430 writeb(0, p + OCT_REG_CR_OFF);
431 iounmap(p);
432 }
433
434 /*
435 * SIIG serial cards have an PCI interface chip which also controls
436 * the UART clocking frequency. Each UART can be clocked independently
437 * (except cards equipped with 4 UARTs) and initial clocking settings
438 * are stored in the EEPROM chip. It can cause problems because this
439 * version of serial driver doesn't support differently clocked UART's
440 * on single PCI card. To prevent this, initialization functions set
441 * high frequency clocking for all UART's on given card. It is safe (I
442 * hope) because it doesn't touch EEPROM settings to prevent conflicts
443 * with other OSes (like M$ DOS).
444 *
445 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
446 *
447 * There is two family of SIIG serial cards with different PCI
448 * interface chip and different configuration methods:
449 * - 10x cards have control registers in IO and/or memory space;
450 * - 20x cards have control registers in standard PCI configuration space.
451 *
452 * Note: all 10x cards have PCI device ids 0x10..
453 * all 20x cards have PCI device ids 0x20..
454 *
455 * There are also Quartet Serial cards which use Oxford Semiconductor
456 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
457 *
458 * Note: some SIIG cards are probed by the parport_serial object.
459 */
460
461 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
462 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
463
pci_siig10x_init(struct pci_dev * dev)464 static int pci_siig10x_init(struct pci_dev *dev)
465 {
466 u16 data;
467 void __iomem *p;
468
469 switch (dev->device & 0xfff8) {
470 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
471 data = 0xffdf;
472 break;
473 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
474 data = 0xf7ff;
475 break;
476 default: /* 1S1P, 4S */
477 data = 0xfffb;
478 break;
479 }
480
481 p = ioremap(pci_resource_start(dev, 0), 0x80);
482 if (p == NULL)
483 return -ENOMEM;
484
485 writew(readw(p + 0x28) & data, p + 0x28);
486 readw(p + 0x28);
487 iounmap(p);
488 return 0;
489 }
490
491 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
492 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
493
pci_siig20x_init(struct pci_dev * dev)494 static int pci_siig20x_init(struct pci_dev *dev)
495 {
496 u8 data;
497
498 /* Change clock frequency for the first UART. */
499 pci_read_config_byte(dev, 0x6f, &data);
500 pci_write_config_byte(dev, 0x6f, data & 0xef);
501
502 /* If this card has 2 UART, we have to do the same with second UART. */
503 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
504 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
505 pci_read_config_byte(dev, 0x73, &data);
506 pci_write_config_byte(dev, 0x73, data & 0xef);
507 }
508 return 0;
509 }
510
pci_siig_init(struct pci_dev * dev)511 static int pci_siig_init(struct pci_dev *dev)
512 {
513 unsigned int type = dev->device & 0xff00;
514
515 if (type == 0x1000)
516 return pci_siig10x_init(dev);
517 else if (type == 0x2000)
518 return pci_siig20x_init(dev);
519
520 moan_device("Unknown SIIG card", dev);
521 return -ENODEV;
522 }
523
pci_siig_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)524 static int pci_siig_setup(struct serial_private *priv,
525 const struct pciserial_board *board,
526 struct uart_8250_port *port, int idx)
527 {
528 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
529
530 if (idx > 3) {
531 bar = 4;
532 offset = (idx - 4) * 8;
533 }
534
535 return setup_port(priv, port, bar, offset, 0);
536 }
537
538 /*
539 * Timedia has an explosion of boards, and to avoid the PCI table from
540 * growing *huge*, we use this function to collapse some 70 entries
541 * in the PCI table into one, for sanity's and compactness's sake.
542 */
543 static const unsigned short timedia_single_port[] = {
544 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
545 };
546
547 static const unsigned short timedia_dual_port[] = {
548 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
549 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
550 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
551 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
552 0xD079, 0
553 };
554
555 static const unsigned short timedia_quad_port[] = {
556 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
557 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
558 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
559 0xB157, 0
560 };
561
562 static const unsigned short timedia_eight_port[] = {
563 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
564 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
565 };
566
567 static const struct timedia_struct {
568 int num;
569 const unsigned short *ids;
570 } timedia_data[] = {
571 { 1, timedia_single_port },
572 { 2, timedia_dual_port },
573 { 4, timedia_quad_port },
574 { 8, timedia_eight_port }
575 };
576
577 /*
578 * There are nearly 70 different Timedia/SUNIX PCI serial devices. Instead of
579 * listing them individually, this driver merely grabs them all with
580 * PCI_ANY_ID. Some of these devices, however, also feature a parallel port,
581 * and should be left free to be claimed by parport_serial instead.
582 */
pci_timedia_probe(struct pci_dev * dev)583 static int pci_timedia_probe(struct pci_dev *dev)
584 {
585 /*
586 * Check the third digit of the subdevice ID
587 * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel)
588 */
589 if ((dev->subsystem_device & 0x00f0) >= 0x70) {
590 pci_info(dev, "ignoring Timedia subdevice %04x for parport_serial\n",
591 dev->subsystem_device);
592 return -ENODEV;
593 }
594
595 return 0;
596 }
597
pci_timedia_init(struct pci_dev * dev)598 static int pci_timedia_init(struct pci_dev *dev)
599 {
600 const unsigned short *ids;
601 int i, j;
602
603 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
604 ids = timedia_data[i].ids;
605 for (j = 0; ids[j]; j++)
606 if (dev->subsystem_device == ids[j])
607 return timedia_data[i].num;
608 }
609 return 0;
610 }
611
612 /*
613 * Timedia/SUNIX uses a mixture of BARs and offsets
614 * Ugh, this is ugly as all hell --- TYT
615 */
616 static int
pci_timedia_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)617 pci_timedia_setup(struct serial_private *priv,
618 const struct pciserial_board *board,
619 struct uart_8250_port *port, int idx)
620 {
621 unsigned int bar = 0, offset = board->first_offset;
622
623 switch (idx) {
624 case 0:
625 bar = 0;
626 break;
627 case 1:
628 offset = board->uart_offset;
629 bar = 0;
630 break;
631 case 2:
632 bar = 1;
633 break;
634 case 3:
635 offset = board->uart_offset;
636 fallthrough;
637 case 4: /* BAR 2 */
638 case 5: /* BAR 3 */
639 case 6: /* BAR 4 */
640 case 7: /* BAR 5 */
641 bar = idx - 2;
642 }
643
644 return setup_port(priv, port, bar, offset, board->reg_shift);
645 }
646
647 /*
648 * Some Titan cards are also a little weird
649 */
650 static int
titan_400l_800l_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)651 titan_400l_800l_setup(struct serial_private *priv,
652 const struct pciserial_board *board,
653 struct uart_8250_port *port, int idx)
654 {
655 unsigned int bar, offset = board->first_offset;
656
657 switch (idx) {
658 case 0:
659 bar = 1;
660 break;
661 case 1:
662 bar = 2;
663 break;
664 default:
665 bar = 4;
666 offset = (idx - 2) * board->uart_offset;
667 }
668
669 return setup_port(priv, port, bar, offset, board->reg_shift);
670 }
671
pci_xircom_init(struct pci_dev * dev)672 static int pci_xircom_init(struct pci_dev *dev)
673 {
674 msleep(100);
675 return 0;
676 }
677
pci_ni8420_init(struct pci_dev * dev)678 static int pci_ni8420_init(struct pci_dev *dev)
679 {
680 void __iomem *p;
681 unsigned int bar = 0;
682
683 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
684 moan_device("no memory in bar", dev);
685 return 0;
686 }
687
688 p = pci_ioremap_bar(dev, bar);
689 if (p == NULL)
690 return -ENOMEM;
691
692 /* Enable CPU Interrupt */
693 writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
694 p + NI8420_INT_ENABLE_REG);
695
696 iounmap(p);
697 return 0;
698 }
699
700 #define MITE_IOWBSR1_WSIZE 0xa
701 #define MITE_IOWBSR1_WIN_OFFSET 0x800
702 #define MITE_IOWBSR1_WENAB (1 << 7)
703 #define MITE_LCIMR1_IO_IE_0 (1 << 24)
704 #define MITE_LCIMR2_SET_CPU_IE (1 << 31)
705 #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
706
pci_ni8430_init(struct pci_dev * dev)707 static int pci_ni8430_init(struct pci_dev *dev)
708 {
709 void __iomem *p;
710 struct pci_bus_region region;
711 u32 device_window;
712 unsigned int bar = 0;
713
714 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
715 moan_device("no memory in bar", dev);
716 return 0;
717 }
718
719 p = pci_ioremap_bar(dev, bar);
720 if (p == NULL)
721 return -ENOMEM;
722
723 /*
724 * Set device window address and size in BAR0, while acknowledging that
725 * the resource structure may contain a translated address that differs
726 * from the address the device responds to.
727 */
728 pcibios_resource_to_bus(dev->bus, ®ion, &dev->resource[bar]);
729 device_window = ((region.start + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
730 | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
731 writel(device_window, p + MITE_IOWBSR1);
732
733 /* Set window access to go to RAMSEL IO address space */
734 writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
735 p + MITE_IOWCR1);
736
737 /* Enable IO Bus Interrupt 0 */
738 writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
739
740 /* Enable CPU Interrupt */
741 writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
742
743 iounmap(p);
744 return 0;
745 }
746
747 /* UART Port Control Register */
748 #define NI8430_PORTCON 0x0f
749 #define NI8430_PORTCON_TXVR_ENABLE (1 << 3)
750
751 static int
pci_ni8430_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)752 pci_ni8430_setup(struct serial_private *priv,
753 const struct pciserial_board *board,
754 struct uart_8250_port *port, int idx)
755 {
756 struct pci_dev *dev = priv->dev;
757 void __iomem *p;
758 unsigned int bar, offset = board->first_offset;
759
760 if (idx >= board->num_ports)
761 return 1;
762
763 bar = FL_GET_BASE(board->flags);
764 offset += idx * board->uart_offset;
765
766 p = pci_ioremap_bar(dev, bar);
767 if (!p)
768 return -ENOMEM;
769
770 /* enable the transceiver */
771 writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
772 p + offset + NI8430_PORTCON);
773
774 iounmap(p);
775
776 return setup_port(priv, port, bar, offset, board->reg_shift);
777 }
778
pci_netmos_9900_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)779 static int pci_netmos_9900_setup(struct serial_private *priv,
780 const struct pciserial_board *board,
781 struct uart_8250_port *port, int idx)
782 {
783 unsigned int bar;
784
785 if ((priv->dev->device != PCI_DEVICE_ID_NETMOS_9865) &&
786 (priv->dev->subsystem_device & 0xff00) == 0x3000) {
787 /* netmos apparently orders BARs by datasheet layout, so serial
788 * ports get BARs 0 and 3 (or 1 and 4 for memmapped)
789 */
790 bar = 3 * idx;
791
792 return setup_port(priv, port, bar, 0, board->reg_shift);
793 } else {
794 return pci_default_setup(priv, board, port, idx);
795 }
796 }
797
798 /* the 99xx series comes with a range of device IDs and a variety
799 * of capabilities:
800 *
801 * 9900 has varying capabilities and can cascade to sub-controllers
802 * (cascading should be purely internal)
803 * 9904 is hardwired with 4 serial ports
804 * 9912 and 9922 are hardwired with 2 serial ports
805 */
pci_netmos_9900_numports(struct pci_dev * dev)806 static int pci_netmos_9900_numports(struct pci_dev *dev)
807 {
808 unsigned int c = dev->class;
809 unsigned int pi;
810 unsigned short sub_serports;
811
812 pi = c & 0xff;
813
814 if (pi == 2)
815 return 1;
816
817 if ((pi == 0) && (dev->device == PCI_DEVICE_ID_NETMOS_9900)) {
818 /* two possibilities: 0x30ps encodes number of parallel and
819 * serial ports, or 0x1000 indicates *something*. This is not
820 * immediately obvious, since the 2s1p+4s configuration seems
821 * to offer all functionality on functions 0..2, while still
822 * advertising the same function 3 as the 4s+2s1p config.
823 */
824 sub_serports = dev->subsystem_device & 0xf;
825 if (sub_serports > 0)
826 return sub_serports;
827
828 pci_err(dev, "NetMos/Mostech serial driver ignoring port on ambiguous config.\n");
829 return 0;
830 }
831
832 moan_device("unknown NetMos/Mostech program interface", dev);
833 return 0;
834 }
835
pci_netmos_init(struct pci_dev * dev)836 static int pci_netmos_init(struct pci_dev *dev)
837 {
838 /* subdevice 0x00PS means <P> parallel, <S> serial */
839 unsigned int num_serial = dev->subsystem_device & 0xf;
840
841 if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) ||
842 (dev->device == PCI_DEVICE_ID_NETMOS_9865))
843 return 0;
844
845 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
846 dev->subsystem_device == 0x0299)
847 return 0;
848
849 switch (dev->device) { /* FALLTHROUGH on all */
850 case PCI_DEVICE_ID_NETMOS_9904:
851 case PCI_DEVICE_ID_NETMOS_9912:
852 case PCI_DEVICE_ID_NETMOS_9922:
853 case PCI_DEVICE_ID_NETMOS_9900:
854 num_serial = pci_netmos_9900_numports(dev);
855 break;
856
857 default:
858 break;
859 }
860
861 if (num_serial == 0) {
862 moan_device("unknown NetMos/Mostech device", dev);
863 return -ENODEV;
864 }
865
866 return num_serial;
867 }
868
869 /*
870 * These chips are available with optionally one parallel port and up to
871 * two serial ports. Unfortunately they all have the same product id.
872 *
873 * Basic configuration is done over a region of 32 I/O ports. The base
874 * ioport is called INTA or INTC, depending on docs/other drivers.
875 *
876 * The region of the 32 I/O ports is configured in POSIO0R...
877 */
878
879 /* registers */
880 #define ITE_887x_MISCR 0x9c
881 #define ITE_887x_INTCBAR 0x78
882 #define ITE_887x_UARTBAR 0x7c
883 #define ITE_887x_PS0BAR 0x10
884 #define ITE_887x_POSIO0 0x60
885
886 /* I/O space size */
887 #define ITE_887x_IOSIZE 32
888 /* I/O space size (bits 26-24; 8 bytes = 011b) */
889 #define ITE_887x_POSIO_IOSIZE_8 (3 << 24)
890 /* I/O space size (bits 26-24; 32 bytes = 101b) */
891 #define ITE_887x_POSIO_IOSIZE_32 (5 << 24)
892 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
893 #define ITE_887x_POSIO_SPEED (3 << 29)
894 /* enable IO_Space bit */
895 #define ITE_887x_POSIO_ENABLE (1 << 31)
896
897 /* inta_addr are the configuration addresses of the ITE */
898 static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0, 0x200, 0x280 };
pci_ite887x_init(struct pci_dev * dev)899 static int pci_ite887x_init(struct pci_dev *dev)
900 {
901 int ret, i, type;
902 struct resource *iobase = NULL;
903 u32 miscr, uartbar, ioport;
904
905 /* search for the base-ioport */
906 for (i = 0; i < ARRAY_SIZE(inta_addr); i++) {
907 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
908 "ite887x");
909 if (iobase != NULL) {
910 /* write POSIO0R - speed | size | ioport */
911 pci_write_config_dword(dev, ITE_887x_POSIO0,
912 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
913 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
914 /* write INTCBAR - ioport */
915 pci_write_config_dword(dev, ITE_887x_INTCBAR,
916 inta_addr[i]);
917 ret = inb(inta_addr[i]);
918 if (ret != 0xff) {
919 /* ioport connected */
920 break;
921 }
922 release_region(iobase->start, ITE_887x_IOSIZE);
923 }
924 }
925
926 if (i == ARRAY_SIZE(inta_addr)) {
927 pci_err(dev, "could not find iobase\n");
928 return -ENODEV;
929 }
930
931 /* start of undocumented type checking (see parport_pc.c) */
932 type = inb(iobase->start + 0x18) & 0x0f;
933
934 switch (type) {
935 case 0x2: /* ITE8871 (1P) */
936 case 0xa: /* ITE8875 (1P) */
937 ret = 0;
938 break;
939 case 0xe: /* ITE8872 (2S1P) */
940 ret = 2;
941 break;
942 case 0x6: /* ITE8873 (1S) */
943 ret = 1;
944 break;
945 case 0x8: /* ITE8874 (2S) */
946 ret = 2;
947 break;
948 default:
949 moan_device("Unknown ITE887x", dev);
950 ret = -ENODEV;
951 }
952
953 /* configure all serial ports */
954 for (i = 0; i < ret; i++) {
955 /* read the I/O port from the device */
956 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
957 &ioport);
958 ioport &= 0x0000FF00; /* the actual base address */
959 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
960 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
961 ITE_887x_POSIO_IOSIZE_8 | ioport);
962
963 /* write the ioport to the UARTBAR */
964 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
965 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */
966 uartbar |= (ioport << (16 * i)); /* set the ioport */
967 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
968
969 /* get current config */
970 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
971 /* disable interrupts (UARTx_Routing[3:0]) */
972 miscr &= ~(0xf << (12 - 4 * i));
973 /* activate the UART (UARTx_En) */
974 miscr |= 1 << (23 - i);
975 /* write new config with activated UART */
976 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
977 }
978
979 if (ret <= 0) {
980 /* the device has no UARTs if we get here */
981 release_region(iobase->start, ITE_887x_IOSIZE);
982 }
983
984 return ret;
985 }
986
pci_ite887x_exit(struct pci_dev * dev)987 static void pci_ite887x_exit(struct pci_dev *dev)
988 {
989 u32 ioport;
990 /* the ioport is bit 0-15 in POSIO0R */
991 pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
992 ioport &= 0xffff;
993 release_region(ioport, ITE_887x_IOSIZE);
994 }
995
996 /*
997 * Oxford Semiconductor Inc.
998 * Check if an OxSemi device is part of the Tornado range of devices.
999 */
1000 #define PCI_VENDOR_ID_ENDRUN 0x7401
1001 #define PCI_DEVICE_ID_ENDRUN_1588 0xe100
1002
pci_oxsemi_tornado_p(struct pci_dev * dev)1003 static bool pci_oxsemi_tornado_p(struct pci_dev *dev)
1004 {
1005 /* OxSemi Tornado devices are all 0xCxxx */
1006 if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
1007 (dev->device & 0xf000) != 0xc000)
1008 return false;
1009
1010 /* EndRun devices are all 0xExxx */
1011 if (dev->vendor == PCI_VENDOR_ID_ENDRUN &&
1012 (dev->device & 0xf000) != 0xe000)
1013 return false;
1014
1015 return true;
1016 }
1017
1018 /*
1019 * Determine the number of ports available on a Tornado device.
1020 */
pci_oxsemi_tornado_init(struct pci_dev * dev)1021 static int pci_oxsemi_tornado_init(struct pci_dev *dev)
1022 {
1023 u8 __iomem *p;
1024 unsigned long deviceID;
1025 unsigned int number_uarts = 0;
1026
1027 if (!pci_oxsemi_tornado_p(dev))
1028 return 0;
1029
1030 p = pci_iomap(dev, 0, 5);
1031 if (p == NULL)
1032 return -ENOMEM;
1033
1034 deviceID = ioread32(p);
1035 /* Tornado device */
1036 if (deviceID == 0x07000200) {
1037 number_uarts = ioread8(p + 4);
1038 pci_dbg(dev, "%d ports detected on %s PCI Express device\n",
1039 number_uarts,
1040 dev->vendor == PCI_VENDOR_ID_ENDRUN ?
1041 "EndRun" : "Oxford");
1042 }
1043 pci_iounmap(dev, p);
1044 return number_uarts;
1045 }
1046
pci_asix_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1047 static int pci_asix_setup(struct serial_private *priv,
1048 const struct pciserial_board *board,
1049 struct uart_8250_port *port, int idx)
1050 {
1051 port->bugs |= UART_BUG_PARITY;
1052 return pci_default_setup(priv, board, port, idx);
1053 }
1054
1055 /* Quatech devices have their own extra interface features */
1056
1057 struct quatech_feature {
1058 u16 devid;
1059 bool amcc;
1060 };
1061
1062 #define QPCR_TEST_FOR1 0x3F
1063 #define QPCR_TEST_GET1 0x00
1064 #define QPCR_TEST_FOR2 0x40
1065 #define QPCR_TEST_GET2 0x40
1066 #define QPCR_TEST_FOR3 0x80
1067 #define QPCR_TEST_GET3 0x40
1068 #define QPCR_TEST_FOR4 0xC0
1069 #define QPCR_TEST_GET4 0x80
1070
1071 #define QOPR_CLOCK_X1 0x0000
1072 #define QOPR_CLOCK_X2 0x0001
1073 #define QOPR_CLOCK_X4 0x0002
1074 #define QOPR_CLOCK_X8 0x0003
1075 #define QOPR_CLOCK_RATE_MASK 0x0003
1076
1077
1078 static struct quatech_feature quatech_cards[] = {
1079 { PCI_DEVICE_ID_QUATECH_QSC100, 1 },
1080 { PCI_DEVICE_ID_QUATECH_DSC100, 1 },
1081 { PCI_DEVICE_ID_QUATECH_DSC100E, 0 },
1082 { PCI_DEVICE_ID_QUATECH_DSC200, 1 },
1083 { PCI_DEVICE_ID_QUATECH_DSC200E, 0 },
1084 { PCI_DEVICE_ID_QUATECH_ESC100D, 1 },
1085 { PCI_DEVICE_ID_QUATECH_ESC100M, 1 },
1086 { PCI_DEVICE_ID_QUATECH_QSCP100, 1 },
1087 { PCI_DEVICE_ID_QUATECH_DSCP100, 1 },
1088 { PCI_DEVICE_ID_QUATECH_QSCP200, 1 },
1089 { PCI_DEVICE_ID_QUATECH_DSCP200, 1 },
1090 { PCI_DEVICE_ID_QUATECH_ESCLP100, 0 },
1091 { PCI_DEVICE_ID_QUATECH_QSCLP100, 0 },
1092 { PCI_DEVICE_ID_QUATECH_DSCLP100, 0 },
1093 { PCI_DEVICE_ID_QUATECH_SSCLP100, 0 },
1094 { PCI_DEVICE_ID_QUATECH_QSCLP200, 0 },
1095 { PCI_DEVICE_ID_QUATECH_DSCLP200, 0 },
1096 { PCI_DEVICE_ID_QUATECH_SSCLP200, 0 },
1097 { PCI_DEVICE_ID_QUATECH_SPPXP_100, 0 },
1098 { 0, }
1099 };
1100
pci_quatech_amcc(struct pci_dev * dev)1101 static int pci_quatech_amcc(struct pci_dev *dev)
1102 {
1103 struct quatech_feature *qf = &quatech_cards[0];
1104 while (qf->devid) {
1105 if (qf->devid == dev->device)
1106 return qf->amcc;
1107 qf++;
1108 }
1109 pci_err(dev, "unknown port type '0x%04X'.\n", dev->device);
1110 return 0;
1111 };
1112
pci_quatech_rqopr(struct uart_8250_port * port)1113 static int pci_quatech_rqopr(struct uart_8250_port *port)
1114 {
1115 unsigned long base = port->port.iobase;
1116 u8 LCR, val;
1117
1118 LCR = inb(base + UART_LCR);
1119 outb(0xBF, base + UART_LCR);
1120 val = inb(base + UART_SCR);
1121 outb(LCR, base + UART_LCR);
1122 return val;
1123 }
1124
pci_quatech_wqopr(struct uart_8250_port * port,u8 qopr)1125 static void pci_quatech_wqopr(struct uart_8250_port *port, u8 qopr)
1126 {
1127 unsigned long base = port->port.iobase;
1128 u8 LCR;
1129
1130 LCR = inb(base + UART_LCR);
1131 outb(0xBF, base + UART_LCR);
1132 inb(base + UART_SCR);
1133 outb(qopr, base + UART_SCR);
1134 outb(LCR, base + UART_LCR);
1135 }
1136
pci_quatech_rqmcr(struct uart_8250_port * port)1137 static int pci_quatech_rqmcr(struct uart_8250_port *port)
1138 {
1139 unsigned long base = port->port.iobase;
1140 u8 LCR, val, qmcr;
1141
1142 LCR = inb(base + UART_LCR);
1143 outb(0xBF, base + UART_LCR);
1144 val = inb(base + UART_SCR);
1145 outb(val | 0x10, base + UART_SCR);
1146 qmcr = inb(base + UART_MCR);
1147 outb(val, base + UART_SCR);
1148 outb(LCR, base + UART_LCR);
1149
1150 return qmcr;
1151 }
1152
pci_quatech_wqmcr(struct uart_8250_port * port,u8 qmcr)1153 static void pci_quatech_wqmcr(struct uart_8250_port *port, u8 qmcr)
1154 {
1155 unsigned long base = port->port.iobase;
1156 u8 LCR, val;
1157
1158 LCR = inb(base + UART_LCR);
1159 outb(0xBF, base + UART_LCR);
1160 val = inb(base + UART_SCR);
1161 outb(val | 0x10, base + UART_SCR);
1162 outb(qmcr, base + UART_MCR);
1163 outb(val, base + UART_SCR);
1164 outb(LCR, base + UART_LCR);
1165 }
1166
pci_quatech_has_qmcr(struct uart_8250_port * port)1167 static int pci_quatech_has_qmcr(struct uart_8250_port *port)
1168 {
1169 unsigned long base = port->port.iobase;
1170 u8 LCR, val;
1171
1172 LCR = inb(base + UART_LCR);
1173 outb(0xBF, base + UART_LCR);
1174 val = inb(base + UART_SCR);
1175 if (val & 0x20) {
1176 outb(0x80, UART_LCR);
1177 if (!(inb(UART_SCR) & 0x20)) {
1178 outb(LCR, base + UART_LCR);
1179 return 1;
1180 }
1181 }
1182 return 0;
1183 }
1184
pci_quatech_test(struct uart_8250_port * port)1185 static int pci_quatech_test(struct uart_8250_port *port)
1186 {
1187 u8 reg, qopr;
1188
1189 qopr = pci_quatech_rqopr(port);
1190 pci_quatech_wqopr(port, qopr & QPCR_TEST_FOR1);
1191 reg = pci_quatech_rqopr(port) & 0xC0;
1192 if (reg != QPCR_TEST_GET1)
1193 return -EINVAL;
1194 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR2);
1195 reg = pci_quatech_rqopr(port) & 0xC0;
1196 if (reg != QPCR_TEST_GET2)
1197 return -EINVAL;
1198 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR3);
1199 reg = pci_quatech_rqopr(port) & 0xC0;
1200 if (reg != QPCR_TEST_GET3)
1201 return -EINVAL;
1202 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR4);
1203 reg = pci_quatech_rqopr(port) & 0xC0;
1204 if (reg != QPCR_TEST_GET4)
1205 return -EINVAL;
1206
1207 pci_quatech_wqopr(port, qopr);
1208 return 0;
1209 }
1210
pci_quatech_clock(struct uart_8250_port * port)1211 static int pci_quatech_clock(struct uart_8250_port *port)
1212 {
1213 u8 qopr, reg, set;
1214 unsigned long clock;
1215
1216 if (pci_quatech_test(port) < 0)
1217 return 1843200;
1218
1219 qopr = pci_quatech_rqopr(port);
1220
1221 pci_quatech_wqopr(port, qopr & ~QOPR_CLOCK_X8);
1222 reg = pci_quatech_rqopr(port);
1223 if (reg & QOPR_CLOCK_X8) {
1224 clock = 1843200;
1225 goto out;
1226 }
1227 pci_quatech_wqopr(port, qopr | QOPR_CLOCK_X8);
1228 reg = pci_quatech_rqopr(port);
1229 if (!(reg & QOPR_CLOCK_X8)) {
1230 clock = 1843200;
1231 goto out;
1232 }
1233 reg &= QOPR_CLOCK_X8;
1234 if (reg == QOPR_CLOCK_X2) {
1235 clock = 3685400;
1236 set = QOPR_CLOCK_X2;
1237 } else if (reg == QOPR_CLOCK_X4) {
1238 clock = 7372800;
1239 set = QOPR_CLOCK_X4;
1240 } else if (reg == QOPR_CLOCK_X8) {
1241 clock = 14745600;
1242 set = QOPR_CLOCK_X8;
1243 } else {
1244 clock = 1843200;
1245 set = QOPR_CLOCK_X1;
1246 }
1247 qopr &= ~QOPR_CLOCK_RATE_MASK;
1248 qopr |= set;
1249
1250 out:
1251 pci_quatech_wqopr(port, qopr);
1252 return clock;
1253 }
1254
pci_quatech_rs422(struct uart_8250_port * port)1255 static int pci_quatech_rs422(struct uart_8250_port *port)
1256 {
1257 u8 qmcr;
1258 int rs422 = 0;
1259
1260 if (!pci_quatech_has_qmcr(port))
1261 return 0;
1262 qmcr = pci_quatech_rqmcr(port);
1263 pci_quatech_wqmcr(port, 0xFF);
1264 if (pci_quatech_rqmcr(port))
1265 rs422 = 1;
1266 pci_quatech_wqmcr(port, qmcr);
1267 return rs422;
1268 }
1269
pci_quatech_init(struct pci_dev * dev)1270 static int pci_quatech_init(struct pci_dev *dev)
1271 {
1272 if (pci_quatech_amcc(dev)) {
1273 unsigned long base = pci_resource_start(dev, 0);
1274 if (base) {
1275 u32 tmp;
1276
1277 outl(inl(base + 0x38) | 0x00002000, base + 0x38);
1278 tmp = inl(base + 0x3c);
1279 outl(tmp | 0x01000000, base + 0x3c);
1280 outl(tmp &= ~0x01000000, base + 0x3c);
1281 }
1282 }
1283 return 0;
1284 }
1285
pci_quatech_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1286 static int pci_quatech_setup(struct serial_private *priv,
1287 const struct pciserial_board *board,
1288 struct uart_8250_port *port, int idx)
1289 {
1290 /* Needed by pci_quatech calls below */
1291 port->port.iobase = pci_resource_start(priv->dev, FL_GET_BASE(board->flags));
1292 /* Set up the clocking */
1293 port->port.uartclk = pci_quatech_clock(port);
1294 /* For now just warn about RS422 */
1295 if (pci_quatech_rs422(port))
1296 pci_warn(priv->dev, "software control of RS422 features not currently supported.\n");
1297 return pci_default_setup(priv, board, port, idx);
1298 }
1299
pci_quatech_exit(struct pci_dev * dev)1300 static void pci_quatech_exit(struct pci_dev *dev)
1301 {
1302 }
1303
pci_default_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1304 static int pci_default_setup(struct serial_private *priv,
1305 const struct pciserial_board *board,
1306 struct uart_8250_port *port, int idx)
1307 {
1308 unsigned int bar, offset = board->first_offset, maxnr;
1309
1310 bar = FL_GET_BASE(board->flags);
1311 if (board->flags & FL_BASE_BARS)
1312 bar += idx;
1313 else
1314 offset += idx * board->uart_offset;
1315
1316 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1317 (board->reg_shift + 3);
1318
1319 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1320 return 1;
1321
1322 return setup_port(priv, port, bar, offset, board->reg_shift);
1323 }
1324 static void
pericom_do_set_divisor(struct uart_port * port,unsigned int baud,unsigned int quot,unsigned int quot_frac)1325 pericom_do_set_divisor(struct uart_port *port, unsigned int baud,
1326 unsigned int quot, unsigned int quot_frac)
1327 {
1328 int scr;
1329 int lcr;
1330
1331 for (scr = 16; scr > 4; scr--) {
1332 unsigned int maxrate = port->uartclk / scr;
1333 unsigned int divisor = max(maxrate / baud, 1U);
1334 int delta = maxrate / divisor - baud;
1335
1336 if (baud > maxrate + baud / 50)
1337 continue;
1338
1339 if (delta > baud / 50)
1340 divisor++;
1341
1342 if (divisor > 0xffff)
1343 continue;
1344
1345 /* Update delta due to possible divisor change */
1346 delta = maxrate / divisor - baud;
1347 if (abs(delta) < baud / 50) {
1348 lcr = serial_port_in(port, UART_LCR);
1349 serial_port_out(port, UART_LCR, lcr | 0x80);
1350 serial_port_out(port, UART_DLL, divisor & 0xff);
1351 serial_port_out(port, UART_DLM, divisor >> 8 & 0xff);
1352 serial_port_out(port, 2, 16 - scr);
1353 serial_port_out(port, UART_LCR, lcr);
1354 return;
1355 }
1356 }
1357 }
pci_pericom_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1358 static int pci_pericom_setup(struct serial_private *priv,
1359 const struct pciserial_board *board,
1360 struct uart_8250_port *port, int idx)
1361 {
1362 unsigned int bar, offset = board->first_offset, maxnr;
1363
1364 bar = FL_GET_BASE(board->flags);
1365 if (board->flags & FL_BASE_BARS)
1366 bar += idx;
1367 else
1368 offset += idx * board->uart_offset;
1369
1370
1371 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1372 (board->reg_shift + 3);
1373
1374 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1375 return 1;
1376
1377 port->port.set_divisor = pericom_do_set_divisor;
1378
1379 return setup_port(priv, port, bar, offset, board->reg_shift);
1380 }
1381
pci_pericom_setup_four_at_eight(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1382 static int pci_pericom_setup_four_at_eight(struct serial_private *priv,
1383 const struct pciserial_board *board,
1384 struct uart_8250_port *port, int idx)
1385 {
1386 unsigned int bar, offset = board->first_offset, maxnr;
1387
1388 bar = FL_GET_BASE(board->flags);
1389 if (board->flags & FL_BASE_BARS)
1390 bar += idx;
1391 else
1392 offset += idx * board->uart_offset;
1393
1394 if (idx==3)
1395 offset = 0x38;
1396
1397 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1398 (board->reg_shift + 3);
1399
1400 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1401 return 1;
1402
1403 port->port.set_divisor = pericom_do_set_divisor;
1404
1405 return setup_port(priv, port, bar, offset, board->reg_shift);
1406 }
1407
1408 static int
ce4100_serial_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1409 ce4100_serial_setup(struct serial_private *priv,
1410 const struct pciserial_board *board,
1411 struct uart_8250_port *port, int idx)
1412 {
1413 int ret;
1414
1415 ret = setup_port(priv, port, idx, 0, board->reg_shift);
1416 port->port.iotype = UPIO_MEM32;
1417 port->port.type = PORT_XSCALE;
1418 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1419 port->port.regshift = 2;
1420
1421 return ret;
1422 }
1423
1424 static int
pci_omegapci_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1425 pci_omegapci_setup(struct serial_private *priv,
1426 const struct pciserial_board *board,
1427 struct uart_8250_port *port, int idx)
1428 {
1429 return setup_port(priv, port, 2, idx * 8, 0);
1430 }
1431
1432 static int
pci_brcm_trumanage_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1433 pci_brcm_trumanage_setup(struct serial_private *priv,
1434 const struct pciserial_board *board,
1435 struct uart_8250_port *port, int idx)
1436 {
1437 int ret = pci_default_setup(priv, board, port, idx);
1438
1439 port->port.type = PORT_BRCM_TRUMANAGE;
1440 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1441 return ret;
1442 }
1443
1444 /* RTS will control by MCR if this bit is 0 */
1445 #define FINTEK_RTS_CONTROL_BY_HW BIT(4)
1446 /* only worked with FINTEK_RTS_CONTROL_BY_HW on */
1447 #define FINTEK_RTS_INVERT BIT(5)
1448
1449 /* We should do proper H/W transceiver setting before change to RS485 mode */
pci_fintek_rs485_config(struct uart_port * port,struct serial_rs485 * rs485)1450 static int pci_fintek_rs485_config(struct uart_port *port,
1451 struct serial_rs485 *rs485)
1452 {
1453 struct pci_dev *pci_dev = to_pci_dev(port->dev);
1454 u8 setting;
1455 u8 *index = (u8 *) port->private_data;
1456
1457 pci_read_config_byte(pci_dev, 0x40 + 8 * *index + 7, &setting);
1458
1459 if (!rs485)
1460 rs485 = &port->rs485;
1461 else if (rs485->flags & SER_RS485_ENABLED)
1462 memset(rs485->padding, 0, sizeof(rs485->padding));
1463 else
1464 memset(rs485, 0, sizeof(*rs485));
1465
1466 /* F81504/508/512 not support RTS delay before or after send */
1467 rs485->flags &= SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND;
1468
1469 if (rs485->flags & SER_RS485_ENABLED) {
1470 /* Enable RTS H/W control mode */
1471 setting |= FINTEK_RTS_CONTROL_BY_HW;
1472
1473 if (rs485->flags & SER_RS485_RTS_ON_SEND) {
1474 /* RTS driving high on TX */
1475 setting &= ~FINTEK_RTS_INVERT;
1476 } else {
1477 /* RTS driving low on TX */
1478 setting |= FINTEK_RTS_INVERT;
1479 }
1480
1481 rs485->delay_rts_after_send = 0;
1482 rs485->delay_rts_before_send = 0;
1483 } else {
1484 /* Disable RTS H/W control mode */
1485 setting &= ~(FINTEK_RTS_CONTROL_BY_HW | FINTEK_RTS_INVERT);
1486 }
1487
1488 pci_write_config_byte(pci_dev, 0x40 + 8 * *index + 7, setting);
1489
1490 if (rs485 != &port->rs485)
1491 port->rs485 = *rs485;
1492
1493 return 0;
1494 }
1495
pci_fintek_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1496 static int pci_fintek_setup(struct serial_private *priv,
1497 const struct pciserial_board *board,
1498 struct uart_8250_port *port, int idx)
1499 {
1500 struct pci_dev *pdev = priv->dev;
1501 u8 *data;
1502 u8 config_base;
1503 u16 iobase;
1504
1505 config_base = 0x40 + 0x08 * idx;
1506
1507 /* Get the io address from configuration space */
1508 pci_read_config_word(pdev, config_base + 4, &iobase);
1509
1510 pci_dbg(pdev, "idx=%d iobase=0x%x", idx, iobase);
1511
1512 port->port.iotype = UPIO_PORT;
1513 port->port.iobase = iobase;
1514 port->port.rs485_config = pci_fintek_rs485_config;
1515
1516 data = devm_kzalloc(&pdev->dev, sizeof(u8), GFP_KERNEL);
1517 if (!data)
1518 return -ENOMEM;
1519
1520 /* preserve index in PCI configuration space */
1521 *data = idx;
1522 port->port.private_data = data;
1523
1524 return 0;
1525 }
1526
pci_fintek_init(struct pci_dev * dev)1527 static int pci_fintek_init(struct pci_dev *dev)
1528 {
1529 unsigned long iobase;
1530 u32 max_port, i;
1531 resource_size_t bar_data[3];
1532 u8 config_base;
1533 struct serial_private *priv = pci_get_drvdata(dev);
1534
1535 if (!(pci_resource_flags(dev, 5) & IORESOURCE_IO) ||
1536 !(pci_resource_flags(dev, 4) & IORESOURCE_IO) ||
1537 !(pci_resource_flags(dev, 3) & IORESOURCE_IO))
1538 return -ENODEV;
1539
1540 switch (dev->device) {
1541 case 0x1104: /* 4 ports */
1542 case 0x1108: /* 8 ports */
1543 max_port = dev->device & 0xff;
1544 break;
1545 case 0x1112: /* 12 ports */
1546 max_port = 12;
1547 break;
1548 default:
1549 return -EINVAL;
1550 }
1551
1552 /* Get the io address dispatch from the BIOS */
1553 bar_data[0] = pci_resource_start(dev, 5);
1554 bar_data[1] = pci_resource_start(dev, 4);
1555 bar_data[2] = pci_resource_start(dev, 3);
1556
1557 for (i = 0; i < max_port; ++i) {
1558 /* UART0 configuration offset start from 0x40 */
1559 config_base = 0x40 + 0x08 * i;
1560
1561 /* Calculate Real IO Port */
1562 iobase = (bar_data[i / 4] & 0xffffffe0) + (i % 4) * 8;
1563
1564 /* Enable UART I/O port */
1565 pci_write_config_byte(dev, config_base + 0x00, 0x01);
1566
1567 /* Select 128-byte FIFO and 8x FIFO threshold */
1568 pci_write_config_byte(dev, config_base + 0x01, 0x33);
1569
1570 /* LSB UART */
1571 pci_write_config_byte(dev, config_base + 0x04,
1572 (u8)(iobase & 0xff));
1573
1574 /* MSB UART */
1575 pci_write_config_byte(dev, config_base + 0x05,
1576 (u8)((iobase & 0xff00) >> 8));
1577
1578 pci_write_config_byte(dev, config_base + 0x06, dev->irq);
1579
1580 if (!priv) {
1581 /* First init without port data
1582 * force init to RS232 Mode
1583 */
1584 pci_write_config_byte(dev, config_base + 0x07, 0x01);
1585 }
1586 }
1587
1588 return max_port;
1589 }
1590
f815xxa_mem_serial_out(struct uart_port * p,int offset,int value)1591 static void f815xxa_mem_serial_out(struct uart_port *p, int offset, int value)
1592 {
1593 struct f815xxa_data *data = p->private_data;
1594 unsigned long flags;
1595
1596 spin_lock_irqsave(&data->lock, flags);
1597 writeb(value, p->membase + offset);
1598 readb(p->membase + UART_SCR); /* Dummy read for flush pcie tx queue */
1599 spin_unlock_irqrestore(&data->lock, flags);
1600 }
1601
pci_fintek_f815xxa_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1602 static int pci_fintek_f815xxa_setup(struct serial_private *priv,
1603 const struct pciserial_board *board,
1604 struct uart_8250_port *port, int idx)
1605 {
1606 struct pci_dev *pdev = priv->dev;
1607 struct f815xxa_data *data;
1608
1609 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
1610 if (!data)
1611 return -ENOMEM;
1612
1613 data->idx = idx;
1614 spin_lock_init(&data->lock);
1615
1616 port->port.private_data = data;
1617 port->port.iotype = UPIO_MEM;
1618 port->port.flags |= UPF_IOREMAP;
1619 port->port.mapbase = pci_resource_start(pdev, 0) + 8 * idx;
1620 port->port.serial_out = f815xxa_mem_serial_out;
1621
1622 return 0;
1623 }
1624
pci_fintek_f815xxa_init(struct pci_dev * dev)1625 static int pci_fintek_f815xxa_init(struct pci_dev *dev)
1626 {
1627 u32 max_port, i;
1628 int config_base;
1629
1630 if (!(pci_resource_flags(dev, 0) & IORESOURCE_MEM))
1631 return -ENODEV;
1632
1633 switch (dev->device) {
1634 case 0x1204: /* 4 ports */
1635 case 0x1208: /* 8 ports */
1636 max_port = dev->device & 0xff;
1637 break;
1638 case 0x1212: /* 12 ports */
1639 max_port = 12;
1640 break;
1641 default:
1642 return -EINVAL;
1643 }
1644
1645 /* Set to mmio decode */
1646 pci_write_config_byte(dev, 0x209, 0x40);
1647
1648 for (i = 0; i < max_port; ++i) {
1649 /* UART0 configuration offset start from 0x2A0 */
1650 config_base = 0x2A0 + 0x08 * i;
1651
1652 /* Select 128-byte FIFO and 8x FIFO threshold */
1653 pci_write_config_byte(dev, config_base + 0x01, 0x33);
1654
1655 /* Enable UART I/O port */
1656 pci_write_config_byte(dev, config_base + 0, 0x01);
1657 }
1658
1659 return max_port;
1660 }
1661
skip_tx_en_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1662 static int skip_tx_en_setup(struct serial_private *priv,
1663 const struct pciserial_board *board,
1664 struct uart_8250_port *port, int idx)
1665 {
1666 port->port.quirks |= UPQ_NO_TXEN_TEST;
1667 pci_dbg(priv->dev,
1668 "serial8250: skipping TxEn test for device [%04x:%04x] subsystem [%04x:%04x]\n",
1669 priv->dev->vendor, priv->dev->device,
1670 priv->dev->subsystem_vendor, priv->dev->subsystem_device);
1671
1672 return pci_default_setup(priv, board, port, idx);
1673 }
1674
kt_handle_break(struct uart_port * p)1675 static void kt_handle_break(struct uart_port *p)
1676 {
1677 struct uart_8250_port *up = up_to_u8250p(p);
1678 /*
1679 * On receipt of a BI, serial device in Intel ME (Intel
1680 * management engine) needs to have its fifos cleared for sane
1681 * SOL (Serial Over Lan) output.
1682 */
1683 serial8250_clear_and_reinit_fifos(up);
1684 }
1685
kt_serial_in(struct uart_port * p,int offset)1686 static unsigned int kt_serial_in(struct uart_port *p, int offset)
1687 {
1688 struct uart_8250_port *up = up_to_u8250p(p);
1689 unsigned int val;
1690
1691 /*
1692 * When the Intel ME (management engine) gets reset its serial
1693 * port registers could return 0 momentarily. Functions like
1694 * serial8250_console_write, read and save the IER, perform
1695 * some operation and then restore it. In order to avoid
1696 * setting IER register inadvertently to 0, if the value read
1697 * is 0, double check with ier value in uart_8250_port and use
1698 * that instead. up->ier should be the same value as what is
1699 * currently configured.
1700 */
1701 val = inb(p->iobase + offset);
1702 if (offset == UART_IER) {
1703 if (val == 0)
1704 val = up->ier;
1705 }
1706 return val;
1707 }
1708
kt_serial_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1709 static int kt_serial_setup(struct serial_private *priv,
1710 const struct pciserial_board *board,
1711 struct uart_8250_port *port, int idx)
1712 {
1713 port->port.flags |= UPF_BUG_THRE;
1714 port->port.serial_in = kt_serial_in;
1715 port->port.handle_break = kt_handle_break;
1716 return skip_tx_en_setup(priv, board, port, idx);
1717 }
1718
pci_eg20t_init(struct pci_dev * dev)1719 static int pci_eg20t_init(struct pci_dev *dev)
1720 {
1721 #if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE)
1722 return -ENODEV;
1723 #else
1724 return 0;
1725 #endif
1726 }
1727
1728 static int
pci_wch_ch353_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1729 pci_wch_ch353_setup(struct serial_private *priv,
1730 const struct pciserial_board *board,
1731 struct uart_8250_port *port, int idx)
1732 {
1733 port->port.flags |= UPF_FIXED_TYPE;
1734 port->port.type = PORT_16550A;
1735 return pci_default_setup(priv, board, port, idx);
1736 }
1737
1738 static int
pci_wch_ch355_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1739 pci_wch_ch355_setup(struct serial_private *priv,
1740 const struct pciserial_board *board,
1741 struct uart_8250_port *port, int idx)
1742 {
1743 port->port.flags |= UPF_FIXED_TYPE;
1744 port->port.type = PORT_16550A;
1745 return pci_default_setup(priv, board, port, idx);
1746 }
1747
1748 static int
pci_wch_ch38x_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1749 pci_wch_ch38x_setup(struct serial_private *priv,
1750 const struct pciserial_board *board,
1751 struct uart_8250_port *port, int idx)
1752 {
1753 port->port.flags |= UPF_FIXED_TYPE;
1754 port->port.type = PORT_16850;
1755 return pci_default_setup(priv, board, port, idx);
1756 }
1757
1758
1759 #define CH384_XINT_ENABLE_REG 0xEB
1760 #define CH384_XINT_ENABLE_BIT 0x02
1761
pci_wch_ch38x_init(struct pci_dev * dev)1762 static int pci_wch_ch38x_init(struct pci_dev *dev)
1763 {
1764 int max_port;
1765 unsigned long iobase;
1766
1767
1768 switch (dev->device) {
1769 case 0x3853: /* 8 ports */
1770 max_port = 8;
1771 break;
1772 default:
1773 return -EINVAL;
1774 }
1775
1776 iobase = pci_resource_start(dev, 0);
1777 outb(CH384_XINT_ENABLE_BIT, iobase + CH384_XINT_ENABLE_REG);
1778
1779 return max_port;
1780 }
1781
pci_wch_ch38x_exit(struct pci_dev * dev)1782 static void pci_wch_ch38x_exit(struct pci_dev *dev)
1783 {
1784 unsigned long iobase;
1785
1786 iobase = pci_resource_start(dev, 0);
1787 outb(0x0, iobase + CH384_XINT_ENABLE_REG);
1788 }
1789
1790
1791 static int
pci_sunix_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1792 pci_sunix_setup(struct serial_private *priv,
1793 const struct pciserial_board *board,
1794 struct uart_8250_port *port, int idx)
1795 {
1796 int bar;
1797 int offset;
1798
1799 port->port.flags |= UPF_FIXED_TYPE;
1800 port->port.type = PORT_SUNIX;
1801
1802 if (idx < 4) {
1803 bar = 0;
1804 offset = idx * board->uart_offset;
1805 } else {
1806 bar = 1;
1807 idx -= 4;
1808 idx = div_s64_rem(idx, 4, &offset);
1809 offset = idx * 64 + offset * board->uart_offset;
1810 }
1811
1812 return setup_port(priv, port, bar, offset, 0);
1813 }
1814
1815 static int
pci_moxa_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1816 pci_moxa_setup(struct serial_private *priv,
1817 const struct pciserial_board *board,
1818 struct uart_8250_port *port, int idx)
1819 {
1820 unsigned int bar = FL_GET_BASE(board->flags);
1821 int offset;
1822
1823 if (board->num_ports == 4 && idx == 3)
1824 offset = 7 * board->uart_offset;
1825 else
1826 offset = idx * board->uart_offset;
1827
1828 return setup_port(priv, port, bar, offset, 0);
1829 }
1830
1831 #define PCI_VENDOR_ID_SBSMODULARIO 0x124B
1832 #define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
1833 #define PCI_DEVICE_ID_OCTPRO 0x0001
1834 #define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
1835 #define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
1836 #define PCI_SUBDEVICE_ID_POCTAL232 0x0308
1837 #define PCI_SUBDEVICE_ID_POCTAL422 0x0408
1838 #define PCI_SUBDEVICE_ID_SIIG_DUAL_00 0x2500
1839 #define PCI_SUBDEVICE_ID_SIIG_DUAL_30 0x2530
1840 #define PCI_VENDOR_ID_ADVANTECH 0x13fe
1841 #define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
1842 #define PCI_DEVICE_ID_ADVANTECH_PCI1600 0x1600
1843 #define PCI_DEVICE_ID_ADVANTECH_PCI1600_1611 0x1611
1844 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
1845 #define PCI_DEVICE_ID_ADVANTECH_PCI3618 0x3618
1846 #define PCI_DEVICE_ID_ADVANTECH_PCIf618 0xf618
1847 #define PCI_DEVICE_ID_TITAN_200I 0x8028
1848 #define PCI_DEVICE_ID_TITAN_400I 0x8048
1849 #define PCI_DEVICE_ID_TITAN_800I 0x8088
1850 #define PCI_DEVICE_ID_TITAN_800EH 0xA007
1851 #define PCI_DEVICE_ID_TITAN_800EHB 0xA008
1852 #define PCI_DEVICE_ID_TITAN_400EH 0xA009
1853 #define PCI_DEVICE_ID_TITAN_100E 0xA010
1854 #define PCI_DEVICE_ID_TITAN_200E 0xA012
1855 #define PCI_DEVICE_ID_TITAN_400E 0xA013
1856 #define PCI_DEVICE_ID_TITAN_800E 0xA014
1857 #define PCI_DEVICE_ID_TITAN_200EI 0xA016
1858 #define PCI_DEVICE_ID_TITAN_200EISI 0xA017
1859 #define PCI_DEVICE_ID_TITAN_200V3 0xA306
1860 #define PCI_DEVICE_ID_TITAN_400V3 0xA310
1861 #define PCI_DEVICE_ID_TITAN_410V3 0xA312
1862 #define PCI_DEVICE_ID_TITAN_800V3 0xA314
1863 #define PCI_DEVICE_ID_TITAN_800V3B 0xA315
1864 #define PCI_DEVICE_ID_OXSEMI_16PCI958 0x9538
1865 #define PCIE_DEVICE_ID_NEO_2_OX_IBM 0x00F6
1866 #define PCI_DEVICE_ID_PLX_CRONYX_OMEGA 0xc001
1867 #define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d
1868 #define PCI_VENDOR_ID_WCH 0x4348
1869 #define PCI_DEVICE_ID_WCH_CH352_2S 0x3253
1870 #define PCI_DEVICE_ID_WCH_CH353_4S 0x3453
1871 #define PCI_DEVICE_ID_WCH_CH353_2S1PF 0x5046
1872 #define PCI_DEVICE_ID_WCH_CH353_1S1P 0x5053
1873 #define PCI_DEVICE_ID_WCH_CH353_2S1P 0x7053
1874 #define PCI_DEVICE_ID_WCH_CH355_4S 0x7173
1875 #define PCI_VENDOR_ID_AGESTAR 0x5372
1876 #define PCI_DEVICE_ID_AGESTAR_9375 0x6872
1877 #define PCI_VENDOR_ID_ASIX 0x9710
1878 #define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a
1879 #define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e
1880
1881 #define PCIE_VENDOR_ID_WCH 0x1c00
1882 #define PCIE_DEVICE_ID_WCH_CH382_2S1P 0x3250
1883 #define PCIE_DEVICE_ID_WCH_CH384_4S 0x3470
1884 #define PCIE_DEVICE_ID_WCH_CH384_8S 0x3853
1885 #define PCIE_DEVICE_ID_WCH_CH382_2S 0x3253
1886
1887 #define PCI_VENDOR_ID_ACCESIO 0x494f
1888 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SDB 0x1051
1889 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2S 0x1053
1890 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SDB 0x105C
1891 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4S 0x105E
1892 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_2DB 0x1091
1893 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_2 0x1093
1894 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4DB 0x1099
1895 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_4 0x109B
1896 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SMDB 0x10D1
1897 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2SM 0x10D3
1898 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SMDB 0x10DA
1899 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4SM 0x10DC
1900 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_1 0x1108
1901 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_2 0x1110
1902 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_2 0x1111
1903 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_4 0x1118
1904 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_4 0x1119
1905 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2S 0x1152
1906 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4S 0x115A
1907 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_2 0x1190
1908 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_2 0x1191
1909 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_4 0x1198
1910 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_4 0x1199
1911 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2SM 0x11D0
1912 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM422_4 0x105A
1913 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM485_4 0x105B
1914 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM422_8 0x106A
1915 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM485_8 0x106B
1916 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4 0x1098
1917 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_8 0x10A9
1918 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SM 0x10D9
1919 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_8SM 0x10E9
1920 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4SM 0x11D8
1921
1922
1923 #define PCI_DEVICE_ID_MOXA_CP102E 0x1024
1924 #define PCI_DEVICE_ID_MOXA_CP102EL 0x1025
1925 #define PCI_DEVICE_ID_MOXA_CP104EL_A 0x1045
1926 #define PCI_DEVICE_ID_MOXA_CP114EL 0x1144
1927 #define PCI_DEVICE_ID_MOXA_CP116E_A_A 0x1160
1928 #define PCI_DEVICE_ID_MOXA_CP116E_A_B 0x1161
1929 #define PCI_DEVICE_ID_MOXA_CP118EL_A 0x1182
1930 #define PCI_DEVICE_ID_MOXA_CP118E_A_I 0x1183
1931 #define PCI_DEVICE_ID_MOXA_CP132EL 0x1322
1932 #define PCI_DEVICE_ID_MOXA_CP134EL_A 0x1342
1933 #define PCI_DEVICE_ID_MOXA_CP138E_A 0x1381
1934 #define PCI_DEVICE_ID_MOXA_CP168EL_A 0x1683
1935
1936 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */
1937 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
1938 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588
1939
1940 /*
1941 * Master list of serial port init/setup/exit quirks.
1942 * This does not describe the general nature of the port.
1943 * (ie, baud base, number and location of ports, etc)
1944 *
1945 * This list is ordered alphabetically by vendor then device.
1946 * Specific entries must come before more generic entries.
1947 */
1948 static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
1949 /*
1950 * ADDI-DATA GmbH communication cards <info@addi-data.com>
1951 */
1952 {
1953 .vendor = PCI_VENDOR_ID_AMCC,
1954 .device = PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
1955 .subvendor = PCI_ANY_ID,
1956 .subdevice = PCI_ANY_ID,
1957 .setup = addidata_apci7800_setup,
1958 },
1959 /*
1960 * AFAVLAB cards - these may be called via parport_serial
1961 * It is not clear whether this applies to all products.
1962 */
1963 {
1964 .vendor = PCI_VENDOR_ID_AFAVLAB,
1965 .device = PCI_ANY_ID,
1966 .subvendor = PCI_ANY_ID,
1967 .subdevice = PCI_ANY_ID,
1968 .setup = afavlab_setup,
1969 },
1970 /*
1971 * HP Diva
1972 */
1973 {
1974 .vendor = PCI_VENDOR_ID_HP,
1975 .device = PCI_DEVICE_ID_HP_DIVA,
1976 .subvendor = PCI_ANY_ID,
1977 .subdevice = PCI_ANY_ID,
1978 .init = pci_hp_diva_init,
1979 .setup = pci_hp_diva_setup,
1980 },
1981 /*
1982 * HPE PCI serial device
1983 */
1984 {
1985 .vendor = PCI_VENDOR_ID_HP_3PAR,
1986 .device = PCI_DEVICE_ID_HPE_PCI_SERIAL,
1987 .subvendor = PCI_ANY_ID,
1988 .subdevice = PCI_ANY_ID,
1989 .setup = pci_hp_diva_setup,
1990 },
1991 /*
1992 * Intel
1993 */
1994 {
1995 .vendor = PCI_VENDOR_ID_INTEL,
1996 .device = PCI_DEVICE_ID_INTEL_80960_RP,
1997 .subvendor = 0xe4bf,
1998 .subdevice = PCI_ANY_ID,
1999 .init = pci_inteli960ni_init,
2000 .setup = pci_default_setup,
2001 },
2002 {
2003 .vendor = PCI_VENDOR_ID_INTEL,
2004 .device = PCI_DEVICE_ID_INTEL_8257X_SOL,
2005 .subvendor = PCI_ANY_ID,
2006 .subdevice = PCI_ANY_ID,
2007 .setup = skip_tx_en_setup,
2008 },
2009 {
2010 .vendor = PCI_VENDOR_ID_INTEL,
2011 .device = PCI_DEVICE_ID_INTEL_82573L_SOL,
2012 .subvendor = PCI_ANY_ID,
2013 .subdevice = PCI_ANY_ID,
2014 .setup = skip_tx_en_setup,
2015 },
2016 {
2017 .vendor = PCI_VENDOR_ID_INTEL,
2018 .device = PCI_DEVICE_ID_INTEL_82573E_SOL,
2019 .subvendor = PCI_ANY_ID,
2020 .subdevice = PCI_ANY_ID,
2021 .setup = skip_tx_en_setup,
2022 },
2023 {
2024 .vendor = PCI_VENDOR_ID_INTEL,
2025 .device = PCI_DEVICE_ID_INTEL_CE4100_UART,
2026 .subvendor = PCI_ANY_ID,
2027 .subdevice = PCI_ANY_ID,
2028 .setup = ce4100_serial_setup,
2029 },
2030 {
2031 .vendor = PCI_VENDOR_ID_INTEL,
2032 .device = PCI_DEVICE_ID_INTEL_PATSBURG_KT,
2033 .subvendor = PCI_ANY_ID,
2034 .subdevice = PCI_ANY_ID,
2035 .setup = kt_serial_setup,
2036 },
2037 /*
2038 * ITE
2039 */
2040 {
2041 .vendor = PCI_VENDOR_ID_ITE,
2042 .device = PCI_DEVICE_ID_ITE_8872,
2043 .subvendor = PCI_ANY_ID,
2044 .subdevice = PCI_ANY_ID,
2045 .init = pci_ite887x_init,
2046 .setup = pci_default_setup,
2047 .exit = pci_ite887x_exit,
2048 },
2049 /*
2050 * National Instruments
2051 */
2052 {
2053 .vendor = PCI_VENDOR_ID_NI,
2054 .device = PCI_DEVICE_ID_NI_PCI23216,
2055 .subvendor = PCI_ANY_ID,
2056 .subdevice = PCI_ANY_ID,
2057 .init = pci_ni8420_init,
2058 .setup = pci_default_setup,
2059 .exit = pci_ni8420_exit,
2060 },
2061 {
2062 .vendor = PCI_VENDOR_ID_NI,
2063 .device = PCI_DEVICE_ID_NI_PCI2328,
2064 .subvendor = PCI_ANY_ID,
2065 .subdevice = PCI_ANY_ID,
2066 .init = pci_ni8420_init,
2067 .setup = pci_default_setup,
2068 .exit = pci_ni8420_exit,
2069 },
2070 {
2071 .vendor = PCI_VENDOR_ID_NI,
2072 .device = PCI_DEVICE_ID_NI_PCI2324,
2073 .subvendor = PCI_ANY_ID,
2074 .subdevice = PCI_ANY_ID,
2075 .init = pci_ni8420_init,
2076 .setup = pci_default_setup,
2077 .exit = pci_ni8420_exit,
2078 },
2079 {
2080 .vendor = PCI_VENDOR_ID_NI,
2081 .device = PCI_DEVICE_ID_NI_PCI2322,
2082 .subvendor = PCI_ANY_ID,
2083 .subdevice = PCI_ANY_ID,
2084 .init = pci_ni8420_init,
2085 .setup = pci_default_setup,
2086 .exit = pci_ni8420_exit,
2087 },
2088 {
2089 .vendor = PCI_VENDOR_ID_NI,
2090 .device = PCI_DEVICE_ID_NI_PCI2324I,
2091 .subvendor = PCI_ANY_ID,
2092 .subdevice = PCI_ANY_ID,
2093 .init = pci_ni8420_init,
2094 .setup = pci_default_setup,
2095 .exit = pci_ni8420_exit,
2096 },
2097 {
2098 .vendor = PCI_VENDOR_ID_NI,
2099 .device = PCI_DEVICE_ID_NI_PCI2322I,
2100 .subvendor = PCI_ANY_ID,
2101 .subdevice = PCI_ANY_ID,
2102 .init = pci_ni8420_init,
2103 .setup = pci_default_setup,
2104 .exit = pci_ni8420_exit,
2105 },
2106 {
2107 .vendor = PCI_VENDOR_ID_NI,
2108 .device = PCI_DEVICE_ID_NI_PXI8420_23216,
2109 .subvendor = PCI_ANY_ID,
2110 .subdevice = PCI_ANY_ID,
2111 .init = pci_ni8420_init,
2112 .setup = pci_default_setup,
2113 .exit = pci_ni8420_exit,
2114 },
2115 {
2116 .vendor = PCI_VENDOR_ID_NI,
2117 .device = PCI_DEVICE_ID_NI_PXI8420_2328,
2118 .subvendor = PCI_ANY_ID,
2119 .subdevice = PCI_ANY_ID,
2120 .init = pci_ni8420_init,
2121 .setup = pci_default_setup,
2122 .exit = pci_ni8420_exit,
2123 },
2124 {
2125 .vendor = PCI_VENDOR_ID_NI,
2126 .device = PCI_DEVICE_ID_NI_PXI8420_2324,
2127 .subvendor = PCI_ANY_ID,
2128 .subdevice = PCI_ANY_ID,
2129 .init = pci_ni8420_init,
2130 .setup = pci_default_setup,
2131 .exit = pci_ni8420_exit,
2132 },
2133 {
2134 .vendor = PCI_VENDOR_ID_NI,
2135 .device = PCI_DEVICE_ID_NI_PXI8420_2322,
2136 .subvendor = PCI_ANY_ID,
2137 .subdevice = PCI_ANY_ID,
2138 .init = pci_ni8420_init,
2139 .setup = pci_default_setup,
2140 .exit = pci_ni8420_exit,
2141 },
2142 {
2143 .vendor = PCI_VENDOR_ID_NI,
2144 .device = PCI_DEVICE_ID_NI_PXI8422_2324,
2145 .subvendor = PCI_ANY_ID,
2146 .subdevice = PCI_ANY_ID,
2147 .init = pci_ni8420_init,
2148 .setup = pci_default_setup,
2149 .exit = pci_ni8420_exit,
2150 },
2151 {
2152 .vendor = PCI_VENDOR_ID_NI,
2153 .device = PCI_DEVICE_ID_NI_PXI8422_2322,
2154 .subvendor = PCI_ANY_ID,
2155 .subdevice = PCI_ANY_ID,
2156 .init = pci_ni8420_init,
2157 .setup = pci_default_setup,
2158 .exit = pci_ni8420_exit,
2159 },
2160 {
2161 .vendor = PCI_VENDOR_ID_NI,
2162 .device = PCI_ANY_ID,
2163 .subvendor = PCI_ANY_ID,
2164 .subdevice = PCI_ANY_ID,
2165 .init = pci_ni8430_init,
2166 .setup = pci_ni8430_setup,
2167 .exit = pci_ni8430_exit,
2168 },
2169 /* Quatech */
2170 {
2171 .vendor = PCI_VENDOR_ID_QUATECH,
2172 .device = PCI_ANY_ID,
2173 .subvendor = PCI_ANY_ID,
2174 .subdevice = PCI_ANY_ID,
2175 .init = pci_quatech_init,
2176 .setup = pci_quatech_setup,
2177 .exit = pci_quatech_exit,
2178 },
2179 /*
2180 * Panacom
2181 */
2182 {
2183 .vendor = PCI_VENDOR_ID_PANACOM,
2184 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM,
2185 .subvendor = PCI_ANY_ID,
2186 .subdevice = PCI_ANY_ID,
2187 .init = pci_plx9050_init,
2188 .setup = pci_default_setup,
2189 .exit = pci_plx9050_exit,
2190 },
2191 {
2192 .vendor = PCI_VENDOR_ID_PANACOM,
2193 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM,
2194 .subvendor = PCI_ANY_ID,
2195 .subdevice = PCI_ANY_ID,
2196 .init = pci_plx9050_init,
2197 .setup = pci_default_setup,
2198 .exit = pci_plx9050_exit,
2199 },
2200 /*
2201 * Pericom (Only 7954 - It have a offset jump for port 4)
2202 */
2203 {
2204 .vendor = PCI_VENDOR_ID_PERICOM,
2205 .device = PCI_DEVICE_ID_PERICOM_PI7C9X7954,
2206 .subvendor = PCI_ANY_ID,
2207 .subdevice = PCI_ANY_ID,
2208 .setup = pci_pericom_setup_four_at_eight,
2209 },
2210 /*
2211 * PLX
2212 */
2213 {
2214 .vendor = PCI_VENDOR_ID_PLX,
2215 .device = PCI_DEVICE_ID_PLX_9050,
2216 .subvendor = PCI_SUBVENDOR_ID_EXSYS,
2217 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055,
2218 .init = pci_plx9050_init,
2219 .setup = pci_default_setup,
2220 .exit = pci_plx9050_exit,
2221 },
2222 {
2223 .vendor = PCI_VENDOR_ID_PLX,
2224 .device = PCI_DEVICE_ID_PLX_9050,
2225 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN,
2226 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
2227 .init = pci_plx9050_init,
2228 .setup = pci_default_setup,
2229 .exit = pci_plx9050_exit,
2230 },
2231 {
2232 .vendor = PCI_VENDOR_ID_PLX,
2233 .device = PCI_DEVICE_ID_PLX_ROMULUS,
2234 .subvendor = PCI_VENDOR_ID_PLX,
2235 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS,
2236 .init = pci_plx9050_init,
2237 .setup = pci_default_setup,
2238 .exit = pci_plx9050_exit,
2239 },
2240 {
2241 .vendor = PCI_VENDOR_ID_ACCESIO,
2242 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SDB,
2243 .subvendor = PCI_ANY_ID,
2244 .subdevice = PCI_ANY_ID,
2245 .setup = pci_pericom_setup_four_at_eight,
2246 },
2247 {
2248 .vendor = PCI_VENDOR_ID_ACCESIO,
2249 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4S,
2250 .subvendor = PCI_ANY_ID,
2251 .subdevice = PCI_ANY_ID,
2252 .setup = pci_pericom_setup_four_at_eight,
2253 },
2254 {
2255 .vendor = PCI_VENDOR_ID_ACCESIO,
2256 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4DB,
2257 .subvendor = PCI_ANY_ID,
2258 .subdevice = PCI_ANY_ID,
2259 .setup = pci_pericom_setup_four_at_eight,
2260 },
2261 {
2262 .vendor = PCI_VENDOR_ID_ACCESIO,
2263 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_4,
2264 .subvendor = PCI_ANY_ID,
2265 .subdevice = PCI_ANY_ID,
2266 .setup = pci_pericom_setup_four_at_eight,
2267 },
2268 {
2269 .vendor = PCI_VENDOR_ID_ACCESIO,
2270 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SMDB,
2271 .subvendor = PCI_ANY_ID,
2272 .subdevice = PCI_ANY_ID,
2273 .setup = pci_pericom_setup_four_at_eight,
2274 },
2275 {
2276 .vendor = PCI_VENDOR_ID_ACCESIO,
2277 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4SM,
2278 .subvendor = PCI_ANY_ID,
2279 .subdevice = PCI_ANY_ID,
2280 .setup = pci_pericom_setup_four_at_eight,
2281 },
2282 {
2283 .vendor = PCI_VENDOR_ID_ACCESIO,
2284 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_4,
2285 .subvendor = PCI_ANY_ID,
2286 .subdevice = PCI_ANY_ID,
2287 .setup = pci_pericom_setup_four_at_eight,
2288 },
2289 {
2290 .vendor = PCI_VENDOR_ID_ACCESIO,
2291 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_4,
2292 .subvendor = PCI_ANY_ID,
2293 .subdevice = PCI_ANY_ID,
2294 .setup = pci_pericom_setup_four_at_eight,
2295 },
2296 {
2297 .vendor = PCI_VENDOR_ID_ACCESIO,
2298 .device = PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_4,
2299 .subvendor = PCI_ANY_ID,
2300 .subdevice = PCI_ANY_ID,
2301 .setup = pci_pericom_setup_four_at_eight,
2302 },
2303 {
2304 .vendor = PCI_VENDOR_ID_ACCESIO,
2305 .device = PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4S,
2306 .subvendor = PCI_ANY_ID,
2307 .subdevice = PCI_ANY_ID,
2308 .setup = pci_pericom_setup_four_at_eight,
2309 },
2310 {
2311 .vendor = PCI_VENDOR_ID_ACCESIO,
2312 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_4,
2313 .subvendor = PCI_ANY_ID,
2314 .subdevice = PCI_ANY_ID,
2315 .setup = pci_pericom_setup_four_at_eight,
2316 },
2317 {
2318 .vendor = PCI_VENDOR_ID_ACCESIO,
2319 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM422_4,
2320 .subvendor = PCI_ANY_ID,
2321 .subdevice = PCI_ANY_ID,
2322 .setup = pci_pericom_setup_four_at_eight,
2323 },
2324 {
2325 .vendor = PCI_VENDOR_ID_ACCESIO,
2326 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM485_4,
2327 .subvendor = PCI_ANY_ID,
2328 .subdevice = PCI_ANY_ID,
2329 .setup = pci_pericom_setup_four_at_eight,
2330 },
2331 {
2332 .vendor = PCI_VENDOR_ID_ACCESIO,
2333 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4,
2334 .subvendor = PCI_ANY_ID,
2335 .subdevice = PCI_ANY_ID,
2336 .setup = pci_pericom_setup_four_at_eight,
2337 },
2338 {
2339 .vendor = PCI_VENDOR_ID_ACCESIO,
2340 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SM,
2341 .subvendor = PCI_ANY_ID,
2342 .subdevice = PCI_ANY_ID,
2343 .setup = pci_pericom_setup_four_at_eight,
2344 },
2345 {
2346 .vendor = PCI_VENDOR_ID_ACCESIO,
2347 .device = PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4SM,
2348 .subvendor = PCI_ANY_ID,
2349 .subdevice = PCI_ANY_ID,
2350 .setup = pci_pericom_setup_four_at_eight,
2351 },
2352 {
2353 .vendor = PCI_VENDOR_ID_ACCESIO,
2354 .device = PCI_ANY_ID,
2355 .subvendor = PCI_ANY_ID,
2356 .subdevice = PCI_ANY_ID,
2357 .setup = pci_pericom_setup,
2358 }, /*
2359 * SBS Technologies, Inc., PMC-OCTALPRO 232
2360 */
2361 {
2362 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2363 .device = PCI_DEVICE_ID_OCTPRO,
2364 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2365 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232,
2366 .init = sbs_init,
2367 .setup = sbs_setup,
2368 .exit = sbs_exit,
2369 },
2370 /*
2371 * SBS Technologies, Inc., PMC-OCTALPRO 422
2372 */
2373 {
2374 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2375 .device = PCI_DEVICE_ID_OCTPRO,
2376 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2377 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422,
2378 .init = sbs_init,
2379 .setup = sbs_setup,
2380 .exit = sbs_exit,
2381 },
2382 /*
2383 * SBS Technologies, Inc., P-Octal 232
2384 */
2385 {
2386 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2387 .device = PCI_DEVICE_ID_OCTPRO,
2388 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2389 .subdevice = PCI_SUBDEVICE_ID_POCTAL232,
2390 .init = sbs_init,
2391 .setup = sbs_setup,
2392 .exit = sbs_exit,
2393 },
2394 /*
2395 * SBS Technologies, Inc., P-Octal 422
2396 */
2397 {
2398 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2399 .device = PCI_DEVICE_ID_OCTPRO,
2400 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2401 .subdevice = PCI_SUBDEVICE_ID_POCTAL422,
2402 .init = sbs_init,
2403 .setup = sbs_setup,
2404 .exit = sbs_exit,
2405 },
2406 /*
2407 * SIIG cards - these may be called via parport_serial
2408 */
2409 {
2410 .vendor = PCI_VENDOR_ID_SIIG,
2411 .device = PCI_ANY_ID,
2412 .subvendor = PCI_ANY_ID,
2413 .subdevice = PCI_ANY_ID,
2414 .init = pci_siig_init,
2415 .setup = pci_siig_setup,
2416 },
2417 /*
2418 * Titan cards
2419 */
2420 {
2421 .vendor = PCI_VENDOR_ID_TITAN,
2422 .device = PCI_DEVICE_ID_TITAN_400L,
2423 .subvendor = PCI_ANY_ID,
2424 .subdevice = PCI_ANY_ID,
2425 .setup = titan_400l_800l_setup,
2426 },
2427 {
2428 .vendor = PCI_VENDOR_ID_TITAN,
2429 .device = PCI_DEVICE_ID_TITAN_800L,
2430 .subvendor = PCI_ANY_ID,
2431 .subdevice = PCI_ANY_ID,
2432 .setup = titan_400l_800l_setup,
2433 },
2434 /*
2435 * Timedia cards
2436 */
2437 {
2438 .vendor = PCI_VENDOR_ID_TIMEDIA,
2439 .device = PCI_DEVICE_ID_TIMEDIA_1889,
2440 .subvendor = PCI_VENDOR_ID_TIMEDIA,
2441 .subdevice = PCI_ANY_ID,
2442 .probe = pci_timedia_probe,
2443 .init = pci_timedia_init,
2444 .setup = pci_timedia_setup,
2445 },
2446 {
2447 .vendor = PCI_VENDOR_ID_TIMEDIA,
2448 .device = PCI_ANY_ID,
2449 .subvendor = PCI_ANY_ID,
2450 .subdevice = PCI_ANY_ID,
2451 .setup = pci_timedia_setup,
2452 },
2453 /*
2454 * Sunix PCI serial boards
2455 */
2456 {
2457 .vendor = PCI_VENDOR_ID_SUNIX,
2458 .device = PCI_DEVICE_ID_SUNIX_1999,
2459 .subvendor = PCI_VENDOR_ID_SUNIX,
2460 .subdevice = PCI_ANY_ID,
2461 .setup = pci_sunix_setup,
2462 },
2463 /*
2464 * Xircom cards
2465 */
2466 {
2467 .vendor = PCI_VENDOR_ID_XIRCOM,
2468 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
2469 .subvendor = PCI_ANY_ID,
2470 .subdevice = PCI_ANY_ID,
2471 .init = pci_xircom_init,
2472 .setup = pci_default_setup,
2473 },
2474 /*
2475 * Netmos cards - these may be called via parport_serial
2476 */
2477 {
2478 .vendor = PCI_VENDOR_ID_NETMOS,
2479 .device = PCI_ANY_ID,
2480 .subvendor = PCI_ANY_ID,
2481 .subdevice = PCI_ANY_ID,
2482 .init = pci_netmos_init,
2483 .setup = pci_netmos_9900_setup,
2484 },
2485 /*
2486 * EndRun Technologies
2487 */
2488 {
2489 .vendor = PCI_VENDOR_ID_ENDRUN,
2490 .device = PCI_ANY_ID,
2491 .subvendor = PCI_ANY_ID,
2492 .subdevice = PCI_ANY_ID,
2493 .init = pci_oxsemi_tornado_init,
2494 .setup = pci_default_setup,
2495 },
2496 /*
2497 * For Oxford Semiconductor Tornado based devices
2498 */
2499 {
2500 .vendor = PCI_VENDOR_ID_OXSEMI,
2501 .device = PCI_ANY_ID,
2502 .subvendor = PCI_ANY_ID,
2503 .subdevice = PCI_ANY_ID,
2504 .init = pci_oxsemi_tornado_init,
2505 .setup = pci_default_setup,
2506 },
2507 {
2508 .vendor = PCI_VENDOR_ID_MAINPINE,
2509 .device = PCI_ANY_ID,
2510 .subvendor = PCI_ANY_ID,
2511 .subdevice = PCI_ANY_ID,
2512 .init = pci_oxsemi_tornado_init,
2513 .setup = pci_default_setup,
2514 },
2515 {
2516 .vendor = PCI_VENDOR_ID_DIGI,
2517 .device = PCIE_DEVICE_ID_NEO_2_OX_IBM,
2518 .subvendor = PCI_SUBVENDOR_ID_IBM,
2519 .subdevice = PCI_ANY_ID,
2520 .init = pci_oxsemi_tornado_init,
2521 .setup = pci_default_setup,
2522 },
2523 {
2524 .vendor = PCI_VENDOR_ID_INTEL,
2525 .device = 0x8811,
2526 .subvendor = PCI_ANY_ID,
2527 .subdevice = PCI_ANY_ID,
2528 .init = pci_eg20t_init,
2529 .setup = pci_default_setup,
2530 },
2531 {
2532 .vendor = PCI_VENDOR_ID_INTEL,
2533 .device = 0x8812,
2534 .subvendor = PCI_ANY_ID,
2535 .subdevice = PCI_ANY_ID,
2536 .init = pci_eg20t_init,
2537 .setup = pci_default_setup,
2538 },
2539 {
2540 .vendor = PCI_VENDOR_ID_INTEL,
2541 .device = 0x8813,
2542 .subvendor = PCI_ANY_ID,
2543 .subdevice = PCI_ANY_ID,
2544 .init = pci_eg20t_init,
2545 .setup = pci_default_setup,
2546 },
2547 {
2548 .vendor = PCI_VENDOR_ID_INTEL,
2549 .device = 0x8814,
2550 .subvendor = PCI_ANY_ID,
2551 .subdevice = PCI_ANY_ID,
2552 .init = pci_eg20t_init,
2553 .setup = pci_default_setup,
2554 },
2555 {
2556 .vendor = 0x10DB,
2557 .device = 0x8027,
2558 .subvendor = PCI_ANY_ID,
2559 .subdevice = PCI_ANY_ID,
2560 .init = pci_eg20t_init,
2561 .setup = pci_default_setup,
2562 },
2563 {
2564 .vendor = 0x10DB,
2565 .device = 0x8028,
2566 .subvendor = PCI_ANY_ID,
2567 .subdevice = PCI_ANY_ID,
2568 .init = pci_eg20t_init,
2569 .setup = pci_default_setup,
2570 },
2571 {
2572 .vendor = 0x10DB,
2573 .device = 0x8029,
2574 .subvendor = PCI_ANY_ID,
2575 .subdevice = PCI_ANY_ID,
2576 .init = pci_eg20t_init,
2577 .setup = pci_default_setup,
2578 },
2579 {
2580 .vendor = 0x10DB,
2581 .device = 0x800C,
2582 .subvendor = PCI_ANY_ID,
2583 .subdevice = PCI_ANY_ID,
2584 .init = pci_eg20t_init,
2585 .setup = pci_default_setup,
2586 },
2587 {
2588 .vendor = 0x10DB,
2589 .device = 0x800D,
2590 .subvendor = PCI_ANY_ID,
2591 .subdevice = PCI_ANY_ID,
2592 .init = pci_eg20t_init,
2593 .setup = pci_default_setup,
2594 },
2595 /*
2596 * Cronyx Omega PCI (PLX-chip based)
2597 */
2598 {
2599 .vendor = PCI_VENDOR_ID_PLX,
2600 .device = PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
2601 .subvendor = PCI_ANY_ID,
2602 .subdevice = PCI_ANY_ID,
2603 .setup = pci_omegapci_setup,
2604 },
2605 /* WCH CH353 1S1P card (16550 clone) */
2606 {
2607 .vendor = PCI_VENDOR_ID_WCH,
2608 .device = PCI_DEVICE_ID_WCH_CH353_1S1P,
2609 .subvendor = PCI_ANY_ID,
2610 .subdevice = PCI_ANY_ID,
2611 .setup = pci_wch_ch353_setup,
2612 },
2613 /* WCH CH353 2S1P card (16550 clone) */
2614 {
2615 .vendor = PCI_VENDOR_ID_WCH,
2616 .device = PCI_DEVICE_ID_WCH_CH353_2S1P,
2617 .subvendor = PCI_ANY_ID,
2618 .subdevice = PCI_ANY_ID,
2619 .setup = pci_wch_ch353_setup,
2620 },
2621 /* WCH CH353 4S card (16550 clone) */
2622 {
2623 .vendor = PCI_VENDOR_ID_WCH,
2624 .device = PCI_DEVICE_ID_WCH_CH353_4S,
2625 .subvendor = PCI_ANY_ID,
2626 .subdevice = PCI_ANY_ID,
2627 .setup = pci_wch_ch353_setup,
2628 },
2629 /* WCH CH353 2S1PF card (16550 clone) */
2630 {
2631 .vendor = PCI_VENDOR_ID_WCH,
2632 .device = PCI_DEVICE_ID_WCH_CH353_2S1PF,
2633 .subvendor = PCI_ANY_ID,
2634 .subdevice = PCI_ANY_ID,
2635 .setup = pci_wch_ch353_setup,
2636 },
2637 /* WCH CH352 2S card (16550 clone) */
2638 {
2639 .vendor = PCI_VENDOR_ID_WCH,
2640 .device = PCI_DEVICE_ID_WCH_CH352_2S,
2641 .subvendor = PCI_ANY_ID,
2642 .subdevice = PCI_ANY_ID,
2643 .setup = pci_wch_ch353_setup,
2644 },
2645 /* WCH CH355 4S card (16550 clone) */
2646 {
2647 .vendor = PCI_VENDOR_ID_WCH,
2648 .device = PCI_DEVICE_ID_WCH_CH355_4S,
2649 .subvendor = PCI_ANY_ID,
2650 .subdevice = PCI_ANY_ID,
2651 .setup = pci_wch_ch355_setup,
2652 },
2653 /* WCH CH382 2S card (16850 clone) */
2654 {
2655 .vendor = PCIE_VENDOR_ID_WCH,
2656 .device = PCIE_DEVICE_ID_WCH_CH382_2S,
2657 .subvendor = PCI_ANY_ID,
2658 .subdevice = PCI_ANY_ID,
2659 .setup = pci_wch_ch38x_setup,
2660 },
2661 /* WCH CH382 2S1P card (16850 clone) */
2662 {
2663 .vendor = PCIE_VENDOR_ID_WCH,
2664 .device = PCIE_DEVICE_ID_WCH_CH382_2S1P,
2665 .subvendor = PCI_ANY_ID,
2666 .subdevice = PCI_ANY_ID,
2667 .setup = pci_wch_ch38x_setup,
2668 },
2669 /* WCH CH384 4S card (16850 clone) */
2670 {
2671 .vendor = PCIE_VENDOR_ID_WCH,
2672 .device = PCIE_DEVICE_ID_WCH_CH384_4S,
2673 .subvendor = PCI_ANY_ID,
2674 .subdevice = PCI_ANY_ID,
2675 .setup = pci_wch_ch38x_setup,
2676 },
2677 /* WCH CH384 8S card (16850 clone) */
2678 {
2679 .vendor = PCIE_VENDOR_ID_WCH,
2680 .device = PCIE_DEVICE_ID_WCH_CH384_8S,
2681 .subvendor = PCI_ANY_ID,
2682 .subdevice = PCI_ANY_ID,
2683 .init = pci_wch_ch38x_init,
2684 .exit = pci_wch_ch38x_exit,
2685 .setup = pci_wch_ch38x_setup,
2686 },
2687 /*
2688 * ASIX devices with FIFO bug
2689 */
2690 {
2691 .vendor = PCI_VENDOR_ID_ASIX,
2692 .device = PCI_ANY_ID,
2693 .subvendor = PCI_ANY_ID,
2694 .subdevice = PCI_ANY_ID,
2695 .setup = pci_asix_setup,
2696 },
2697 /*
2698 * Broadcom TruManage (NetXtreme)
2699 */
2700 {
2701 .vendor = PCI_VENDOR_ID_BROADCOM,
2702 .device = PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
2703 .subvendor = PCI_ANY_ID,
2704 .subdevice = PCI_ANY_ID,
2705 .setup = pci_brcm_trumanage_setup,
2706 },
2707 {
2708 .vendor = 0x1c29,
2709 .device = 0x1104,
2710 .subvendor = PCI_ANY_ID,
2711 .subdevice = PCI_ANY_ID,
2712 .setup = pci_fintek_setup,
2713 .init = pci_fintek_init,
2714 },
2715 {
2716 .vendor = 0x1c29,
2717 .device = 0x1108,
2718 .subvendor = PCI_ANY_ID,
2719 .subdevice = PCI_ANY_ID,
2720 .setup = pci_fintek_setup,
2721 .init = pci_fintek_init,
2722 },
2723 {
2724 .vendor = 0x1c29,
2725 .device = 0x1112,
2726 .subvendor = PCI_ANY_ID,
2727 .subdevice = PCI_ANY_ID,
2728 .setup = pci_fintek_setup,
2729 .init = pci_fintek_init,
2730 },
2731 /*
2732 * MOXA
2733 */
2734 {
2735 .vendor = PCI_VENDOR_ID_MOXA,
2736 .device = PCI_ANY_ID,
2737 .subvendor = PCI_ANY_ID,
2738 .subdevice = PCI_ANY_ID,
2739 .setup = pci_moxa_setup,
2740 },
2741 {
2742 .vendor = 0x1c29,
2743 .device = 0x1204,
2744 .subvendor = PCI_ANY_ID,
2745 .subdevice = PCI_ANY_ID,
2746 .setup = pci_fintek_f815xxa_setup,
2747 .init = pci_fintek_f815xxa_init,
2748 },
2749 {
2750 .vendor = 0x1c29,
2751 .device = 0x1208,
2752 .subvendor = PCI_ANY_ID,
2753 .subdevice = PCI_ANY_ID,
2754 .setup = pci_fintek_f815xxa_setup,
2755 .init = pci_fintek_f815xxa_init,
2756 },
2757 {
2758 .vendor = 0x1c29,
2759 .device = 0x1212,
2760 .subvendor = PCI_ANY_ID,
2761 .subdevice = PCI_ANY_ID,
2762 .setup = pci_fintek_f815xxa_setup,
2763 .init = pci_fintek_f815xxa_init,
2764 },
2765
2766 /*
2767 * Default "match everything" terminator entry
2768 */
2769 {
2770 .vendor = PCI_ANY_ID,
2771 .device = PCI_ANY_ID,
2772 .subvendor = PCI_ANY_ID,
2773 .subdevice = PCI_ANY_ID,
2774 .setup = pci_default_setup,
2775 }
2776 };
2777
quirk_id_matches(u32 quirk_id,u32 dev_id)2778 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
2779 {
2780 return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
2781 }
2782
find_quirk(struct pci_dev * dev)2783 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
2784 {
2785 struct pci_serial_quirk *quirk;
2786
2787 for (quirk = pci_serial_quirks; ; quirk++)
2788 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
2789 quirk_id_matches(quirk->device, dev->device) &&
2790 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
2791 quirk_id_matches(quirk->subdevice, dev->subsystem_device))
2792 break;
2793 return quirk;
2794 }
2795
2796 /*
2797 * This is the configuration table for all of the PCI serial boards
2798 * which we support. It is directly indexed by the pci_board_num_t enum
2799 * value, which is encoded in the pci_device_id PCI probe table's
2800 * driver_data member.
2801 *
2802 * The makeup of these names are:
2803 * pbn_bn{_bt}_n_baud{_offsetinhex}
2804 *
2805 * bn = PCI BAR number
2806 * bt = Index using PCI BARs
2807 * n = number of serial ports
2808 * baud = baud rate
2809 * offsetinhex = offset for each sequential port (in hex)
2810 *
2811 * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
2812 *
2813 * Please note: in theory if n = 1, _bt infix should make no difference.
2814 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
2815 */
2816 enum pci_board_num_t {
2817 pbn_default = 0,
2818
2819 pbn_b0_1_115200,
2820 pbn_b0_2_115200,
2821 pbn_b0_4_115200,
2822 pbn_b0_5_115200,
2823 pbn_b0_8_115200,
2824
2825 pbn_b0_1_921600,
2826 pbn_b0_2_921600,
2827 pbn_b0_4_921600,
2828
2829 pbn_b0_2_1130000,
2830
2831 pbn_b0_4_1152000,
2832
2833 pbn_b0_4_1250000,
2834
2835 pbn_b0_2_1843200,
2836 pbn_b0_4_1843200,
2837
2838 pbn_b0_1_3906250,
2839
2840 pbn_b0_bt_1_115200,
2841 pbn_b0_bt_2_115200,
2842 pbn_b0_bt_4_115200,
2843 pbn_b0_bt_8_115200,
2844
2845 pbn_b0_bt_1_460800,
2846 pbn_b0_bt_2_460800,
2847 pbn_b0_bt_4_460800,
2848
2849 pbn_b0_bt_1_921600,
2850 pbn_b0_bt_2_921600,
2851 pbn_b0_bt_4_921600,
2852 pbn_b0_bt_8_921600,
2853
2854 pbn_b1_1_115200,
2855 pbn_b1_2_115200,
2856 pbn_b1_4_115200,
2857 pbn_b1_8_115200,
2858 pbn_b1_16_115200,
2859
2860 pbn_b1_1_921600,
2861 pbn_b1_2_921600,
2862 pbn_b1_4_921600,
2863 pbn_b1_8_921600,
2864
2865 pbn_b1_2_1250000,
2866
2867 pbn_b1_bt_1_115200,
2868 pbn_b1_bt_2_115200,
2869 pbn_b1_bt_4_115200,
2870
2871 pbn_b1_bt_2_921600,
2872
2873 pbn_b1_1_1382400,
2874 pbn_b1_2_1382400,
2875 pbn_b1_4_1382400,
2876 pbn_b1_8_1382400,
2877
2878 pbn_b2_1_115200,
2879 pbn_b2_2_115200,
2880 pbn_b2_4_115200,
2881 pbn_b2_8_115200,
2882
2883 pbn_b2_1_460800,
2884 pbn_b2_4_460800,
2885 pbn_b2_8_460800,
2886 pbn_b2_16_460800,
2887
2888 pbn_b2_1_921600,
2889 pbn_b2_4_921600,
2890 pbn_b2_8_921600,
2891
2892 pbn_b2_8_1152000,
2893
2894 pbn_b2_bt_1_115200,
2895 pbn_b2_bt_2_115200,
2896 pbn_b2_bt_4_115200,
2897
2898 pbn_b2_bt_2_921600,
2899 pbn_b2_bt_4_921600,
2900
2901 pbn_b3_2_115200,
2902 pbn_b3_4_115200,
2903 pbn_b3_8_115200,
2904
2905 pbn_b4_bt_2_921600,
2906 pbn_b4_bt_4_921600,
2907 pbn_b4_bt_8_921600,
2908
2909 /*
2910 * Board-specific versions.
2911 */
2912 pbn_panacom,
2913 pbn_panacom2,
2914 pbn_panacom4,
2915 pbn_plx_romulus,
2916 pbn_oxsemi,
2917 pbn_oxsemi_1_3906250,
2918 pbn_oxsemi_2_3906250,
2919 pbn_oxsemi_4_3906250,
2920 pbn_oxsemi_8_3906250,
2921 pbn_intel_i960,
2922 pbn_sgi_ioc3,
2923 pbn_computone_4,
2924 pbn_computone_6,
2925 pbn_computone_8,
2926 pbn_sbsxrsio,
2927 pbn_pasemi_1682M,
2928 pbn_ni8430_2,
2929 pbn_ni8430_4,
2930 pbn_ni8430_8,
2931 pbn_ni8430_16,
2932 pbn_ADDIDATA_PCIe_1_3906250,
2933 pbn_ADDIDATA_PCIe_2_3906250,
2934 pbn_ADDIDATA_PCIe_4_3906250,
2935 pbn_ADDIDATA_PCIe_8_3906250,
2936 pbn_ce4100_1_115200,
2937 pbn_omegapci,
2938 pbn_NETMOS9900_2s_115200,
2939 pbn_brcm_trumanage,
2940 pbn_fintek_4,
2941 pbn_fintek_8,
2942 pbn_fintek_12,
2943 pbn_fintek_F81504A,
2944 pbn_fintek_F81508A,
2945 pbn_fintek_F81512A,
2946 pbn_wch382_2,
2947 pbn_wch384_4,
2948 pbn_wch384_8,
2949 pbn_pericom_PI7C9X7951,
2950 pbn_pericom_PI7C9X7952,
2951 pbn_pericom_PI7C9X7954,
2952 pbn_pericom_PI7C9X7958,
2953 pbn_sunix_pci_1s,
2954 pbn_sunix_pci_2s,
2955 pbn_sunix_pci_4s,
2956 pbn_sunix_pci_8s,
2957 pbn_sunix_pci_16s,
2958 pbn_titan_1_4000000,
2959 pbn_titan_2_4000000,
2960 pbn_titan_4_4000000,
2961 pbn_titan_8_4000000,
2962 pbn_moxa8250_2p,
2963 pbn_moxa8250_4p,
2964 pbn_moxa8250_8p,
2965 };
2966
2967 /*
2968 * uart_offset - the space between channels
2969 * reg_shift - describes how the UART registers are mapped
2970 * to PCI memory by the card.
2971 * For example IER register on SBS, Inc. PMC-OctPro is located at
2972 * offset 0x10 from the UART base, while UART_IER is defined as 1
2973 * in include/linux/serial_reg.h,
2974 * see first lines of serial_in() and serial_out() in 8250.c
2975 */
2976
2977 static struct pciserial_board pci_boards[] = {
2978 [pbn_default] = {
2979 .flags = FL_BASE0,
2980 .num_ports = 1,
2981 .base_baud = 115200,
2982 .uart_offset = 8,
2983 },
2984 [pbn_b0_1_115200] = {
2985 .flags = FL_BASE0,
2986 .num_ports = 1,
2987 .base_baud = 115200,
2988 .uart_offset = 8,
2989 },
2990 [pbn_b0_2_115200] = {
2991 .flags = FL_BASE0,
2992 .num_ports = 2,
2993 .base_baud = 115200,
2994 .uart_offset = 8,
2995 },
2996 [pbn_b0_4_115200] = {
2997 .flags = FL_BASE0,
2998 .num_ports = 4,
2999 .base_baud = 115200,
3000 .uart_offset = 8,
3001 },
3002 [pbn_b0_5_115200] = {
3003 .flags = FL_BASE0,
3004 .num_ports = 5,
3005 .base_baud = 115200,
3006 .uart_offset = 8,
3007 },
3008 [pbn_b0_8_115200] = {
3009 .flags = FL_BASE0,
3010 .num_ports = 8,
3011 .base_baud = 115200,
3012 .uart_offset = 8,
3013 },
3014 [pbn_b0_1_921600] = {
3015 .flags = FL_BASE0,
3016 .num_ports = 1,
3017 .base_baud = 921600,
3018 .uart_offset = 8,
3019 },
3020 [pbn_b0_2_921600] = {
3021 .flags = FL_BASE0,
3022 .num_ports = 2,
3023 .base_baud = 921600,
3024 .uart_offset = 8,
3025 },
3026 [pbn_b0_4_921600] = {
3027 .flags = FL_BASE0,
3028 .num_ports = 4,
3029 .base_baud = 921600,
3030 .uart_offset = 8,
3031 },
3032
3033 [pbn_b0_2_1130000] = {
3034 .flags = FL_BASE0,
3035 .num_ports = 2,
3036 .base_baud = 1130000,
3037 .uart_offset = 8,
3038 },
3039
3040 [pbn_b0_4_1152000] = {
3041 .flags = FL_BASE0,
3042 .num_ports = 4,
3043 .base_baud = 1152000,
3044 .uart_offset = 8,
3045 },
3046
3047 [pbn_b0_4_1250000] = {
3048 .flags = FL_BASE0,
3049 .num_ports = 4,
3050 .base_baud = 1250000,
3051 .uart_offset = 8,
3052 },
3053
3054 [pbn_b0_2_1843200] = {
3055 .flags = FL_BASE0,
3056 .num_ports = 2,
3057 .base_baud = 1843200,
3058 .uart_offset = 8,
3059 },
3060 [pbn_b0_4_1843200] = {
3061 .flags = FL_BASE0,
3062 .num_ports = 4,
3063 .base_baud = 1843200,
3064 .uart_offset = 8,
3065 },
3066
3067 [pbn_b0_1_3906250] = {
3068 .flags = FL_BASE0,
3069 .num_ports = 1,
3070 .base_baud = 3906250,
3071 .uart_offset = 8,
3072 },
3073
3074 [pbn_b0_bt_1_115200] = {
3075 .flags = FL_BASE0|FL_BASE_BARS,
3076 .num_ports = 1,
3077 .base_baud = 115200,
3078 .uart_offset = 8,
3079 },
3080 [pbn_b0_bt_2_115200] = {
3081 .flags = FL_BASE0|FL_BASE_BARS,
3082 .num_ports = 2,
3083 .base_baud = 115200,
3084 .uart_offset = 8,
3085 },
3086 [pbn_b0_bt_4_115200] = {
3087 .flags = FL_BASE0|FL_BASE_BARS,
3088 .num_ports = 4,
3089 .base_baud = 115200,
3090 .uart_offset = 8,
3091 },
3092 [pbn_b0_bt_8_115200] = {
3093 .flags = FL_BASE0|FL_BASE_BARS,
3094 .num_ports = 8,
3095 .base_baud = 115200,
3096 .uart_offset = 8,
3097 },
3098
3099 [pbn_b0_bt_1_460800] = {
3100 .flags = FL_BASE0|FL_BASE_BARS,
3101 .num_ports = 1,
3102 .base_baud = 460800,
3103 .uart_offset = 8,
3104 },
3105 [pbn_b0_bt_2_460800] = {
3106 .flags = FL_BASE0|FL_BASE_BARS,
3107 .num_ports = 2,
3108 .base_baud = 460800,
3109 .uart_offset = 8,
3110 },
3111 [pbn_b0_bt_4_460800] = {
3112 .flags = FL_BASE0|FL_BASE_BARS,
3113 .num_ports = 4,
3114 .base_baud = 460800,
3115 .uart_offset = 8,
3116 },
3117
3118 [pbn_b0_bt_1_921600] = {
3119 .flags = FL_BASE0|FL_BASE_BARS,
3120 .num_ports = 1,
3121 .base_baud = 921600,
3122 .uart_offset = 8,
3123 },
3124 [pbn_b0_bt_2_921600] = {
3125 .flags = FL_BASE0|FL_BASE_BARS,
3126 .num_ports = 2,
3127 .base_baud = 921600,
3128 .uart_offset = 8,
3129 },
3130 [pbn_b0_bt_4_921600] = {
3131 .flags = FL_BASE0|FL_BASE_BARS,
3132 .num_ports = 4,
3133 .base_baud = 921600,
3134 .uart_offset = 8,
3135 },
3136 [pbn_b0_bt_8_921600] = {
3137 .flags = FL_BASE0|FL_BASE_BARS,
3138 .num_ports = 8,
3139 .base_baud = 921600,
3140 .uart_offset = 8,
3141 },
3142
3143 [pbn_b1_1_115200] = {
3144 .flags = FL_BASE1,
3145 .num_ports = 1,
3146 .base_baud = 115200,
3147 .uart_offset = 8,
3148 },
3149 [pbn_b1_2_115200] = {
3150 .flags = FL_BASE1,
3151 .num_ports = 2,
3152 .base_baud = 115200,
3153 .uart_offset = 8,
3154 },
3155 [pbn_b1_4_115200] = {
3156 .flags = FL_BASE1,
3157 .num_ports = 4,
3158 .base_baud = 115200,
3159 .uart_offset = 8,
3160 },
3161 [pbn_b1_8_115200] = {
3162 .flags = FL_BASE1,
3163 .num_ports = 8,
3164 .base_baud = 115200,
3165 .uart_offset = 8,
3166 },
3167 [pbn_b1_16_115200] = {
3168 .flags = FL_BASE1,
3169 .num_ports = 16,
3170 .base_baud = 115200,
3171 .uart_offset = 8,
3172 },
3173
3174 [pbn_b1_1_921600] = {
3175 .flags = FL_BASE1,
3176 .num_ports = 1,
3177 .base_baud = 921600,
3178 .uart_offset = 8,
3179 },
3180 [pbn_b1_2_921600] = {
3181 .flags = FL_BASE1,
3182 .num_ports = 2,
3183 .base_baud = 921600,
3184 .uart_offset = 8,
3185 },
3186 [pbn_b1_4_921600] = {
3187 .flags = FL_BASE1,
3188 .num_ports = 4,
3189 .base_baud = 921600,
3190 .uart_offset = 8,
3191 },
3192 [pbn_b1_8_921600] = {
3193 .flags = FL_BASE1,
3194 .num_ports = 8,
3195 .base_baud = 921600,
3196 .uart_offset = 8,
3197 },
3198 [pbn_b1_2_1250000] = {
3199 .flags = FL_BASE1,
3200 .num_ports = 2,
3201 .base_baud = 1250000,
3202 .uart_offset = 8,
3203 },
3204
3205 [pbn_b1_bt_1_115200] = {
3206 .flags = FL_BASE1|FL_BASE_BARS,
3207 .num_ports = 1,
3208 .base_baud = 115200,
3209 .uart_offset = 8,
3210 },
3211 [pbn_b1_bt_2_115200] = {
3212 .flags = FL_BASE1|FL_BASE_BARS,
3213 .num_ports = 2,
3214 .base_baud = 115200,
3215 .uart_offset = 8,
3216 },
3217 [pbn_b1_bt_4_115200] = {
3218 .flags = FL_BASE1|FL_BASE_BARS,
3219 .num_ports = 4,
3220 .base_baud = 115200,
3221 .uart_offset = 8,
3222 },
3223
3224 [pbn_b1_bt_2_921600] = {
3225 .flags = FL_BASE1|FL_BASE_BARS,
3226 .num_ports = 2,
3227 .base_baud = 921600,
3228 .uart_offset = 8,
3229 },
3230
3231 [pbn_b1_1_1382400] = {
3232 .flags = FL_BASE1,
3233 .num_ports = 1,
3234 .base_baud = 1382400,
3235 .uart_offset = 8,
3236 },
3237 [pbn_b1_2_1382400] = {
3238 .flags = FL_BASE1,
3239 .num_ports = 2,
3240 .base_baud = 1382400,
3241 .uart_offset = 8,
3242 },
3243 [pbn_b1_4_1382400] = {
3244 .flags = FL_BASE1,
3245 .num_ports = 4,
3246 .base_baud = 1382400,
3247 .uart_offset = 8,
3248 },
3249 [pbn_b1_8_1382400] = {
3250 .flags = FL_BASE1,
3251 .num_ports = 8,
3252 .base_baud = 1382400,
3253 .uart_offset = 8,
3254 },
3255
3256 [pbn_b2_1_115200] = {
3257 .flags = FL_BASE2,
3258 .num_ports = 1,
3259 .base_baud = 115200,
3260 .uart_offset = 8,
3261 },
3262 [pbn_b2_2_115200] = {
3263 .flags = FL_BASE2,
3264 .num_ports = 2,
3265 .base_baud = 115200,
3266 .uart_offset = 8,
3267 },
3268 [pbn_b2_4_115200] = {
3269 .flags = FL_BASE2,
3270 .num_ports = 4,
3271 .base_baud = 115200,
3272 .uart_offset = 8,
3273 },
3274 [pbn_b2_8_115200] = {
3275 .flags = FL_BASE2,
3276 .num_ports = 8,
3277 .base_baud = 115200,
3278 .uart_offset = 8,
3279 },
3280
3281 [pbn_b2_1_460800] = {
3282 .flags = FL_BASE2,
3283 .num_ports = 1,
3284 .base_baud = 460800,
3285 .uart_offset = 8,
3286 },
3287 [pbn_b2_4_460800] = {
3288 .flags = FL_BASE2,
3289 .num_ports = 4,
3290 .base_baud = 460800,
3291 .uart_offset = 8,
3292 },
3293 [pbn_b2_8_460800] = {
3294 .flags = FL_BASE2,
3295 .num_ports = 8,
3296 .base_baud = 460800,
3297 .uart_offset = 8,
3298 },
3299 [pbn_b2_16_460800] = {
3300 .flags = FL_BASE2,
3301 .num_ports = 16,
3302 .base_baud = 460800,
3303 .uart_offset = 8,
3304 },
3305
3306 [pbn_b2_1_921600] = {
3307 .flags = FL_BASE2,
3308 .num_ports = 1,
3309 .base_baud = 921600,
3310 .uart_offset = 8,
3311 },
3312 [pbn_b2_4_921600] = {
3313 .flags = FL_BASE2,
3314 .num_ports = 4,
3315 .base_baud = 921600,
3316 .uart_offset = 8,
3317 },
3318 [pbn_b2_8_921600] = {
3319 .flags = FL_BASE2,
3320 .num_ports = 8,
3321 .base_baud = 921600,
3322 .uart_offset = 8,
3323 },
3324
3325 [pbn_b2_8_1152000] = {
3326 .flags = FL_BASE2,
3327 .num_ports = 8,
3328 .base_baud = 1152000,
3329 .uart_offset = 8,
3330 },
3331
3332 [pbn_b2_bt_1_115200] = {
3333 .flags = FL_BASE2|FL_BASE_BARS,
3334 .num_ports = 1,
3335 .base_baud = 115200,
3336 .uart_offset = 8,
3337 },
3338 [pbn_b2_bt_2_115200] = {
3339 .flags = FL_BASE2|FL_BASE_BARS,
3340 .num_ports = 2,
3341 .base_baud = 115200,
3342 .uart_offset = 8,
3343 },
3344 [pbn_b2_bt_4_115200] = {
3345 .flags = FL_BASE2|FL_BASE_BARS,
3346 .num_ports = 4,
3347 .base_baud = 115200,
3348 .uart_offset = 8,
3349 },
3350
3351 [pbn_b2_bt_2_921600] = {
3352 .flags = FL_BASE2|FL_BASE_BARS,
3353 .num_ports = 2,
3354 .base_baud = 921600,
3355 .uart_offset = 8,
3356 },
3357 [pbn_b2_bt_4_921600] = {
3358 .flags = FL_BASE2|FL_BASE_BARS,
3359 .num_ports = 4,
3360 .base_baud = 921600,
3361 .uart_offset = 8,
3362 },
3363
3364 [pbn_b3_2_115200] = {
3365 .flags = FL_BASE3,
3366 .num_ports = 2,
3367 .base_baud = 115200,
3368 .uart_offset = 8,
3369 },
3370 [pbn_b3_4_115200] = {
3371 .flags = FL_BASE3,
3372 .num_ports = 4,
3373 .base_baud = 115200,
3374 .uart_offset = 8,
3375 },
3376 [pbn_b3_8_115200] = {
3377 .flags = FL_BASE3,
3378 .num_ports = 8,
3379 .base_baud = 115200,
3380 .uart_offset = 8,
3381 },
3382
3383 [pbn_b4_bt_2_921600] = {
3384 .flags = FL_BASE4,
3385 .num_ports = 2,
3386 .base_baud = 921600,
3387 .uart_offset = 8,
3388 },
3389 [pbn_b4_bt_4_921600] = {
3390 .flags = FL_BASE4,
3391 .num_ports = 4,
3392 .base_baud = 921600,
3393 .uart_offset = 8,
3394 },
3395 [pbn_b4_bt_8_921600] = {
3396 .flags = FL_BASE4,
3397 .num_ports = 8,
3398 .base_baud = 921600,
3399 .uart_offset = 8,
3400 },
3401
3402 /*
3403 * Entries following this are board-specific.
3404 */
3405
3406 /*
3407 * Panacom - IOMEM
3408 */
3409 [pbn_panacom] = {
3410 .flags = FL_BASE2,
3411 .num_ports = 2,
3412 .base_baud = 921600,
3413 .uart_offset = 0x400,
3414 .reg_shift = 7,
3415 },
3416 [pbn_panacom2] = {
3417 .flags = FL_BASE2|FL_BASE_BARS,
3418 .num_ports = 2,
3419 .base_baud = 921600,
3420 .uart_offset = 0x400,
3421 .reg_shift = 7,
3422 },
3423 [pbn_panacom4] = {
3424 .flags = FL_BASE2|FL_BASE_BARS,
3425 .num_ports = 4,
3426 .base_baud = 921600,
3427 .uart_offset = 0x400,
3428 .reg_shift = 7,
3429 },
3430
3431 /* I think this entry is broken - the first_offset looks wrong --rmk */
3432 [pbn_plx_romulus] = {
3433 .flags = FL_BASE2,
3434 .num_ports = 4,
3435 .base_baud = 921600,
3436 .uart_offset = 8 << 2,
3437 .reg_shift = 2,
3438 .first_offset = 0x03,
3439 },
3440
3441 /*
3442 * This board uses the size of PCI Base region 0 to
3443 * signal now many ports are available
3444 */
3445 [pbn_oxsemi] = {
3446 .flags = FL_BASE0|FL_REGION_SZ_CAP,
3447 .num_ports = 32,
3448 .base_baud = 115200,
3449 .uart_offset = 8,
3450 },
3451 [pbn_oxsemi_1_3906250] = {
3452 .flags = FL_BASE0,
3453 .num_ports = 1,
3454 .base_baud = 3906250,
3455 .uart_offset = 0x200,
3456 .first_offset = 0x1000,
3457 },
3458 [pbn_oxsemi_2_3906250] = {
3459 .flags = FL_BASE0,
3460 .num_ports = 2,
3461 .base_baud = 3906250,
3462 .uart_offset = 0x200,
3463 .first_offset = 0x1000,
3464 },
3465 [pbn_oxsemi_4_3906250] = {
3466 .flags = FL_BASE0,
3467 .num_ports = 4,
3468 .base_baud = 3906250,
3469 .uart_offset = 0x200,
3470 .first_offset = 0x1000,
3471 },
3472 [pbn_oxsemi_8_3906250] = {
3473 .flags = FL_BASE0,
3474 .num_ports = 8,
3475 .base_baud = 3906250,
3476 .uart_offset = 0x200,
3477 .first_offset = 0x1000,
3478 },
3479
3480
3481 /*
3482 * EKF addition for i960 Boards form EKF with serial port.
3483 * Max 256 ports.
3484 */
3485 [pbn_intel_i960] = {
3486 .flags = FL_BASE0,
3487 .num_ports = 32,
3488 .base_baud = 921600,
3489 .uart_offset = 8 << 2,
3490 .reg_shift = 2,
3491 .first_offset = 0x10000,
3492 },
3493 [pbn_sgi_ioc3] = {
3494 .flags = FL_BASE0|FL_NOIRQ,
3495 .num_ports = 1,
3496 .base_baud = 458333,
3497 .uart_offset = 8,
3498 .reg_shift = 0,
3499 .first_offset = 0x20178,
3500 },
3501
3502 /*
3503 * Computone - uses IOMEM.
3504 */
3505 [pbn_computone_4] = {
3506 .flags = FL_BASE0,
3507 .num_ports = 4,
3508 .base_baud = 921600,
3509 .uart_offset = 0x40,
3510 .reg_shift = 2,
3511 .first_offset = 0x200,
3512 },
3513 [pbn_computone_6] = {
3514 .flags = FL_BASE0,
3515 .num_ports = 6,
3516 .base_baud = 921600,
3517 .uart_offset = 0x40,
3518 .reg_shift = 2,
3519 .first_offset = 0x200,
3520 },
3521 [pbn_computone_8] = {
3522 .flags = FL_BASE0,
3523 .num_ports = 8,
3524 .base_baud = 921600,
3525 .uart_offset = 0x40,
3526 .reg_shift = 2,
3527 .first_offset = 0x200,
3528 },
3529 [pbn_sbsxrsio] = {
3530 .flags = FL_BASE0,
3531 .num_ports = 8,
3532 .base_baud = 460800,
3533 .uart_offset = 256,
3534 .reg_shift = 4,
3535 },
3536 /*
3537 * PA Semi PWRficient PA6T-1682M on-chip UART
3538 */
3539 [pbn_pasemi_1682M] = {
3540 .flags = FL_BASE0,
3541 .num_ports = 1,
3542 .base_baud = 8333333,
3543 },
3544 /*
3545 * National Instruments 843x
3546 */
3547 [pbn_ni8430_16] = {
3548 .flags = FL_BASE0,
3549 .num_ports = 16,
3550 .base_baud = 3686400,
3551 .uart_offset = 0x10,
3552 .first_offset = 0x800,
3553 },
3554 [pbn_ni8430_8] = {
3555 .flags = FL_BASE0,
3556 .num_ports = 8,
3557 .base_baud = 3686400,
3558 .uart_offset = 0x10,
3559 .first_offset = 0x800,
3560 },
3561 [pbn_ni8430_4] = {
3562 .flags = FL_BASE0,
3563 .num_ports = 4,
3564 .base_baud = 3686400,
3565 .uart_offset = 0x10,
3566 .first_offset = 0x800,
3567 },
3568 [pbn_ni8430_2] = {
3569 .flags = FL_BASE0,
3570 .num_ports = 2,
3571 .base_baud = 3686400,
3572 .uart_offset = 0x10,
3573 .first_offset = 0x800,
3574 },
3575 /*
3576 * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com>
3577 */
3578 [pbn_ADDIDATA_PCIe_1_3906250] = {
3579 .flags = FL_BASE0,
3580 .num_ports = 1,
3581 .base_baud = 3906250,
3582 .uart_offset = 0x200,
3583 .first_offset = 0x1000,
3584 },
3585 [pbn_ADDIDATA_PCIe_2_3906250] = {
3586 .flags = FL_BASE0,
3587 .num_ports = 2,
3588 .base_baud = 3906250,
3589 .uart_offset = 0x200,
3590 .first_offset = 0x1000,
3591 },
3592 [pbn_ADDIDATA_PCIe_4_3906250] = {
3593 .flags = FL_BASE0,
3594 .num_ports = 4,
3595 .base_baud = 3906250,
3596 .uart_offset = 0x200,
3597 .first_offset = 0x1000,
3598 },
3599 [pbn_ADDIDATA_PCIe_8_3906250] = {
3600 .flags = FL_BASE0,
3601 .num_ports = 8,
3602 .base_baud = 3906250,
3603 .uart_offset = 0x200,
3604 .first_offset = 0x1000,
3605 },
3606 [pbn_ce4100_1_115200] = {
3607 .flags = FL_BASE_BARS,
3608 .num_ports = 2,
3609 .base_baud = 921600,
3610 .reg_shift = 2,
3611 },
3612 [pbn_omegapci] = {
3613 .flags = FL_BASE0,
3614 .num_ports = 8,
3615 .base_baud = 115200,
3616 .uart_offset = 0x200,
3617 },
3618 [pbn_NETMOS9900_2s_115200] = {
3619 .flags = FL_BASE0,
3620 .num_ports = 2,
3621 .base_baud = 115200,
3622 },
3623 [pbn_brcm_trumanage] = {
3624 .flags = FL_BASE0,
3625 .num_ports = 1,
3626 .reg_shift = 2,
3627 .base_baud = 115200,
3628 },
3629 [pbn_fintek_4] = {
3630 .num_ports = 4,
3631 .uart_offset = 8,
3632 .base_baud = 115200,
3633 .first_offset = 0x40,
3634 },
3635 [pbn_fintek_8] = {
3636 .num_ports = 8,
3637 .uart_offset = 8,
3638 .base_baud = 115200,
3639 .first_offset = 0x40,
3640 },
3641 [pbn_fintek_12] = {
3642 .num_ports = 12,
3643 .uart_offset = 8,
3644 .base_baud = 115200,
3645 .first_offset = 0x40,
3646 },
3647 [pbn_fintek_F81504A] = {
3648 .num_ports = 4,
3649 .uart_offset = 8,
3650 .base_baud = 115200,
3651 },
3652 [pbn_fintek_F81508A] = {
3653 .num_ports = 8,
3654 .uart_offset = 8,
3655 .base_baud = 115200,
3656 },
3657 [pbn_fintek_F81512A] = {
3658 .num_ports = 12,
3659 .uart_offset = 8,
3660 .base_baud = 115200,
3661 },
3662 [pbn_wch382_2] = {
3663 .flags = FL_BASE0,
3664 .num_ports = 2,
3665 .base_baud = 115200,
3666 .uart_offset = 8,
3667 .first_offset = 0xC0,
3668 },
3669 [pbn_wch384_4] = {
3670 .flags = FL_BASE0,
3671 .num_ports = 4,
3672 .base_baud = 115200,
3673 .uart_offset = 8,
3674 .first_offset = 0xC0,
3675 },
3676 [pbn_wch384_8] = {
3677 .flags = FL_BASE0,
3678 .num_ports = 8,
3679 .base_baud = 115200,
3680 .uart_offset = 8,
3681 .first_offset = 0x00,
3682 },
3683 /*
3684 * Pericom PI7C9X795[1248] Uno/Dual/Quad/Octal UART
3685 */
3686 [pbn_pericom_PI7C9X7951] = {
3687 .flags = FL_BASE0,
3688 .num_ports = 1,
3689 .base_baud = 921600,
3690 .uart_offset = 0x8,
3691 },
3692 [pbn_pericom_PI7C9X7952] = {
3693 .flags = FL_BASE0,
3694 .num_ports = 2,
3695 .base_baud = 921600,
3696 .uart_offset = 0x8,
3697 },
3698 [pbn_pericom_PI7C9X7954] = {
3699 .flags = FL_BASE0,
3700 .num_ports = 4,
3701 .base_baud = 921600,
3702 .uart_offset = 0x8,
3703 },
3704 [pbn_pericom_PI7C9X7958] = {
3705 .flags = FL_BASE0,
3706 .num_ports = 8,
3707 .base_baud = 921600,
3708 .uart_offset = 0x8,
3709 },
3710 [pbn_sunix_pci_1s] = {
3711 .num_ports = 1,
3712 .base_baud = 921600,
3713 .uart_offset = 0x8,
3714 },
3715 [pbn_sunix_pci_2s] = {
3716 .num_ports = 2,
3717 .base_baud = 921600,
3718 .uart_offset = 0x8,
3719 },
3720 [pbn_sunix_pci_4s] = {
3721 .num_ports = 4,
3722 .base_baud = 921600,
3723 .uart_offset = 0x8,
3724 },
3725 [pbn_sunix_pci_8s] = {
3726 .num_ports = 8,
3727 .base_baud = 921600,
3728 .uart_offset = 0x8,
3729 },
3730 [pbn_sunix_pci_16s] = {
3731 .num_ports = 16,
3732 .base_baud = 921600,
3733 .uart_offset = 0x8,
3734 },
3735 [pbn_titan_1_4000000] = {
3736 .flags = FL_BASE0,
3737 .num_ports = 1,
3738 .base_baud = 4000000,
3739 .uart_offset = 0x200,
3740 .first_offset = 0x1000,
3741 },
3742 [pbn_titan_2_4000000] = {
3743 .flags = FL_BASE0,
3744 .num_ports = 2,
3745 .base_baud = 4000000,
3746 .uart_offset = 0x200,
3747 .first_offset = 0x1000,
3748 },
3749 [pbn_titan_4_4000000] = {
3750 .flags = FL_BASE0,
3751 .num_ports = 4,
3752 .base_baud = 4000000,
3753 .uart_offset = 0x200,
3754 .first_offset = 0x1000,
3755 },
3756 [pbn_titan_8_4000000] = {
3757 .flags = FL_BASE0,
3758 .num_ports = 8,
3759 .base_baud = 4000000,
3760 .uart_offset = 0x200,
3761 .first_offset = 0x1000,
3762 },
3763 [pbn_moxa8250_2p] = {
3764 .flags = FL_BASE1,
3765 .num_ports = 2,
3766 .base_baud = 921600,
3767 .uart_offset = 0x200,
3768 },
3769 [pbn_moxa8250_4p] = {
3770 .flags = FL_BASE1,
3771 .num_ports = 4,
3772 .base_baud = 921600,
3773 .uart_offset = 0x200,
3774 },
3775 [pbn_moxa8250_8p] = {
3776 .flags = FL_BASE1,
3777 .num_ports = 8,
3778 .base_baud = 921600,
3779 .uart_offset = 0x200,
3780 },
3781 };
3782
3783 static const struct pci_device_id blacklist[] = {
3784 /* softmodems */
3785 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
3786 { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */
3787 { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */
3788
3789 /* multi-io cards handled by parport_serial */
3790 { PCI_DEVICE(0x4348, 0x7053), }, /* WCH CH353 2S1P */
3791 { PCI_DEVICE(0x4348, 0x5053), }, /* WCH CH353 1S1P */
3792 { PCI_DEVICE(0x1c00, 0x3250), }, /* WCH CH382 2S1P */
3793
3794 /* Intel platforms with MID UART */
3795 { PCI_VDEVICE(INTEL, 0x081b), },
3796 { PCI_VDEVICE(INTEL, 0x081c), },
3797 { PCI_VDEVICE(INTEL, 0x081d), },
3798 { PCI_VDEVICE(INTEL, 0x1191), },
3799 { PCI_VDEVICE(INTEL, 0x18d8), },
3800 { PCI_VDEVICE(INTEL, 0x19d8), },
3801
3802 /* Intel platforms with DesignWare UART */
3803 { PCI_VDEVICE(INTEL, 0x0936), },
3804 { PCI_VDEVICE(INTEL, 0x0f0a), },
3805 { PCI_VDEVICE(INTEL, 0x0f0c), },
3806 { PCI_VDEVICE(INTEL, 0x228a), },
3807 { PCI_VDEVICE(INTEL, 0x228c), },
3808 { PCI_VDEVICE(INTEL, 0x4b96), },
3809 { PCI_VDEVICE(INTEL, 0x4b97), },
3810 { PCI_VDEVICE(INTEL, 0x4b98), },
3811 { PCI_VDEVICE(INTEL, 0x4b99), },
3812 { PCI_VDEVICE(INTEL, 0x4b9a), },
3813 { PCI_VDEVICE(INTEL, 0x4b9b), },
3814 { PCI_VDEVICE(INTEL, 0x9ce3), },
3815 { PCI_VDEVICE(INTEL, 0x9ce4), },
3816
3817 /* Exar devices */
3818 { PCI_VDEVICE(EXAR, PCI_ANY_ID), },
3819 { PCI_VDEVICE(COMMTECH, PCI_ANY_ID), },
3820
3821 /* End of the black list */
3822 { }
3823 };
3824
serial_pci_is_class_communication(struct pci_dev * dev)3825 static int serial_pci_is_class_communication(struct pci_dev *dev)
3826 {
3827 /*
3828 * If it is not a communications device or the programming
3829 * interface is greater than 6, give up.
3830 */
3831 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
3832 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MULTISERIAL) &&
3833 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
3834 (dev->class & 0xff) > 6)
3835 return -ENODEV;
3836
3837 return 0;
3838 }
3839
3840 /*
3841 * Given a complete unknown PCI device, try to use some heuristics to
3842 * guess what the configuration might be, based on the pitiful PCI
3843 * serial specs. Returns 0 on success, -ENODEV on failure.
3844 */
3845 static int
serial_pci_guess_board(struct pci_dev * dev,struct pciserial_board * board)3846 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
3847 {
3848 int num_iomem, num_port, first_port = -1, i;
3849 int rc;
3850
3851 rc = serial_pci_is_class_communication(dev);
3852 if (rc)
3853 return rc;
3854
3855 /*
3856 * Should we try to make guesses for multiport serial devices later?
3857 */
3858 if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_MULTISERIAL)
3859 return -ENODEV;
3860
3861 num_iomem = num_port = 0;
3862 for (i = 0; i < PCI_STD_NUM_BARS; i++) {
3863 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
3864 num_port++;
3865 if (first_port == -1)
3866 first_port = i;
3867 }
3868 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
3869 num_iomem++;
3870 }
3871
3872 /*
3873 * If there is 1 or 0 iomem regions, and exactly one port,
3874 * use it. We guess the number of ports based on the IO
3875 * region size.
3876 */
3877 if (num_iomem <= 1 && num_port == 1) {
3878 board->flags = first_port;
3879 board->num_ports = pci_resource_len(dev, first_port) / 8;
3880 return 0;
3881 }
3882
3883 /*
3884 * Now guess if we've got a board which indexes by BARs.
3885 * Each IO BAR should be 8 bytes, and they should follow
3886 * consecutively.
3887 */
3888 first_port = -1;
3889 num_port = 0;
3890 for (i = 0; i < PCI_STD_NUM_BARS; i++) {
3891 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
3892 pci_resource_len(dev, i) == 8 &&
3893 (first_port == -1 || (first_port + num_port) == i)) {
3894 num_port++;
3895 if (first_port == -1)
3896 first_port = i;
3897 }
3898 }
3899
3900 if (num_port > 1) {
3901 board->flags = first_port | FL_BASE_BARS;
3902 board->num_ports = num_port;
3903 return 0;
3904 }
3905
3906 return -ENODEV;
3907 }
3908
3909 static inline int
serial_pci_matches(const struct pciserial_board * board,const struct pciserial_board * guessed)3910 serial_pci_matches(const struct pciserial_board *board,
3911 const struct pciserial_board *guessed)
3912 {
3913 return
3914 board->num_ports == guessed->num_ports &&
3915 board->base_baud == guessed->base_baud &&
3916 board->uart_offset == guessed->uart_offset &&
3917 board->reg_shift == guessed->reg_shift &&
3918 board->first_offset == guessed->first_offset;
3919 }
3920
3921 struct serial_private *
pciserial_init_ports(struct pci_dev * dev,const struct pciserial_board * board)3922 pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
3923 {
3924 struct uart_8250_port uart;
3925 struct serial_private *priv;
3926 struct pci_serial_quirk *quirk;
3927 int rc, nr_ports, i;
3928
3929 nr_ports = board->num_ports;
3930
3931 /*
3932 * Find an init and setup quirks.
3933 */
3934 quirk = find_quirk(dev);
3935
3936 /*
3937 * Run the new-style initialization function.
3938 * The initialization function returns:
3939 * <0 - error
3940 * 0 - use board->num_ports
3941 * >0 - number of ports
3942 */
3943 if (quirk->init) {
3944 rc = quirk->init(dev);
3945 if (rc < 0) {
3946 priv = ERR_PTR(rc);
3947 goto err_out;
3948 }
3949 if (rc)
3950 nr_ports = rc;
3951 }
3952
3953 priv = kzalloc(sizeof(struct serial_private) +
3954 sizeof(unsigned int) * nr_ports,
3955 GFP_KERNEL);
3956 if (!priv) {
3957 priv = ERR_PTR(-ENOMEM);
3958 goto err_deinit;
3959 }
3960
3961 priv->dev = dev;
3962 priv->quirk = quirk;
3963
3964 memset(&uart, 0, sizeof(uart));
3965 uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
3966 uart.port.uartclk = board->base_baud * 16;
3967
3968 if (board->flags & FL_NOIRQ) {
3969 uart.port.irq = 0;
3970 } else {
3971 if (pci_match_id(pci_use_msi, dev)) {
3972 pci_dbg(dev, "Using MSI(-X) interrupts\n");
3973 pci_set_master(dev);
3974 uart.port.flags &= ~UPF_SHARE_IRQ;
3975 rc = pci_alloc_irq_vectors(dev, 1, 1, PCI_IRQ_ALL_TYPES);
3976 } else {
3977 pci_dbg(dev, "Using legacy interrupts\n");
3978 rc = pci_alloc_irq_vectors(dev, 1, 1, PCI_IRQ_LEGACY);
3979 }
3980 if (rc < 0) {
3981 kfree(priv);
3982 priv = ERR_PTR(rc);
3983 goto err_deinit;
3984 }
3985
3986 uart.port.irq = pci_irq_vector(dev, 0);
3987 }
3988
3989 uart.port.dev = &dev->dev;
3990
3991 for (i = 0; i < nr_ports; i++) {
3992 if (quirk->setup(priv, board, &uart, i))
3993 break;
3994
3995 pci_dbg(dev, "Setup PCI port: port %lx, irq %d, type %d\n",
3996 uart.port.iobase, uart.port.irq, uart.port.iotype);
3997
3998 priv->line[i] = serial8250_register_8250_port(&uart);
3999 if (priv->line[i] < 0) {
4000 pci_err(dev,
4001 "Couldn't register serial port %lx, irq %d, type %d, error %d\n",
4002 uart.port.iobase, uart.port.irq,
4003 uart.port.iotype, priv->line[i]);
4004 break;
4005 }
4006 }
4007 priv->nr = i;
4008 priv->board = board;
4009 return priv;
4010
4011 err_deinit:
4012 if (quirk->exit)
4013 quirk->exit(dev);
4014 err_out:
4015 return priv;
4016 }
4017 EXPORT_SYMBOL_GPL(pciserial_init_ports);
4018
pciserial_detach_ports(struct serial_private * priv)4019 static void pciserial_detach_ports(struct serial_private *priv)
4020 {
4021 struct pci_serial_quirk *quirk;
4022 int i;
4023
4024 for (i = 0; i < priv->nr; i++)
4025 serial8250_unregister_port(priv->line[i]);
4026
4027 /*
4028 * Find the exit quirks.
4029 */
4030 quirk = find_quirk(priv->dev);
4031 if (quirk->exit)
4032 quirk->exit(priv->dev);
4033 }
4034
pciserial_remove_ports(struct serial_private * priv)4035 void pciserial_remove_ports(struct serial_private *priv)
4036 {
4037 pciserial_detach_ports(priv);
4038 kfree(priv);
4039 }
4040 EXPORT_SYMBOL_GPL(pciserial_remove_ports);
4041
pciserial_suspend_ports(struct serial_private * priv)4042 void pciserial_suspend_ports(struct serial_private *priv)
4043 {
4044 int i;
4045
4046 for (i = 0; i < priv->nr; i++)
4047 if (priv->line[i] >= 0)
4048 serial8250_suspend_port(priv->line[i]);
4049
4050 /*
4051 * Ensure that every init quirk is properly torn down
4052 */
4053 if (priv->quirk->exit)
4054 priv->quirk->exit(priv->dev);
4055 }
4056 EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
4057
pciserial_resume_ports(struct serial_private * priv)4058 void pciserial_resume_ports(struct serial_private *priv)
4059 {
4060 int i;
4061
4062 /*
4063 * Ensure that the board is correctly configured.
4064 */
4065 if (priv->quirk->init)
4066 priv->quirk->init(priv->dev);
4067
4068 for (i = 0; i < priv->nr; i++)
4069 if (priv->line[i] >= 0)
4070 serial8250_resume_port(priv->line[i]);
4071 }
4072 EXPORT_SYMBOL_GPL(pciserial_resume_ports);
4073
4074 /*
4075 * Probe one serial board. Unfortunately, there is no rhyme nor reason
4076 * to the arrangement of serial ports on a PCI card.
4077 */
4078 static int
pciserial_init_one(struct pci_dev * dev,const struct pci_device_id * ent)4079 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
4080 {
4081 struct pci_serial_quirk *quirk;
4082 struct serial_private *priv;
4083 const struct pciserial_board *board;
4084 const struct pci_device_id *exclude;
4085 struct pciserial_board tmp;
4086 int rc;
4087
4088 quirk = find_quirk(dev);
4089 if (quirk->probe) {
4090 rc = quirk->probe(dev);
4091 if (rc)
4092 return rc;
4093 }
4094
4095 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
4096 pci_err(dev, "invalid driver_data: %ld\n", ent->driver_data);
4097 return -EINVAL;
4098 }
4099
4100 board = &pci_boards[ent->driver_data];
4101
4102 exclude = pci_match_id(blacklist, dev);
4103 if (exclude)
4104 return -ENODEV;
4105
4106 rc = pcim_enable_device(dev);
4107 pci_save_state(dev);
4108 if (rc)
4109 return rc;
4110
4111 if (ent->driver_data == pbn_default) {
4112 /*
4113 * Use a copy of the pci_board entry for this;
4114 * avoid changing entries in the table.
4115 */
4116 memcpy(&tmp, board, sizeof(struct pciserial_board));
4117 board = &tmp;
4118
4119 /*
4120 * We matched one of our class entries. Try to
4121 * determine the parameters of this board.
4122 */
4123 rc = serial_pci_guess_board(dev, &tmp);
4124 if (rc)
4125 return rc;
4126 } else {
4127 /*
4128 * We matched an explicit entry. If we are able to
4129 * detect this boards settings with our heuristic,
4130 * then we no longer need this entry.
4131 */
4132 memcpy(&tmp, &pci_boards[pbn_default],
4133 sizeof(struct pciserial_board));
4134 rc = serial_pci_guess_board(dev, &tmp);
4135 if (rc == 0 && serial_pci_matches(board, &tmp))
4136 moan_device("Redundant entry in serial pci_table.",
4137 dev);
4138 }
4139
4140 priv = pciserial_init_ports(dev, board);
4141 if (IS_ERR(priv))
4142 return PTR_ERR(priv);
4143
4144 pci_set_drvdata(dev, priv);
4145 return 0;
4146 }
4147
pciserial_remove_one(struct pci_dev * dev)4148 static void pciserial_remove_one(struct pci_dev *dev)
4149 {
4150 struct serial_private *priv = pci_get_drvdata(dev);
4151
4152 pciserial_remove_ports(priv);
4153 }
4154
4155 #ifdef CONFIG_PM_SLEEP
pciserial_suspend_one(struct device * dev)4156 static int pciserial_suspend_one(struct device *dev)
4157 {
4158 struct serial_private *priv = dev_get_drvdata(dev);
4159
4160 if (priv)
4161 pciserial_suspend_ports(priv);
4162
4163 return 0;
4164 }
4165
pciserial_resume_one(struct device * dev)4166 static int pciserial_resume_one(struct device *dev)
4167 {
4168 struct pci_dev *pdev = to_pci_dev(dev);
4169 struct serial_private *priv = pci_get_drvdata(pdev);
4170 int err;
4171
4172 if (priv) {
4173 /*
4174 * The device may have been disabled. Re-enable it.
4175 */
4176 err = pci_enable_device(pdev);
4177 /* FIXME: We cannot simply error out here */
4178 if (err)
4179 pci_err(pdev, "Unable to re-enable ports, trying to continue.\n");
4180 pciserial_resume_ports(priv);
4181 }
4182 return 0;
4183 }
4184 #endif
4185
4186 static SIMPLE_DEV_PM_OPS(pciserial_pm_ops, pciserial_suspend_one,
4187 pciserial_resume_one);
4188
4189 static const struct pci_device_id serial_pci_tbl[] = {
4190 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI1600,
4191 PCI_DEVICE_ID_ADVANTECH_PCI1600_1611, PCI_ANY_ID, 0, 0,
4192 pbn_b0_4_921600 },
4193 /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
4194 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
4195 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
4196 pbn_b2_8_921600 },
4197 /* Advantech also use 0x3618 and 0xf618 */
4198 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3618,
4199 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
4200 pbn_b0_4_921600 },
4201 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCIf618,
4202 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
4203 pbn_b0_4_921600 },
4204 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4205 PCI_SUBVENDOR_ID_CONNECT_TECH,
4206 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
4207 pbn_b1_8_1382400 },
4208 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4209 PCI_SUBVENDOR_ID_CONNECT_TECH,
4210 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
4211 pbn_b1_4_1382400 },
4212 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4213 PCI_SUBVENDOR_ID_CONNECT_TECH,
4214 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
4215 pbn_b1_2_1382400 },
4216 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4217 PCI_SUBVENDOR_ID_CONNECT_TECH,
4218 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
4219 pbn_b1_8_1382400 },
4220 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4221 PCI_SUBVENDOR_ID_CONNECT_TECH,
4222 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
4223 pbn_b1_4_1382400 },
4224 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4225 PCI_SUBVENDOR_ID_CONNECT_TECH,
4226 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
4227 pbn_b1_2_1382400 },
4228 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4229 PCI_SUBVENDOR_ID_CONNECT_TECH,
4230 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
4231 pbn_b1_8_921600 },
4232 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4233 PCI_SUBVENDOR_ID_CONNECT_TECH,
4234 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
4235 pbn_b1_8_921600 },
4236 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4237 PCI_SUBVENDOR_ID_CONNECT_TECH,
4238 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
4239 pbn_b1_4_921600 },
4240 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4241 PCI_SUBVENDOR_ID_CONNECT_TECH,
4242 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
4243 pbn_b1_4_921600 },
4244 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4245 PCI_SUBVENDOR_ID_CONNECT_TECH,
4246 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
4247 pbn_b1_2_921600 },
4248 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4249 PCI_SUBVENDOR_ID_CONNECT_TECH,
4250 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
4251 pbn_b1_8_921600 },
4252 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4253 PCI_SUBVENDOR_ID_CONNECT_TECH,
4254 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
4255 pbn_b1_8_921600 },
4256 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4257 PCI_SUBVENDOR_ID_CONNECT_TECH,
4258 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
4259 pbn_b1_4_921600 },
4260 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4261 PCI_SUBVENDOR_ID_CONNECT_TECH,
4262 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
4263 pbn_b1_2_1250000 },
4264 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4265 PCI_SUBVENDOR_ID_CONNECT_TECH,
4266 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
4267 pbn_b0_2_1843200 },
4268 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4269 PCI_SUBVENDOR_ID_CONNECT_TECH,
4270 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
4271 pbn_b0_4_1843200 },
4272 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4273 PCI_VENDOR_ID_AFAVLAB,
4274 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
4275 pbn_b0_4_1152000 },
4276 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
4277 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4278 pbn_b2_bt_1_115200 },
4279 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
4280 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4281 pbn_b2_bt_2_115200 },
4282 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
4283 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4284 pbn_b2_bt_4_115200 },
4285 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
4286 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4287 pbn_b2_bt_2_115200 },
4288 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
4289 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4290 pbn_b2_bt_4_115200 },
4291 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
4292 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4293 pbn_b2_8_115200 },
4294 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
4295 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4296 pbn_b2_8_460800 },
4297 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
4298 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4299 pbn_b2_8_115200 },
4300
4301 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
4302 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4303 pbn_b2_bt_2_115200 },
4304 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
4305 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4306 pbn_b2_bt_2_921600 },
4307 /*
4308 * VScom SPCOM800, from sl@s.pl
4309 */
4310 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
4311 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4312 pbn_b2_8_921600 },
4313 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
4314 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4315 pbn_b2_4_921600 },
4316 /* Unknown card - subdevice 0x1584 */
4317 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4318 PCI_VENDOR_ID_PLX,
4319 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
4320 pbn_b2_4_115200 },
4321 /* Unknown card - subdevice 0x1588 */
4322 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4323 PCI_VENDOR_ID_PLX,
4324 PCI_SUBDEVICE_ID_UNKNOWN_0x1588, 0, 0,
4325 pbn_b2_8_115200 },
4326 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4327 PCI_SUBVENDOR_ID_KEYSPAN,
4328 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
4329 pbn_panacom },
4330 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
4331 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4332 pbn_panacom4 },
4333 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
4334 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4335 pbn_panacom2 },
4336 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4337 PCI_VENDOR_ID_ESDGMBH,
4338 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
4339 pbn_b2_4_115200 },
4340 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4341 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4342 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
4343 pbn_b2_4_460800 },
4344 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4345 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4346 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
4347 pbn_b2_8_460800 },
4348 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4349 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4350 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
4351 pbn_b2_16_460800 },
4352 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4353 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4354 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
4355 pbn_b2_16_460800 },
4356 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4357 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
4358 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
4359 pbn_b2_4_460800 },
4360 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4361 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
4362 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
4363 pbn_b2_8_460800 },
4364 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4365 PCI_SUBVENDOR_ID_EXSYS,
4366 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
4367 pbn_b2_4_115200 },
4368 /*
4369 * Megawolf Romulus PCI Serial Card, from Mike Hudson
4370 * (Exoray@isys.ca)
4371 */
4372 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
4373 0x10b5, 0x106a, 0, 0,
4374 pbn_plx_romulus },
4375 /*
4376 * Quatech cards. These actually have configurable clocks but for
4377 * now we just use the default.
4378 *
4379 * 100 series are RS232, 200 series RS422,
4380 */
4381 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
4382 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4383 pbn_b1_4_115200 },
4384 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
4385 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4386 pbn_b1_2_115200 },
4387 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100E,
4388 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4389 pbn_b2_2_115200 },
4390 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200,
4391 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4392 pbn_b1_2_115200 },
4393 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200E,
4394 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4395 pbn_b2_2_115200 },
4396 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC200,
4397 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4398 pbn_b1_4_115200 },
4399 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
4400 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4401 pbn_b1_8_115200 },
4402 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
4403 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4404 pbn_b1_8_115200 },
4405 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP100,
4406 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4407 pbn_b1_4_115200 },
4408 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP100,
4409 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4410 pbn_b1_2_115200 },
4411 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP200,
4412 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4413 pbn_b1_4_115200 },
4414 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP200,
4415 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4416 pbn_b1_2_115200 },
4417 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP100,
4418 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4419 pbn_b2_4_115200 },
4420 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP100,
4421 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4422 pbn_b2_2_115200 },
4423 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP100,
4424 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4425 pbn_b2_1_115200 },
4426 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP200,
4427 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4428 pbn_b2_4_115200 },
4429 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP200,
4430 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4431 pbn_b2_2_115200 },
4432 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP200,
4433 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4434 pbn_b2_1_115200 },
4435 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESCLP100,
4436 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4437 pbn_b0_8_115200 },
4438
4439 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
4440 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
4441 0, 0,
4442 pbn_b0_4_921600 },
4443 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4444 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
4445 0, 0,
4446 pbn_b0_4_1152000 },
4447 { PCI_VENDOR_ID_OXSEMI, 0x9505,
4448 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4449 pbn_b0_bt_2_921600 },
4450
4451 /*
4452 * The below card is a little controversial since it is the
4453 * subject of a PCI vendor/device ID clash. (See
4454 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
4455 * For now just used the hex ID 0x950a.
4456 */
4457 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4458 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_00,
4459 0, 0, pbn_b0_2_115200 },
4460 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4461 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_30,
4462 0, 0, pbn_b0_2_115200 },
4463 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4464 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4465 pbn_b0_2_1130000 },
4466 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
4467 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
4468 pbn_b0_1_921600 },
4469 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4470 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4471 pbn_b0_4_115200 },
4472 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
4473 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4474 pbn_b0_bt_2_921600 },
4475 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958,
4476 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4477 pbn_b2_8_1152000 },
4478
4479 /*
4480 * Oxford Semiconductor Inc. Tornado PCI express device range.
4481 */
4482 { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */
4483 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4484 pbn_b0_1_3906250 },
4485 { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */
4486 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4487 pbn_b0_1_3906250 },
4488 { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */
4489 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4490 pbn_oxsemi_1_3906250 },
4491 { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */
4492 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4493 pbn_oxsemi_1_3906250 },
4494 { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */
4495 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4496 pbn_b0_1_3906250 },
4497 { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */
4498 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4499 pbn_b0_1_3906250 },
4500 { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */
4501 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4502 pbn_oxsemi_1_3906250 },
4503 { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */
4504 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4505 pbn_oxsemi_1_3906250 },
4506 { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */
4507 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4508 pbn_b0_1_3906250 },
4509 { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */
4510 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4511 pbn_b0_1_3906250 },
4512 { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */
4513 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4514 pbn_b0_1_3906250 },
4515 { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */
4516 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4517 pbn_b0_1_3906250 },
4518 { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */
4519 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4520 pbn_oxsemi_2_3906250 },
4521 { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */
4522 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4523 pbn_oxsemi_2_3906250 },
4524 { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */
4525 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4526 pbn_oxsemi_4_3906250 },
4527 { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */
4528 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4529 pbn_oxsemi_4_3906250 },
4530 { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */
4531 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4532 pbn_oxsemi_8_3906250 },
4533 { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */
4534 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4535 pbn_oxsemi_8_3906250 },
4536 { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */
4537 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4538 pbn_oxsemi_1_3906250 },
4539 { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */
4540 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4541 pbn_oxsemi_1_3906250 },
4542 { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */
4543 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4544 pbn_oxsemi_1_3906250 },
4545 { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */
4546 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4547 pbn_oxsemi_1_3906250 },
4548 { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */
4549 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4550 pbn_oxsemi_1_3906250 },
4551 { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */
4552 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4553 pbn_oxsemi_1_3906250 },
4554 { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */
4555 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4556 pbn_oxsemi_1_3906250 },
4557 { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */
4558 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4559 pbn_oxsemi_1_3906250 },
4560 { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */
4561 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4562 pbn_oxsemi_1_3906250 },
4563 { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */
4564 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4565 pbn_oxsemi_1_3906250 },
4566 { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */
4567 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4568 pbn_oxsemi_1_3906250 },
4569 { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */
4570 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4571 pbn_oxsemi_1_3906250 },
4572 { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */
4573 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4574 pbn_oxsemi_1_3906250 },
4575 { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */
4576 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4577 pbn_oxsemi_1_3906250 },
4578 { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */
4579 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4580 pbn_oxsemi_1_3906250 },
4581 { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */
4582 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4583 pbn_oxsemi_1_3906250 },
4584 { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */
4585 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4586 pbn_oxsemi_1_3906250 },
4587 { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */
4588 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4589 pbn_oxsemi_1_3906250 },
4590 { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */
4591 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4592 pbn_oxsemi_1_3906250 },
4593 { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */
4594 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4595 pbn_oxsemi_1_3906250 },
4596 { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */
4597 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4598 pbn_oxsemi_1_3906250 },
4599 { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */
4600 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4601 pbn_oxsemi_1_3906250 },
4602 { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */
4603 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4604 pbn_oxsemi_1_3906250 },
4605 { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */
4606 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4607 pbn_oxsemi_1_3906250 },
4608 { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */
4609 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4610 pbn_oxsemi_1_3906250 },
4611 { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */
4612 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4613 pbn_oxsemi_1_3906250 },
4614 /*
4615 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
4616 */
4617 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
4618 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
4619 pbn_oxsemi_1_3906250 },
4620 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
4621 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
4622 pbn_oxsemi_2_3906250 },
4623 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
4624 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
4625 pbn_oxsemi_4_3906250 },
4626 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
4627 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
4628 pbn_oxsemi_8_3906250 },
4629
4630 /*
4631 * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado
4632 */
4633 { PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM,
4634 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0,
4635 pbn_oxsemi_2_3906250 },
4636 /*
4637 * EndRun Technologies. PCI express device range.
4638 * EndRun PTP/1588 has 2 Native UARTs utilizing OxSemi 952.
4639 */
4640 { PCI_VENDOR_ID_ENDRUN, PCI_DEVICE_ID_ENDRUN_1588,
4641 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4642 pbn_oxsemi_2_3906250 },
4643
4644 /*
4645 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
4646 * from skokodyn@yahoo.com
4647 */
4648 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4649 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
4650 pbn_sbsxrsio },
4651 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4652 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
4653 pbn_sbsxrsio },
4654 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4655 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
4656 pbn_sbsxrsio },
4657 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4658 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
4659 pbn_sbsxrsio },
4660
4661 /*
4662 * Digitan DS560-558, from jimd@esoft.com
4663 */
4664 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
4665 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4666 pbn_b1_1_115200 },
4667
4668 /*
4669 * Titan Electronic cards
4670 * The 400L and 800L have a custom setup quirk.
4671 */
4672 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
4673 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4674 pbn_b0_1_921600 },
4675 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
4676 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4677 pbn_b0_2_921600 },
4678 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
4679 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4680 pbn_b0_4_921600 },
4681 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
4682 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4683 pbn_b0_4_921600 },
4684 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
4685 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4686 pbn_b1_1_921600 },
4687 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
4688 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4689 pbn_b1_bt_2_921600 },
4690 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
4691 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4692 pbn_b0_bt_4_921600 },
4693 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
4694 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4695 pbn_b0_bt_8_921600 },
4696 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I,
4697 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4698 pbn_b4_bt_2_921600 },
4699 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I,
4700 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4701 pbn_b4_bt_4_921600 },
4702 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I,
4703 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4704 pbn_b4_bt_8_921600 },
4705 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH,
4706 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4707 pbn_b0_4_921600 },
4708 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH,
4709 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4710 pbn_b0_4_921600 },
4711 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB,
4712 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4713 pbn_b0_4_921600 },
4714 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E,
4715 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4716 pbn_titan_1_4000000 },
4717 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E,
4718 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4719 pbn_titan_2_4000000 },
4720 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E,
4721 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4722 pbn_titan_4_4000000 },
4723 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E,
4724 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4725 pbn_titan_8_4000000 },
4726 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI,
4727 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4728 pbn_titan_2_4000000 },
4729 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI,
4730 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4731 pbn_titan_2_4000000 },
4732 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200V3,
4733 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4734 pbn_b0_bt_2_921600 },
4735 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3,
4736 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4737 pbn_b0_4_921600 },
4738 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3,
4739 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4740 pbn_b0_4_921600 },
4741 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3,
4742 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4743 pbn_b0_4_921600 },
4744 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B,
4745 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4746 pbn_b0_4_921600 },
4747
4748 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
4749 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4750 pbn_b2_1_460800 },
4751 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
4752 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4753 pbn_b2_1_460800 },
4754 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
4755 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4756 pbn_b2_1_460800 },
4757 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
4758 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4759 pbn_b2_bt_2_921600 },
4760 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
4761 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4762 pbn_b2_bt_2_921600 },
4763 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
4764 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4765 pbn_b2_bt_2_921600 },
4766 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
4767 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4768 pbn_b2_bt_4_921600 },
4769 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
4770 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4771 pbn_b2_bt_4_921600 },
4772 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
4773 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4774 pbn_b2_bt_4_921600 },
4775 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
4776 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4777 pbn_b0_1_921600 },
4778 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
4779 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4780 pbn_b0_1_921600 },
4781 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
4782 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4783 pbn_b0_1_921600 },
4784 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
4785 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4786 pbn_b0_bt_2_921600 },
4787 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
4788 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4789 pbn_b0_bt_2_921600 },
4790 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
4791 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4792 pbn_b0_bt_2_921600 },
4793 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
4794 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4795 pbn_b0_bt_4_921600 },
4796 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
4797 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4798 pbn_b0_bt_4_921600 },
4799 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
4800 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4801 pbn_b0_bt_4_921600 },
4802 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
4803 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4804 pbn_b0_bt_8_921600 },
4805 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
4806 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4807 pbn_b0_bt_8_921600 },
4808 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
4809 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4810 pbn_b0_bt_8_921600 },
4811
4812 /*
4813 * Computone devices submitted by Doug McNash dmcnash@computone.com
4814 */
4815 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4816 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
4817 0, 0, pbn_computone_4 },
4818 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4819 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
4820 0, 0, pbn_computone_8 },
4821 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4822 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
4823 0, 0, pbn_computone_6 },
4824
4825 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
4826 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4827 pbn_oxsemi },
4828 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
4829 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
4830 pbn_b0_bt_1_921600 },
4831
4832 /*
4833 * Sunix PCI serial boards
4834 */
4835 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4836 PCI_VENDOR_ID_SUNIX, 0x0001, 0, 0,
4837 pbn_sunix_pci_1s },
4838 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4839 PCI_VENDOR_ID_SUNIX, 0x0002, 0, 0,
4840 pbn_sunix_pci_2s },
4841 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4842 PCI_VENDOR_ID_SUNIX, 0x0004, 0, 0,
4843 pbn_sunix_pci_4s },
4844 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4845 PCI_VENDOR_ID_SUNIX, 0x0084, 0, 0,
4846 pbn_sunix_pci_4s },
4847 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4848 PCI_VENDOR_ID_SUNIX, 0x0008, 0, 0,
4849 pbn_sunix_pci_8s },
4850 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4851 PCI_VENDOR_ID_SUNIX, 0x0088, 0, 0,
4852 pbn_sunix_pci_8s },
4853 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4854 PCI_VENDOR_ID_SUNIX, 0x0010, 0, 0,
4855 pbn_sunix_pci_16s },
4856
4857 /*
4858 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
4859 */
4860 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
4861 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4862 pbn_b0_bt_8_115200 },
4863 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
4864 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4865 pbn_b0_bt_8_115200 },
4866
4867 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
4868 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4869 pbn_b0_bt_2_115200 },
4870 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
4871 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4872 pbn_b0_bt_2_115200 },
4873 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
4874 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4875 pbn_b0_bt_2_115200 },
4876 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A,
4877 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4878 pbn_b0_bt_2_115200 },
4879 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B,
4880 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4881 pbn_b0_bt_2_115200 },
4882 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
4883 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4884 pbn_b0_bt_4_460800 },
4885 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
4886 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4887 pbn_b0_bt_4_460800 },
4888 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
4889 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4890 pbn_b0_bt_2_460800 },
4891 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
4892 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4893 pbn_b0_bt_2_460800 },
4894 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
4895 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4896 pbn_b0_bt_2_460800 },
4897 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
4898 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4899 pbn_b0_bt_1_115200 },
4900 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
4901 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4902 pbn_b0_bt_1_460800 },
4903
4904 /*
4905 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
4906 * Cards are identified by their subsystem vendor IDs, which
4907 * (in hex) match the model number.
4908 *
4909 * Note that JC140x are RS422/485 cards which require ox950
4910 * ACR = 0x10, and as such are not currently fully supported.
4911 */
4912 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4913 0x1204, 0x0004, 0, 0,
4914 pbn_b0_4_921600 },
4915 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4916 0x1208, 0x0004, 0, 0,
4917 pbn_b0_4_921600 },
4918 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4919 0x1402, 0x0002, 0, 0,
4920 pbn_b0_2_921600 }, */
4921 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4922 0x1404, 0x0004, 0, 0,
4923 pbn_b0_4_921600 }, */
4924 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
4925 0x1208, 0x0004, 0, 0,
4926 pbn_b0_4_921600 },
4927
4928 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
4929 0x1204, 0x0004, 0, 0,
4930 pbn_b0_4_921600 },
4931 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
4932 0x1208, 0x0004, 0, 0,
4933 pbn_b0_4_921600 },
4934 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3,
4935 0x1208, 0x0004, 0, 0,
4936 pbn_b0_4_921600 },
4937 /*
4938 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
4939 */
4940 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
4941 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4942 pbn_b1_1_1382400 },
4943
4944 /*
4945 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
4946 */
4947 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
4948 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4949 pbn_b1_1_1382400 },
4950
4951 /*
4952 * RAStel 2 port modem, gerg@moreton.com.au
4953 */
4954 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
4955 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4956 pbn_b2_bt_2_115200 },
4957
4958 /*
4959 * EKF addition for i960 Boards form EKF with serial port
4960 */
4961 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
4962 0xE4BF, PCI_ANY_ID, 0, 0,
4963 pbn_intel_i960 },
4964
4965 /*
4966 * Xircom Cardbus/Ethernet combos
4967 */
4968 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
4969 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4970 pbn_b0_1_115200 },
4971 /*
4972 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
4973 */
4974 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
4975 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4976 pbn_b0_1_115200 },
4977
4978 /*
4979 * Untested PCI modems, sent in from various folks...
4980 */
4981
4982 /*
4983 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
4984 */
4985 { PCI_VENDOR_ID_ROCKWELL, 0x1004,
4986 0x1048, 0x1500, 0, 0,
4987 pbn_b1_1_115200 },
4988
4989 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
4990 0xFF00, 0, 0, 0,
4991 pbn_sgi_ioc3 },
4992
4993 /*
4994 * HP Diva card
4995 */
4996 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
4997 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
4998 pbn_b1_1_115200 },
4999 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
5000 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5001 pbn_b0_5_115200 },
5002 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
5003 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5004 pbn_b2_1_115200 },
5005 /* HPE PCI serial device */
5006 { PCI_VENDOR_ID_HP_3PAR, PCI_DEVICE_ID_HPE_PCI_SERIAL,
5007 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5008 pbn_b1_1_115200 },
5009
5010 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
5011 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5012 pbn_b3_2_115200 },
5013 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
5014 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5015 pbn_b3_4_115200 },
5016 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
5017 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5018 pbn_b3_8_115200 },
5019 /*
5020 * Pericom PI7C9X795[1248] Uno/Dual/Quad/Octal UART
5021 */
5022 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7951,
5023 PCI_ANY_ID, PCI_ANY_ID,
5024 0,
5025 0, pbn_pericom_PI7C9X7951 },
5026 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7952,
5027 PCI_ANY_ID, PCI_ANY_ID,
5028 0,
5029 0, pbn_pericom_PI7C9X7952 },
5030 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7954,
5031 PCI_ANY_ID, PCI_ANY_ID,
5032 0,
5033 0, pbn_pericom_PI7C9X7954 },
5034 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7958,
5035 PCI_ANY_ID, PCI_ANY_ID,
5036 0,
5037 0, pbn_pericom_PI7C9X7958 },
5038 /*
5039 * ACCES I/O Products quad
5040 */
5041 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SDB,
5042 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5043 pbn_pericom_PI7C9X7952 },
5044 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2S,
5045 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5046 pbn_pericom_PI7C9X7952 },
5047 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SDB,
5048 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5049 pbn_pericom_PI7C9X7954 },
5050 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4S,
5051 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5052 pbn_pericom_PI7C9X7954 },
5053 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_2DB,
5054 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5055 pbn_pericom_PI7C9X7952 },
5056 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_2,
5057 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5058 pbn_pericom_PI7C9X7952 },
5059 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4DB,
5060 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5061 pbn_pericom_PI7C9X7954 },
5062 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_4,
5063 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5064 pbn_pericom_PI7C9X7954 },
5065 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SMDB,
5066 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5067 pbn_pericom_PI7C9X7952 },
5068 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2SM,
5069 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5070 pbn_pericom_PI7C9X7952 },
5071 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SMDB,
5072 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5073 pbn_pericom_PI7C9X7954 },
5074 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4SM,
5075 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5076 pbn_pericom_PI7C9X7954 },
5077 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_1,
5078 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5079 pbn_pericom_PI7C9X7951 },
5080 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_2,
5081 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5082 pbn_pericom_PI7C9X7952 },
5083 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_2,
5084 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5085 pbn_pericom_PI7C9X7952 },
5086 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_4,
5087 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5088 pbn_pericom_PI7C9X7954 },
5089 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_4,
5090 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5091 pbn_pericom_PI7C9X7954 },
5092 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2S,
5093 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5094 pbn_pericom_PI7C9X7952 },
5095 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4S,
5096 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5097 pbn_pericom_PI7C9X7954 },
5098 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_2,
5099 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5100 pbn_pericom_PI7C9X7952 },
5101 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_2,
5102 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5103 pbn_pericom_PI7C9X7952 },
5104 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_4,
5105 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5106 pbn_pericom_PI7C9X7954 },
5107 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_4,
5108 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5109 pbn_pericom_PI7C9X7954 },
5110 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2SM,
5111 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5112 pbn_pericom_PI7C9X7952 },
5113 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM422_4,
5114 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5115 pbn_pericom_PI7C9X7954 },
5116 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM485_4,
5117 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5118 pbn_pericom_PI7C9X7954 },
5119 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM422_8,
5120 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5121 pbn_pericom_PI7C9X7958 },
5122 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM485_8,
5123 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5124 pbn_pericom_PI7C9X7958 },
5125 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4,
5126 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5127 pbn_pericom_PI7C9X7954 },
5128 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_8,
5129 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5130 pbn_pericom_PI7C9X7958 },
5131 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SM,
5132 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5133 pbn_pericom_PI7C9X7954 },
5134 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_8SM,
5135 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5136 pbn_pericom_PI7C9X7958 },
5137 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4SM,
5138 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5139 pbn_pericom_PI7C9X7954 },
5140 /*
5141 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
5142 */
5143 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
5144 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5145 pbn_b0_1_115200 },
5146 /*
5147 * ITE
5148 */
5149 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
5150 PCI_ANY_ID, PCI_ANY_ID,
5151 0, 0,
5152 pbn_b1_bt_1_115200 },
5153
5154 /*
5155 * IntaShield IS-200
5156 */
5157 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
5158 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */
5159 pbn_b2_2_115200 },
5160 /*
5161 * IntaShield IS-400
5162 */
5163 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
5164 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */
5165 pbn_b2_4_115200 },
5166 /* Brainboxes Devices */
5167 /*
5168 * Brainboxes UC-101
5169 */
5170 { PCI_VENDOR_ID_INTASHIELD, 0x0BA1,
5171 PCI_ANY_ID, PCI_ANY_ID,
5172 0, 0,
5173 pbn_b2_2_115200 },
5174 /*
5175 * Brainboxes UC-235/246
5176 */
5177 { PCI_VENDOR_ID_INTASHIELD, 0x0AA1,
5178 PCI_ANY_ID, PCI_ANY_ID,
5179 0, 0,
5180 pbn_b2_1_115200 },
5181 /*
5182 * Brainboxes UC-257
5183 */
5184 { PCI_VENDOR_ID_INTASHIELD, 0x0861,
5185 PCI_ANY_ID, PCI_ANY_ID,
5186 0, 0,
5187 pbn_b2_2_115200 },
5188 /*
5189 * Brainboxes UC-260/271/701/756
5190 */
5191 { PCI_VENDOR_ID_INTASHIELD, 0x0D21,
5192 PCI_ANY_ID, PCI_ANY_ID,
5193 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
5194 pbn_b2_4_115200 },
5195 { PCI_VENDOR_ID_INTASHIELD, 0x0E34,
5196 PCI_ANY_ID, PCI_ANY_ID,
5197 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
5198 pbn_b2_4_115200 },
5199 /*
5200 * Brainboxes UC-268
5201 */
5202 { PCI_VENDOR_ID_INTASHIELD, 0x0841,
5203 PCI_ANY_ID, PCI_ANY_ID,
5204 0, 0,
5205 pbn_b2_4_115200 },
5206 /*
5207 * Brainboxes UC-275/279
5208 */
5209 { PCI_VENDOR_ID_INTASHIELD, 0x0881,
5210 PCI_ANY_ID, PCI_ANY_ID,
5211 0, 0,
5212 pbn_b2_8_115200 },
5213 /*
5214 * Brainboxes UC-302
5215 */
5216 { PCI_VENDOR_ID_INTASHIELD, 0x08E1,
5217 PCI_ANY_ID, PCI_ANY_ID,
5218 0, 0,
5219 pbn_b2_2_115200 },
5220 /*
5221 * Brainboxes UC-310
5222 */
5223 { PCI_VENDOR_ID_INTASHIELD, 0x08C1,
5224 PCI_ANY_ID, PCI_ANY_ID,
5225 0, 0,
5226 pbn_b2_2_115200 },
5227 /*
5228 * Brainboxes UC-313
5229 */
5230 { PCI_VENDOR_ID_INTASHIELD, 0x08A3,
5231 PCI_ANY_ID, PCI_ANY_ID,
5232 0, 0,
5233 pbn_b2_2_115200 },
5234 /*
5235 * Brainboxes UC-320/324
5236 */
5237 { PCI_VENDOR_ID_INTASHIELD, 0x0A61,
5238 PCI_ANY_ID, PCI_ANY_ID,
5239 0, 0,
5240 pbn_b2_1_115200 },
5241 /*
5242 * Brainboxes UC-346
5243 */
5244 { PCI_VENDOR_ID_INTASHIELD, 0x0B02,
5245 PCI_ANY_ID, PCI_ANY_ID,
5246 0, 0,
5247 pbn_b2_4_115200 },
5248 /*
5249 * Brainboxes UC-357
5250 */
5251 { PCI_VENDOR_ID_INTASHIELD, 0x0A81,
5252 PCI_ANY_ID, PCI_ANY_ID,
5253 0, 0,
5254 pbn_b2_2_115200 },
5255 { PCI_VENDOR_ID_INTASHIELD, 0x0A83,
5256 PCI_ANY_ID, PCI_ANY_ID,
5257 0, 0,
5258 pbn_b2_2_115200 },
5259 /*
5260 * Brainboxes UC-368
5261 */
5262 { PCI_VENDOR_ID_INTASHIELD, 0x0C41,
5263 PCI_ANY_ID, PCI_ANY_ID,
5264 0, 0,
5265 pbn_b2_4_115200 },
5266 /*
5267 * Brainboxes UC-420/431
5268 */
5269 { PCI_VENDOR_ID_INTASHIELD, 0x0921,
5270 PCI_ANY_ID, PCI_ANY_ID,
5271 0, 0,
5272 pbn_b2_4_115200 },
5273 /*
5274 * Perle PCI-RAS cards
5275 */
5276 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
5277 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
5278 0, 0, pbn_b2_4_921600 },
5279 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
5280 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
5281 0, 0, pbn_b2_8_921600 },
5282
5283 /*
5284 * Mainpine series cards: Fairly standard layout but fools
5285 * parts of the autodetect in some cases and uses otherwise
5286 * unmatched communications subclasses in the PCI Express case
5287 */
5288
5289 { /* RockForceDUO */
5290 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5291 PCI_VENDOR_ID_MAINPINE, 0x0200,
5292 0, 0, pbn_b0_2_115200 },
5293 { /* RockForceQUATRO */
5294 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5295 PCI_VENDOR_ID_MAINPINE, 0x0300,
5296 0, 0, pbn_b0_4_115200 },
5297 { /* RockForceDUO+ */
5298 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5299 PCI_VENDOR_ID_MAINPINE, 0x0400,
5300 0, 0, pbn_b0_2_115200 },
5301 { /* RockForceQUATRO+ */
5302 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5303 PCI_VENDOR_ID_MAINPINE, 0x0500,
5304 0, 0, pbn_b0_4_115200 },
5305 { /* RockForce+ */
5306 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5307 PCI_VENDOR_ID_MAINPINE, 0x0600,
5308 0, 0, pbn_b0_2_115200 },
5309 { /* RockForce+ */
5310 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5311 PCI_VENDOR_ID_MAINPINE, 0x0700,
5312 0, 0, pbn_b0_4_115200 },
5313 { /* RockForceOCTO+ */
5314 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5315 PCI_VENDOR_ID_MAINPINE, 0x0800,
5316 0, 0, pbn_b0_8_115200 },
5317 { /* RockForceDUO+ */
5318 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5319 PCI_VENDOR_ID_MAINPINE, 0x0C00,
5320 0, 0, pbn_b0_2_115200 },
5321 { /* RockForceQUARTRO+ */
5322 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5323 PCI_VENDOR_ID_MAINPINE, 0x0D00,
5324 0, 0, pbn_b0_4_115200 },
5325 { /* RockForceOCTO+ */
5326 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5327 PCI_VENDOR_ID_MAINPINE, 0x1D00,
5328 0, 0, pbn_b0_8_115200 },
5329 { /* RockForceD1 */
5330 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5331 PCI_VENDOR_ID_MAINPINE, 0x2000,
5332 0, 0, pbn_b0_1_115200 },
5333 { /* RockForceF1 */
5334 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5335 PCI_VENDOR_ID_MAINPINE, 0x2100,
5336 0, 0, pbn_b0_1_115200 },
5337 { /* RockForceD2 */
5338 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5339 PCI_VENDOR_ID_MAINPINE, 0x2200,
5340 0, 0, pbn_b0_2_115200 },
5341 { /* RockForceF2 */
5342 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5343 PCI_VENDOR_ID_MAINPINE, 0x2300,
5344 0, 0, pbn_b0_2_115200 },
5345 { /* RockForceD4 */
5346 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5347 PCI_VENDOR_ID_MAINPINE, 0x2400,
5348 0, 0, pbn_b0_4_115200 },
5349 { /* RockForceF4 */
5350 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5351 PCI_VENDOR_ID_MAINPINE, 0x2500,
5352 0, 0, pbn_b0_4_115200 },
5353 { /* RockForceD8 */
5354 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5355 PCI_VENDOR_ID_MAINPINE, 0x2600,
5356 0, 0, pbn_b0_8_115200 },
5357 { /* RockForceF8 */
5358 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5359 PCI_VENDOR_ID_MAINPINE, 0x2700,
5360 0, 0, pbn_b0_8_115200 },
5361 { /* IQ Express D1 */
5362 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5363 PCI_VENDOR_ID_MAINPINE, 0x3000,
5364 0, 0, pbn_b0_1_115200 },
5365 { /* IQ Express F1 */
5366 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5367 PCI_VENDOR_ID_MAINPINE, 0x3100,
5368 0, 0, pbn_b0_1_115200 },
5369 { /* IQ Express D2 */
5370 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5371 PCI_VENDOR_ID_MAINPINE, 0x3200,
5372 0, 0, pbn_b0_2_115200 },
5373 { /* IQ Express F2 */
5374 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5375 PCI_VENDOR_ID_MAINPINE, 0x3300,
5376 0, 0, pbn_b0_2_115200 },
5377 { /* IQ Express D4 */
5378 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5379 PCI_VENDOR_ID_MAINPINE, 0x3400,
5380 0, 0, pbn_b0_4_115200 },
5381 { /* IQ Express F4 */
5382 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5383 PCI_VENDOR_ID_MAINPINE, 0x3500,
5384 0, 0, pbn_b0_4_115200 },
5385 { /* IQ Express D8 */
5386 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5387 PCI_VENDOR_ID_MAINPINE, 0x3C00,
5388 0, 0, pbn_b0_8_115200 },
5389 { /* IQ Express F8 */
5390 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5391 PCI_VENDOR_ID_MAINPINE, 0x3D00,
5392 0, 0, pbn_b0_8_115200 },
5393
5394
5395 /*
5396 * PA Semi PA6T-1682M on-chip UART
5397 */
5398 { PCI_VENDOR_ID_PASEMI, 0xa004,
5399 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5400 pbn_pasemi_1682M },
5401
5402 /*
5403 * National Instruments
5404 */
5405 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
5406 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5407 pbn_b1_16_115200 },
5408 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
5409 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5410 pbn_b1_8_115200 },
5411 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
5412 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5413 pbn_b1_bt_4_115200 },
5414 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
5415 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5416 pbn_b1_bt_2_115200 },
5417 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
5418 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5419 pbn_b1_bt_4_115200 },
5420 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
5421 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5422 pbn_b1_bt_2_115200 },
5423 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
5424 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5425 pbn_b1_16_115200 },
5426 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
5427 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5428 pbn_b1_8_115200 },
5429 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
5430 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5431 pbn_b1_bt_4_115200 },
5432 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
5433 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5434 pbn_b1_bt_2_115200 },
5435 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
5436 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5437 pbn_b1_bt_4_115200 },
5438 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
5439 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5440 pbn_b1_bt_2_115200 },
5441 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
5442 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5443 pbn_ni8430_2 },
5444 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
5445 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5446 pbn_ni8430_2 },
5447 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
5448 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5449 pbn_ni8430_4 },
5450 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
5451 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5452 pbn_ni8430_4 },
5453 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
5454 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5455 pbn_ni8430_8 },
5456 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
5457 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5458 pbn_ni8430_8 },
5459 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
5460 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5461 pbn_ni8430_16 },
5462 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
5463 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5464 pbn_ni8430_16 },
5465 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
5466 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5467 pbn_ni8430_2 },
5468 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
5469 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5470 pbn_ni8430_2 },
5471 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
5472 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5473 pbn_ni8430_4 },
5474 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
5475 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5476 pbn_ni8430_4 },
5477
5478 /*
5479 * MOXA
5480 */
5481 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP102E,
5482 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5483 pbn_moxa8250_2p },
5484 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP102EL,
5485 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5486 pbn_moxa8250_2p },
5487 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP104EL_A,
5488 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5489 pbn_moxa8250_4p },
5490 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP114EL,
5491 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5492 pbn_moxa8250_4p },
5493 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP116E_A_A,
5494 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5495 pbn_moxa8250_8p },
5496 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP116E_A_B,
5497 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5498 pbn_moxa8250_8p },
5499 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP118EL_A,
5500 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5501 pbn_moxa8250_8p },
5502 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP118E_A_I,
5503 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5504 pbn_moxa8250_8p },
5505 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP132EL,
5506 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5507 pbn_moxa8250_2p },
5508 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP134EL_A,
5509 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5510 pbn_moxa8250_4p },
5511 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP138E_A,
5512 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5513 pbn_moxa8250_8p },
5514 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP168EL_A,
5515 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5516 pbn_moxa8250_8p },
5517
5518 /*
5519 * ADDI-DATA GmbH communication cards <info@addi-data.com>
5520 */
5521 { PCI_VENDOR_ID_ADDIDATA,
5522 PCI_DEVICE_ID_ADDIDATA_APCI7500,
5523 PCI_ANY_ID,
5524 PCI_ANY_ID,
5525 0,
5526 0,
5527 pbn_b0_4_115200 },
5528
5529 { PCI_VENDOR_ID_ADDIDATA,
5530 PCI_DEVICE_ID_ADDIDATA_APCI7420,
5531 PCI_ANY_ID,
5532 PCI_ANY_ID,
5533 0,
5534 0,
5535 pbn_b0_2_115200 },
5536
5537 { PCI_VENDOR_ID_ADDIDATA,
5538 PCI_DEVICE_ID_ADDIDATA_APCI7300,
5539 PCI_ANY_ID,
5540 PCI_ANY_ID,
5541 0,
5542 0,
5543 pbn_b0_1_115200 },
5544
5545 { PCI_VENDOR_ID_AMCC,
5546 PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
5547 PCI_ANY_ID,
5548 PCI_ANY_ID,
5549 0,
5550 0,
5551 pbn_b1_8_115200 },
5552
5553 { PCI_VENDOR_ID_ADDIDATA,
5554 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
5555 PCI_ANY_ID,
5556 PCI_ANY_ID,
5557 0,
5558 0,
5559 pbn_b0_4_115200 },
5560
5561 { PCI_VENDOR_ID_ADDIDATA,
5562 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
5563 PCI_ANY_ID,
5564 PCI_ANY_ID,
5565 0,
5566 0,
5567 pbn_b0_2_115200 },
5568
5569 { PCI_VENDOR_ID_ADDIDATA,
5570 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
5571 PCI_ANY_ID,
5572 PCI_ANY_ID,
5573 0,
5574 0,
5575 pbn_b0_1_115200 },
5576
5577 { PCI_VENDOR_ID_ADDIDATA,
5578 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
5579 PCI_ANY_ID,
5580 PCI_ANY_ID,
5581 0,
5582 0,
5583 pbn_b0_4_115200 },
5584
5585 { PCI_VENDOR_ID_ADDIDATA,
5586 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
5587 PCI_ANY_ID,
5588 PCI_ANY_ID,
5589 0,
5590 0,
5591 pbn_b0_2_115200 },
5592
5593 { PCI_VENDOR_ID_ADDIDATA,
5594 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
5595 PCI_ANY_ID,
5596 PCI_ANY_ID,
5597 0,
5598 0,
5599 pbn_b0_1_115200 },
5600
5601 { PCI_VENDOR_ID_ADDIDATA,
5602 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
5603 PCI_ANY_ID,
5604 PCI_ANY_ID,
5605 0,
5606 0,
5607 pbn_b0_8_115200 },
5608
5609 { PCI_VENDOR_ID_ADDIDATA,
5610 PCI_DEVICE_ID_ADDIDATA_APCIe7500,
5611 PCI_ANY_ID,
5612 PCI_ANY_ID,
5613 0,
5614 0,
5615 pbn_ADDIDATA_PCIe_4_3906250 },
5616
5617 { PCI_VENDOR_ID_ADDIDATA,
5618 PCI_DEVICE_ID_ADDIDATA_APCIe7420,
5619 PCI_ANY_ID,
5620 PCI_ANY_ID,
5621 0,
5622 0,
5623 pbn_ADDIDATA_PCIe_2_3906250 },
5624
5625 { PCI_VENDOR_ID_ADDIDATA,
5626 PCI_DEVICE_ID_ADDIDATA_APCIe7300,
5627 PCI_ANY_ID,
5628 PCI_ANY_ID,
5629 0,
5630 0,
5631 pbn_ADDIDATA_PCIe_1_3906250 },
5632
5633 { PCI_VENDOR_ID_ADDIDATA,
5634 PCI_DEVICE_ID_ADDIDATA_APCIe7800,
5635 PCI_ANY_ID,
5636 PCI_ANY_ID,
5637 0,
5638 0,
5639 pbn_ADDIDATA_PCIe_8_3906250 },
5640
5641 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
5642 PCI_VENDOR_ID_IBM, 0x0299,
5643 0, 0, pbn_b0_bt_2_115200 },
5644
5645 /*
5646 * other NetMos 9835 devices are most likely handled by the
5647 * parport_serial driver, check drivers/parport/parport_serial.c
5648 * before adding them here.
5649 */
5650
5651 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
5652 0xA000, 0x1000,
5653 0, 0, pbn_b0_1_115200 },
5654
5655 /* the 9901 is a rebranded 9912 */
5656 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
5657 0xA000, 0x1000,
5658 0, 0, pbn_b0_1_115200 },
5659
5660 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
5661 0xA000, 0x1000,
5662 0, 0, pbn_b0_1_115200 },
5663
5664 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904,
5665 0xA000, 0x1000,
5666 0, 0, pbn_b0_1_115200 },
5667
5668 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5669 0xA000, 0x1000,
5670 0, 0, pbn_b0_1_115200 },
5671
5672 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5673 0xA000, 0x3002,
5674 0, 0, pbn_NETMOS9900_2s_115200 },
5675
5676 /*
5677 * Best Connectivity and Rosewill PCI Multi I/O cards
5678 */
5679
5680 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5681 0xA000, 0x1000,
5682 0, 0, pbn_b0_1_115200 },
5683
5684 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5685 0xA000, 0x3002,
5686 0, 0, pbn_b0_bt_2_115200 },
5687
5688 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5689 0xA000, 0x3004,
5690 0, 0, pbn_b0_bt_4_115200 },
5691 /* Intel CE4100 */
5692 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART,
5693 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5694 pbn_ce4100_1_115200 },
5695
5696 /*
5697 * Cronyx Omega PCI
5698 */
5699 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
5700 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5701 pbn_omegapci },
5702
5703 /*
5704 * Broadcom TruManage
5705 */
5706 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
5707 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5708 pbn_brcm_trumanage },
5709
5710 /*
5711 * AgeStar as-prs2-009
5712 */
5713 { PCI_VENDOR_ID_AGESTAR, PCI_DEVICE_ID_AGESTAR_9375,
5714 PCI_ANY_ID, PCI_ANY_ID,
5715 0, 0, pbn_b0_bt_2_115200 },
5716
5717 /*
5718 * WCH CH353 series devices: The 2S1P is handled by parport_serial
5719 * so not listed here.
5720 */
5721 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_4S,
5722 PCI_ANY_ID, PCI_ANY_ID,
5723 0, 0, pbn_b0_bt_4_115200 },
5724
5725 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_2S1PF,
5726 PCI_ANY_ID, PCI_ANY_ID,
5727 0, 0, pbn_b0_bt_2_115200 },
5728
5729 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH355_4S,
5730 PCI_ANY_ID, PCI_ANY_ID,
5731 0, 0, pbn_b0_bt_4_115200 },
5732
5733 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH382_2S,
5734 PCI_ANY_ID, PCI_ANY_ID,
5735 0, 0, pbn_wch382_2 },
5736
5737 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH384_4S,
5738 PCI_ANY_ID, PCI_ANY_ID,
5739 0, 0, pbn_wch384_4 },
5740
5741 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH384_8S,
5742 PCI_ANY_ID, PCI_ANY_ID,
5743 0, 0, pbn_wch384_8 },
5744 /*
5745 * Realtek RealManage
5746 */
5747 { PCI_VENDOR_ID_REALTEK, 0x816a,
5748 PCI_ANY_ID, PCI_ANY_ID,
5749 0, 0, pbn_b0_1_115200 },
5750
5751 { PCI_VENDOR_ID_REALTEK, 0x816b,
5752 PCI_ANY_ID, PCI_ANY_ID,
5753 0, 0, pbn_b0_1_115200 },
5754
5755 /* Fintek PCI serial cards */
5756 { PCI_DEVICE(0x1c29, 0x1104), .driver_data = pbn_fintek_4 },
5757 { PCI_DEVICE(0x1c29, 0x1108), .driver_data = pbn_fintek_8 },
5758 { PCI_DEVICE(0x1c29, 0x1112), .driver_data = pbn_fintek_12 },
5759 { PCI_DEVICE(0x1c29, 0x1204), .driver_data = pbn_fintek_F81504A },
5760 { PCI_DEVICE(0x1c29, 0x1208), .driver_data = pbn_fintek_F81508A },
5761 { PCI_DEVICE(0x1c29, 0x1212), .driver_data = pbn_fintek_F81512A },
5762
5763 /* MKS Tenta SCOM-080x serial cards */
5764 { PCI_DEVICE(0x1601, 0x0800), .driver_data = pbn_b0_4_1250000 },
5765 { PCI_DEVICE(0x1601, 0xa801), .driver_data = pbn_b0_4_1250000 },
5766
5767 /* Amazon PCI serial device */
5768 { PCI_DEVICE(0x1d0f, 0x8250), .driver_data = pbn_b0_1_115200 },
5769
5770 /*
5771 * These entries match devices with class COMMUNICATION_SERIAL,
5772 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
5773 */
5774 { PCI_ANY_ID, PCI_ANY_ID,
5775 PCI_ANY_ID, PCI_ANY_ID,
5776 PCI_CLASS_COMMUNICATION_SERIAL << 8,
5777 0xffff00, pbn_default },
5778 { PCI_ANY_ID, PCI_ANY_ID,
5779 PCI_ANY_ID, PCI_ANY_ID,
5780 PCI_CLASS_COMMUNICATION_MODEM << 8,
5781 0xffff00, pbn_default },
5782 { PCI_ANY_ID, PCI_ANY_ID,
5783 PCI_ANY_ID, PCI_ANY_ID,
5784 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
5785 0xffff00, pbn_default },
5786 { 0, }
5787 };
5788
serial8250_io_error_detected(struct pci_dev * dev,pci_channel_state_t state)5789 static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev,
5790 pci_channel_state_t state)
5791 {
5792 struct serial_private *priv = pci_get_drvdata(dev);
5793
5794 if (state == pci_channel_io_perm_failure)
5795 return PCI_ERS_RESULT_DISCONNECT;
5796
5797 if (priv)
5798 pciserial_detach_ports(priv);
5799
5800 pci_disable_device(dev);
5801
5802 return PCI_ERS_RESULT_NEED_RESET;
5803 }
5804
serial8250_io_slot_reset(struct pci_dev * dev)5805 static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev)
5806 {
5807 int rc;
5808
5809 rc = pci_enable_device(dev);
5810
5811 if (rc)
5812 return PCI_ERS_RESULT_DISCONNECT;
5813
5814 pci_restore_state(dev);
5815 pci_save_state(dev);
5816
5817 return PCI_ERS_RESULT_RECOVERED;
5818 }
5819
serial8250_io_resume(struct pci_dev * dev)5820 static void serial8250_io_resume(struct pci_dev *dev)
5821 {
5822 struct serial_private *priv = pci_get_drvdata(dev);
5823 struct serial_private *new;
5824
5825 if (!priv)
5826 return;
5827
5828 new = pciserial_init_ports(dev, priv->board);
5829 if (!IS_ERR(new)) {
5830 pci_set_drvdata(dev, new);
5831 kfree(priv);
5832 }
5833 }
5834
5835 static const struct pci_error_handlers serial8250_err_handler = {
5836 .error_detected = serial8250_io_error_detected,
5837 .slot_reset = serial8250_io_slot_reset,
5838 .resume = serial8250_io_resume,
5839 };
5840
5841 static struct pci_driver serial_pci_driver = {
5842 .name = "serial",
5843 .probe = pciserial_init_one,
5844 .remove = pciserial_remove_one,
5845 .driver = {
5846 .pm = &pciserial_pm_ops,
5847 },
5848 .id_table = serial_pci_tbl,
5849 .err_handler = &serial8250_err_handler,
5850 };
5851
5852 module_pci_driver(serial_pci_driver);
5853
5854 MODULE_LICENSE("GPL");
5855 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
5856 MODULE_DEVICE_TABLE(pci, serial_pci_tbl);
5857