1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2018, The Linux Foundation. All rights reserved.
3 *
4 * Inspired by dwc3-of-simple.c
5 */
6
7 #include <linux/acpi.h>
8 #include <linux/io.h>
9 #include <linux/of.h>
10 #include <linux/clk.h>
11 #include <linux/irq.h>
12 #include <linux/of_clk.h>
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/extcon.h>
16 #include <linux/interconnect.h>
17 #include <linux/of_platform.h>
18 #include <linux/platform_device.h>
19 #include <linux/phy/phy.h>
20 #include <linux/usb/of.h>
21 #include <linux/reset.h>
22 #include <linux/iopoll.h>
23
24 #include "core.h"
25
26 /* USB QSCRATCH Hardware registers */
27 #define QSCRATCH_HS_PHY_CTRL 0x10
28 #define UTMI_OTG_VBUS_VALID BIT(20)
29 #define SW_SESSVLD_SEL BIT(28)
30
31 #define QSCRATCH_SS_PHY_CTRL 0x30
32 #define LANE0_PWR_PRESENT BIT(24)
33
34 #define QSCRATCH_GENERAL_CFG 0x08
35 #define PIPE_UTMI_CLK_SEL BIT(0)
36 #define PIPE3_PHYSTATUS_SW BIT(3)
37 #define PIPE_UTMI_CLK_DIS BIT(8)
38
39 #define PWR_EVNT_IRQ_STAT_REG 0x58
40 #define PWR_EVNT_LPM_IN_L2_MASK BIT(4)
41 #define PWR_EVNT_LPM_OUT_L2_MASK BIT(5)
42
43 #define SDM845_QSCRATCH_BASE_OFFSET 0xf8800
44 #define SDM845_QSCRATCH_SIZE 0x400
45 #define SDM845_DWC3_CORE_SIZE 0xcd00
46
47 /* Interconnect path bandwidths in MBps */
48 #define USB_MEMORY_AVG_HS_BW MBps_to_icc(240)
49 #define USB_MEMORY_PEAK_HS_BW MBps_to_icc(700)
50 #define USB_MEMORY_AVG_SS_BW MBps_to_icc(1000)
51 #define USB_MEMORY_PEAK_SS_BW MBps_to_icc(2500)
52 #define APPS_USB_AVG_BW 0
53 #define APPS_USB_PEAK_BW MBps_to_icc(40)
54
55 struct dwc3_acpi_pdata {
56 u32 qscratch_base_offset;
57 u32 qscratch_base_size;
58 u32 dwc3_core_base_size;
59 int hs_phy_irq_index;
60 int dp_hs_phy_irq_index;
61 int dm_hs_phy_irq_index;
62 int ss_phy_irq_index;
63 bool is_urs;
64 };
65
66 struct dwc3_qcom {
67 struct device *dev;
68 void __iomem *qscratch_base;
69 struct platform_device *dwc3;
70 struct platform_device *urs_usb;
71 struct clk **clks;
72 int num_clocks;
73 struct reset_control *resets;
74
75 int hs_phy_irq;
76 int dp_hs_phy_irq;
77 int dm_hs_phy_irq;
78 int ss_phy_irq;
79
80 struct extcon_dev *edev;
81 struct extcon_dev *host_edev;
82 struct notifier_block vbus_nb;
83 struct notifier_block host_nb;
84
85 const struct dwc3_acpi_pdata *acpi_pdata;
86
87 enum usb_dr_mode mode;
88 bool is_suspended;
89 bool pm_suspended;
90 struct icc_path *icc_path_ddr;
91 struct icc_path *icc_path_apps;
92 };
93
dwc3_qcom_setbits(void __iomem * base,u32 offset,u32 val)94 static inline void dwc3_qcom_setbits(void __iomem *base, u32 offset, u32 val)
95 {
96 u32 reg;
97
98 reg = readl(base + offset);
99 reg |= val;
100 writel(reg, base + offset);
101
102 /* ensure that above write is through */
103 readl(base + offset);
104 }
105
dwc3_qcom_clrbits(void __iomem * base,u32 offset,u32 val)106 static inline void dwc3_qcom_clrbits(void __iomem *base, u32 offset, u32 val)
107 {
108 u32 reg;
109
110 reg = readl(base + offset);
111 reg &= ~val;
112 writel(reg, base + offset);
113
114 /* ensure that above write is through */
115 readl(base + offset);
116 }
117
dwc3_qcom_vbus_override_enable(struct dwc3_qcom * qcom,bool enable)118 static void dwc3_qcom_vbus_override_enable(struct dwc3_qcom *qcom, bool enable)
119 {
120 if (enable) {
121 dwc3_qcom_setbits(qcom->qscratch_base, QSCRATCH_SS_PHY_CTRL,
122 LANE0_PWR_PRESENT);
123 dwc3_qcom_setbits(qcom->qscratch_base, QSCRATCH_HS_PHY_CTRL,
124 UTMI_OTG_VBUS_VALID | SW_SESSVLD_SEL);
125 } else {
126 dwc3_qcom_clrbits(qcom->qscratch_base, QSCRATCH_SS_PHY_CTRL,
127 LANE0_PWR_PRESENT);
128 dwc3_qcom_clrbits(qcom->qscratch_base, QSCRATCH_HS_PHY_CTRL,
129 UTMI_OTG_VBUS_VALID | SW_SESSVLD_SEL);
130 }
131 }
132
dwc3_qcom_vbus_notifier(struct notifier_block * nb,unsigned long event,void * ptr)133 static int dwc3_qcom_vbus_notifier(struct notifier_block *nb,
134 unsigned long event, void *ptr)
135 {
136 struct dwc3_qcom *qcom = container_of(nb, struct dwc3_qcom, vbus_nb);
137
138 /* enable vbus override for device mode */
139 dwc3_qcom_vbus_override_enable(qcom, event);
140 qcom->mode = event ? USB_DR_MODE_PERIPHERAL : USB_DR_MODE_HOST;
141
142 return NOTIFY_DONE;
143 }
144
dwc3_qcom_host_notifier(struct notifier_block * nb,unsigned long event,void * ptr)145 static int dwc3_qcom_host_notifier(struct notifier_block *nb,
146 unsigned long event, void *ptr)
147 {
148 struct dwc3_qcom *qcom = container_of(nb, struct dwc3_qcom, host_nb);
149
150 /* disable vbus override in host mode */
151 dwc3_qcom_vbus_override_enable(qcom, !event);
152 qcom->mode = event ? USB_DR_MODE_HOST : USB_DR_MODE_PERIPHERAL;
153
154 return NOTIFY_DONE;
155 }
156
dwc3_qcom_register_extcon(struct dwc3_qcom * qcom)157 static int dwc3_qcom_register_extcon(struct dwc3_qcom *qcom)
158 {
159 struct device *dev = qcom->dev;
160 struct extcon_dev *host_edev;
161 int ret;
162
163 if (!of_property_read_bool(dev->of_node, "extcon"))
164 return 0;
165
166 qcom->edev = extcon_get_edev_by_phandle(dev, 0);
167 if (IS_ERR(qcom->edev))
168 return PTR_ERR(qcom->edev);
169
170 qcom->vbus_nb.notifier_call = dwc3_qcom_vbus_notifier;
171
172 qcom->host_edev = extcon_get_edev_by_phandle(dev, 1);
173 if (IS_ERR(qcom->host_edev))
174 qcom->host_edev = NULL;
175
176 ret = devm_extcon_register_notifier(dev, qcom->edev, EXTCON_USB,
177 &qcom->vbus_nb);
178 if (ret < 0) {
179 dev_err(dev, "VBUS notifier register failed\n");
180 return ret;
181 }
182
183 if (qcom->host_edev)
184 host_edev = qcom->host_edev;
185 else
186 host_edev = qcom->edev;
187
188 qcom->host_nb.notifier_call = dwc3_qcom_host_notifier;
189 ret = devm_extcon_register_notifier(dev, host_edev, EXTCON_USB_HOST,
190 &qcom->host_nb);
191 if (ret < 0) {
192 dev_err(dev, "Host notifier register failed\n");
193 return ret;
194 }
195
196 /* Update initial VBUS override based on extcon state */
197 if (extcon_get_state(qcom->edev, EXTCON_USB) ||
198 !extcon_get_state(host_edev, EXTCON_USB_HOST))
199 dwc3_qcom_vbus_notifier(&qcom->vbus_nb, true, qcom->edev);
200 else
201 dwc3_qcom_vbus_notifier(&qcom->vbus_nb, false, qcom->edev);
202
203 return 0;
204 }
205
dwc3_qcom_interconnect_enable(struct dwc3_qcom * qcom)206 static int dwc3_qcom_interconnect_enable(struct dwc3_qcom *qcom)
207 {
208 int ret;
209
210 ret = icc_enable(qcom->icc_path_ddr);
211 if (ret)
212 return ret;
213
214 ret = icc_enable(qcom->icc_path_apps);
215 if (ret)
216 icc_disable(qcom->icc_path_ddr);
217
218 return ret;
219 }
220
dwc3_qcom_interconnect_disable(struct dwc3_qcom * qcom)221 static int dwc3_qcom_interconnect_disable(struct dwc3_qcom *qcom)
222 {
223 int ret;
224
225 ret = icc_disable(qcom->icc_path_ddr);
226 if (ret)
227 return ret;
228
229 ret = icc_disable(qcom->icc_path_apps);
230 if (ret)
231 icc_enable(qcom->icc_path_ddr);
232
233 return ret;
234 }
235
236 /**
237 * dwc3_qcom_interconnect_init() - Get interconnect path handles
238 * and set bandwidhth.
239 * @qcom: Pointer to the concerned usb core.
240 *
241 */
dwc3_qcom_interconnect_init(struct dwc3_qcom * qcom)242 static int dwc3_qcom_interconnect_init(struct dwc3_qcom *qcom)
243 {
244 struct device *dev = qcom->dev;
245 int ret;
246
247 if (has_acpi_companion(dev))
248 return 0;
249
250 qcom->icc_path_ddr = of_icc_get(dev, "usb-ddr");
251 if (IS_ERR(qcom->icc_path_ddr)) {
252 dev_err(dev, "failed to get usb-ddr path: %ld\n",
253 PTR_ERR(qcom->icc_path_ddr));
254 return PTR_ERR(qcom->icc_path_ddr);
255 }
256
257 qcom->icc_path_apps = of_icc_get(dev, "apps-usb");
258 if (IS_ERR(qcom->icc_path_apps)) {
259 dev_err(dev, "failed to get apps-usb path: %ld\n",
260 PTR_ERR(qcom->icc_path_apps));
261 ret = PTR_ERR(qcom->icc_path_apps);
262 goto put_path_ddr;
263 }
264
265 if (usb_get_maximum_speed(&qcom->dwc3->dev) >= USB_SPEED_SUPER ||
266 usb_get_maximum_speed(&qcom->dwc3->dev) == USB_SPEED_UNKNOWN)
267 ret = icc_set_bw(qcom->icc_path_ddr,
268 USB_MEMORY_AVG_SS_BW, USB_MEMORY_PEAK_SS_BW);
269 else
270 ret = icc_set_bw(qcom->icc_path_ddr,
271 USB_MEMORY_AVG_HS_BW, USB_MEMORY_PEAK_HS_BW);
272
273 if (ret) {
274 dev_err(dev, "failed to set bandwidth for usb-ddr path: %d\n", ret);
275 goto put_path_apps;
276 }
277
278 ret = icc_set_bw(qcom->icc_path_apps,
279 APPS_USB_AVG_BW, APPS_USB_PEAK_BW);
280 if (ret) {
281 dev_err(dev, "failed to set bandwidth for apps-usb path: %d\n", ret);
282 goto put_path_apps;
283 }
284
285 return 0;
286
287 put_path_apps:
288 icc_put(qcom->icc_path_apps);
289 put_path_ddr:
290 icc_put(qcom->icc_path_ddr);
291 return ret;
292 }
293
294 /**
295 * dwc3_qcom_interconnect_exit() - Release interconnect path handles
296 * @qcom: Pointer to the concerned usb core.
297 *
298 * This function is used to release interconnect path handle.
299 */
dwc3_qcom_interconnect_exit(struct dwc3_qcom * qcom)300 static void dwc3_qcom_interconnect_exit(struct dwc3_qcom *qcom)
301 {
302 icc_put(qcom->icc_path_ddr);
303 icc_put(qcom->icc_path_apps);
304 }
305
306 /* Only usable in contexts where the role can not change. */
dwc3_qcom_is_host(struct dwc3_qcom * qcom)307 static bool dwc3_qcom_is_host(struct dwc3_qcom *qcom)
308 {
309 struct dwc3 *dwc = platform_get_drvdata(qcom->dwc3);
310
311 return dwc->xhci;
312 }
313
dwc3_qcom_disable_interrupts(struct dwc3_qcom * qcom)314 static void dwc3_qcom_disable_interrupts(struct dwc3_qcom *qcom)
315 {
316 if (qcom->hs_phy_irq) {
317 disable_irq_wake(qcom->hs_phy_irq);
318 disable_irq_nosync(qcom->hs_phy_irq);
319 }
320
321 if (qcom->dp_hs_phy_irq) {
322 disable_irq_wake(qcom->dp_hs_phy_irq);
323 disable_irq_nosync(qcom->dp_hs_phy_irq);
324 }
325
326 if (qcom->dm_hs_phy_irq) {
327 disable_irq_wake(qcom->dm_hs_phy_irq);
328 disable_irq_nosync(qcom->dm_hs_phy_irq);
329 }
330
331 if (qcom->ss_phy_irq) {
332 disable_irq_wake(qcom->ss_phy_irq);
333 disable_irq_nosync(qcom->ss_phy_irq);
334 }
335 }
336
dwc3_qcom_enable_interrupts(struct dwc3_qcom * qcom)337 static void dwc3_qcom_enable_interrupts(struct dwc3_qcom *qcom)
338 {
339 if (qcom->hs_phy_irq) {
340 enable_irq(qcom->hs_phy_irq);
341 enable_irq_wake(qcom->hs_phy_irq);
342 }
343
344 if (qcom->dp_hs_phy_irq) {
345 enable_irq(qcom->dp_hs_phy_irq);
346 enable_irq_wake(qcom->dp_hs_phy_irq);
347 }
348
349 if (qcom->dm_hs_phy_irq) {
350 enable_irq(qcom->dm_hs_phy_irq);
351 enable_irq_wake(qcom->dm_hs_phy_irq);
352 }
353
354 if (qcom->ss_phy_irq) {
355 enable_irq(qcom->ss_phy_irq);
356 enable_irq_wake(qcom->ss_phy_irq);
357 }
358 }
359
dwc3_qcom_suspend(struct dwc3_qcom * qcom)360 static int dwc3_qcom_suspend(struct dwc3_qcom *qcom)
361 {
362 u32 val;
363 int i, ret;
364
365 if (qcom->is_suspended)
366 return 0;
367
368 val = readl(qcom->qscratch_base + PWR_EVNT_IRQ_STAT_REG);
369 if (!(val & PWR_EVNT_LPM_IN_L2_MASK))
370 dev_err(qcom->dev, "HS-PHY not in L2\n");
371
372 for (i = qcom->num_clocks - 1; i >= 0; i--)
373 clk_disable_unprepare(qcom->clks[i]);
374
375 ret = dwc3_qcom_interconnect_disable(qcom);
376 if (ret)
377 dev_warn(qcom->dev, "failed to disable interconnect: %d\n", ret);
378
379 if (device_may_wakeup(qcom->dev))
380 dwc3_qcom_enable_interrupts(qcom);
381
382 qcom->is_suspended = true;
383
384 return 0;
385 }
386
dwc3_qcom_resume(struct dwc3_qcom * qcom)387 static int dwc3_qcom_resume(struct dwc3_qcom *qcom)
388 {
389 int ret;
390 int i;
391
392 if (!qcom->is_suspended)
393 return 0;
394
395 if (device_may_wakeup(qcom->dev))
396 dwc3_qcom_disable_interrupts(qcom);
397
398 for (i = 0; i < qcom->num_clocks; i++) {
399 ret = clk_prepare_enable(qcom->clks[i]);
400 if (ret < 0) {
401 while (--i >= 0)
402 clk_disable_unprepare(qcom->clks[i]);
403 return ret;
404 }
405 }
406
407 ret = dwc3_qcom_interconnect_enable(qcom);
408 if (ret)
409 dev_warn(qcom->dev, "failed to enable interconnect: %d\n", ret);
410
411 /* Clear existing events from PHY related to L2 in/out */
412 dwc3_qcom_setbits(qcom->qscratch_base, PWR_EVNT_IRQ_STAT_REG,
413 PWR_EVNT_LPM_IN_L2_MASK | PWR_EVNT_LPM_OUT_L2_MASK);
414
415 qcom->is_suspended = false;
416
417 return 0;
418 }
419
qcom_dwc3_resume_irq(int irq,void * data)420 static irqreturn_t qcom_dwc3_resume_irq(int irq, void *data)
421 {
422 struct dwc3_qcom *qcom = data;
423 struct dwc3 *dwc = platform_get_drvdata(qcom->dwc3);
424
425 /* If pm_suspended then let pm_resume take care of resuming h/w */
426 if (qcom->pm_suspended)
427 return IRQ_HANDLED;
428
429 /*
430 * This is safe as role switching is done from a freezable workqueue
431 * and the wakeup interrupts are disabled as part of resume.
432 */
433 if (dwc3_qcom_is_host(qcom))
434 pm_runtime_resume(&dwc->xhci->dev);
435
436 return IRQ_HANDLED;
437 }
438
dwc3_qcom_select_utmi_clk(struct dwc3_qcom * qcom)439 static void dwc3_qcom_select_utmi_clk(struct dwc3_qcom *qcom)
440 {
441 /* Configure dwc3 to use UTMI clock as PIPE clock not present */
442 dwc3_qcom_setbits(qcom->qscratch_base, QSCRATCH_GENERAL_CFG,
443 PIPE_UTMI_CLK_DIS);
444
445 usleep_range(100, 1000);
446
447 dwc3_qcom_setbits(qcom->qscratch_base, QSCRATCH_GENERAL_CFG,
448 PIPE_UTMI_CLK_SEL | PIPE3_PHYSTATUS_SW);
449
450 usleep_range(100, 1000);
451
452 dwc3_qcom_clrbits(qcom->qscratch_base, QSCRATCH_GENERAL_CFG,
453 PIPE_UTMI_CLK_DIS);
454 }
455
dwc3_qcom_get_irq(struct platform_device * pdev,const char * name,int num)456 static int dwc3_qcom_get_irq(struct platform_device *pdev,
457 const char *name, int num)
458 {
459 struct dwc3_qcom *qcom = platform_get_drvdata(pdev);
460 struct platform_device *pdev_irq = qcom->urs_usb ? qcom->urs_usb : pdev;
461 struct device_node *np = pdev->dev.of_node;
462 int ret;
463
464 if (np)
465 ret = platform_get_irq_byname_optional(pdev_irq, name);
466 else
467 ret = platform_get_irq_optional(pdev_irq, num);
468
469 return ret;
470 }
471
dwc3_qcom_setup_irq(struct platform_device * pdev)472 static int dwc3_qcom_setup_irq(struct platform_device *pdev)
473 {
474 struct dwc3_qcom *qcom = platform_get_drvdata(pdev);
475 const struct dwc3_acpi_pdata *pdata = qcom->acpi_pdata;
476 int irq;
477 int ret;
478
479 irq = dwc3_qcom_get_irq(pdev, "hs_phy_irq",
480 pdata ? pdata->hs_phy_irq_index : -1);
481 if (irq > 0) {
482 /* Keep wakeup interrupts disabled until suspend */
483 irq_set_status_flags(irq, IRQ_NOAUTOEN);
484 ret = devm_request_threaded_irq(qcom->dev, irq, NULL,
485 qcom_dwc3_resume_irq,
486 IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
487 "qcom_dwc3 HS", qcom);
488 if (ret) {
489 dev_err(qcom->dev, "hs_phy_irq failed: %d\n", ret);
490 return ret;
491 }
492 qcom->hs_phy_irq = irq;
493 }
494
495 irq = dwc3_qcom_get_irq(pdev, "dp_hs_phy_irq",
496 pdata ? pdata->dp_hs_phy_irq_index : -1);
497 if (irq > 0) {
498 irq_set_status_flags(irq, IRQ_NOAUTOEN);
499 ret = devm_request_threaded_irq(qcom->dev, irq, NULL,
500 qcom_dwc3_resume_irq,
501 IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
502 "qcom_dwc3 DP_HS", qcom);
503 if (ret) {
504 dev_err(qcom->dev, "dp_hs_phy_irq failed: %d\n", ret);
505 return ret;
506 }
507 qcom->dp_hs_phy_irq = irq;
508 }
509
510 irq = dwc3_qcom_get_irq(pdev, "dm_hs_phy_irq",
511 pdata ? pdata->dm_hs_phy_irq_index : -1);
512 if (irq > 0) {
513 irq_set_status_flags(irq, IRQ_NOAUTOEN);
514 ret = devm_request_threaded_irq(qcom->dev, irq, NULL,
515 qcom_dwc3_resume_irq,
516 IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
517 "qcom_dwc3 DM_HS", qcom);
518 if (ret) {
519 dev_err(qcom->dev, "dm_hs_phy_irq failed: %d\n", ret);
520 return ret;
521 }
522 qcom->dm_hs_phy_irq = irq;
523 }
524
525 irq = dwc3_qcom_get_irq(pdev, "ss_phy_irq",
526 pdata ? pdata->ss_phy_irq_index : -1);
527 if (irq > 0) {
528 irq_set_status_flags(irq, IRQ_NOAUTOEN);
529 ret = devm_request_threaded_irq(qcom->dev, irq, NULL,
530 qcom_dwc3_resume_irq,
531 IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
532 "qcom_dwc3 SS", qcom);
533 if (ret) {
534 dev_err(qcom->dev, "ss_phy_irq failed: %d\n", ret);
535 return ret;
536 }
537 qcom->ss_phy_irq = irq;
538 }
539
540 return 0;
541 }
542
dwc3_qcom_clk_init(struct dwc3_qcom * qcom,int count)543 static int dwc3_qcom_clk_init(struct dwc3_qcom *qcom, int count)
544 {
545 struct device *dev = qcom->dev;
546 struct device_node *np = dev->of_node;
547 int i;
548
549 if (!np || !count)
550 return 0;
551
552 if (count < 0)
553 return count;
554
555 qcom->num_clocks = count;
556
557 qcom->clks = devm_kcalloc(dev, qcom->num_clocks,
558 sizeof(struct clk *), GFP_KERNEL);
559 if (!qcom->clks)
560 return -ENOMEM;
561
562 for (i = 0; i < qcom->num_clocks; i++) {
563 struct clk *clk;
564 int ret;
565
566 clk = of_clk_get(np, i);
567 if (IS_ERR(clk)) {
568 while (--i >= 0)
569 clk_put(qcom->clks[i]);
570 return PTR_ERR(clk);
571 }
572
573 ret = clk_prepare_enable(clk);
574 if (ret < 0) {
575 while (--i >= 0) {
576 clk_disable_unprepare(qcom->clks[i]);
577 clk_put(qcom->clks[i]);
578 }
579 clk_put(clk);
580
581 return ret;
582 }
583
584 qcom->clks[i] = clk;
585 }
586
587 return 0;
588 }
589
590 static const struct property_entry dwc3_qcom_acpi_properties[] = {
591 PROPERTY_ENTRY_STRING("dr_mode", "host"),
592 {}
593 };
594
dwc3_qcom_acpi_register_core(struct platform_device * pdev)595 static int dwc3_qcom_acpi_register_core(struct platform_device *pdev)
596 {
597 struct dwc3_qcom *qcom = platform_get_drvdata(pdev);
598 struct device *dev = &pdev->dev;
599 struct resource *res, *child_res = NULL;
600 struct platform_device *pdev_irq = qcom->urs_usb ? qcom->urs_usb :
601 pdev;
602 int irq;
603 int ret;
604
605 qcom->dwc3 = platform_device_alloc("dwc3", PLATFORM_DEVID_AUTO);
606 if (!qcom->dwc3)
607 return -ENOMEM;
608
609 qcom->dwc3->dev.parent = dev;
610 qcom->dwc3->dev.type = dev->type;
611 qcom->dwc3->dev.dma_mask = dev->dma_mask;
612 qcom->dwc3->dev.dma_parms = dev->dma_parms;
613 qcom->dwc3->dev.coherent_dma_mask = dev->coherent_dma_mask;
614
615 child_res = kcalloc(2, sizeof(*child_res), GFP_KERNEL);
616 if (!child_res) {
617 platform_device_put(qcom->dwc3);
618 return -ENOMEM;
619 }
620
621 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
622 if (!res) {
623 dev_err(&pdev->dev, "failed to get memory resource\n");
624 ret = -ENODEV;
625 goto out;
626 }
627
628 child_res[0].flags = res->flags;
629 child_res[0].start = res->start;
630 child_res[0].end = child_res[0].start +
631 qcom->acpi_pdata->dwc3_core_base_size;
632
633 irq = platform_get_irq(pdev_irq, 0);
634 if (irq < 0) {
635 ret = irq;
636 goto out;
637 }
638 child_res[1].flags = IORESOURCE_IRQ;
639 child_res[1].start = child_res[1].end = irq;
640
641 ret = platform_device_add_resources(qcom->dwc3, child_res, 2);
642 if (ret) {
643 dev_err(&pdev->dev, "failed to add resources\n");
644 goto out;
645 }
646
647 ret = platform_device_add_properties(qcom->dwc3,
648 dwc3_qcom_acpi_properties);
649 if (ret < 0) {
650 dev_err(&pdev->dev, "failed to add properties\n");
651 goto out;
652 }
653
654 ret = platform_device_add(qcom->dwc3);
655 if (ret) {
656 dev_err(&pdev->dev, "failed to add device\n");
657 goto out;
658 }
659 kfree(child_res);
660 return 0;
661
662 out:
663 platform_device_put(qcom->dwc3);
664 kfree(child_res);
665 return ret;
666 }
667
dwc3_qcom_of_register_core(struct platform_device * pdev)668 static int dwc3_qcom_of_register_core(struct platform_device *pdev)
669 {
670 struct dwc3_qcom *qcom = platform_get_drvdata(pdev);
671 struct device_node *np = pdev->dev.of_node, *dwc3_np;
672 struct device *dev = &pdev->dev;
673 int ret;
674
675 dwc3_np = of_get_child_by_name(np, "dwc3");
676 if (!dwc3_np) {
677 dev_err(dev, "failed to find dwc3 core child\n");
678 return -ENODEV;
679 }
680
681 ret = of_platform_populate(np, NULL, NULL, dev);
682 if (ret) {
683 dev_err(dev, "failed to register dwc3 core - %d\n", ret);
684 goto node_put;
685 }
686
687 qcom->dwc3 = of_find_device_by_node(dwc3_np);
688 if (!qcom->dwc3) {
689 ret = -ENODEV;
690 dev_err(dev, "failed to get dwc3 platform device\n");
691 }
692
693 node_put:
694 of_node_put(dwc3_np);
695
696 return ret;
697 }
698
699 static struct platform_device *
dwc3_qcom_create_urs_usb_platdev(struct device * dev)700 dwc3_qcom_create_urs_usb_platdev(struct device *dev)
701 {
702 struct fwnode_handle *fwh;
703 struct acpi_device *adev;
704 char name[8];
705 int ret;
706 int id;
707
708 /* Figure out device id */
709 ret = sscanf(fwnode_get_name(dev->fwnode), "URS%d", &id);
710 if (!ret)
711 return NULL;
712
713 /* Find the child using name */
714 snprintf(name, sizeof(name), "USB%d", id);
715 fwh = fwnode_get_named_child_node(dev->fwnode, name);
716 if (!fwh)
717 return NULL;
718
719 adev = to_acpi_device_node(fwh);
720 if (!adev)
721 return NULL;
722
723 return acpi_create_platform_device(adev, NULL);
724 }
725
dwc3_qcom_probe(struct platform_device * pdev)726 static int dwc3_qcom_probe(struct platform_device *pdev)
727 {
728 struct device_node *np = pdev->dev.of_node;
729 struct device *dev = &pdev->dev;
730 struct dwc3_qcom *qcom;
731 struct resource *res, *parent_res = NULL;
732 int ret, i;
733 bool ignore_pipe_clk;
734
735 qcom = devm_kzalloc(&pdev->dev, sizeof(*qcom), GFP_KERNEL);
736 if (!qcom)
737 return -ENOMEM;
738
739 platform_set_drvdata(pdev, qcom);
740 qcom->dev = &pdev->dev;
741
742 if (has_acpi_companion(dev)) {
743 qcom->acpi_pdata = acpi_device_get_match_data(dev);
744 if (!qcom->acpi_pdata) {
745 dev_err(&pdev->dev, "no supporting ACPI device data\n");
746 return -EINVAL;
747 }
748 }
749
750 qcom->resets = devm_reset_control_array_get_optional_exclusive(dev);
751 if (IS_ERR(qcom->resets)) {
752 ret = PTR_ERR(qcom->resets);
753 dev_err(&pdev->dev, "failed to get resets, err=%d\n", ret);
754 return ret;
755 }
756
757 ret = reset_control_assert(qcom->resets);
758 if (ret) {
759 dev_err(&pdev->dev, "failed to assert resets, err=%d\n", ret);
760 return ret;
761 }
762
763 usleep_range(10, 1000);
764
765 ret = reset_control_deassert(qcom->resets);
766 if (ret) {
767 dev_err(&pdev->dev, "failed to deassert resets, err=%d\n", ret);
768 goto reset_assert;
769 }
770
771 ret = dwc3_qcom_clk_init(qcom, of_clk_get_parent_count(np));
772 if (ret) {
773 dev_err(dev, "failed to get clocks\n");
774 goto reset_assert;
775 }
776
777 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
778
779 if (np) {
780 parent_res = res;
781 } else {
782 parent_res = kmemdup(res, sizeof(struct resource), GFP_KERNEL);
783 if (!parent_res)
784 return -ENOMEM;
785
786 parent_res->start = res->start +
787 qcom->acpi_pdata->qscratch_base_offset;
788 parent_res->end = parent_res->start +
789 qcom->acpi_pdata->qscratch_base_size;
790
791 if (qcom->acpi_pdata->is_urs) {
792 qcom->urs_usb = dwc3_qcom_create_urs_usb_platdev(dev);
793 if (IS_ERR_OR_NULL(qcom->urs_usb)) {
794 dev_err(dev, "failed to create URS USB platdev\n");
795 if (!qcom->urs_usb)
796 return -ENODEV;
797 else
798 return PTR_ERR(qcom->urs_usb);
799 }
800 }
801 }
802
803 qcom->qscratch_base = devm_ioremap_resource(dev, parent_res);
804 if (IS_ERR(qcom->qscratch_base)) {
805 dev_err(dev, "failed to map qscratch, err=%d\n", ret);
806 ret = PTR_ERR(qcom->qscratch_base);
807 goto clk_disable;
808 }
809
810 ret = dwc3_qcom_setup_irq(pdev);
811 if (ret) {
812 dev_err(dev, "failed to setup IRQs, err=%d\n", ret);
813 goto clk_disable;
814 }
815
816 /*
817 * Disable pipe_clk requirement if specified. Used when dwc3
818 * operates without SSPHY and only HS/FS/LS modes are supported.
819 */
820 ignore_pipe_clk = device_property_read_bool(dev,
821 "qcom,select-utmi-as-pipe-clk");
822 if (ignore_pipe_clk)
823 dwc3_qcom_select_utmi_clk(qcom);
824
825 if (np)
826 ret = dwc3_qcom_of_register_core(pdev);
827 else
828 ret = dwc3_qcom_acpi_register_core(pdev);
829
830 if (ret) {
831 dev_err(dev, "failed to register DWC3 Core, err=%d\n", ret);
832 goto depopulate;
833 }
834
835 ret = dwc3_qcom_interconnect_init(qcom);
836 if (ret)
837 goto depopulate;
838
839 qcom->mode = usb_get_dr_mode(&qcom->dwc3->dev);
840
841 /* enable vbus override for device mode */
842 if (qcom->mode != USB_DR_MODE_HOST)
843 dwc3_qcom_vbus_override_enable(qcom, true);
844
845 /* register extcon to override sw_vbus on Vbus change later */
846 ret = dwc3_qcom_register_extcon(qcom);
847 if (ret)
848 goto interconnect_exit;
849
850 device_init_wakeup(&pdev->dev, 1);
851 qcom->is_suspended = false;
852 pm_runtime_set_active(dev);
853 pm_runtime_enable(dev);
854 pm_runtime_forbid(dev);
855
856 return 0;
857
858 interconnect_exit:
859 dwc3_qcom_interconnect_exit(qcom);
860 depopulate:
861 if (np)
862 of_platform_depopulate(&pdev->dev);
863 else
864 platform_device_put(pdev);
865 clk_disable:
866 for (i = qcom->num_clocks - 1; i >= 0; i--) {
867 clk_disable_unprepare(qcom->clks[i]);
868 clk_put(qcom->clks[i]);
869 }
870 reset_assert:
871 reset_control_assert(qcom->resets);
872
873 return ret;
874 }
875
dwc3_qcom_remove(struct platform_device * pdev)876 static int dwc3_qcom_remove(struct platform_device *pdev)
877 {
878 struct dwc3_qcom *qcom = platform_get_drvdata(pdev);
879 struct device *dev = &pdev->dev;
880 int i;
881
882 of_platform_depopulate(dev);
883
884 for (i = qcom->num_clocks - 1; i >= 0; i--) {
885 clk_disable_unprepare(qcom->clks[i]);
886 clk_put(qcom->clks[i]);
887 }
888 qcom->num_clocks = 0;
889
890 dwc3_qcom_interconnect_exit(qcom);
891 reset_control_assert(qcom->resets);
892
893 pm_runtime_allow(dev);
894 pm_runtime_disable(dev);
895
896 return 0;
897 }
898
dwc3_qcom_pm_suspend(struct device * dev)899 static int __maybe_unused dwc3_qcom_pm_suspend(struct device *dev)
900 {
901 struct dwc3_qcom *qcom = dev_get_drvdata(dev);
902 int ret = 0;
903
904 ret = dwc3_qcom_suspend(qcom);
905 if (!ret)
906 qcom->pm_suspended = true;
907
908 return ret;
909 }
910
dwc3_qcom_pm_resume(struct device * dev)911 static int __maybe_unused dwc3_qcom_pm_resume(struct device *dev)
912 {
913 struct dwc3_qcom *qcom = dev_get_drvdata(dev);
914 int ret;
915
916 ret = dwc3_qcom_resume(qcom);
917 if (!ret)
918 qcom->pm_suspended = false;
919
920 return ret;
921 }
922
dwc3_qcom_runtime_suspend(struct device * dev)923 static int __maybe_unused dwc3_qcom_runtime_suspend(struct device *dev)
924 {
925 struct dwc3_qcom *qcom = dev_get_drvdata(dev);
926
927 return dwc3_qcom_suspend(qcom);
928 }
929
dwc3_qcom_runtime_resume(struct device * dev)930 static int __maybe_unused dwc3_qcom_runtime_resume(struct device *dev)
931 {
932 struct dwc3_qcom *qcom = dev_get_drvdata(dev);
933
934 return dwc3_qcom_resume(qcom);
935 }
936
937 static const struct dev_pm_ops dwc3_qcom_dev_pm_ops = {
938 SET_SYSTEM_SLEEP_PM_OPS(dwc3_qcom_pm_suspend, dwc3_qcom_pm_resume)
939 SET_RUNTIME_PM_OPS(dwc3_qcom_runtime_suspend, dwc3_qcom_runtime_resume,
940 NULL)
941 };
942
943 static const struct of_device_id dwc3_qcom_of_match[] = {
944 { .compatible = "qcom,dwc3" },
945 { .compatible = "qcom,msm8996-dwc3" },
946 { .compatible = "qcom,msm8998-dwc3" },
947 { .compatible = "qcom,sdm845-dwc3" },
948 { }
949 };
950 MODULE_DEVICE_TABLE(of, dwc3_qcom_of_match);
951
952 #ifdef CONFIG_ACPI
953 static const struct dwc3_acpi_pdata sdm845_acpi_pdata = {
954 .qscratch_base_offset = SDM845_QSCRATCH_BASE_OFFSET,
955 .qscratch_base_size = SDM845_QSCRATCH_SIZE,
956 .dwc3_core_base_size = SDM845_DWC3_CORE_SIZE,
957 .hs_phy_irq_index = 1,
958 .dp_hs_phy_irq_index = 4,
959 .dm_hs_phy_irq_index = 3,
960 .ss_phy_irq_index = 2
961 };
962
963 static const struct dwc3_acpi_pdata sdm845_acpi_urs_pdata = {
964 .qscratch_base_offset = SDM845_QSCRATCH_BASE_OFFSET,
965 .qscratch_base_size = SDM845_QSCRATCH_SIZE,
966 .dwc3_core_base_size = SDM845_DWC3_CORE_SIZE,
967 .hs_phy_irq_index = 1,
968 .dp_hs_phy_irq_index = 4,
969 .dm_hs_phy_irq_index = 3,
970 .ss_phy_irq_index = 2,
971 .is_urs = true,
972 };
973
974 static const struct acpi_device_id dwc3_qcom_acpi_match[] = {
975 { "QCOM2430", (unsigned long)&sdm845_acpi_pdata },
976 { "QCOM0304", (unsigned long)&sdm845_acpi_urs_pdata },
977 { "QCOM0497", (unsigned long)&sdm845_acpi_urs_pdata },
978 { "QCOM04A6", (unsigned long)&sdm845_acpi_pdata },
979 { },
980 };
981 MODULE_DEVICE_TABLE(acpi, dwc3_qcom_acpi_match);
982 #endif
983
984 static struct platform_driver dwc3_qcom_driver = {
985 .probe = dwc3_qcom_probe,
986 .remove = dwc3_qcom_remove,
987 .driver = {
988 .name = "dwc3-qcom",
989 .pm = &dwc3_qcom_dev_pm_ops,
990 .of_match_table = dwc3_qcom_of_match,
991 .acpi_match_table = ACPI_PTR(dwc3_qcom_acpi_match),
992 },
993 };
994
995 module_platform_driver(dwc3_qcom_driver);
996
997 MODULE_LICENSE("GPL v2");
998 MODULE_DESCRIPTION("DesignWare DWC3 QCOM Glue Driver");
999