1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2017, The Linux Foundation. All rights reserved. 4 */ 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/qcom,gcc-ipq8074.h> 8 9/ { 10 model = "Qualcomm Technologies, Inc. IPQ8074"; 11 compatible = "qcom,ipq8074"; 12 13 clocks { 14 sleep_clk: sleep_clk { 15 compatible = "fixed-clock"; 16 clock-frequency = <32768>; 17 #clock-cells = <0>; 18 }; 19 20 xo: xo { 21 compatible = "fixed-clock"; 22 clock-frequency = <19200000>; 23 #clock-cells = <0>; 24 }; 25 }; 26 27 cpus { 28 #address-cells = <0x1>; 29 #size-cells = <0x0>; 30 31 CPU0: cpu@0 { 32 device_type = "cpu"; 33 compatible = "arm,cortex-a53"; 34 reg = <0x0>; 35 next-level-cache = <&L2_0>; 36 enable-method = "psci"; 37 }; 38 39 CPU1: cpu@1 { 40 device_type = "cpu"; 41 compatible = "arm,cortex-a53"; 42 enable-method = "psci"; 43 reg = <0x1>; 44 next-level-cache = <&L2_0>; 45 }; 46 47 CPU2: cpu@2 { 48 device_type = "cpu"; 49 compatible = "arm,cortex-a53"; 50 enable-method = "psci"; 51 reg = <0x2>; 52 next-level-cache = <&L2_0>; 53 }; 54 55 CPU3: cpu@3 { 56 device_type = "cpu"; 57 compatible = "arm,cortex-a53"; 58 enable-method = "psci"; 59 reg = <0x3>; 60 next-level-cache = <&L2_0>; 61 }; 62 63 L2_0: l2-cache { 64 compatible = "cache"; 65 cache-level = <0x2>; 66 }; 67 }; 68 69 pmu { 70 compatible = "arm,cortex-a53-pmu"; 71 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 72 }; 73 74 psci { 75 compatible = "arm,psci-1.0"; 76 method = "smc"; 77 }; 78 79 soc: soc { 80 #address-cells = <0x1>; 81 #size-cells = <0x1>; 82 ranges = <0 0 0 0xffffffff>; 83 compatible = "simple-bus"; 84 85 ssphy_1: phy@58000 { 86 compatible = "qcom,ipq8074-qmp-usb3-phy"; 87 reg = <0x00058000 0x1c4>; 88 #clock-cells = <1>; 89 #address-cells = <1>; 90 #size-cells = <1>; 91 ranges; 92 93 clocks = <&gcc GCC_USB1_AUX_CLK>, 94 <&gcc GCC_USB1_PHY_CFG_AHB_CLK>, 95 <&xo>; 96 clock-names = "aux", "cfg_ahb", "ref"; 97 98 resets = <&gcc GCC_USB1_PHY_BCR>, 99 <&gcc GCC_USB3PHY_1_PHY_BCR>; 100 reset-names = "phy","common"; 101 status = "disabled"; 102 103 usb1_ssphy: lane@58200 { 104 reg = <0x00058200 0x130>, /* Tx */ 105 <0x00058400 0x200>, /* Rx */ 106 <0x00058800 0x1f8>, /* PCS */ 107 <0x00058600 0x044>; /* PCS misc*/ 108 #phy-cells = <0>; 109 clocks = <&gcc GCC_USB1_PIPE_CLK>; 110 clock-names = "pipe0"; 111 clock-output-names = "usb3phy_1_cc_pipe_clk"; 112 }; 113 }; 114 115 qusb_phy_1: phy@59000 { 116 compatible = "qcom,ipq8074-qusb2-phy"; 117 reg = <0x00059000 0x180>; 118 #phy-cells = <0>; 119 120 clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>, 121 <&xo>; 122 clock-names = "cfg_ahb", "ref"; 123 124 resets = <&gcc GCC_QUSB2_1_PHY_BCR>; 125 status = "disabled"; 126 }; 127 128 ssphy_0: phy@78000 { 129 compatible = "qcom,ipq8074-qmp-usb3-phy"; 130 reg = <0x00078000 0x1c4>; 131 #clock-cells = <1>; 132 #address-cells = <1>; 133 #size-cells = <1>; 134 ranges; 135 136 clocks = <&gcc GCC_USB0_AUX_CLK>, 137 <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, 138 <&xo>; 139 clock-names = "aux", "cfg_ahb", "ref"; 140 141 resets = <&gcc GCC_USB0_PHY_BCR>, 142 <&gcc GCC_USB3PHY_0_PHY_BCR>; 143 reset-names = "phy","common"; 144 status = "disabled"; 145 146 usb0_ssphy: lane@78200 { 147 reg = <0x00078200 0x130>, /* Tx */ 148 <0x00078400 0x200>, /* Rx */ 149 <0x00078800 0x1f8>, /* PCS */ 150 <0x00078600 0x044>; /* PCS misc*/ 151 #phy-cells = <0>; 152 clocks = <&gcc GCC_USB0_PIPE_CLK>; 153 clock-names = "pipe0"; 154 clock-output-names = "usb3phy_0_cc_pipe_clk"; 155 }; 156 }; 157 158 qusb_phy_0: phy@79000 { 159 compatible = "qcom,ipq8074-qusb2-phy"; 160 reg = <0x00079000 0x180>; 161 #phy-cells = <0>; 162 163 clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, 164 <&xo>; 165 clock-names = "cfg_ahb", "ref"; 166 167 resets = <&gcc GCC_QUSB2_0_PHY_BCR>; 168 }; 169 170 pcie_qmp0: phy@84000 { 171 compatible = "qcom,ipq8074-qmp-gen3-pcie-phy"; 172 reg = <0x00084000 0x1bc>; 173 #address-cells = <1>; 174 #size-cells = <1>; 175 ranges; 176 177 clocks = <&gcc GCC_PCIE0_AUX_CLK>, 178 <&gcc GCC_PCIE0_AHB_CLK>; 179 clock-names = "aux", "cfg_ahb"; 180 resets = <&gcc GCC_PCIE0_PHY_BCR>, 181 <&gcc GCC_PCIE0PHY_PHY_BCR>; 182 reset-names = "phy", 183 "common"; 184 status = "disabled"; 185 186 pcie_phy0: phy@84200 { 187 reg = <0x84200 0x16c>, 188 <0x84400 0x200>, 189 <0x84800 0x1f0>, 190 <0x84c00 0xf4>; 191 #phy-cells = <0>; 192 #clock-cells = <0>; 193 clocks = <&gcc GCC_PCIE0_PIPE_CLK>; 194 clock-names = "pipe0"; 195 clock-output-names = "pcie20_phy0_pipe_clk"; 196 }; 197 }; 198 199 pcie_qmp1: phy@8e000 { 200 compatible = "qcom,ipq8074-qmp-pcie-phy"; 201 reg = <0x0008e000 0x1c4>; 202 #address-cells = <1>; 203 #size-cells = <1>; 204 ranges; 205 206 clocks = <&gcc GCC_PCIE1_AUX_CLK>, 207 <&gcc GCC_PCIE1_AHB_CLK>; 208 clock-names = "aux", "cfg_ahb"; 209 resets = <&gcc GCC_PCIE1_PHY_BCR>, 210 <&gcc GCC_PCIE1PHY_PHY_BCR>; 211 reset-names = "phy", 212 "common"; 213 status = "disabled"; 214 215 pcie_phy1: phy@8e200 { 216 reg = <0x8e200 0x130>, 217 <0x8e400 0x200>, 218 <0x8e800 0x1f8>; 219 #phy-cells = <0>; 220 #clock-cells = <0>; 221 clocks = <&gcc GCC_PCIE1_PIPE_CLK>; 222 clock-names = "pipe0"; 223 clock-output-names = "pcie20_phy1_pipe_clk"; 224 }; 225 }; 226 227 tlmm: pinctrl@1000000 { 228 compatible = "qcom,ipq8074-pinctrl"; 229 reg = <0x01000000 0x300000>; 230 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 231 gpio-controller; 232 gpio-ranges = <&tlmm 0 0 70>; 233 #gpio-cells = <0x2>; 234 interrupt-controller; 235 #interrupt-cells = <0x2>; 236 237 serial_4_pins: serial4-pinmux { 238 pins = "gpio23", "gpio24"; 239 function = "blsp4_uart1"; 240 drive-strength = <8>; 241 bias-disable; 242 }; 243 244 i2c_0_pins: i2c-0-pinmux { 245 pins = "gpio42", "gpio43"; 246 function = "blsp1_i2c"; 247 drive-strength = <8>; 248 bias-disable; 249 }; 250 251 spi_0_pins: spi-0-pins { 252 pins = "gpio38", "gpio39", "gpio40", "gpio41"; 253 function = "blsp0_spi"; 254 drive-strength = <8>; 255 bias-disable; 256 }; 257 258 hsuart_pins: hsuart-pins { 259 pins = "gpio46", "gpio47", "gpio48", "gpio49"; 260 function = "blsp2_uart"; 261 drive-strength = <8>; 262 bias-disable; 263 }; 264 265 qpic_pins: qpic-pins { 266 pins = "gpio1", "gpio3", "gpio4", 267 "gpio5", "gpio6", "gpio7", 268 "gpio8", "gpio10", "gpio11", 269 "gpio12", "gpio13", "gpio14", 270 "gpio15", "gpio16", "gpio17"; 271 function = "qpic"; 272 drive-strength = <8>; 273 bias-disable; 274 }; 275 }; 276 277 gcc: gcc@1800000 { 278 compatible = "qcom,gcc-ipq8074"; 279 reg = <0x01800000 0x80000>; 280 #clock-cells = <0x1>; 281 #reset-cells = <0x1>; 282 }; 283 284 sdhc_1: sdhci@7824900 { 285 compatible = "qcom,sdhci-msm-v4"; 286 reg = <0x7824900 0x500>, <0x7824000 0x800>; 287 reg-names = "hc_mem", "core_mem"; 288 289 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 290 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 291 interrupt-names = "hc_irq", "pwr_irq"; 292 293 clocks = <&xo>, 294 <&gcc GCC_SDCC1_AHB_CLK>, 295 <&gcc GCC_SDCC1_APPS_CLK>; 296 clock-names = "xo", "iface", "core"; 297 max-frequency = <384000000>; 298 mmc-ddr-1_8v; 299 mmc-hs200-1_8v; 300 mmc-hs400-1_8v; 301 bus-width = <8>; 302 303 status = "disabled"; 304 }; 305 306 blsp_dma: dma@7884000 { 307 compatible = "qcom,bam-v1.7.0"; 308 reg = <0x07884000 0x2b000>; 309 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 310 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 311 clock-names = "bam_clk"; 312 #dma-cells = <1>; 313 qcom,ee = <0>; 314 }; 315 316 blsp1_uart1: serial@78af000 { 317 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 318 reg = <0x078af000 0x200>; 319 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 320 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, 321 <&gcc GCC_BLSP1_AHB_CLK>; 322 clock-names = "core", "iface"; 323 status = "disabled"; 324 }; 325 326 blsp1_uart3: serial@78b1000 { 327 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 328 reg = <0x078b1000 0x200>; 329 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; 330 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, 331 <&gcc GCC_BLSP1_AHB_CLK>; 332 clock-names = "core", "iface"; 333 dmas = <&blsp_dma 4>, 334 <&blsp_dma 5>; 335 dma-names = "tx", "rx"; 336 pinctrl-0 = <&hsuart_pins>; 337 pinctrl-names = "default"; 338 status = "disabled"; 339 }; 340 341 blsp1_uart5: serial@78b3000 { 342 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 343 reg = <0x078b3000 0x200>; 344 interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>; 345 clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>, 346 <&gcc GCC_BLSP1_AHB_CLK>; 347 clock-names = "core", "iface"; 348 pinctrl-0 = <&serial_4_pins>; 349 pinctrl-names = "default"; 350 status = "disabled"; 351 }; 352 353 blsp1_spi1: spi@78b5000 { 354 compatible = "qcom,spi-qup-v2.2.1"; 355 #address-cells = <1>; 356 #size-cells = <0>; 357 reg = <0x078b5000 0x600>; 358 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 359 spi-max-frequency = <50000000>; 360 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 361 <&gcc GCC_BLSP1_AHB_CLK>; 362 clock-names = "core", "iface"; 363 dmas = <&blsp_dma 12>, <&blsp_dma 13>; 364 dma-names = "tx", "rx"; 365 pinctrl-0 = <&spi_0_pins>; 366 pinctrl-names = "default"; 367 status = "disabled"; 368 }; 369 370 blsp1_i2c2: i2c@78b6000 { 371 compatible = "qcom,i2c-qup-v2.2.1"; 372 #address-cells = <1>; 373 #size-cells = <0>; 374 reg = <0x078b6000 0x600>; 375 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 376 clocks = <&gcc GCC_BLSP1_AHB_CLK>, 377 <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; 378 clock-names = "iface", "core"; 379 clock-frequency = <400000>; 380 dmas = <&blsp_dma 15>, <&blsp_dma 14>; 381 dma-names = "rx", "tx"; 382 pinctrl-0 = <&i2c_0_pins>; 383 pinctrl-names = "default"; 384 status = "disabled"; 385 }; 386 387 blsp1_i2c3: i2c@78b7000 { 388 compatible = "qcom,i2c-qup-v2.2.1"; 389 #address-cells = <1>; 390 #size-cells = <0>; 391 reg = <0x078b7000 0x600>; 392 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 393 clocks = <&gcc GCC_BLSP1_AHB_CLK>, 394 <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; 395 clock-names = "iface", "core"; 396 clock-frequency = <100000>; 397 dmas = <&blsp_dma 17>, <&blsp_dma 16>; 398 dma-names = "rx", "tx"; 399 status = "disabled"; 400 }; 401 402 qpic_bam: dma@7984000 { 403 compatible = "qcom,bam-v1.7.0"; 404 reg = <0x07984000 0x1a000>; 405 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 406 clocks = <&gcc GCC_QPIC_AHB_CLK>; 407 clock-names = "bam_clk"; 408 #dma-cells = <1>; 409 qcom,ee = <0>; 410 status = "disabled"; 411 }; 412 413 qpic_nand: nand-controller@79b0000 { 414 compatible = "qcom,ipq8074-nand"; 415 reg = <0x079b0000 0x10000>; 416 #address-cells = <1>; 417 #size-cells = <0>; 418 clocks = <&gcc GCC_QPIC_CLK>, 419 <&gcc GCC_QPIC_AHB_CLK>; 420 clock-names = "core", "aon"; 421 422 dmas = <&qpic_bam 0>, 423 <&qpic_bam 1>, 424 <&qpic_bam 2>; 425 dma-names = "tx", "rx", "cmd"; 426 pinctrl-0 = <&qpic_pins>; 427 pinctrl-names = "default"; 428 status = "disabled"; 429 }; 430 431 usb_0: usb@8af8800 { 432 compatible = "qcom,dwc3"; 433 reg = <0x08af8800 0x400>; 434 #address-cells = <1>; 435 #size-cells = <1>; 436 ranges; 437 438 clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>, 439 <&gcc GCC_USB0_MASTER_CLK>, 440 <&gcc GCC_USB0_SLEEP_CLK>, 441 <&gcc GCC_USB0_MOCK_UTMI_CLK>; 442 clock-names = "sys_noc_axi", 443 "master", 444 "sleep", 445 "mock_utmi"; 446 447 assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>, 448 <&gcc GCC_USB0_MASTER_CLK>, 449 <&gcc GCC_USB0_MOCK_UTMI_CLK>; 450 assigned-clock-rates = <133330000>, 451 <133330000>, 452 <19200000>; 453 454 resets = <&gcc GCC_USB0_BCR>; 455 status = "disabled"; 456 457 dwc_0: dwc3@8a00000 { 458 compatible = "snps,dwc3"; 459 reg = <0x8a00000 0xcd00>; 460 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 461 phys = <&qusb_phy_0>, <&usb0_ssphy>; 462 phy-names = "usb2-phy", "usb3-phy"; 463 tx-fifo-resize; 464 snps,is-utmi-l1-suspend; 465 snps,hird-threshold = /bits/ 8 <0x0>; 466 snps,dis_u2_susphy_quirk; 467 snps,dis_u3_susphy_quirk; 468 dr_mode = "host"; 469 }; 470 }; 471 472 usb_1: usb@8cf8800 { 473 compatible = "qcom,dwc3"; 474 reg = <0x08cf8800 0x400>; 475 #address-cells = <1>; 476 #size-cells = <1>; 477 ranges; 478 479 clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>, 480 <&gcc GCC_USB1_MASTER_CLK>, 481 <&gcc GCC_USB1_SLEEP_CLK>, 482 <&gcc GCC_USB1_MOCK_UTMI_CLK>; 483 clock-names = "sys_noc_axi", 484 "master", 485 "sleep", 486 "mock_utmi"; 487 488 assigned-clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>, 489 <&gcc GCC_USB1_MASTER_CLK>, 490 <&gcc GCC_USB1_MOCK_UTMI_CLK>; 491 assigned-clock-rates = <133330000>, 492 <133330000>, 493 <19200000>; 494 495 resets = <&gcc GCC_USB1_BCR>; 496 status = "disabled"; 497 498 dwc_1: dwc3@8c00000 { 499 compatible = "snps,dwc3"; 500 reg = <0x8c00000 0xcd00>; 501 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 502 phys = <&qusb_phy_1>, <&usb1_ssphy>; 503 phy-names = "usb2-phy", "usb3-phy"; 504 tx-fifo-resize; 505 snps,is-utmi-l1-suspend; 506 snps,hird-threshold = /bits/ 8 <0x0>; 507 snps,dis_u2_susphy_quirk; 508 snps,dis_u3_susphy_quirk; 509 dr_mode = "host"; 510 }; 511 }; 512 513 intc: interrupt-controller@b000000 { 514 compatible = "qcom,msm-qgic2"; 515 interrupt-controller; 516 #interrupt-cells = <0x3>; 517 reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>; 518 }; 519 520 timer { 521 compatible = "arm,armv8-timer"; 522 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 523 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 524 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 525 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 526 }; 527 528 watchdog: watchdog@b017000 { 529 compatible = "qcom,kpss-wdt"; 530 reg = <0xb017000 0x1000>; 531 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; 532 clocks = <&sleep_clk>; 533 timeout-sec = <30>; 534 }; 535 536 timer@b120000 { 537 #address-cells = <1>; 538 #size-cells = <1>; 539 ranges; 540 compatible = "arm,armv7-timer-mem"; 541 reg = <0x0b120000 0x1000>; 542 clock-frequency = <19200000>; 543 544 frame@b120000 { 545 frame-number = <0>; 546 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 547 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 548 reg = <0x0b121000 0x1000>, 549 <0x0b122000 0x1000>; 550 }; 551 552 frame@b123000 { 553 frame-number = <1>; 554 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 555 reg = <0x0b123000 0x1000>; 556 status = "disabled"; 557 }; 558 559 frame@b124000 { 560 frame-number = <2>; 561 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 562 reg = <0x0b124000 0x1000>; 563 status = "disabled"; 564 }; 565 566 frame@b125000 { 567 frame-number = <3>; 568 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 569 reg = <0x0b125000 0x1000>; 570 status = "disabled"; 571 }; 572 573 frame@b126000 { 574 frame-number = <4>; 575 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 576 reg = <0x0b126000 0x1000>; 577 status = "disabled"; 578 }; 579 580 frame@b127000 { 581 frame-number = <5>; 582 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 583 reg = <0x0b127000 0x1000>; 584 status = "disabled"; 585 }; 586 587 frame@b128000 { 588 frame-number = <6>; 589 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 590 reg = <0x0b128000 0x1000>; 591 status = "disabled"; 592 }; 593 }; 594 595 pcie1: pci@10000000 { 596 compatible = "qcom,pcie-ipq8074"; 597 reg = <0x10000000 0xf1d>, 598 <0x10000f20 0xa8>, 599 <0x00088000 0x2000>, 600 <0x10100000 0x1000>; 601 reg-names = "dbi", "elbi", "parf", "config"; 602 device_type = "pci"; 603 linux,pci-domain = <1>; 604 bus-range = <0x00 0xff>; 605 num-lanes = <1>; 606 #address-cells = <3>; 607 #size-cells = <2>; 608 609 phys = <&pcie_phy1>; 610 phy-names = "pciephy"; 611 612 ranges = <0x81000000 0x0 0x00000000 0x10200000 0x0 0x10000>, /* I/O */ 613 <0x82000000 0x0 0x10220000 0x10220000 0x0 0xfde0000>; /* MEM */ 614 615 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 616 interrupt-names = "msi"; 617 #interrupt-cells = <1>; 618 interrupt-map-mask = <0 0 0 0x7>; 619 interrupt-map = <0 0 0 1 &intc 0 142 620 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 621 <0 0 0 2 &intc 0 143 622 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 623 <0 0 0 3 &intc 0 144 624 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 625 <0 0 0 4 &intc 0 145 626 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 627 628 clocks = <&gcc GCC_SYS_NOC_PCIE1_AXI_CLK>, 629 <&gcc GCC_PCIE1_AXI_M_CLK>, 630 <&gcc GCC_PCIE1_AXI_S_CLK>, 631 <&gcc GCC_PCIE1_AHB_CLK>, 632 <&gcc GCC_PCIE1_AUX_CLK>; 633 clock-names = "iface", 634 "axi_m", 635 "axi_s", 636 "ahb", 637 "aux"; 638 resets = <&gcc GCC_PCIE1_PIPE_ARES>, 639 <&gcc GCC_PCIE1_SLEEP_ARES>, 640 <&gcc GCC_PCIE1_CORE_STICKY_ARES>, 641 <&gcc GCC_PCIE1_AXI_MASTER_ARES>, 642 <&gcc GCC_PCIE1_AXI_SLAVE_ARES>, 643 <&gcc GCC_PCIE1_AHB_ARES>, 644 <&gcc GCC_PCIE1_AXI_MASTER_STICKY_ARES>; 645 reset-names = "pipe", 646 "sleep", 647 "sticky", 648 "axi_m", 649 "axi_s", 650 "ahb", 651 "axi_m_sticky"; 652 status = "disabled"; 653 }; 654 655 pcie0: pci@20000000 { 656 compatible = "qcom,pcie-ipq8074-gen3"; 657 reg = <0x20000000 0xf1d>, 658 <0x20000f20 0xa8>, 659 <0x20001000 0x1000>, 660 <0x00080000 0x4000>, 661 <0x20100000 0x1000>; 662 reg-names = "dbi", "elbi", "atu", "parf", "config"; 663 device_type = "pci"; 664 linux,pci-domain = <0>; 665 bus-range = <0x00 0xff>; 666 num-lanes = <1>; 667 max-link-speed = <3>; 668 #address-cells = <3>; 669 #size-cells = <2>; 670 671 phys = <&pcie_phy0>; 672 phy-names = "pciephy"; 673 674 ranges = <0x81000000 0x0 0x00000000 0x20200000 0x0 0x10000>, /* I/O */ 675 <0x82000000 0x0 0x20220000 0x20220000 0x0 0xfde0000>; /* MEM */ 676 677 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 678 interrupt-names = "msi"; 679 #interrupt-cells = <1>; 680 interrupt-map-mask = <0 0 0 0x7>; 681 interrupt-map = <0 0 0 1 &intc 0 75 682 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 683 <0 0 0 2 &intc 0 78 684 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 685 <0 0 0 3 &intc 0 79 686 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 687 <0 0 0 4 &intc 0 83 688 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 689 690 clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>, 691 <&gcc GCC_PCIE0_AXI_M_CLK>, 692 <&gcc GCC_PCIE0_AXI_S_CLK>, 693 <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>, 694 <&gcc GCC_PCIE0_RCHNG_CLK>; 695 clock-names = "iface", 696 "axi_m", 697 "axi_s", 698 "axi_bridge", 699 "rchng"; 700 701 resets = <&gcc GCC_PCIE0_PIPE_ARES>, 702 <&gcc GCC_PCIE0_SLEEP_ARES>, 703 <&gcc GCC_PCIE0_CORE_STICKY_ARES>, 704 <&gcc GCC_PCIE0_AXI_MASTER_ARES>, 705 <&gcc GCC_PCIE0_AXI_SLAVE_ARES>, 706 <&gcc GCC_PCIE0_AHB_ARES>, 707 <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>, 708 <&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>; 709 reset-names = "pipe", 710 "sleep", 711 "sticky", 712 "axi_m", 713 "axi_s", 714 "ahb", 715 "axi_m_sticky", 716 "axi_s_sticky"; 717 status = "disabled"; 718 }; 719 }; 720}; 721