1// SPDX-License-Identifier: GPL-2.0 2/* 3 * SDM845 SoC device tree source 4 * 5 * Copyright (c) 2018, The Linux Foundation. All rights reserved. 6 */ 7 8#include <dt-bindings/clock/qcom,camcc-sdm845.h> 9#include <dt-bindings/clock/qcom,dispcc-sdm845.h> 10#include <dt-bindings/clock/qcom,gcc-sdm845.h> 11#include <dt-bindings/clock/qcom,gpucc-sdm845.h> 12#include <dt-bindings/clock/qcom,lpass-sdm845.h> 13#include <dt-bindings/clock/qcom,rpmh.h> 14#include <dt-bindings/clock/qcom,videocc-sdm845.h> 15#include <dt-bindings/interconnect/qcom,osm-l3.h> 16#include <dt-bindings/interconnect/qcom,sdm845.h> 17#include <dt-bindings/interrupt-controller/arm-gic.h> 18#include <dt-bindings/phy/phy-qcom-qusb2.h> 19#include <dt-bindings/power/qcom-rpmpd.h> 20#include <dt-bindings/reset/qcom,sdm845-aoss.h> 21#include <dt-bindings/reset/qcom,sdm845-pdc.h> 22#include <dt-bindings/soc/qcom,apr.h> 23#include <dt-bindings/soc/qcom,rpmh-rsc.h> 24#include <dt-bindings/clock/qcom,gcc-sdm845.h> 25#include <dt-bindings/thermal/thermal.h> 26 27/ { 28 interrupt-parent = <&intc>; 29 30 #address-cells = <2>; 31 #size-cells = <2>; 32 33 aliases { 34 i2c0 = &i2c0; 35 i2c1 = &i2c1; 36 i2c2 = &i2c2; 37 i2c3 = &i2c3; 38 i2c4 = &i2c4; 39 i2c5 = &i2c5; 40 i2c6 = &i2c6; 41 i2c7 = &i2c7; 42 i2c8 = &i2c8; 43 i2c9 = &i2c9; 44 i2c10 = &i2c10; 45 i2c11 = &i2c11; 46 i2c12 = &i2c12; 47 i2c13 = &i2c13; 48 i2c14 = &i2c14; 49 i2c15 = &i2c15; 50 spi0 = &spi0; 51 spi1 = &spi1; 52 spi2 = &spi2; 53 spi3 = &spi3; 54 spi4 = &spi4; 55 spi5 = &spi5; 56 spi6 = &spi6; 57 spi7 = &spi7; 58 spi8 = &spi8; 59 spi9 = &spi9; 60 spi10 = &spi10; 61 spi11 = &spi11; 62 spi12 = &spi12; 63 spi13 = &spi13; 64 spi14 = &spi14; 65 spi15 = &spi15; 66 }; 67 68 chosen { }; 69 70 memory@80000000 { 71 device_type = "memory"; 72 /* We expect the bootloader to fill in the size */ 73 reg = <0 0x80000000 0 0>; 74 }; 75 76 reserved-memory { 77 #address-cells = <2>; 78 #size-cells = <2>; 79 ranges; 80 81 hyp_mem: memory@85700000 { 82 reg = <0 0x85700000 0 0x600000>; 83 no-map; 84 }; 85 86 xbl_mem: memory@85e00000 { 87 reg = <0 0x85e00000 0 0x100000>; 88 no-map; 89 }; 90 91 aop_mem: memory@85fc0000 { 92 reg = <0 0x85fc0000 0 0x20000>; 93 no-map; 94 }; 95 96 aop_cmd_db_mem: memory@85fe0000 { 97 compatible = "qcom,cmd-db"; 98 reg = <0x0 0x85fe0000 0 0x20000>; 99 no-map; 100 }; 101 102 smem_mem: memory@86000000 { 103 reg = <0x0 0x86000000 0 0x200000>; 104 no-map; 105 }; 106 107 tz_mem: memory@86200000 { 108 reg = <0 0x86200000 0 0x2d00000>; 109 no-map; 110 }; 111 112 rmtfs_mem: memory@88f00000 { 113 compatible = "qcom,rmtfs-mem"; 114 reg = <0 0x88f00000 0 0x200000>; 115 no-map; 116 117 qcom,client-id = <1>; 118 qcom,vmid = <15>; 119 }; 120 121 qseecom_mem: memory@8ab00000 { 122 reg = <0 0x8ab00000 0 0x1400000>; 123 no-map; 124 }; 125 126 camera_mem: memory@8bf00000 { 127 reg = <0 0x8bf00000 0 0x500000>; 128 no-map; 129 }; 130 131 ipa_fw_mem: memory@8c400000 { 132 reg = <0 0x8c400000 0 0x10000>; 133 no-map; 134 }; 135 136 ipa_gsi_mem: memory@8c410000 { 137 reg = <0 0x8c410000 0 0x5000>; 138 no-map; 139 }; 140 141 gpu_mem: memory@8c415000 { 142 reg = <0 0x8c415000 0 0x2000>; 143 no-map; 144 }; 145 146 adsp_mem: memory@8c500000 { 147 reg = <0 0x8c500000 0 0x1a00000>; 148 no-map; 149 }; 150 151 wlan_msa_mem: memory@8df00000 { 152 reg = <0 0x8df00000 0 0x100000>; 153 no-map; 154 }; 155 156 mpss_region: memory@8e000000 { 157 reg = <0 0x8e000000 0 0x7800000>; 158 no-map; 159 }; 160 161 venus_mem: memory@95800000 { 162 reg = <0 0x95800000 0 0x500000>; 163 no-map; 164 }; 165 166 cdsp_mem: memory@95d00000 { 167 reg = <0 0x95d00000 0 0x800000>; 168 no-map; 169 }; 170 171 mba_region: memory@96500000 { 172 reg = <0 0x96500000 0 0x200000>; 173 no-map; 174 }; 175 176 slpi_mem: memory@96700000 { 177 reg = <0 0x96700000 0 0x1400000>; 178 no-map; 179 }; 180 181 spss_mem: memory@97b00000 { 182 reg = <0 0x97b00000 0 0x100000>; 183 no-map; 184 }; 185 }; 186 187 cpus { 188 #address-cells = <2>; 189 #size-cells = <0>; 190 191 CPU0: cpu@0 { 192 device_type = "cpu"; 193 compatible = "qcom,kryo385"; 194 reg = <0x0 0x0>; 195 enable-method = "psci"; 196 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 197 &LITTLE_CPU_SLEEP_1 198 &CLUSTER_SLEEP_0>; 199 capacity-dmips-mhz = <611>; 200 dynamic-power-coefficient = <154>; 201 qcom,freq-domain = <&cpufreq_hw 0>; 202 operating-points-v2 = <&cpu0_opp_table>; 203 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 204 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 205 #cooling-cells = <2>; 206 next-level-cache = <&L2_0>; 207 L2_0: l2-cache { 208 compatible = "cache"; 209 next-level-cache = <&L3_0>; 210 L3_0: l3-cache { 211 compatible = "cache"; 212 }; 213 }; 214 }; 215 216 CPU1: cpu@100 { 217 device_type = "cpu"; 218 compatible = "qcom,kryo385"; 219 reg = <0x0 0x100>; 220 enable-method = "psci"; 221 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 222 &LITTLE_CPU_SLEEP_1 223 &CLUSTER_SLEEP_0>; 224 capacity-dmips-mhz = <611>; 225 dynamic-power-coefficient = <154>; 226 qcom,freq-domain = <&cpufreq_hw 0>; 227 operating-points-v2 = <&cpu0_opp_table>; 228 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 229 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 230 #cooling-cells = <2>; 231 next-level-cache = <&L2_100>; 232 L2_100: l2-cache { 233 compatible = "cache"; 234 next-level-cache = <&L3_0>; 235 }; 236 }; 237 238 CPU2: cpu@200 { 239 device_type = "cpu"; 240 compatible = "qcom,kryo385"; 241 reg = <0x0 0x200>; 242 enable-method = "psci"; 243 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 244 &LITTLE_CPU_SLEEP_1 245 &CLUSTER_SLEEP_0>; 246 capacity-dmips-mhz = <611>; 247 dynamic-power-coefficient = <154>; 248 qcom,freq-domain = <&cpufreq_hw 0>; 249 operating-points-v2 = <&cpu0_opp_table>; 250 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 251 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 252 #cooling-cells = <2>; 253 next-level-cache = <&L2_200>; 254 L2_200: l2-cache { 255 compatible = "cache"; 256 next-level-cache = <&L3_0>; 257 }; 258 }; 259 260 CPU3: cpu@300 { 261 device_type = "cpu"; 262 compatible = "qcom,kryo385"; 263 reg = <0x0 0x300>; 264 enable-method = "psci"; 265 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 266 &LITTLE_CPU_SLEEP_1 267 &CLUSTER_SLEEP_0>; 268 capacity-dmips-mhz = <611>; 269 dynamic-power-coefficient = <154>; 270 qcom,freq-domain = <&cpufreq_hw 0>; 271 operating-points-v2 = <&cpu0_opp_table>; 272 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 273 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 274 #cooling-cells = <2>; 275 next-level-cache = <&L2_300>; 276 L2_300: l2-cache { 277 compatible = "cache"; 278 next-level-cache = <&L3_0>; 279 }; 280 }; 281 282 CPU4: cpu@400 { 283 device_type = "cpu"; 284 compatible = "qcom,kryo385"; 285 reg = <0x0 0x400>; 286 enable-method = "psci"; 287 capacity-dmips-mhz = <1024>; 288 cpu-idle-states = <&BIG_CPU_SLEEP_0 289 &BIG_CPU_SLEEP_1 290 &CLUSTER_SLEEP_0>; 291 dynamic-power-coefficient = <442>; 292 qcom,freq-domain = <&cpufreq_hw 1>; 293 operating-points-v2 = <&cpu4_opp_table>; 294 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 295 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 296 #cooling-cells = <2>; 297 next-level-cache = <&L2_400>; 298 L2_400: l2-cache { 299 compatible = "cache"; 300 next-level-cache = <&L3_0>; 301 }; 302 }; 303 304 CPU5: cpu@500 { 305 device_type = "cpu"; 306 compatible = "qcom,kryo385"; 307 reg = <0x0 0x500>; 308 enable-method = "psci"; 309 capacity-dmips-mhz = <1024>; 310 cpu-idle-states = <&BIG_CPU_SLEEP_0 311 &BIG_CPU_SLEEP_1 312 &CLUSTER_SLEEP_0>; 313 dynamic-power-coefficient = <442>; 314 qcom,freq-domain = <&cpufreq_hw 1>; 315 operating-points-v2 = <&cpu4_opp_table>; 316 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 317 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 318 #cooling-cells = <2>; 319 next-level-cache = <&L2_500>; 320 L2_500: l2-cache { 321 compatible = "cache"; 322 next-level-cache = <&L3_0>; 323 }; 324 }; 325 326 CPU6: cpu@600 { 327 device_type = "cpu"; 328 compatible = "qcom,kryo385"; 329 reg = <0x0 0x600>; 330 enable-method = "psci"; 331 capacity-dmips-mhz = <1024>; 332 cpu-idle-states = <&BIG_CPU_SLEEP_0 333 &BIG_CPU_SLEEP_1 334 &CLUSTER_SLEEP_0>; 335 dynamic-power-coefficient = <442>; 336 qcom,freq-domain = <&cpufreq_hw 1>; 337 operating-points-v2 = <&cpu4_opp_table>; 338 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 339 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 340 #cooling-cells = <2>; 341 next-level-cache = <&L2_600>; 342 L2_600: l2-cache { 343 compatible = "cache"; 344 next-level-cache = <&L3_0>; 345 }; 346 }; 347 348 CPU7: cpu@700 { 349 device_type = "cpu"; 350 compatible = "qcom,kryo385"; 351 reg = <0x0 0x700>; 352 enable-method = "psci"; 353 capacity-dmips-mhz = <1024>; 354 cpu-idle-states = <&BIG_CPU_SLEEP_0 355 &BIG_CPU_SLEEP_1 356 &CLUSTER_SLEEP_0>; 357 dynamic-power-coefficient = <442>; 358 qcom,freq-domain = <&cpufreq_hw 1>; 359 operating-points-v2 = <&cpu4_opp_table>; 360 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 361 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 362 #cooling-cells = <2>; 363 next-level-cache = <&L2_700>; 364 L2_700: l2-cache { 365 compatible = "cache"; 366 next-level-cache = <&L3_0>; 367 }; 368 }; 369 370 cpu-map { 371 cluster0 { 372 core0 { 373 cpu = <&CPU0>; 374 }; 375 376 core1 { 377 cpu = <&CPU1>; 378 }; 379 380 core2 { 381 cpu = <&CPU2>; 382 }; 383 384 core3 { 385 cpu = <&CPU3>; 386 }; 387 388 core4 { 389 cpu = <&CPU4>; 390 }; 391 392 core5 { 393 cpu = <&CPU5>; 394 }; 395 396 core6 { 397 cpu = <&CPU6>; 398 }; 399 400 core7 { 401 cpu = <&CPU7>; 402 }; 403 }; 404 }; 405 406 idle-states { 407 entry-method = "psci"; 408 409 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 410 compatible = "arm,idle-state"; 411 idle-state-name = "little-power-down"; 412 arm,psci-suspend-param = <0x40000003>; 413 entry-latency-us = <350>; 414 exit-latency-us = <461>; 415 min-residency-us = <1890>; 416 local-timer-stop; 417 }; 418 419 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 420 compatible = "arm,idle-state"; 421 idle-state-name = "little-rail-power-down"; 422 arm,psci-suspend-param = <0x40000004>; 423 entry-latency-us = <360>; 424 exit-latency-us = <531>; 425 min-residency-us = <3934>; 426 local-timer-stop; 427 }; 428 429 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 430 compatible = "arm,idle-state"; 431 idle-state-name = "big-power-down"; 432 arm,psci-suspend-param = <0x40000003>; 433 entry-latency-us = <264>; 434 exit-latency-us = <621>; 435 min-residency-us = <952>; 436 local-timer-stop; 437 }; 438 439 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 440 compatible = "arm,idle-state"; 441 idle-state-name = "big-rail-power-down"; 442 arm,psci-suspend-param = <0x40000004>; 443 entry-latency-us = <702>; 444 exit-latency-us = <1061>; 445 min-residency-us = <4488>; 446 local-timer-stop; 447 }; 448 449 CLUSTER_SLEEP_0: cluster-sleep-0 { 450 compatible = "arm,idle-state"; 451 idle-state-name = "cluster-power-down"; 452 arm,psci-suspend-param = <0x400000F4>; 453 entry-latency-us = <3263>; 454 exit-latency-us = <6562>; 455 min-residency-us = <9987>; 456 local-timer-stop; 457 }; 458 }; 459 }; 460 461 cpu0_opp_table: cpu0_opp_table { 462 compatible = "operating-points-v2"; 463 opp-shared; 464 465 cpu0_opp1: opp-300000000 { 466 opp-hz = /bits/ 64 <300000000>; 467 opp-peak-kBps = <800000 4800000>; 468 }; 469 470 cpu0_opp2: opp-403200000 { 471 opp-hz = /bits/ 64 <403200000>; 472 opp-peak-kBps = <800000 4800000>; 473 }; 474 475 cpu0_opp3: opp-480000000 { 476 opp-hz = /bits/ 64 <480000000>; 477 opp-peak-kBps = <800000 6451200>; 478 }; 479 480 cpu0_opp4: opp-576000000 { 481 opp-hz = /bits/ 64 <576000000>; 482 opp-peak-kBps = <800000 6451200>; 483 }; 484 485 cpu0_opp5: opp-652800000 { 486 opp-hz = /bits/ 64 <652800000>; 487 opp-peak-kBps = <800000 7680000>; 488 }; 489 490 cpu0_opp6: opp-748800000 { 491 opp-hz = /bits/ 64 <748800000>; 492 opp-peak-kBps = <1804000 9216000>; 493 }; 494 495 cpu0_opp7: opp-825600000 { 496 opp-hz = /bits/ 64 <825600000>; 497 opp-peak-kBps = <1804000 9216000>; 498 }; 499 500 cpu0_opp8: opp-902400000 { 501 opp-hz = /bits/ 64 <902400000>; 502 opp-peak-kBps = <1804000 10444800>; 503 }; 504 505 cpu0_opp9: opp-979200000 { 506 opp-hz = /bits/ 64 <979200000>; 507 opp-peak-kBps = <1804000 11980800>; 508 }; 509 510 cpu0_opp10: opp-1056000000 { 511 opp-hz = /bits/ 64 <1056000000>; 512 opp-peak-kBps = <1804000 11980800>; 513 }; 514 515 cpu0_opp11: opp-1132800000 { 516 opp-hz = /bits/ 64 <1132800000>; 517 opp-peak-kBps = <2188000 13516800>; 518 }; 519 520 cpu0_opp12: opp-1228800000 { 521 opp-hz = /bits/ 64 <1228800000>; 522 opp-peak-kBps = <2188000 15052800>; 523 }; 524 525 cpu0_opp13: opp-1324800000 { 526 opp-hz = /bits/ 64 <1324800000>; 527 opp-peak-kBps = <2188000 16588800>; 528 }; 529 530 cpu0_opp14: opp-1420800000 { 531 opp-hz = /bits/ 64 <1420800000>; 532 opp-peak-kBps = <3072000 18124800>; 533 }; 534 535 cpu0_opp15: opp-1516800000 { 536 opp-hz = /bits/ 64 <1516800000>; 537 opp-peak-kBps = <3072000 19353600>; 538 }; 539 540 cpu0_opp16: opp-1612800000 { 541 opp-hz = /bits/ 64 <1612800000>; 542 opp-peak-kBps = <4068000 19353600>; 543 }; 544 545 cpu0_opp17: opp-1689600000 { 546 opp-hz = /bits/ 64 <1689600000>; 547 opp-peak-kBps = <4068000 20889600>; 548 }; 549 550 cpu0_opp18: opp-1766400000 { 551 opp-hz = /bits/ 64 <1766400000>; 552 opp-peak-kBps = <4068000 22425600>; 553 }; 554 }; 555 556 cpu4_opp_table: cpu4_opp_table { 557 compatible = "operating-points-v2"; 558 opp-shared; 559 560 cpu4_opp1: opp-300000000 { 561 opp-hz = /bits/ 64 <300000000>; 562 opp-peak-kBps = <800000 4800000>; 563 }; 564 565 cpu4_opp2: opp-403200000 { 566 opp-hz = /bits/ 64 <403200000>; 567 opp-peak-kBps = <800000 4800000>; 568 }; 569 570 cpu4_opp3: opp-480000000 { 571 opp-hz = /bits/ 64 <480000000>; 572 opp-peak-kBps = <1804000 4800000>; 573 }; 574 575 cpu4_opp4: opp-576000000 { 576 opp-hz = /bits/ 64 <576000000>; 577 opp-peak-kBps = <1804000 4800000>; 578 }; 579 580 cpu4_opp5: opp-652800000 { 581 opp-hz = /bits/ 64 <652800000>; 582 opp-peak-kBps = <1804000 4800000>; 583 }; 584 585 cpu4_opp6: opp-748800000 { 586 opp-hz = /bits/ 64 <748800000>; 587 opp-peak-kBps = <1804000 4800000>; 588 }; 589 590 cpu4_opp7: opp-825600000 { 591 opp-hz = /bits/ 64 <825600000>; 592 opp-peak-kBps = <2188000 9216000>; 593 }; 594 595 cpu4_opp8: opp-902400000 { 596 opp-hz = /bits/ 64 <902400000>; 597 opp-peak-kBps = <2188000 9216000>; 598 }; 599 600 cpu4_opp9: opp-979200000 { 601 opp-hz = /bits/ 64 <979200000>; 602 opp-peak-kBps = <2188000 9216000>; 603 }; 604 605 cpu4_opp10: opp-1056000000 { 606 opp-hz = /bits/ 64 <1056000000>; 607 opp-peak-kBps = <3072000 9216000>; 608 }; 609 610 cpu4_opp11: opp-1132800000 { 611 opp-hz = /bits/ 64 <1132800000>; 612 opp-peak-kBps = <3072000 11980800>; 613 }; 614 615 cpu4_opp12: opp-1209600000 { 616 opp-hz = /bits/ 64 <1209600000>; 617 opp-peak-kBps = <4068000 11980800>; 618 }; 619 620 cpu4_opp13: opp-1286400000 { 621 opp-hz = /bits/ 64 <1286400000>; 622 opp-peak-kBps = <4068000 11980800>; 623 }; 624 625 cpu4_opp14: opp-1363200000 { 626 opp-hz = /bits/ 64 <1363200000>; 627 opp-peak-kBps = <4068000 15052800>; 628 }; 629 630 cpu4_opp15: opp-1459200000 { 631 opp-hz = /bits/ 64 <1459200000>; 632 opp-peak-kBps = <4068000 15052800>; 633 }; 634 635 cpu4_opp16: opp-1536000000 { 636 opp-hz = /bits/ 64 <1536000000>; 637 opp-peak-kBps = <5412000 15052800>; 638 }; 639 640 cpu4_opp17: opp-1612800000 { 641 opp-hz = /bits/ 64 <1612800000>; 642 opp-peak-kBps = <5412000 15052800>; 643 }; 644 645 cpu4_opp18: opp-1689600000 { 646 opp-hz = /bits/ 64 <1689600000>; 647 opp-peak-kBps = <5412000 19353600>; 648 }; 649 650 cpu4_opp19: opp-1766400000 { 651 opp-hz = /bits/ 64 <1766400000>; 652 opp-peak-kBps = <6220000 19353600>; 653 }; 654 655 cpu4_opp20: opp-1843200000 { 656 opp-hz = /bits/ 64 <1843200000>; 657 opp-peak-kBps = <6220000 19353600>; 658 }; 659 660 cpu4_opp21: opp-1920000000 { 661 opp-hz = /bits/ 64 <1920000000>; 662 opp-peak-kBps = <7216000 19353600>; 663 }; 664 665 cpu4_opp22: opp-1996800000 { 666 opp-hz = /bits/ 64 <1996800000>; 667 opp-peak-kBps = <7216000 20889600>; 668 }; 669 670 cpu4_opp23: opp-2092800000 { 671 opp-hz = /bits/ 64 <2092800000>; 672 opp-peak-kBps = <7216000 20889600>; 673 }; 674 675 cpu4_opp24: opp-2169600000 { 676 opp-hz = /bits/ 64 <2169600000>; 677 opp-peak-kBps = <7216000 20889600>; 678 }; 679 680 cpu4_opp25: opp-2246400000 { 681 opp-hz = /bits/ 64 <2246400000>; 682 opp-peak-kBps = <7216000 20889600>; 683 }; 684 685 cpu4_opp26: opp-2323200000 { 686 opp-hz = /bits/ 64 <2323200000>; 687 opp-peak-kBps = <7216000 20889600>; 688 }; 689 690 cpu4_opp27: opp-2400000000 { 691 opp-hz = /bits/ 64 <2400000000>; 692 opp-peak-kBps = <7216000 22425600>; 693 }; 694 695 cpu4_opp28: opp-2476800000 { 696 opp-hz = /bits/ 64 <2476800000>; 697 opp-peak-kBps = <7216000 22425600>; 698 }; 699 700 cpu4_opp29: opp-2553600000 { 701 opp-hz = /bits/ 64 <2553600000>; 702 opp-peak-kBps = <7216000 22425600>; 703 }; 704 705 cpu4_opp30: opp-2649600000 { 706 opp-hz = /bits/ 64 <2649600000>; 707 opp-peak-kBps = <7216000 22425600>; 708 }; 709 710 cpu4_opp31: opp-2745600000 { 711 opp-hz = /bits/ 64 <2745600000>; 712 opp-peak-kBps = <7216000 25497600>; 713 }; 714 715 cpu4_opp32: opp-2803200000 { 716 opp-hz = /bits/ 64 <2803200000>; 717 opp-peak-kBps = <7216000 25497600>; 718 }; 719 }; 720 721 pmu { 722 compatible = "arm,armv8-pmuv3"; 723 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; 724 }; 725 726 timer { 727 compatible = "arm,armv8-timer"; 728 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 729 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 730 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 731 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 732 }; 733 734 clocks { 735 xo_board: xo-board { 736 compatible = "fixed-clock"; 737 #clock-cells = <0>; 738 clock-frequency = <38400000>; 739 clock-output-names = "xo_board"; 740 }; 741 742 sleep_clk: sleep-clk { 743 compatible = "fixed-clock"; 744 #clock-cells = <0>; 745 clock-frequency = <32764>; 746 }; 747 }; 748 749 firmware { 750 scm { 751 compatible = "qcom,scm-sdm845", "qcom,scm"; 752 }; 753 }; 754 755 adsp_pas: remoteproc-adsp { 756 compatible = "qcom,sdm845-adsp-pas"; 757 758 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 759 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 760 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 761 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 762 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 763 interrupt-names = "wdog", "fatal", "ready", 764 "handover", "stop-ack"; 765 766 clocks = <&rpmhcc RPMH_CXO_CLK>; 767 clock-names = "xo"; 768 769 memory-region = <&adsp_mem>; 770 771 qcom,smem-states = <&adsp_smp2p_out 0>; 772 qcom,smem-state-names = "stop"; 773 774 status = "disabled"; 775 776 glink-edge { 777 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 778 label = "lpass"; 779 qcom,remote-pid = <2>; 780 mboxes = <&apss_shared 8>; 781 782 apr { 783 compatible = "qcom,apr-v2"; 784 qcom,glink-channels = "apr_audio_svc"; 785 qcom,apr-domain = <APR_DOMAIN_ADSP>; 786 #address-cells = <1>; 787 #size-cells = <0>; 788 qcom,intents = <512 20>; 789 790 apr-service@3 { 791 reg = <APR_SVC_ADSP_CORE>; 792 compatible = "qcom,q6core"; 793 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 794 }; 795 796 q6afe: apr-service@4 { 797 compatible = "qcom,q6afe"; 798 reg = <APR_SVC_AFE>; 799 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 800 q6afedai: dais { 801 compatible = "qcom,q6afe-dais"; 802 #address-cells = <1>; 803 #size-cells = <0>; 804 #sound-dai-cells = <1>; 805 }; 806 }; 807 808 q6asm: apr-service@7 { 809 compatible = "qcom,q6asm"; 810 reg = <APR_SVC_ASM>; 811 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 812 q6asmdai: dais { 813 compatible = "qcom,q6asm-dais"; 814 #address-cells = <1>; 815 #size-cells = <0>; 816 #sound-dai-cells = <1>; 817 iommus = <&apps_smmu 0x1821 0x0>; 818 }; 819 }; 820 821 q6adm: apr-service@8 { 822 compatible = "qcom,q6adm"; 823 reg = <APR_SVC_ADM>; 824 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 825 q6routing: routing { 826 compatible = "qcom,q6adm-routing"; 827 #sound-dai-cells = <0>; 828 }; 829 }; 830 }; 831 832 fastrpc { 833 compatible = "qcom,fastrpc"; 834 qcom,glink-channels = "fastrpcglink-apps-dsp"; 835 label = "adsp"; 836 #address-cells = <1>; 837 #size-cells = <0>; 838 839 compute-cb@3 { 840 compatible = "qcom,fastrpc-compute-cb"; 841 reg = <3>; 842 iommus = <&apps_smmu 0x1823 0x0>; 843 }; 844 845 compute-cb@4 { 846 compatible = "qcom,fastrpc-compute-cb"; 847 reg = <4>; 848 iommus = <&apps_smmu 0x1824 0x0>; 849 }; 850 }; 851 }; 852 }; 853 854 cdsp_pas: remoteproc-cdsp { 855 compatible = "qcom,sdm845-cdsp-pas"; 856 857 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 858 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 859 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 860 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 861 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 862 interrupt-names = "wdog", "fatal", "ready", 863 "handover", "stop-ack"; 864 865 clocks = <&rpmhcc RPMH_CXO_CLK>; 866 clock-names = "xo"; 867 868 memory-region = <&cdsp_mem>; 869 870 qcom,smem-states = <&cdsp_smp2p_out 0>; 871 qcom,smem-state-names = "stop"; 872 873 status = "disabled"; 874 875 glink-edge { 876 interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>; 877 label = "turing"; 878 qcom,remote-pid = <5>; 879 mboxes = <&apss_shared 4>; 880 fastrpc { 881 compatible = "qcom,fastrpc"; 882 qcom,glink-channels = "fastrpcglink-apps-dsp"; 883 label = "cdsp"; 884 #address-cells = <1>; 885 #size-cells = <0>; 886 887 compute-cb@1 { 888 compatible = "qcom,fastrpc-compute-cb"; 889 reg = <1>; 890 iommus = <&apps_smmu 0x1401 0x30>; 891 }; 892 893 compute-cb@2 { 894 compatible = "qcom,fastrpc-compute-cb"; 895 reg = <2>; 896 iommus = <&apps_smmu 0x1402 0x30>; 897 }; 898 899 compute-cb@3 { 900 compatible = "qcom,fastrpc-compute-cb"; 901 reg = <3>; 902 iommus = <&apps_smmu 0x1403 0x30>; 903 }; 904 905 compute-cb@4 { 906 compatible = "qcom,fastrpc-compute-cb"; 907 reg = <4>; 908 iommus = <&apps_smmu 0x1404 0x30>; 909 }; 910 911 compute-cb@5 { 912 compatible = "qcom,fastrpc-compute-cb"; 913 reg = <5>; 914 iommus = <&apps_smmu 0x1405 0x30>; 915 }; 916 917 compute-cb@6 { 918 compatible = "qcom,fastrpc-compute-cb"; 919 reg = <6>; 920 iommus = <&apps_smmu 0x1406 0x30>; 921 }; 922 923 compute-cb@7 { 924 compatible = "qcom,fastrpc-compute-cb"; 925 reg = <7>; 926 iommus = <&apps_smmu 0x1407 0x30>; 927 }; 928 929 compute-cb@8 { 930 compatible = "qcom,fastrpc-compute-cb"; 931 reg = <8>; 932 iommus = <&apps_smmu 0x1408 0x30>; 933 }; 934 }; 935 }; 936 }; 937 938 tcsr_mutex: hwlock { 939 compatible = "qcom,tcsr-mutex"; 940 syscon = <&tcsr_mutex_regs 0 0x1000>; 941 #hwlock-cells = <1>; 942 }; 943 944 smem { 945 compatible = "qcom,smem"; 946 memory-region = <&smem_mem>; 947 hwlocks = <&tcsr_mutex 3>; 948 }; 949 950 smp2p-cdsp { 951 compatible = "qcom,smp2p"; 952 qcom,smem = <94>, <432>; 953 954 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>; 955 956 mboxes = <&apss_shared 6>; 957 958 qcom,local-pid = <0>; 959 qcom,remote-pid = <5>; 960 961 cdsp_smp2p_out: master-kernel { 962 qcom,entry-name = "master-kernel"; 963 #qcom,smem-state-cells = <1>; 964 }; 965 966 cdsp_smp2p_in: slave-kernel { 967 qcom,entry-name = "slave-kernel"; 968 969 interrupt-controller; 970 #interrupt-cells = <2>; 971 }; 972 }; 973 974 smp2p-lpass { 975 compatible = "qcom,smp2p"; 976 qcom,smem = <443>, <429>; 977 978 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 979 980 mboxes = <&apss_shared 10>; 981 982 qcom,local-pid = <0>; 983 qcom,remote-pid = <2>; 984 985 adsp_smp2p_out: master-kernel { 986 qcom,entry-name = "master-kernel"; 987 #qcom,smem-state-cells = <1>; 988 }; 989 990 adsp_smp2p_in: slave-kernel { 991 qcom,entry-name = "slave-kernel"; 992 993 interrupt-controller; 994 #interrupt-cells = <2>; 995 }; 996 }; 997 998 smp2p-mpss { 999 compatible = "qcom,smp2p"; 1000 qcom,smem = <435>, <428>; 1001 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 1002 mboxes = <&apss_shared 14>; 1003 qcom,local-pid = <0>; 1004 qcom,remote-pid = <1>; 1005 1006 modem_smp2p_out: master-kernel { 1007 qcom,entry-name = "master-kernel"; 1008 #qcom,smem-state-cells = <1>; 1009 }; 1010 1011 modem_smp2p_in: slave-kernel { 1012 qcom,entry-name = "slave-kernel"; 1013 interrupt-controller; 1014 #interrupt-cells = <2>; 1015 }; 1016 1017 ipa_smp2p_out: ipa-ap-to-modem { 1018 qcom,entry-name = "ipa"; 1019 #qcom,smem-state-cells = <1>; 1020 }; 1021 1022 ipa_smp2p_in: ipa-modem-to-ap { 1023 qcom,entry-name = "ipa"; 1024 interrupt-controller; 1025 #interrupt-cells = <2>; 1026 }; 1027 }; 1028 1029 smp2p-slpi { 1030 compatible = "qcom,smp2p"; 1031 qcom,smem = <481>, <430>; 1032 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>; 1033 mboxes = <&apss_shared 26>; 1034 qcom,local-pid = <0>; 1035 qcom,remote-pid = <3>; 1036 1037 slpi_smp2p_out: master-kernel { 1038 qcom,entry-name = "master-kernel"; 1039 #qcom,smem-state-cells = <1>; 1040 }; 1041 1042 slpi_smp2p_in: slave-kernel { 1043 qcom,entry-name = "slave-kernel"; 1044 interrupt-controller; 1045 #interrupt-cells = <2>; 1046 }; 1047 }; 1048 1049 psci { 1050 compatible = "arm,psci-1.0"; 1051 method = "smc"; 1052 }; 1053 1054 soc: soc@0 { 1055 #address-cells = <2>; 1056 #size-cells = <2>; 1057 ranges = <0 0 0 0 0x10 0>; 1058 dma-ranges = <0 0 0 0 0x10 0>; 1059 compatible = "simple-bus"; 1060 1061 gcc: clock-controller@100000 { 1062 compatible = "qcom,gcc-sdm845"; 1063 reg = <0 0x00100000 0 0x1f0000>; 1064 #clock-cells = <1>; 1065 #reset-cells = <1>; 1066 #power-domain-cells = <1>; 1067 }; 1068 1069 qfprom@784000 { 1070 compatible = "qcom,qfprom"; 1071 reg = <0 0x00784000 0 0x8ff>; 1072 #address-cells = <1>; 1073 #size-cells = <1>; 1074 1075 qusb2p_hstx_trim: hstx-trim-primary@1eb { 1076 reg = <0x1eb 0x1>; 1077 bits = <1 4>; 1078 }; 1079 1080 qusb2s_hstx_trim: hstx-trim-secondary@1eb { 1081 reg = <0x1eb 0x2>; 1082 bits = <6 4>; 1083 }; 1084 }; 1085 1086 rng: rng@793000 { 1087 compatible = "qcom,prng-ee"; 1088 reg = <0 0x00793000 0 0x1000>; 1089 clocks = <&gcc GCC_PRNG_AHB_CLK>; 1090 clock-names = "core"; 1091 }; 1092 1093 qup_opp_table: qup-opp-table { 1094 compatible = "operating-points-v2"; 1095 1096 opp-50000000 { 1097 opp-hz = /bits/ 64 <50000000>; 1098 required-opps = <&rpmhpd_opp_min_svs>; 1099 }; 1100 1101 opp-75000000 { 1102 opp-hz = /bits/ 64 <75000000>; 1103 required-opps = <&rpmhpd_opp_low_svs>; 1104 }; 1105 1106 opp-100000000 { 1107 opp-hz = /bits/ 64 <100000000>; 1108 required-opps = <&rpmhpd_opp_svs>; 1109 }; 1110 1111 opp-128000000 { 1112 opp-hz = /bits/ 64 <128000000>; 1113 required-opps = <&rpmhpd_opp_nom>; 1114 }; 1115 }; 1116 1117 qupv3_id_0: geniqup@8c0000 { 1118 compatible = "qcom,geni-se-qup"; 1119 reg = <0 0x008c0000 0 0x6000>; 1120 clock-names = "m-ahb", "s-ahb"; 1121 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1122 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1123 #address-cells = <2>; 1124 #size-cells = <2>; 1125 ranges; 1126 status = "disabled"; 1127 1128 i2c0: i2c@880000 { 1129 compatible = "qcom,geni-i2c"; 1130 reg = <0 0x00880000 0 0x4000>; 1131 clock-names = "se"; 1132 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1133 pinctrl-names = "default"; 1134 pinctrl-0 = <&qup_i2c0_default>; 1135 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1136 #address-cells = <1>; 1137 #size-cells = <0>; 1138 power-domains = <&rpmhpd SDM845_CX>; 1139 operating-points-v2 = <&qup_opp_table>; 1140 status = "disabled"; 1141 }; 1142 1143 spi0: spi@880000 { 1144 compatible = "qcom,geni-spi"; 1145 reg = <0 0x00880000 0 0x4000>; 1146 clock-names = "se"; 1147 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1148 pinctrl-names = "default"; 1149 pinctrl-0 = <&qup_spi0_default>; 1150 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1151 #address-cells = <1>; 1152 #size-cells = <0>; 1153 status = "disabled"; 1154 }; 1155 1156 uart0: serial@880000 { 1157 compatible = "qcom,geni-uart"; 1158 reg = <0 0x00880000 0 0x4000>; 1159 clock-names = "se"; 1160 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1161 pinctrl-names = "default"; 1162 pinctrl-0 = <&qup_uart0_default>; 1163 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1164 power-domains = <&rpmhpd SDM845_CX>; 1165 operating-points-v2 = <&qup_opp_table>; 1166 status = "disabled"; 1167 }; 1168 1169 i2c1: i2c@884000 { 1170 compatible = "qcom,geni-i2c"; 1171 reg = <0 0x00884000 0 0x4000>; 1172 clock-names = "se"; 1173 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1174 pinctrl-names = "default"; 1175 pinctrl-0 = <&qup_i2c1_default>; 1176 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1177 #address-cells = <1>; 1178 #size-cells = <0>; 1179 power-domains = <&rpmhpd SDM845_CX>; 1180 operating-points-v2 = <&qup_opp_table>; 1181 status = "disabled"; 1182 }; 1183 1184 spi1: spi@884000 { 1185 compatible = "qcom,geni-spi"; 1186 reg = <0 0x00884000 0 0x4000>; 1187 clock-names = "se"; 1188 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1189 pinctrl-names = "default"; 1190 pinctrl-0 = <&qup_spi1_default>; 1191 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1192 #address-cells = <1>; 1193 #size-cells = <0>; 1194 status = "disabled"; 1195 }; 1196 1197 uart1: serial@884000 { 1198 compatible = "qcom,geni-uart"; 1199 reg = <0 0x00884000 0 0x4000>; 1200 clock-names = "se"; 1201 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1202 pinctrl-names = "default"; 1203 pinctrl-0 = <&qup_uart1_default>; 1204 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1205 power-domains = <&rpmhpd SDM845_CX>; 1206 operating-points-v2 = <&qup_opp_table>; 1207 status = "disabled"; 1208 }; 1209 1210 i2c2: i2c@888000 { 1211 compatible = "qcom,geni-i2c"; 1212 reg = <0 0x00888000 0 0x4000>; 1213 clock-names = "se"; 1214 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1215 pinctrl-names = "default"; 1216 pinctrl-0 = <&qup_i2c2_default>; 1217 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1218 #address-cells = <1>; 1219 #size-cells = <0>; 1220 power-domains = <&rpmhpd SDM845_CX>; 1221 operating-points-v2 = <&qup_opp_table>; 1222 status = "disabled"; 1223 }; 1224 1225 spi2: spi@888000 { 1226 compatible = "qcom,geni-spi"; 1227 reg = <0 0x00888000 0 0x4000>; 1228 clock-names = "se"; 1229 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1230 pinctrl-names = "default"; 1231 pinctrl-0 = <&qup_spi2_default>; 1232 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1233 #address-cells = <1>; 1234 #size-cells = <0>; 1235 status = "disabled"; 1236 }; 1237 1238 uart2: serial@888000 { 1239 compatible = "qcom,geni-uart"; 1240 reg = <0 0x00888000 0 0x4000>; 1241 clock-names = "se"; 1242 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1243 pinctrl-names = "default"; 1244 pinctrl-0 = <&qup_uart2_default>; 1245 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1246 power-domains = <&rpmhpd SDM845_CX>; 1247 operating-points-v2 = <&qup_opp_table>; 1248 status = "disabled"; 1249 }; 1250 1251 i2c3: i2c@88c000 { 1252 compatible = "qcom,geni-i2c"; 1253 reg = <0 0x0088c000 0 0x4000>; 1254 clock-names = "se"; 1255 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1256 pinctrl-names = "default"; 1257 pinctrl-0 = <&qup_i2c3_default>; 1258 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1259 #address-cells = <1>; 1260 #size-cells = <0>; 1261 power-domains = <&rpmhpd SDM845_CX>; 1262 operating-points-v2 = <&qup_opp_table>; 1263 status = "disabled"; 1264 }; 1265 1266 spi3: spi@88c000 { 1267 compatible = "qcom,geni-spi"; 1268 reg = <0 0x0088c000 0 0x4000>; 1269 clock-names = "se"; 1270 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1271 pinctrl-names = "default"; 1272 pinctrl-0 = <&qup_spi3_default>; 1273 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1274 #address-cells = <1>; 1275 #size-cells = <0>; 1276 status = "disabled"; 1277 }; 1278 1279 uart3: serial@88c000 { 1280 compatible = "qcom,geni-uart"; 1281 reg = <0 0x0088c000 0 0x4000>; 1282 clock-names = "se"; 1283 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1284 pinctrl-names = "default"; 1285 pinctrl-0 = <&qup_uart3_default>; 1286 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1287 power-domains = <&rpmhpd SDM845_CX>; 1288 operating-points-v2 = <&qup_opp_table>; 1289 status = "disabled"; 1290 }; 1291 1292 i2c4: i2c@890000 { 1293 compatible = "qcom,geni-i2c"; 1294 reg = <0 0x00890000 0 0x4000>; 1295 clock-names = "se"; 1296 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1297 pinctrl-names = "default"; 1298 pinctrl-0 = <&qup_i2c4_default>; 1299 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1300 #address-cells = <1>; 1301 #size-cells = <0>; 1302 power-domains = <&rpmhpd SDM845_CX>; 1303 operating-points-v2 = <&qup_opp_table>; 1304 status = "disabled"; 1305 }; 1306 1307 spi4: spi@890000 { 1308 compatible = "qcom,geni-spi"; 1309 reg = <0 0x00890000 0 0x4000>; 1310 clock-names = "se"; 1311 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1312 pinctrl-names = "default"; 1313 pinctrl-0 = <&qup_spi4_default>; 1314 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1315 #address-cells = <1>; 1316 #size-cells = <0>; 1317 status = "disabled"; 1318 }; 1319 1320 uart4: serial@890000 { 1321 compatible = "qcom,geni-uart"; 1322 reg = <0 0x00890000 0 0x4000>; 1323 clock-names = "se"; 1324 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1325 pinctrl-names = "default"; 1326 pinctrl-0 = <&qup_uart4_default>; 1327 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1328 power-domains = <&rpmhpd SDM845_CX>; 1329 operating-points-v2 = <&qup_opp_table>; 1330 status = "disabled"; 1331 }; 1332 1333 i2c5: i2c@894000 { 1334 compatible = "qcom,geni-i2c"; 1335 reg = <0 0x00894000 0 0x4000>; 1336 clock-names = "se"; 1337 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1338 pinctrl-names = "default"; 1339 pinctrl-0 = <&qup_i2c5_default>; 1340 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1341 #address-cells = <1>; 1342 #size-cells = <0>; 1343 power-domains = <&rpmhpd SDM845_CX>; 1344 operating-points-v2 = <&qup_opp_table>; 1345 status = "disabled"; 1346 }; 1347 1348 spi5: spi@894000 { 1349 compatible = "qcom,geni-spi"; 1350 reg = <0 0x00894000 0 0x4000>; 1351 clock-names = "se"; 1352 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1353 pinctrl-names = "default"; 1354 pinctrl-0 = <&qup_spi5_default>; 1355 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1356 #address-cells = <1>; 1357 #size-cells = <0>; 1358 status = "disabled"; 1359 }; 1360 1361 uart5: serial@894000 { 1362 compatible = "qcom,geni-uart"; 1363 reg = <0 0x00894000 0 0x4000>; 1364 clock-names = "se"; 1365 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1366 pinctrl-names = "default"; 1367 pinctrl-0 = <&qup_uart5_default>; 1368 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1369 power-domains = <&rpmhpd SDM845_CX>; 1370 operating-points-v2 = <&qup_opp_table>; 1371 status = "disabled"; 1372 }; 1373 1374 i2c6: i2c@898000 { 1375 compatible = "qcom,geni-i2c"; 1376 reg = <0 0x00898000 0 0x4000>; 1377 clock-names = "se"; 1378 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1379 pinctrl-names = "default"; 1380 pinctrl-0 = <&qup_i2c6_default>; 1381 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1382 #address-cells = <1>; 1383 #size-cells = <0>; 1384 power-domains = <&rpmhpd SDM845_CX>; 1385 operating-points-v2 = <&qup_opp_table>; 1386 status = "disabled"; 1387 }; 1388 1389 spi6: spi@898000 { 1390 compatible = "qcom,geni-spi"; 1391 reg = <0 0x00898000 0 0x4000>; 1392 clock-names = "se"; 1393 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1394 pinctrl-names = "default"; 1395 pinctrl-0 = <&qup_spi6_default>; 1396 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1397 #address-cells = <1>; 1398 #size-cells = <0>; 1399 status = "disabled"; 1400 }; 1401 1402 uart6: serial@898000 { 1403 compatible = "qcom,geni-uart"; 1404 reg = <0 0x00898000 0 0x4000>; 1405 clock-names = "se"; 1406 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1407 pinctrl-names = "default"; 1408 pinctrl-0 = <&qup_uart6_default>; 1409 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1410 power-domains = <&rpmhpd SDM845_CX>; 1411 operating-points-v2 = <&qup_opp_table>; 1412 status = "disabled"; 1413 }; 1414 1415 i2c7: i2c@89c000 { 1416 compatible = "qcom,geni-i2c"; 1417 reg = <0 0x0089c000 0 0x4000>; 1418 clock-names = "se"; 1419 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1420 pinctrl-names = "default"; 1421 pinctrl-0 = <&qup_i2c7_default>; 1422 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1423 #address-cells = <1>; 1424 #size-cells = <0>; 1425 power-domains = <&rpmhpd SDM845_CX>; 1426 operating-points-v2 = <&qup_opp_table>; 1427 status = "disabled"; 1428 }; 1429 1430 spi7: spi@89c000 { 1431 compatible = "qcom,geni-spi"; 1432 reg = <0 0x0089c000 0 0x4000>; 1433 clock-names = "se"; 1434 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1435 pinctrl-names = "default"; 1436 pinctrl-0 = <&qup_spi7_default>; 1437 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1438 #address-cells = <1>; 1439 #size-cells = <0>; 1440 status = "disabled"; 1441 }; 1442 1443 uart7: serial@89c000 { 1444 compatible = "qcom,geni-uart"; 1445 reg = <0 0x0089c000 0 0x4000>; 1446 clock-names = "se"; 1447 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1448 pinctrl-names = "default"; 1449 pinctrl-0 = <&qup_uart7_default>; 1450 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1451 power-domains = <&rpmhpd SDM845_CX>; 1452 operating-points-v2 = <&qup_opp_table>; 1453 status = "disabled"; 1454 }; 1455 }; 1456 1457 qupv3_id_1: geniqup@ac0000 { 1458 compatible = "qcom,geni-se-qup"; 1459 reg = <0 0x00ac0000 0 0x6000>; 1460 clock-names = "m-ahb", "s-ahb"; 1461 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1462 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1463 #address-cells = <2>; 1464 #size-cells = <2>; 1465 ranges; 1466 status = "disabled"; 1467 1468 i2c8: i2c@a80000 { 1469 compatible = "qcom,geni-i2c"; 1470 reg = <0 0x00a80000 0 0x4000>; 1471 clock-names = "se"; 1472 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1473 pinctrl-names = "default"; 1474 pinctrl-0 = <&qup_i2c8_default>; 1475 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1476 #address-cells = <1>; 1477 #size-cells = <0>; 1478 power-domains = <&rpmhpd SDM845_CX>; 1479 operating-points-v2 = <&qup_opp_table>; 1480 status = "disabled"; 1481 }; 1482 1483 spi8: spi@a80000 { 1484 compatible = "qcom,geni-spi"; 1485 reg = <0 0x00a80000 0 0x4000>; 1486 clock-names = "se"; 1487 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1488 pinctrl-names = "default"; 1489 pinctrl-0 = <&qup_spi8_default>; 1490 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1491 #address-cells = <1>; 1492 #size-cells = <0>; 1493 status = "disabled"; 1494 }; 1495 1496 uart8: serial@a80000 { 1497 compatible = "qcom,geni-uart"; 1498 reg = <0 0x00a80000 0 0x4000>; 1499 clock-names = "se"; 1500 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1501 pinctrl-names = "default"; 1502 pinctrl-0 = <&qup_uart8_default>; 1503 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1504 power-domains = <&rpmhpd SDM845_CX>; 1505 operating-points-v2 = <&qup_opp_table>; 1506 status = "disabled"; 1507 }; 1508 1509 i2c9: i2c@a84000 { 1510 compatible = "qcom,geni-i2c"; 1511 reg = <0 0x00a84000 0 0x4000>; 1512 clock-names = "se"; 1513 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1514 pinctrl-names = "default"; 1515 pinctrl-0 = <&qup_i2c9_default>; 1516 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1517 #address-cells = <1>; 1518 #size-cells = <0>; 1519 power-domains = <&rpmhpd SDM845_CX>; 1520 operating-points-v2 = <&qup_opp_table>; 1521 status = "disabled"; 1522 }; 1523 1524 spi9: spi@a84000 { 1525 compatible = "qcom,geni-spi"; 1526 reg = <0 0x00a84000 0 0x4000>; 1527 clock-names = "se"; 1528 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1529 pinctrl-names = "default"; 1530 pinctrl-0 = <&qup_spi9_default>; 1531 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1532 #address-cells = <1>; 1533 #size-cells = <0>; 1534 status = "disabled"; 1535 }; 1536 1537 uart9: serial@a84000 { 1538 compatible = "qcom,geni-debug-uart"; 1539 reg = <0 0x00a84000 0 0x4000>; 1540 clock-names = "se"; 1541 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1542 pinctrl-names = "default"; 1543 pinctrl-0 = <&qup_uart9_default>; 1544 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1545 power-domains = <&rpmhpd SDM845_CX>; 1546 operating-points-v2 = <&qup_opp_table>; 1547 status = "disabled"; 1548 }; 1549 1550 i2c10: i2c@a88000 { 1551 compatible = "qcom,geni-i2c"; 1552 reg = <0 0x00a88000 0 0x4000>; 1553 clock-names = "se"; 1554 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1555 pinctrl-names = "default"; 1556 pinctrl-0 = <&qup_i2c10_default>; 1557 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1558 #address-cells = <1>; 1559 #size-cells = <0>; 1560 power-domains = <&rpmhpd SDM845_CX>; 1561 operating-points-v2 = <&qup_opp_table>; 1562 status = "disabled"; 1563 }; 1564 1565 spi10: spi@a88000 { 1566 compatible = "qcom,geni-spi"; 1567 reg = <0 0x00a88000 0 0x4000>; 1568 clock-names = "se"; 1569 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1570 pinctrl-names = "default"; 1571 pinctrl-0 = <&qup_spi10_default>; 1572 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1573 #address-cells = <1>; 1574 #size-cells = <0>; 1575 status = "disabled"; 1576 }; 1577 1578 uart10: serial@a88000 { 1579 compatible = "qcom,geni-uart"; 1580 reg = <0 0x00a88000 0 0x4000>; 1581 clock-names = "se"; 1582 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1583 pinctrl-names = "default"; 1584 pinctrl-0 = <&qup_uart10_default>; 1585 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1586 power-domains = <&rpmhpd SDM845_CX>; 1587 operating-points-v2 = <&qup_opp_table>; 1588 status = "disabled"; 1589 }; 1590 1591 i2c11: i2c@a8c000 { 1592 compatible = "qcom,geni-i2c"; 1593 reg = <0 0x00a8c000 0 0x4000>; 1594 clock-names = "se"; 1595 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1596 pinctrl-names = "default"; 1597 pinctrl-0 = <&qup_i2c11_default>; 1598 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1599 #address-cells = <1>; 1600 #size-cells = <0>; 1601 power-domains = <&rpmhpd SDM845_CX>; 1602 operating-points-v2 = <&qup_opp_table>; 1603 status = "disabled"; 1604 }; 1605 1606 spi11: spi@a8c000 { 1607 compatible = "qcom,geni-spi"; 1608 reg = <0 0x00a8c000 0 0x4000>; 1609 clock-names = "se"; 1610 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1611 pinctrl-names = "default"; 1612 pinctrl-0 = <&qup_spi11_default>; 1613 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1614 #address-cells = <1>; 1615 #size-cells = <0>; 1616 status = "disabled"; 1617 }; 1618 1619 uart11: serial@a8c000 { 1620 compatible = "qcom,geni-uart"; 1621 reg = <0 0x00a8c000 0 0x4000>; 1622 clock-names = "se"; 1623 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1624 pinctrl-names = "default"; 1625 pinctrl-0 = <&qup_uart11_default>; 1626 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1627 power-domains = <&rpmhpd SDM845_CX>; 1628 operating-points-v2 = <&qup_opp_table>; 1629 status = "disabled"; 1630 }; 1631 1632 i2c12: i2c@a90000 { 1633 compatible = "qcom,geni-i2c"; 1634 reg = <0 0x00a90000 0 0x4000>; 1635 clock-names = "se"; 1636 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1637 pinctrl-names = "default"; 1638 pinctrl-0 = <&qup_i2c12_default>; 1639 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1640 #address-cells = <1>; 1641 #size-cells = <0>; 1642 power-domains = <&rpmhpd SDM845_CX>; 1643 operating-points-v2 = <&qup_opp_table>; 1644 status = "disabled"; 1645 }; 1646 1647 spi12: spi@a90000 { 1648 compatible = "qcom,geni-spi"; 1649 reg = <0 0x00a90000 0 0x4000>; 1650 clock-names = "se"; 1651 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1652 pinctrl-names = "default"; 1653 pinctrl-0 = <&qup_spi12_default>; 1654 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1655 #address-cells = <1>; 1656 #size-cells = <0>; 1657 status = "disabled"; 1658 }; 1659 1660 uart12: serial@a90000 { 1661 compatible = "qcom,geni-uart"; 1662 reg = <0 0x00a90000 0 0x4000>; 1663 clock-names = "se"; 1664 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1665 pinctrl-names = "default"; 1666 pinctrl-0 = <&qup_uart12_default>; 1667 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1668 power-domains = <&rpmhpd SDM845_CX>; 1669 operating-points-v2 = <&qup_opp_table>; 1670 status = "disabled"; 1671 }; 1672 1673 i2c13: i2c@a94000 { 1674 compatible = "qcom,geni-i2c"; 1675 reg = <0 0x00a94000 0 0x4000>; 1676 clock-names = "se"; 1677 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1678 pinctrl-names = "default"; 1679 pinctrl-0 = <&qup_i2c13_default>; 1680 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1681 #address-cells = <1>; 1682 #size-cells = <0>; 1683 power-domains = <&rpmhpd SDM845_CX>; 1684 operating-points-v2 = <&qup_opp_table>; 1685 status = "disabled"; 1686 }; 1687 1688 spi13: spi@a94000 { 1689 compatible = "qcom,geni-spi"; 1690 reg = <0 0x00a94000 0 0x4000>; 1691 clock-names = "se"; 1692 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1693 pinctrl-names = "default"; 1694 pinctrl-0 = <&qup_spi13_default>; 1695 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1696 #address-cells = <1>; 1697 #size-cells = <0>; 1698 status = "disabled"; 1699 }; 1700 1701 uart13: serial@a94000 { 1702 compatible = "qcom,geni-uart"; 1703 reg = <0 0x00a94000 0 0x4000>; 1704 clock-names = "se"; 1705 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1706 pinctrl-names = "default"; 1707 pinctrl-0 = <&qup_uart13_default>; 1708 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1709 power-domains = <&rpmhpd SDM845_CX>; 1710 operating-points-v2 = <&qup_opp_table>; 1711 status = "disabled"; 1712 }; 1713 1714 i2c14: i2c@a98000 { 1715 compatible = "qcom,geni-i2c"; 1716 reg = <0 0x00a98000 0 0x4000>; 1717 clock-names = "se"; 1718 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1719 pinctrl-names = "default"; 1720 pinctrl-0 = <&qup_i2c14_default>; 1721 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 1722 #address-cells = <1>; 1723 #size-cells = <0>; 1724 power-domains = <&rpmhpd SDM845_CX>; 1725 operating-points-v2 = <&qup_opp_table>; 1726 status = "disabled"; 1727 }; 1728 1729 spi14: spi@a98000 { 1730 compatible = "qcom,geni-spi"; 1731 reg = <0 0x00a98000 0 0x4000>; 1732 clock-names = "se"; 1733 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1734 pinctrl-names = "default"; 1735 pinctrl-0 = <&qup_spi14_default>; 1736 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 1737 #address-cells = <1>; 1738 #size-cells = <0>; 1739 status = "disabled"; 1740 }; 1741 1742 uart14: serial@a98000 { 1743 compatible = "qcom,geni-uart"; 1744 reg = <0 0x00a98000 0 0x4000>; 1745 clock-names = "se"; 1746 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1747 pinctrl-names = "default"; 1748 pinctrl-0 = <&qup_uart14_default>; 1749 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 1750 power-domains = <&rpmhpd SDM845_CX>; 1751 operating-points-v2 = <&qup_opp_table>; 1752 status = "disabled"; 1753 }; 1754 1755 i2c15: i2c@a9c000 { 1756 compatible = "qcom,geni-i2c"; 1757 reg = <0 0x00a9c000 0 0x4000>; 1758 clock-names = "se"; 1759 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1760 pinctrl-names = "default"; 1761 pinctrl-0 = <&qup_i2c15_default>; 1762 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 1763 #address-cells = <1>; 1764 #size-cells = <0>; 1765 power-domains = <&rpmhpd SDM845_CX>; 1766 operating-points-v2 = <&qup_opp_table>; 1767 status = "disabled"; 1768 }; 1769 1770 spi15: spi@a9c000 { 1771 compatible = "qcom,geni-spi"; 1772 reg = <0 0x00a9c000 0 0x4000>; 1773 clock-names = "se"; 1774 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1775 pinctrl-names = "default"; 1776 pinctrl-0 = <&qup_spi15_default>; 1777 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 1778 #address-cells = <1>; 1779 #size-cells = <0>; 1780 status = "disabled"; 1781 }; 1782 1783 uart15: serial@a9c000 { 1784 compatible = "qcom,geni-uart"; 1785 reg = <0 0x00a9c000 0 0x4000>; 1786 clock-names = "se"; 1787 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1788 pinctrl-names = "default"; 1789 pinctrl-0 = <&qup_uart15_default>; 1790 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 1791 power-domains = <&rpmhpd SDM845_CX>; 1792 operating-points-v2 = <&qup_opp_table>; 1793 status = "disabled"; 1794 }; 1795 }; 1796 1797 system-cache-controller@1100000 { 1798 compatible = "qcom,sdm845-llcc"; 1799 reg = <0 0x01100000 0 0x200000>, <0 0x01300000 0 0x50000>; 1800 reg-names = "llcc_base", "llcc_broadcast_base"; 1801 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 1802 }; 1803 1804 pcie0: pci@1c00000 { 1805 compatible = "qcom,pcie-sdm845", "snps,dw-pcie"; 1806 reg = <0 0x01c00000 0 0x2000>, 1807 <0 0x60000000 0 0xf1d>, 1808 <0 0x60000f20 0 0xa8>, 1809 <0 0x60100000 0 0x100000>; 1810 reg-names = "parf", "dbi", "elbi", "config"; 1811 device_type = "pci"; 1812 linux,pci-domain = <0>; 1813 bus-range = <0x00 0xff>; 1814 num-lanes = <1>; 1815 1816 #address-cells = <3>; 1817 #size-cells = <2>; 1818 1819 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, 1820 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0xd00000>; 1821 1822 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 1823 interrupt-names = "msi"; 1824 #interrupt-cells = <1>; 1825 interrupt-map-mask = <0 0 0 0x7>; 1826 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1827 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1828 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1829 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1830 1831 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 1832 <&gcc GCC_PCIE_0_AUX_CLK>, 1833 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1834 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1835 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1836 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 1837 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; 1838 clock-names = "pipe", 1839 "aux", 1840 "cfg", 1841 "bus_master", 1842 "bus_slave", 1843 "slave_q2a", 1844 "tbu"; 1845 1846 iommus = <&apps_smmu 0x1c10 0xf>; 1847 iommu-map = <0x0 &apps_smmu 0x1c10 0x1>, 1848 <0x100 &apps_smmu 0x1c11 0x1>, 1849 <0x200 &apps_smmu 0x1c12 0x1>, 1850 <0x300 &apps_smmu 0x1c13 0x1>, 1851 <0x400 &apps_smmu 0x1c14 0x1>, 1852 <0x500 &apps_smmu 0x1c15 0x1>, 1853 <0x600 &apps_smmu 0x1c16 0x1>, 1854 <0x700 &apps_smmu 0x1c17 0x1>, 1855 <0x800 &apps_smmu 0x1c18 0x1>, 1856 <0x900 &apps_smmu 0x1c19 0x1>, 1857 <0xa00 &apps_smmu 0x1c1a 0x1>, 1858 <0xb00 &apps_smmu 0x1c1b 0x1>, 1859 <0xc00 &apps_smmu 0x1c1c 0x1>, 1860 <0xd00 &apps_smmu 0x1c1d 0x1>, 1861 <0xe00 &apps_smmu 0x1c1e 0x1>, 1862 <0xf00 &apps_smmu 0x1c1f 0x1>; 1863 1864 resets = <&gcc GCC_PCIE_0_BCR>; 1865 reset-names = "pci"; 1866 1867 power-domains = <&gcc PCIE_0_GDSC>; 1868 1869 phys = <&pcie0_lane>; 1870 phy-names = "pciephy"; 1871 1872 status = "disabled"; 1873 }; 1874 1875 pcie0_phy: phy@1c06000 { 1876 compatible = "qcom,sdm845-qmp-pcie-phy"; 1877 reg = <0 0x01c06000 0 0x18c>; 1878 #address-cells = <2>; 1879 #size-cells = <2>; 1880 ranges; 1881 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1882 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1883 <&gcc GCC_PCIE_0_CLKREF_CLK>, 1884 <&gcc GCC_PCIE_PHY_REFGEN_CLK>; 1885 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 1886 1887 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1888 reset-names = "phy"; 1889 1890 assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>; 1891 assigned-clock-rates = <100000000>; 1892 1893 status = "disabled"; 1894 1895 pcie0_lane: lanes@1c06200 { 1896 reg = <0 0x01c06200 0 0x128>, 1897 <0 0x01c06400 0 0x1fc>, 1898 <0 0x01c06800 0 0x218>, 1899 <0 0x01c06600 0 0x70>; 1900 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; 1901 clock-names = "pipe0"; 1902 1903 #phy-cells = <0>; 1904 clock-output-names = "pcie_0_pipe_clk"; 1905 }; 1906 }; 1907 1908 pcie1: pci@1c08000 { 1909 compatible = "qcom,pcie-sdm845", "snps,dw-pcie"; 1910 reg = <0 0x01c08000 0 0x2000>, 1911 <0 0x40000000 0 0xf1d>, 1912 <0 0x40000f20 0 0xa8>, 1913 <0 0x40100000 0 0x100000>; 1914 reg-names = "parf", "dbi", "elbi", "config"; 1915 device_type = "pci"; 1916 linux,pci-domain = <1>; 1917 bus-range = <0x00 0xff>; 1918 num-lanes = <1>; 1919 1920 #address-cells = <3>; 1921 #size-cells = <2>; 1922 1923 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 1924 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1925 1926 interrupts = <GIC_SPI 307 IRQ_TYPE_EDGE_RISING>; 1927 interrupt-names = "msi"; 1928 #interrupt-cells = <1>; 1929 interrupt-map-mask = <0 0 0 0x7>; 1930 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1931 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1932 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1933 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1934 1935 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 1936 <&gcc GCC_PCIE_1_AUX_CLK>, 1937 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1938 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1939 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1940 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1941 <&gcc GCC_PCIE_1_CLKREF_CLK>, 1942 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; 1943 clock-names = "pipe", 1944 "aux", 1945 "cfg", 1946 "bus_master", 1947 "bus_slave", 1948 "slave_q2a", 1949 "ref", 1950 "tbu"; 1951 1952 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 1953 assigned-clock-rates = <19200000>; 1954 1955 iommus = <&apps_smmu 0x1c00 0xf>; 1956 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, 1957 <0x100 &apps_smmu 0x1c01 0x1>, 1958 <0x200 &apps_smmu 0x1c02 0x1>, 1959 <0x300 &apps_smmu 0x1c03 0x1>, 1960 <0x400 &apps_smmu 0x1c04 0x1>, 1961 <0x500 &apps_smmu 0x1c05 0x1>, 1962 <0x600 &apps_smmu 0x1c06 0x1>, 1963 <0x700 &apps_smmu 0x1c07 0x1>, 1964 <0x800 &apps_smmu 0x1c08 0x1>, 1965 <0x900 &apps_smmu 0x1c09 0x1>, 1966 <0xa00 &apps_smmu 0x1c0a 0x1>, 1967 <0xb00 &apps_smmu 0x1c0b 0x1>, 1968 <0xc00 &apps_smmu 0x1c0c 0x1>, 1969 <0xd00 &apps_smmu 0x1c0d 0x1>, 1970 <0xe00 &apps_smmu 0x1c0e 0x1>, 1971 <0xf00 &apps_smmu 0x1c0f 0x1>; 1972 1973 resets = <&gcc GCC_PCIE_1_BCR>; 1974 reset-names = "pci"; 1975 1976 power-domains = <&gcc PCIE_1_GDSC>; 1977 1978 phys = <&pcie1_lane>; 1979 phy-names = "pciephy"; 1980 1981 status = "disabled"; 1982 }; 1983 1984 pcie1_phy: phy@1c0a000 { 1985 compatible = "qcom,sdm845-qhp-pcie-phy"; 1986 reg = <0 0x01c0a000 0 0x800>; 1987 #address-cells = <2>; 1988 #size-cells = <2>; 1989 ranges; 1990 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1991 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1992 <&gcc GCC_PCIE_1_CLKREF_CLK>, 1993 <&gcc GCC_PCIE_PHY_REFGEN_CLK>; 1994 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 1995 1996 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 1997 reset-names = "phy"; 1998 1999 assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>; 2000 assigned-clock-rates = <100000000>; 2001 2002 status = "disabled"; 2003 2004 pcie1_lane: lanes@1c06200 { 2005 reg = <0 0x01c0a800 0 0x800>, 2006 <0 0x01c0a800 0 0x800>, 2007 <0 0x01c0b800 0 0x400>; 2008 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 2009 clock-names = "pipe0"; 2010 2011 #phy-cells = <0>; 2012 clock-output-names = "pcie_1_pipe_clk"; 2013 }; 2014 }; 2015 2016 mem_noc: interconnect@1380000 { 2017 compatible = "qcom,sdm845-mem-noc"; 2018 reg = <0 0x01380000 0 0x27200>; 2019 #interconnect-cells = <2>; 2020 qcom,bcm-voters = <&apps_bcm_voter>; 2021 }; 2022 2023 dc_noc: interconnect@14e0000 { 2024 compatible = "qcom,sdm845-dc-noc"; 2025 reg = <0 0x014e0000 0 0x400>; 2026 #interconnect-cells = <2>; 2027 qcom,bcm-voters = <&apps_bcm_voter>; 2028 }; 2029 2030 config_noc: interconnect@1500000 { 2031 compatible = "qcom,sdm845-config-noc"; 2032 reg = <0 0x01500000 0 0x5080>; 2033 #interconnect-cells = <2>; 2034 qcom,bcm-voters = <&apps_bcm_voter>; 2035 }; 2036 2037 system_noc: interconnect@1620000 { 2038 compatible = "qcom,sdm845-system-noc"; 2039 reg = <0 0x01620000 0 0x18080>; 2040 #interconnect-cells = <2>; 2041 qcom,bcm-voters = <&apps_bcm_voter>; 2042 }; 2043 2044 aggre1_noc: interconnect@16e0000 { 2045 compatible = "qcom,sdm845-aggre1-noc"; 2046 reg = <0 0x016e0000 0 0x15080>; 2047 #interconnect-cells = <2>; 2048 qcom,bcm-voters = <&apps_bcm_voter>; 2049 }; 2050 2051 aggre2_noc: interconnect@1700000 { 2052 compatible = "qcom,sdm845-aggre2-noc"; 2053 reg = <0 0x01700000 0 0x1f300>; 2054 #interconnect-cells = <2>; 2055 qcom,bcm-voters = <&apps_bcm_voter>; 2056 }; 2057 2058 mmss_noc: interconnect@1740000 { 2059 compatible = "qcom,sdm845-mmss-noc"; 2060 reg = <0 0x01740000 0 0x1c100>; 2061 #interconnect-cells = <2>; 2062 qcom,bcm-voters = <&apps_bcm_voter>; 2063 }; 2064 2065 ufs_mem_hc: ufshc@1d84000 { 2066 compatible = "qcom,sdm845-ufshc", "qcom,ufshc", 2067 "jedec,ufs-2.0"; 2068 reg = <0 0x01d84000 0 0x2500>, 2069 <0 0x01d90000 0 0x8000>; 2070 reg-names = "std", "ice"; 2071 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 2072 phys = <&ufs_mem_phy_lanes>; 2073 phy-names = "ufsphy"; 2074 lanes-per-direction = <2>; 2075 power-domains = <&gcc UFS_PHY_GDSC>; 2076 #reset-cells = <1>; 2077 resets = <&gcc GCC_UFS_PHY_BCR>; 2078 reset-names = "rst"; 2079 2080 iommus = <&apps_smmu 0x100 0xf>; 2081 2082 clock-names = 2083 "core_clk", 2084 "bus_aggr_clk", 2085 "iface_clk", 2086 "core_clk_unipro", 2087 "ref_clk", 2088 "tx_lane0_sync_clk", 2089 "rx_lane0_sync_clk", 2090 "rx_lane1_sync_clk", 2091 "ice_core_clk"; 2092 clocks = 2093 <&gcc GCC_UFS_PHY_AXI_CLK>, 2094 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2095 <&gcc GCC_UFS_PHY_AHB_CLK>, 2096 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 2097 <&rpmhcc RPMH_CXO_CLK>, 2098 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 2099 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 2100 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, 2101 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 2102 freq-table-hz = 2103 <50000000 200000000>, 2104 <0 0>, 2105 <0 0>, 2106 <37500000 150000000>, 2107 <0 0>, 2108 <0 0>, 2109 <0 0>, 2110 <0 0>, 2111 <0 300000000>; 2112 2113 status = "disabled"; 2114 }; 2115 2116 ufs_mem_phy: phy@1d87000 { 2117 compatible = "qcom,sdm845-qmp-ufs-phy"; 2118 reg = <0 0x01d87000 0 0x18c>; 2119 #address-cells = <2>; 2120 #size-cells = <2>; 2121 ranges; 2122 clock-names = "ref", 2123 "ref_aux"; 2124 clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, 2125 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 2126 2127 resets = <&ufs_mem_hc 0>; 2128 reset-names = "ufsphy"; 2129 status = "disabled"; 2130 2131 ufs_mem_phy_lanes: lanes@1d87400 { 2132 reg = <0 0x01d87400 0 0x108>, 2133 <0 0x01d87600 0 0x1e0>, 2134 <0 0x01d87c00 0 0x1dc>, 2135 <0 0x01d87800 0 0x108>, 2136 <0 0x01d87a00 0 0x1e0>; 2137 #phy-cells = <0>; 2138 }; 2139 }; 2140 2141 ipa: ipa@1e40000 { 2142 compatible = "qcom,sdm845-ipa"; 2143 2144 iommus = <&apps_smmu 0x720 0x0>, 2145 <&apps_smmu 0x722 0x0>; 2146 reg = <0 0x1e40000 0 0x7000>, 2147 <0 0x1e47000 0 0x2000>, 2148 <0 0x1e04000 0 0x2c000>; 2149 reg-names = "ipa-reg", 2150 "ipa-shared", 2151 "gsi"; 2152 2153 interrupts-extended = <&intc 0 311 IRQ_TYPE_EDGE_RISING>, 2154 <&intc 0 432 IRQ_TYPE_LEVEL_HIGH>, 2155 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2156 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 2157 interrupt-names = "ipa", 2158 "gsi", 2159 "ipa-clock-query", 2160 "ipa-setup-ready"; 2161 2162 clocks = <&rpmhcc RPMH_IPA_CLK>; 2163 clock-names = "core"; 2164 2165 interconnects = <&aggre2_noc MASTER_IPA 0 &mem_noc SLAVE_EBI1 0>, 2166 <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_IMEM 0>, 2167 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>; 2168 interconnect-names = "memory", 2169 "imem", 2170 "config"; 2171 2172 qcom,smem-states = <&ipa_smp2p_out 0>, 2173 <&ipa_smp2p_out 1>; 2174 qcom,smem-state-names = "ipa-clock-enabled-valid", 2175 "ipa-clock-enabled"; 2176 2177 modem-remoteproc = <&mss_pil>; 2178 2179 status = "disabled"; 2180 }; 2181 2182 tcsr_mutex_regs: syscon@1f40000 { 2183 compatible = "syscon"; 2184 reg = <0 0x01f40000 0 0x40000>; 2185 }; 2186 2187 tlmm: pinctrl@3400000 { 2188 compatible = "qcom,sdm845-pinctrl"; 2189 reg = <0 0x03400000 0 0xc00000>; 2190 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 2191 gpio-controller; 2192 #gpio-cells = <2>; 2193 interrupt-controller; 2194 #interrupt-cells = <2>; 2195 gpio-ranges = <&tlmm 0 0 151>; 2196 wakeup-parent = <&pdc_intc>; 2197 2198 cci0_default: cci0-default { 2199 /* SDA, SCL */ 2200 pins = "gpio17", "gpio18"; 2201 function = "cci_i2c"; 2202 2203 bias-pull-up; 2204 drive-strength = <2>; /* 2 mA */ 2205 }; 2206 2207 cci0_sleep: cci0-sleep { 2208 /* SDA, SCL */ 2209 pins = "gpio17", "gpio18"; 2210 function = "cci_i2c"; 2211 2212 drive-strength = <2>; /* 2 mA */ 2213 bias-pull-down; 2214 }; 2215 2216 cci1_default: cci1-default { 2217 /* SDA, SCL */ 2218 pins = "gpio19", "gpio20"; 2219 function = "cci_i2c"; 2220 2221 bias-pull-up; 2222 drive-strength = <2>; /* 2 mA */ 2223 }; 2224 2225 cci1_sleep: cci1-sleep { 2226 /* SDA, SCL */ 2227 pins = "gpio19", "gpio20"; 2228 function = "cci_i2c"; 2229 2230 drive-strength = <2>; /* 2 mA */ 2231 bias-pull-down; 2232 }; 2233 2234 qspi_clk: qspi-clk { 2235 pinmux { 2236 pins = "gpio95"; 2237 function = "qspi_clk"; 2238 }; 2239 }; 2240 2241 qspi_cs0: qspi-cs0 { 2242 pinmux { 2243 pins = "gpio90"; 2244 function = "qspi_cs"; 2245 }; 2246 }; 2247 2248 qspi_cs1: qspi-cs1 { 2249 pinmux { 2250 pins = "gpio89"; 2251 function = "qspi_cs"; 2252 }; 2253 }; 2254 2255 qspi_data01: qspi-data01 { 2256 pinmux-data { 2257 pins = "gpio91", "gpio92"; 2258 function = "qspi_data"; 2259 }; 2260 }; 2261 2262 qspi_data12: qspi-data12 { 2263 pinmux-data { 2264 pins = "gpio93", "gpio94"; 2265 function = "qspi_data"; 2266 }; 2267 }; 2268 2269 qup_i2c0_default: qup-i2c0-default { 2270 pinmux { 2271 pins = "gpio0", "gpio1"; 2272 function = "qup0"; 2273 }; 2274 }; 2275 2276 qup_i2c1_default: qup-i2c1-default { 2277 pinmux { 2278 pins = "gpio17", "gpio18"; 2279 function = "qup1"; 2280 }; 2281 }; 2282 2283 qup_i2c2_default: qup-i2c2-default { 2284 pinmux { 2285 pins = "gpio27", "gpio28"; 2286 function = "qup2"; 2287 }; 2288 }; 2289 2290 qup_i2c3_default: qup-i2c3-default { 2291 pinmux { 2292 pins = "gpio41", "gpio42"; 2293 function = "qup3"; 2294 }; 2295 }; 2296 2297 qup_i2c4_default: qup-i2c4-default { 2298 pinmux { 2299 pins = "gpio89", "gpio90"; 2300 function = "qup4"; 2301 }; 2302 }; 2303 2304 qup_i2c5_default: qup-i2c5-default { 2305 pinmux { 2306 pins = "gpio85", "gpio86"; 2307 function = "qup5"; 2308 }; 2309 }; 2310 2311 qup_i2c6_default: qup-i2c6-default { 2312 pinmux { 2313 pins = "gpio45", "gpio46"; 2314 function = "qup6"; 2315 }; 2316 }; 2317 2318 qup_i2c7_default: qup-i2c7-default { 2319 pinmux { 2320 pins = "gpio93", "gpio94"; 2321 function = "qup7"; 2322 }; 2323 }; 2324 2325 qup_i2c8_default: qup-i2c8-default { 2326 pinmux { 2327 pins = "gpio65", "gpio66"; 2328 function = "qup8"; 2329 }; 2330 }; 2331 2332 qup_i2c9_default: qup-i2c9-default { 2333 pinmux { 2334 pins = "gpio6", "gpio7"; 2335 function = "qup9"; 2336 }; 2337 }; 2338 2339 qup_i2c10_default: qup-i2c10-default { 2340 pinmux { 2341 pins = "gpio55", "gpio56"; 2342 function = "qup10"; 2343 }; 2344 }; 2345 2346 qup_i2c11_default: qup-i2c11-default { 2347 pinmux { 2348 pins = "gpio31", "gpio32"; 2349 function = "qup11"; 2350 }; 2351 }; 2352 2353 qup_i2c12_default: qup-i2c12-default { 2354 pinmux { 2355 pins = "gpio49", "gpio50"; 2356 function = "qup12"; 2357 }; 2358 }; 2359 2360 qup_i2c13_default: qup-i2c13-default { 2361 pinmux { 2362 pins = "gpio105", "gpio106"; 2363 function = "qup13"; 2364 }; 2365 }; 2366 2367 qup_i2c14_default: qup-i2c14-default { 2368 pinmux { 2369 pins = "gpio33", "gpio34"; 2370 function = "qup14"; 2371 }; 2372 }; 2373 2374 qup_i2c15_default: qup-i2c15-default { 2375 pinmux { 2376 pins = "gpio81", "gpio82"; 2377 function = "qup15"; 2378 }; 2379 }; 2380 2381 qup_spi0_default: qup-spi0-default { 2382 pinmux { 2383 pins = "gpio0", "gpio1", 2384 "gpio2", "gpio3"; 2385 function = "qup0"; 2386 }; 2387 }; 2388 2389 qup_spi1_default: qup-spi1-default { 2390 pinmux { 2391 pins = "gpio17", "gpio18", 2392 "gpio19", "gpio20"; 2393 function = "qup1"; 2394 }; 2395 }; 2396 2397 qup_spi2_default: qup-spi2-default { 2398 pinmux { 2399 pins = "gpio27", "gpio28", 2400 "gpio29", "gpio30"; 2401 function = "qup2"; 2402 }; 2403 }; 2404 2405 qup_spi3_default: qup-spi3-default { 2406 pinmux { 2407 pins = "gpio41", "gpio42", 2408 "gpio43", "gpio44"; 2409 function = "qup3"; 2410 }; 2411 }; 2412 2413 qup_spi4_default: qup-spi4-default { 2414 pinmux { 2415 pins = "gpio89", "gpio90", 2416 "gpio91", "gpio92"; 2417 function = "qup4"; 2418 }; 2419 }; 2420 2421 qup_spi5_default: qup-spi5-default { 2422 pinmux { 2423 pins = "gpio85", "gpio86", 2424 "gpio87", "gpio88"; 2425 function = "qup5"; 2426 }; 2427 }; 2428 2429 qup_spi6_default: qup-spi6-default { 2430 pinmux { 2431 pins = "gpio45", "gpio46", 2432 "gpio47", "gpio48"; 2433 function = "qup6"; 2434 }; 2435 }; 2436 2437 qup_spi7_default: qup-spi7-default { 2438 pinmux { 2439 pins = "gpio93", "gpio94", 2440 "gpio95", "gpio96"; 2441 function = "qup7"; 2442 }; 2443 }; 2444 2445 qup_spi8_default: qup-spi8-default { 2446 pinmux { 2447 pins = "gpio65", "gpio66", 2448 "gpio67", "gpio68"; 2449 function = "qup8"; 2450 }; 2451 }; 2452 2453 qup_spi9_default: qup-spi9-default { 2454 pinmux { 2455 pins = "gpio6", "gpio7", 2456 "gpio4", "gpio5"; 2457 function = "qup9"; 2458 }; 2459 }; 2460 2461 qup_spi10_default: qup-spi10-default { 2462 pinmux { 2463 pins = "gpio55", "gpio56", 2464 "gpio53", "gpio54"; 2465 function = "qup10"; 2466 }; 2467 }; 2468 2469 qup_spi11_default: qup-spi11-default { 2470 pinmux { 2471 pins = "gpio31", "gpio32", 2472 "gpio33", "gpio34"; 2473 function = "qup11"; 2474 }; 2475 }; 2476 2477 qup_spi12_default: qup-spi12-default { 2478 pinmux { 2479 pins = "gpio49", "gpio50", 2480 "gpio51", "gpio52"; 2481 function = "qup12"; 2482 }; 2483 }; 2484 2485 qup_spi13_default: qup-spi13-default { 2486 pinmux { 2487 pins = "gpio105", "gpio106", 2488 "gpio107", "gpio108"; 2489 function = "qup13"; 2490 }; 2491 }; 2492 2493 qup_spi14_default: qup-spi14-default { 2494 pinmux { 2495 pins = "gpio33", "gpio34", 2496 "gpio31", "gpio32"; 2497 function = "qup14"; 2498 }; 2499 }; 2500 2501 qup_spi15_default: qup-spi15-default { 2502 pinmux { 2503 pins = "gpio81", "gpio82", 2504 "gpio83", "gpio84"; 2505 function = "qup15"; 2506 }; 2507 }; 2508 2509 qup_uart0_default: qup-uart0-default { 2510 pinmux { 2511 pins = "gpio2", "gpio3"; 2512 function = "qup0"; 2513 }; 2514 }; 2515 2516 qup_uart1_default: qup-uart1-default { 2517 pinmux { 2518 pins = "gpio19", "gpio20"; 2519 function = "qup1"; 2520 }; 2521 }; 2522 2523 qup_uart2_default: qup-uart2-default { 2524 pinmux { 2525 pins = "gpio29", "gpio30"; 2526 function = "qup2"; 2527 }; 2528 }; 2529 2530 qup_uart3_default: qup-uart3-default { 2531 pinmux { 2532 pins = "gpio43", "gpio44"; 2533 function = "qup3"; 2534 }; 2535 }; 2536 2537 qup_uart4_default: qup-uart4-default { 2538 pinmux { 2539 pins = "gpio91", "gpio92"; 2540 function = "qup4"; 2541 }; 2542 }; 2543 2544 qup_uart5_default: qup-uart5-default { 2545 pinmux { 2546 pins = "gpio87", "gpio88"; 2547 function = "qup5"; 2548 }; 2549 }; 2550 2551 qup_uart6_default: qup-uart6-default { 2552 pinmux { 2553 pins = "gpio47", "gpio48"; 2554 function = "qup6"; 2555 }; 2556 }; 2557 2558 qup_uart7_default: qup-uart7-default { 2559 pinmux { 2560 pins = "gpio95", "gpio96"; 2561 function = "qup7"; 2562 }; 2563 }; 2564 2565 qup_uart8_default: qup-uart8-default { 2566 pinmux { 2567 pins = "gpio67", "gpio68"; 2568 function = "qup8"; 2569 }; 2570 }; 2571 2572 qup_uart9_default: qup-uart9-default { 2573 pinmux { 2574 pins = "gpio4", "gpio5"; 2575 function = "qup9"; 2576 }; 2577 }; 2578 2579 qup_uart10_default: qup-uart10-default { 2580 pinmux { 2581 pins = "gpio53", "gpio54"; 2582 function = "qup10"; 2583 }; 2584 }; 2585 2586 qup_uart11_default: qup-uart11-default { 2587 pinmux { 2588 pins = "gpio33", "gpio34"; 2589 function = "qup11"; 2590 }; 2591 }; 2592 2593 qup_uart12_default: qup-uart12-default { 2594 pinmux { 2595 pins = "gpio51", "gpio52"; 2596 function = "qup12"; 2597 }; 2598 }; 2599 2600 qup_uart13_default: qup-uart13-default { 2601 pinmux { 2602 pins = "gpio107", "gpio108"; 2603 function = "qup13"; 2604 }; 2605 }; 2606 2607 qup_uart14_default: qup-uart14-default { 2608 pinmux { 2609 pins = "gpio31", "gpio32"; 2610 function = "qup14"; 2611 }; 2612 }; 2613 2614 qup_uart15_default: qup-uart15-default { 2615 pinmux { 2616 pins = "gpio83", "gpio84"; 2617 function = "qup15"; 2618 }; 2619 }; 2620 2621 quat_mi2s_sleep: quat_mi2s_sleep { 2622 mux { 2623 pins = "gpio58", "gpio59"; 2624 function = "gpio"; 2625 }; 2626 2627 config { 2628 pins = "gpio58", "gpio59"; 2629 drive-strength = <2>; 2630 bias-pull-down; 2631 input-enable; 2632 }; 2633 }; 2634 2635 quat_mi2s_active: quat_mi2s_active { 2636 mux { 2637 pins = "gpio58", "gpio59"; 2638 function = "qua_mi2s"; 2639 }; 2640 2641 config { 2642 pins = "gpio58", "gpio59"; 2643 drive-strength = <8>; 2644 bias-disable; 2645 output-high; 2646 }; 2647 }; 2648 2649 quat_mi2s_sd0_sleep: quat_mi2s_sd0_sleep { 2650 mux { 2651 pins = "gpio60"; 2652 function = "gpio"; 2653 }; 2654 2655 config { 2656 pins = "gpio60"; 2657 drive-strength = <2>; 2658 bias-pull-down; 2659 input-enable; 2660 }; 2661 }; 2662 2663 quat_mi2s_sd0_active: quat_mi2s_sd0_active { 2664 mux { 2665 pins = "gpio60"; 2666 function = "qua_mi2s"; 2667 }; 2668 2669 config { 2670 pins = "gpio60"; 2671 drive-strength = <8>; 2672 bias-disable; 2673 }; 2674 }; 2675 2676 quat_mi2s_sd1_sleep: quat_mi2s_sd1_sleep { 2677 mux { 2678 pins = "gpio61"; 2679 function = "gpio"; 2680 }; 2681 2682 config { 2683 pins = "gpio61"; 2684 drive-strength = <2>; 2685 bias-pull-down; 2686 input-enable; 2687 }; 2688 }; 2689 2690 quat_mi2s_sd1_active: quat_mi2s_sd1_active { 2691 mux { 2692 pins = "gpio61"; 2693 function = "qua_mi2s"; 2694 }; 2695 2696 config { 2697 pins = "gpio61"; 2698 drive-strength = <8>; 2699 bias-disable; 2700 }; 2701 }; 2702 2703 quat_mi2s_sd2_sleep: quat_mi2s_sd2_sleep { 2704 mux { 2705 pins = "gpio62"; 2706 function = "gpio"; 2707 }; 2708 2709 config { 2710 pins = "gpio62"; 2711 drive-strength = <2>; 2712 bias-pull-down; 2713 input-enable; 2714 }; 2715 }; 2716 2717 quat_mi2s_sd2_active: quat_mi2s_sd2_active { 2718 mux { 2719 pins = "gpio62"; 2720 function = "qua_mi2s"; 2721 }; 2722 2723 config { 2724 pins = "gpio62"; 2725 drive-strength = <8>; 2726 bias-disable; 2727 }; 2728 }; 2729 2730 quat_mi2s_sd3_sleep: quat_mi2s_sd3_sleep { 2731 mux { 2732 pins = "gpio63"; 2733 function = "gpio"; 2734 }; 2735 2736 config { 2737 pins = "gpio63"; 2738 drive-strength = <2>; 2739 bias-pull-down; 2740 input-enable; 2741 }; 2742 }; 2743 2744 quat_mi2s_sd3_active: quat_mi2s_sd3_active { 2745 mux { 2746 pins = "gpio63"; 2747 function = "qua_mi2s"; 2748 }; 2749 2750 config { 2751 pins = "gpio63"; 2752 drive-strength = <8>; 2753 bias-disable; 2754 }; 2755 }; 2756 }; 2757 2758 mss_pil: remoteproc@4080000 { 2759 compatible = "qcom,sdm845-mss-pil"; 2760 reg = <0 0x04080000 0 0x408>, <0 0x04180000 0 0x48>; 2761 reg-names = "qdsp6", "rmb"; 2762 2763 interrupts-extended = 2764 <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, 2765 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2766 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2767 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2768 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 2769 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 2770 interrupt-names = "wdog", "fatal", "ready", 2771 "handover", "stop-ack", 2772 "shutdown-ack"; 2773 2774 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 2775 <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>, 2776 <&gcc GCC_BOOT_ROM_AHB_CLK>, 2777 <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>, 2778 <&gcc GCC_MSS_SNOC_AXI_CLK>, 2779 <&gcc GCC_MSS_MFAB_AXIS_CLK>, 2780 <&gcc GCC_PRNG_AHB_CLK>, 2781 <&rpmhcc RPMH_CXO_CLK>; 2782 clock-names = "iface", "bus", "mem", "gpll0_mss", 2783 "snoc_axi", "mnoc_axi", "prng", "xo"; 2784 2785 qcom,smem-states = <&modem_smp2p_out 0>; 2786 qcom,smem-state-names = "stop"; 2787 2788 resets = <&aoss_reset AOSS_CC_MSS_RESTART>, 2789 <&pdc_reset PDC_MODEM_SYNC_RESET>; 2790 reset-names = "mss_restart", "pdc_reset"; 2791 2792 qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>; 2793 2794 power-domains = <&aoss_qmp 2>, 2795 <&rpmhpd SDM845_CX>, 2796 <&rpmhpd SDM845_MX>, 2797 <&rpmhpd SDM845_MSS>; 2798 power-domain-names = "load_state", "cx", "mx", "mss"; 2799 2800 mba { 2801 memory-region = <&mba_region>; 2802 }; 2803 2804 mpss { 2805 memory-region = <&mpss_region>; 2806 }; 2807 2808 glink-edge { 2809 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; 2810 label = "modem"; 2811 qcom,remote-pid = <1>; 2812 mboxes = <&apss_shared 12>; 2813 }; 2814 }; 2815 2816 gpucc: clock-controller@5090000 { 2817 compatible = "qcom,sdm845-gpucc"; 2818 reg = <0 0x05090000 0 0x9000>; 2819 #clock-cells = <1>; 2820 #reset-cells = <1>; 2821 #power-domain-cells = <1>; 2822 clocks = <&rpmhcc RPMH_CXO_CLK>, 2823 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2824 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2825 clock-names = "bi_tcxo", 2826 "gcc_gpu_gpll0_clk_src", 2827 "gcc_gpu_gpll0_div_clk_src"; 2828 }; 2829 2830 stm@6002000 { 2831 compatible = "arm,coresight-stm", "arm,primecell"; 2832 reg = <0 0x06002000 0 0x1000>, 2833 <0 0x16280000 0 0x180000>; 2834 reg-names = "stm-base", "stm-stimulus-base"; 2835 2836 clocks = <&aoss_qmp>; 2837 clock-names = "apb_pclk"; 2838 2839 out-ports { 2840 port { 2841 stm_out: endpoint { 2842 remote-endpoint = 2843 <&funnel0_in7>; 2844 }; 2845 }; 2846 }; 2847 }; 2848 2849 funnel@6041000 { 2850 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2851 reg = <0 0x06041000 0 0x1000>; 2852 2853 clocks = <&aoss_qmp>; 2854 clock-names = "apb_pclk"; 2855 2856 out-ports { 2857 port { 2858 funnel0_out: endpoint { 2859 remote-endpoint = 2860 <&merge_funnel_in0>; 2861 }; 2862 }; 2863 }; 2864 2865 in-ports { 2866 #address-cells = <1>; 2867 #size-cells = <0>; 2868 2869 port@7 { 2870 reg = <7>; 2871 funnel0_in7: endpoint { 2872 remote-endpoint = <&stm_out>; 2873 }; 2874 }; 2875 }; 2876 }; 2877 2878 funnel@6043000 { 2879 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2880 reg = <0 0x06043000 0 0x1000>; 2881 2882 clocks = <&aoss_qmp>; 2883 clock-names = "apb_pclk"; 2884 2885 out-ports { 2886 port { 2887 funnel2_out: endpoint { 2888 remote-endpoint = 2889 <&merge_funnel_in2>; 2890 }; 2891 }; 2892 }; 2893 2894 in-ports { 2895 #address-cells = <1>; 2896 #size-cells = <0>; 2897 2898 port@5 { 2899 reg = <5>; 2900 funnel2_in5: endpoint { 2901 remote-endpoint = 2902 <&apss_merge_funnel_out>; 2903 }; 2904 }; 2905 }; 2906 }; 2907 2908 funnel@6045000 { 2909 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2910 reg = <0 0x06045000 0 0x1000>; 2911 2912 clocks = <&aoss_qmp>; 2913 clock-names = "apb_pclk"; 2914 2915 out-ports { 2916 port { 2917 merge_funnel_out: endpoint { 2918 remote-endpoint = <&etf_in>; 2919 }; 2920 }; 2921 }; 2922 2923 in-ports { 2924 #address-cells = <1>; 2925 #size-cells = <0>; 2926 2927 port@0 { 2928 reg = <0>; 2929 merge_funnel_in0: endpoint { 2930 remote-endpoint = 2931 <&funnel0_out>; 2932 }; 2933 }; 2934 2935 port@2 { 2936 reg = <2>; 2937 merge_funnel_in2: endpoint { 2938 remote-endpoint = 2939 <&funnel2_out>; 2940 }; 2941 }; 2942 }; 2943 }; 2944 2945 replicator@6046000 { 2946 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2947 reg = <0 0x06046000 0 0x1000>; 2948 2949 clocks = <&aoss_qmp>; 2950 clock-names = "apb_pclk"; 2951 2952 out-ports { 2953 port { 2954 replicator_out: endpoint { 2955 remote-endpoint = <&etr_in>; 2956 }; 2957 }; 2958 }; 2959 2960 in-ports { 2961 port { 2962 replicator_in: endpoint { 2963 remote-endpoint = <&etf_out>; 2964 }; 2965 }; 2966 }; 2967 }; 2968 2969 etf@6047000 { 2970 compatible = "arm,coresight-tmc", "arm,primecell"; 2971 reg = <0 0x06047000 0 0x1000>; 2972 2973 clocks = <&aoss_qmp>; 2974 clock-names = "apb_pclk"; 2975 2976 out-ports { 2977 port { 2978 etf_out: endpoint { 2979 remote-endpoint = 2980 <&replicator_in>; 2981 }; 2982 }; 2983 }; 2984 2985 in-ports { 2986 #address-cells = <1>; 2987 #size-cells = <0>; 2988 2989 port@1 { 2990 reg = <1>; 2991 etf_in: endpoint { 2992 remote-endpoint = 2993 <&merge_funnel_out>; 2994 }; 2995 }; 2996 }; 2997 }; 2998 2999 etr@6048000 { 3000 compatible = "arm,coresight-tmc", "arm,primecell"; 3001 reg = <0 0x06048000 0 0x1000>; 3002 3003 clocks = <&aoss_qmp>; 3004 clock-names = "apb_pclk"; 3005 arm,scatter-gather; 3006 3007 in-ports { 3008 port { 3009 etr_in: endpoint { 3010 remote-endpoint = 3011 <&replicator_out>; 3012 }; 3013 }; 3014 }; 3015 }; 3016 3017 etm@7040000 { 3018 compatible = "arm,coresight-etm4x", "arm,primecell"; 3019 reg = <0 0x07040000 0 0x1000>; 3020 3021 cpu = <&CPU0>; 3022 3023 clocks = <&aoss_qmp>; 3024 clock-names = "apb_pclk"; 3025 arm,coresight-loses-context-with-cpu; 3026 3027 out-ports { 3028 port { 3029 etm0_out: endpoint { 3030 remote-endpoint = 3031 <&apss_funnel_in0>; 3032 }; 3033 }; 3034 }; 3035 }; 3036 3037 etm@7140000 { 3038 compatible = "arm,coresight-etm4x", "arm,primecell"; 3039 reg = <0 0x07140000 0 0x1000>; 3040 3041 cpu = <&CPU1>; 3042 3043 clocks = <&aoss_qmp>; 3044 clock-names = "apb_pclk"; 3045 arm,coresight-loses-context-with-cpu; 3046 3047 out-ports { 3048 port { 3049 etm1_out: endpoint { 3050 remote-endpoint = 3051 <&apss_funnel_in1>; 3052 }; 3053 }; 3054 }; 3055 }; 3056 3057 etm@7240000 { 3058 compatible = "arm,coresight-etm4x", "arm,primecell"; 3059 reg = <0 0x07240000 0 0x1000>; 3060 3061 cpu = <&CPU2>; 3062 3063 clocks = <&aoss_qmp>; 3064 clock-names = "apb_pclk"; 3065 arm,coresight-loses-context-with-cpu; 3066 3067 out-ports { 3068 port { 3069 etm2_out: endpoint { 3070 remote-endpoint = 3071 <&apss_funnel_in2>; 3072 }; 3073 }; 3074 }; 3075 }; 3076 3077 etm@7340000 { 3078 compatible = "arm,coresight-etm4x", "arm,primecell"; 3079 reg = <0 0x07340000 0 0x1000>; 3080 3081 cpu = <&CPU3>; 3082 3083 clocks = <&aoss_qmp>; 3084 clock-names = "apb_pclk"; 3085 arm,coresight-loses-context-with-cpu; 3086 3087 out-ports { 3088 port { 3089 etm3_out: endpoint { 3090 remote-endpoint = 3091 <&apss_funnel_in3>; 3092 }; 3093 }; 3094 }; 3095 }; 3096 3097 etm@7440000 { 3098 compatible = "arm,coresight-etm4x", "arm,primecell"; 3099 reg = <0 0x07440000 0 0x1000>; 3100 3101 cpu = <&CPU4>; 3102 3103 clocks = <&aoss_qmp>; 3104 clock-names = "apb_pclk"; 3105 arm,coresight-loses-context-with-cpu; 3106 3107 out-ports { 3108 port { 3109 etm4_out: endpoint { 3110 remote-endpoint = 3111 <&apss_funnel_in4>; 3112 }; 3113 }; 3114 }; 3115 }; 3116 3117 etm@7540000 { 3118 compatible = "arm,coresight-etm4x", "arm,primecell"; 3119 reg = <0 0x07540000 0 0x1000>; 3120 3121 cpu = <&CPU5>; 3122 3123 clocks = <&aoss_qmp>; 3124 clock-names = "apb_pclk"; 3125 arm,coresight-loses-context-with-cpu; 3126 3127 out-ports { 3128 port { 3129 etm5_out: endpoint { 3130 remote-endpoint = 3131 <&apss_funnel_in5>; 3132 }; 3133 }; 3134 }; 3135 }; 3136 3137 etm@7640000 { 3138 compatible = "arm,coresight-etm4x", "arm,primecell"; 3139 reg = <0 0x07640000 0 0x1000>; 3140 3141 cpu = <&CPU6>; 3142 3143 clocks = <&aoss_qmp>; 3144 clock-names = "apb_pclk"; 3145 arm,coresight-loses-context-with-cpu; 3146 3147 out-ports { 3148 port { 3149 etm6_out: endpoint { 3150 remote-endpoint = 3151 <&apss_funnel_in6>; 3152 }; 3153 }; 3154 }; 3155 }; 3156 3157 etm@7740000 { 3158 compatible = "arm,coresight-etm4x", "arm,primecell"; 3159 reg = <0 0x07740000 0 0x1000>; 3160 3161 cpu = <&CPU7>; 3162 3163 clocks = <&aoss_qmp>; 3164 clock-names = "apb_pclk"; 3165 arm,coresight-loses-context-with-cpu; 3166 3167 out-ports { 3168 port { 3169 etm7_out: endpoint { 3170 remote-endpoint = 3171 <&apss_funnel_in7>; 3172 }; 3173 }; 3174 }; 3175 }; 3176 3177 funnel@7800000 { /* APSS Funnel */ 3178 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3179 reg = <0 0x07800000 0 0x1000>; 3180 3181 clocks = <&aoss_qmp>; 3182 clock-names = "apb_pclk"; 3183 3184 out-ports { 3185 port { 3186 apss_funnel_out: endpoint { 3187 remote-endpoint = 3188 <&apss_merge_funnel_in>; 3189 }; 3190 }; 3191 }; 3192 3193 in-ports { 3194 #address-cells = <1>; 3195 #size-cells = <0>; 3196 3197 port@0 { 3198 reg = <0>; 3199 apss_funnel_in0: endpoint { 3200 remote-endpoint = 3201 <&etm0_out>; 3202 }; 3203 }; 3204 3205 port@1 { 3206 reg = <1>; 3207 apss_funnel_in1: endpoint { 3208 remote-endpoint = 3209 <&etm1_out>; 3210 }; 3211 }; 3212 3213 port@2 { 3214 reg = <2>; 3215 apss_funnel_in2: endpoint { 3216 remote-endpoint = 3217 <&etm2_out>; 3218 }; 3219 }; 3220 3221 port@3 { 3222 reg = <3>; 3223 apss_funnel_in3: endpoint { 3224 remote-endpoint = 3225 <&etm3_out>; 3226 }; 3227 }; 3228 3229 port@4 { 3230 reg = <4>; 3231 apss_funnel_in4: endpoint { 3232 remote-endpoint = 3233 <&etm4_out>; 3234 }; 3235 }; 3236 3237 port@5 { 3238 reg = <5>; 3239 apss_funnel_in5: endpoint { 3240 remote-endpoint = 3241 <&etm5_out>; 3242 }; 3243 }; 3244 3245 port@6 { 3246 reg = <6>; 3247 apss_funnel_in6: endpoint { 3248 remote-endpoint = 3249 <&etm6_out>; 3250 }; 3251 }; 3252 3253 port@7 { 3254 reg = <7>; 3255 apss_funnel_in7: endpoint { 3256 remote-endpoint = 3257 <&etm7_out>; 3258 }; 3259 }; 3260 }; 3261 }; 3262 3263 funnel@7810000 { 3264 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3265 reg = <0 0x07810000 0 0x1000>; 3266 3267 clocks = <&aoss_qmp>; 3268 clock-names = "apb_pclk"; 3269 3270 out-ports { 3271 port { 3272 apss_merge_funnel_out: endpoint { 3273 remote-endpoint = 3274 <&funnel2_in5>; 3275 }; 3276 }; 3277 }; 3278 3279 in-ports { 3280 port { 3281 apss_merge_funnel_in: endpoint { 3282 remote-endpoint = 3283 <&apss_funnel_out>; 3284 }; 3285 }; 3286 }; 3287 }; 3288 3289 sdhc_2: sdhci@8804000 { 3290 compatible = "qcom,sdm845-sdhci", "qcom,sdhci-msm-v5"; 3291 reg = <0 0x08804000 0 0x1000>; 3292 3293 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 3294 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 3295 interrupt-names = "hc_irq", "pwr_irq"; 3296 3297 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3298 <&gcc GCC_SDCC2_APPS_CLK>; 3299 clock-names = "iface", "core"; 3300 iommus = <&apps_smmu 0xa0 0xf>; 3301 power-domains = <&rpmhpd SDM845_CX>; 3302 operating-points-v2 = <&sdhc2_opp_table>; 3303 3304 status = "disabled"; 3305 3306 sdhc2_opp_table: sdhc2-opp-table { 3307 compatible = "operating-points-v2"; 3308 3309 opp-9600000 { 3310 opp-hz = /bits/ 64 <9600000>; 3311 required-opps = <&rpmhpd_opp_min_svs>; 3312 }; 3313 3314 opp-19200000 { 3315 opp-hz = /bits/ 64 <19200000>; 3316 required-opps = <&rpmhpd_opp_low_svs>; 3317 }; 3318 3319 opp-100000000 { 3320 opp-hz = /bits/ 64 <100000000>; 3321 required-opps = <&rpmhpd_opp_svs>; 3322 }; 3323 3324 opp-201500000 { 3325 opp-hz = /bits/ 64 <201500000>; 3326 required-opps = <&rpmhpd_opp_svs_l1>; 3327 }; 3328 }; 3329 }; 3330 3331 qspi_opp_table: qspi-opp-table { 3332 compatible = "operating-points-v2"; 3333 3334 opp-19200000 { 3335 opp-hz = /bits/ 64 <19200000>; 3336 required-opps = <&rpmhpd_opp_min_svs>; 3337 }; 3338 3339 opp-100000000 { 3340 opp-hz = /bits/ 64 <100000000>; 3341 required-opps = <&rpmhpd_opp_low_svs>; 3342 }; 3343 3344 opp-150000000 { 3345 opp-hz = /bits/ 64 <150000000>; 3346 required-opps = <&rpmhpd_opp_svs>; 3347 }; 3348 3349 opp-300000000 { 3350 opp-hz = /bits/ 64 <300000000>; 3351 required-opps = <&rpmhpd_opp_nom>; 3352 }; 3353 }; 3354 3355 qspi: spi@88df000 { 3356 compatible = "qcom,sdm845-qspi", "qcom,qspi-v1"; 3357 reg = <0 0x088df000 0 0x600>; 3358 #address-cells = <1>; 3359 #size-cells = <0>; 3360 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 3361 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 3362 <&gcc GCC_QSPI_CORE_CLK>; 3363 clock-names = "iface", "core"; 3364 power-domains = <&rpmhpd SDM845_CX>; 3365 operating-points-v2 = <&qspi_opp_table>; 3366 status = "disabled"; 3367 }; 3368 3369 slim: slim@171c0000 { 3370 compatible = "qcom,slim-ngd-v2.1.0"; 3371 reg = <0 0x171c0000 0 0x2c000>; 3372 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 3373 3374 qcom,apps-ch-pipes = <0x780000>; 3375 qcom,ea-pc = <0x270>; 3376 status = "okay"; 3377 dmas = <&slimbam 3>, <&slimbam 4>, 3378 <&slimbam 5>, <&slimbam 6>; 3379 dma-names = "rx", "tx", "tx2", "rx2"; 3380 3381 iommus = <&apps_smmu 0x1806 0x0>; 3382 #address-cells = <1>; 3383 #size-cells = <0>; 3384 3385 ngd@1 { 3386 reg = <1>; 3387 #address-cells = <2>; 3388 #size-cells = <0>; 3389 3390 wcd9340_ifd: ifd@0{ 3391 compatible = "slim217,250"; 3392 reg = <0 0>; 3393 }; 3394 3395 wcd9340: codec@1{ 3396 compatible = "slim217,250"; 3397 reg = <1 0>; 3398 slim-ifc-dev = <&wcd9340_ifd>; 3399 3400 #sound-dai-cells = <1>; 3401 3402 interrupts-extended = <&tlmm 54 IRQ_TYPE_LEVEL_HIGH>; 3403 interrupt-controller; 3404 #interrupt-cells = <1>; 3405 3406 #clock-cells = <0>; 3407 clock-frequency = <9600000>; 3408 clock-output-names = "mclk"; 3409 qcom,micbias1-microvolt = <1800000>; 3410 qcom,micbias2-microvolt = <1800000>; 3411 qcom,micbias3-microvolt = <1800000>; 3412 qcom,micbias4-microvolt = <1800000>; 3413 3414 #address-cells = <1>; 3415 #size-cells = <1>; 3416 3417 wcdgpio: gpio-controller@42 { 3418 compatible = "qcom,wcd9340-gpio"; 3419 gpio-controller; 3420 #gpio-cells = <2>; 3421 reg = <0x42 0x2>; 3422 }; 3423 3424 swm: swm@c85 { 3425 compatible = "qcom,soundwire-v1.3.0"; 3426 reg = <0xc85 0x40>; 3427 interrupts-extended = <&wcd9340 20>; 3428 3429 qcom,dout-ports = <6>; 3430 qcom,din-ports = <2>; 3431 qcom,ports-sinterval-low =/bits/ 8 <0x07 0x1F 0x3F 0x7 0x1F 0x3F 0x0F 0x0F>; 3432 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0C 0x6 0x12 0x0D 0x07 0x0A >; 3433 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x1F 0x00 0x00 0x1F 0x00 0x00>; 3434 3435 #sound-dai-cells = <1>; 3436 clocks = <&wcd9340>; 3437 clock-names = "iface"; 3438 #address-cells = <2>; 3439 #size-cells = <0>; 3440 3441 3442 }; 3443 }; 3444 }; 3445 }; 3446 3447 sound: sound { 3448 }; 3449 3450 usb_1_hsphy: phy@88e2000 { 3451 compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy"; 3452 reg = <0 0x088e2000 0 0x400>; 3453 status = "disabled"; 3454 #phy-cells = <0>; 3455 3456 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 3457 <&rpmhcc RPMH_CXO_CLK>; 3458 clock-names = "cfg_ahb", "ref"; 3459 3460 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 3461 3462 nvmem-cells = <&qusb2p_hstx_trim>; 3463 }; 3464 3465 usb_2_hsphy: phy@88e3000 { 3466 compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy"; 3467 reg = <0 0x088e3000 0 0x400>; 3468 status = "disabled"; 3469 #phy-cells = <0>; 3470 3471 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 3472 <&rpmhcc RPMH_CXO_CLK>; 3473 clock-names = "cfg_ahb", "ref"; 3474 3475 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 3476 3477 nvmem-cells = <&qusb2s_hstx_trim>; 3478 }; 3479 3480 usb_1_qmpphy: phy@88e9000 { 3481 compatible = "qcom,sdm845-qmp-usb3-phy"; 3482 reg = <0 0x088e9000 0 0x18c>, 3483 <0 0x088e8000 0 0x10>; 3484 reg-names = "reg-base", "dp_com"; 3485 status = "disabled"; 3486 #clock-cells = <1>; 3487 #address-cells = <2>; 3488 #size-cells = <2>; 3489 ranges; 3490 3491 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 3492 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 3493 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 3494 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 3495 clock-names = "aux", "cfg_ahb", "ref", "com_aux"; 3496 3497 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 3498 <&gcc GCC_USB3_PHY_PRIM_BCR>; 3499 reset-names = "phy", "common"; 3500 3501 usb_1_ssphy: lanes@88e9200 { 3502 reg = <0 0x088e9200 0 0x128>, 3503 <0 0x088e9400 0 0x200>, 3504 <0 0x088e9c00 0 0x218>, 3505 <0 0x088e9600 0 0x128>, 3506 <0 0x088e9800 0 0x200>, 3507 <0 0x088e9a00 0 0x100>; 3508 #phy-cells = <0>; 3509 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 3510 clock-names = "pipe0"; 3511 clock-output-names = "usb3_phy_pipe_clk_src"; 3512 }; 3513 }; 3514 3515 usb_2_qmpphy: phy@88eb000 { 3516 compatible = "qcom,sdm845-qmp-usb3-uni-phy"; 3517 reg = <0 0x088eb000 0 0x18c>; 3518 status = "disabled"; 3519 #clock-cells = <1>; 3520 #address-cells = <2>; 3521 #size-cells = <2>; 3522 ranges; 3523 3524 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 3525 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 3526 <&gcc GCC_USB3_SEC_CLKREF_CLK>, 3527 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; 3528 clock-names = "aux", "cfg_ahb", "ref", "com_aux"; 3529 3530 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, 3531 <&gcc GCC_USB3_PHY_SEC_BCR>; 3532 reset-names = "phy", "common"; 3533 3534 usb_2_ssphy: lane@88eb200 { 3535 reg = <0 0x088eb200 0 0x128>, 3536 <0 0x088eb400 0 0x1fc>, 3537 <0 0x088eb800 0 0x218>, 3538 <0 0x088eb600 0 0x70>; 3539 #phy-cells = <0>; 3540 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 3541 clock-names = "pipe0"; 3542 clock-output-names = "usb3_uni_phy_pipe_clk_src"; 3543 }; 3544 }; 3545 3546 usb_1: usb@a6f8800 { 3547 compatible = "qcom,sdm845-dwc3", "qcom,dwc3"; 3548 reg = <0 0x0a6f8800 0 0x400>; 3549 status = "disabled"; 3550 #address-cells = <2>; 3551 #size-cells = <2>; 3552 ranges; 3553 dma-ranges; 3554 3555 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 3556 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 3557 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 3558 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3559 <&gcc GCC_USB30_PRIM_SLEEP_CLK>; 3560 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 3561 "sleep"; 3562 3563 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3564 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 3565 assigned-clock-rates = <19200000>, <150000000>; 3566 3567 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 3568 <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>, 3569 <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>, 3570 <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>; 3571 interrupt-names = "hs_phy_irq", "ss_phy_irq", 3572 "dm_hs_phy_irq", "dp_hs_phy_irq"; 3573 3574 power-domains = <&gcc USB30_PRIM_GDSC>; 3575 3576 resets = <&gcc GCC_USB30_PRIM_BCR>; 3577 3578 interconnects = <&aggre2_noc MASTER_USB3_0 0 &mem_noc SLAVE_EBI1 0>, 3579 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; 3580 interconnect-names = "usb-ddr", "apps-usb"; 3581 3582 usb_1_dwc3: dwc3@a600000 { 3583 compatible = "snps,dwc3"; 3584 reg = <0 0x0a600000 0 0xcd00>; 3585 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 3586 iommus = <&apps_smmu 0x740 0>; 3587 snps,dis_u2_susphy_quirk; 3588 snps,dis_enblslpm_quirk; 3589 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 3590 phy-names = "usb2-phy", "usb3-phy"; 3591 }; 3592 }; 3593 3594 usb_2: usb@a8f8800 { 3595 compatible = "qcom,sdm845-dwc3", "qcom,dwc3"; 3596 reg = <0 0x0a8f8800 0 0x400>; 3597 status = "disabled"; 3598 #address-cells = <2>; 3599 #size-cells = <2>; 3600 ranges; 3601 dma-ranges; 3602 3603 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 3604 <&gcc GCC_USB30_SEC_MASTER_CLK>, 3605 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 3606 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3607 <&gcc GCC_USB30_SEC_SLEEP_CLK>; 3608 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 3609 "sleep"; 3610 3611 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3612 <&gcc GCC_USB30_SEC_MASTER_CLK>; 3613 assigned-clock-rates = <19200000>, <150000000>; 3614 3615 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 3616 <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>, 3617 <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>, 3618 <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>; 3619 interrupt-names = "hs_phy_irq", "ss_phy_irq", 3620 "dm_hs_phy_irq", "dp_hs_phy_irq"; 3621 3622 power-domains = <&gcc USB30_SEC_GDSC>; 3623 3624 resets = <&gcc GCC_USB30_SEC_BCR>; 3625 3626 interconnects = <&aggre2_noc MASTER_USB3_1 0 &mem_noc SLAVE_EBI1 0>, 3627 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>; 3628 interconnect-names = "usb-ddr", "apps-usb"; 3629 3630 usb_2_dwc3: dwc3@a800000 { 3631 compatible = "snps,dwc3"; 3632 reg = <0 0x0a800000 0 0xcd00>; 3633 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 3634 iommus = <&apps_smmu 0x760 0>; 3635 snps,dis_u2_susphy_quirk; 3636 snps,dis_enblslpm_quirk; 3637 phys = <&usb_2_hsphy>, <&usb_2_ssphy>; 3638 phy-names = "usb2-phy", "usb3-phy"; 3639 }; 3640 }; 3641 3642 venus: video-codec@aa00000 { 3643 compatible = "qcom,sdm845-venus-v2"; 3644 reg = <0 0x0aa00000 0 0xff000>; 3645 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 3646 power-domains = <&videocc VENUS_GDSC>, 3647 <&videocc VCODEC0_GDSC>, 3648 <&videocc VCODEC1_GDSC>, 3649 <&rpmhpd SDM845_CX>; 3650 power-domain-names = "venus", "vcodec0", "vcodec1", "cx"; 3651 operating-points-v2 = <&venus_opp_table>; 3652 clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>, 3653 <&videocc VIDEO_CC_VENUS_AHB_CLK>, 3654 <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>, 3655 <&videocc VIDEO_CC_VCODEC0_CORE_CLK>, 3656 <&videocc VIDEO_CC_VCODEC0_AXI_CLK>, 3657 <&videocc VIDEO_CC_VCODEC1_CORE_CLK>, 3658 <&videocc VIDEO_CC_VCODEC1_AXI_CLK>; 3659 clock-names = "core", "iface", "bus", 3660 "vcodec0_core", "vcodec0_bus", 3661 "vcodec1_core", "vcodec1_bus"; 3662 iommus = <&apps_smmu 0x10a0 0x8>, 3663 <&apps_smmu 0x10b0 0x0>; 3664 memory-region = <&venus_mem>; 3665 3666 video-core0 { 3667 compatible = "venus-decoder"; 3668 }; 3669 3670 video-core1 { 3671 compatible = "venus-encoder"; 3672 }; 3673 3674 venus_opp_table: venus-opp-table { 3675 compatible = "operating-points-v2"; 3676 3677 opp-100000000 { 3678 opp-hz = /bits/ 64 <100000000>; 3679 required-opps = <&rpmhpd_opp_min_svs>; 3680 }; 3681 3682 opp-200000000 { 3683 opp-hz = /bits/ 64 <200000000>; 3684 required-opps = <&rpmhpd_opp_low_svs>; 3685 }; 3686 3687 opp-320000000 { 3688 opp-hz = /bits/ 64 <320000000>; 3689 required-opps = <&rpmhpd_opp_svs>; 3690 }; 3691 3692 opp-380000000 { 3693 opp-hz = /bits/ 64 <380000000>; 3694 required-opps = <&rpmhpd_opp_svs_l1>; 3695 }; 3696 3697 opp-444000000 { 3698 opp-hz = /bits/ 64 <444000000>; 3699 required-opps = <&rpmhpd_opp_nom>; 3700 }; 3701 3702 opp-533000097 { 3703 opp-hz = /bits/ 64 <533000097>; 3704 required-opps = <&rpmhpd_opp_turbo>; 3705 }; 3706 }; 3707 }; 3708 3709 videocc: clock-controller@ab00000 { 3710 compatible = "qcom,sdm845-videocc"; 3711 reg = <0 0x0ab00000 0 0x10000>; 3712 clocks = <&rpmhcc RPMH_CXO_CLK>; 3713 clock-names = "bi_tcxo"; 3714 #clock-cells = <1>; 3715 #power-domain-cells = <1>; 3716 #reset-cells = <1>; 3717 }; 3718 3719 cci: cci@ac4a000 { 3720 compatible = "qcom,sdm845-cci"; 3721 #address-cells = <1>; 3722 #size-cells = <0>; 3723 3724 reg = <0 0x0ac4a000 0 0x4000>; 3725 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>; 3726 power-domains = <&clock_camcc TITAN_TOP_GDSC>; 3727 3728 clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, 3729 <&clock_camcc CAM_CC_SOC_AHB_CLK>, 3730 <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, 3731 <&clock_camcc CAM_CC_CPAS_AHB_CLK>, 3732 <&clock_camcc CAM_CC_CCI_CLK>, 3733 <&clock_camcc CAM_CC_CCI_CLK_SRC>; 3734 clock-names = "camnoc_axi", 3735 "soc_ahb", 3736 "slow_ahb_src", 3737 "cpas_ahb", 3738 "cci", 3739 "cci_src"; 3740 3741 assigned-clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, 3742 <&clock_camcc CAM_CC_CCI_CLK>; 3743 assigned-clock-rates = <80000000>, <37500000>; 3744 3745 pinctrl-names = "default", "sleep"; 3746 pinctrl-0 = <&cci0_default &cci1_default>; 3747 pinctrl-1 = <&cci0_sleep &cci1_sleep>; 3748 3749 status = "disabled"; 3750 3751 cci_i2c0: i2c-bus@0 { 3752 reg = <0>; 3753 clock-frequency = <1000000>; 3754 #address-cells = <1>; 3755 #size-cells = <0>; 3756 }; 3757 3758 cci_i2c1: i2c-bus@1 { 3759 reg = <1>; 3760 clock-frequency = <1000000>; 3761 #address-cells = <1>; 3762 #size-cells = <0>; 3763 }; 3764 }; 3765 3766 clock_camcc: clock-controller@ad00000 { 3767 compatible = "qcom,sdm845-camcc"; 3768 reg = <0 0x0ad00000 0 0x10000>; 3769 #clock-cells = <1>; 3770 #reset-cells = <1>; 3771 #power-domain-cells = <1>; 3772 }; 3773 3774 dsi_opp_table: dsi-opp-table { 3775 compatible = "operating-points-v2"; 3776 3777 opp-19200000 { 3778 opp-hz = /bits/ 64 <19200000>; 3779 required-opps = <&rpmhpd_opp_min_svs>; 3780 }; 3781 3782 opp-180000000 { 3783 opp-hz = /bits/ 64 <180000000>; 3784 required-opps = <&rpmhpd_opp_low_svs>; 3785 }; 3786 3787 opp-275000000 { 3788 opp-hz = /bits/ 64 <275000000>; 3789 required-opps = <&rpmhpd_opp_svs>; 3790 }; 3791 3792 opp-328580000 { 3793 opp-hz = /bits/ 64 <328580000>; 3794 required-opps = <&rpmhpd_opp_svs_l1>; 3795 }; 3796 3797 opp-358000000 { 3798 opp-hz = /bits/ 64 <358000000>; 3799 required-opps = <&rpmhpd_opp_nom>; 3800 }; 3801 }; 3802 3803 mdss: mdss@ae00000 { 3804 compatible = "qcom,sdm845-mdss"; 3805 reg = <0 0x0ae00000 0 0x1000>; 3806 reg-names = "mdss"; 3807 3808 power-domains = <&dispcc MDSS_GDSC>; 3809 3810 clocks = <&gcc GCC_DISP_AHB_CLK>, 3811 <&gcc GCC_DISP_AXI_CLK>, 3812 <&dispcc DISP_CC_MDSS_MDP_CLK>; 3813 clock-names = "iface", "bus", "core"; 3814 3815 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; 3816 assigned-clock-rates = <300000000>; 3817 3818 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 3819 interrupt-controller; 3820 #interrupt-cells = <1>; 3821 3822 interconnects = <&mmss_noc MASTER_MDP0 0 &mem_noc SLAVE_EBI1 0>, 3823 <&mmss_noc MASTER_MDP1 0 &mem_noc SLAVE_EBI1 0>; 3824 interconnect-names = "mdp0-mem", "mdp1-mem"; 3825 3826 iommus = <&apps_smmu 0x880 0x8>, 3827 <&apps_smmu 0xc80 0x8>; 3828 3829 status = "disabled"; 3830 3831 #address-cells = <2>; 3832 #size-cells = <2>; 3833 ranges; 3834 3835 mdss_mdp: mdp@ae01000 { 3836 compatible = "qcom,sdm845-dpu"; 3837 reg = <0 0x0ae01000 0 0x8f000>, 3838 <0 0x0aeb0000 0 0x2008>; 3839 reg-names = "mdp", "vbif"; 3840 3841 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3842 <&dispcc DISP_CC_MDSS_AXI_CLK>, 3843 <&dispcc DISP_CC_MDSS_MDP_CLK>, 3844 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3845 clock-names = "iface", "bus", "core", "vsync"; 3846 3847 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, 3848 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3849 assigned-clock-rates = <300000000>, 3850 <19200000>; 3851 operating-points-v2 = <&mdp_opp_table>; 3852 power-domains = <&rpmhpd SDM845_CX>; 3853 3854 interrupt-parent = <&mdss>; 3855 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; 3856 3857 status = "disabled"; 3858 3859 ports { 3860 #address-cells = <1>; 3861 #size-cells = <0>; 3862 3863 port@0 { 3864 reg = <0>; 3865 dpu_intf1_out: endpoint { 3866 remote-endpoint = <&dsi0_in>; 3867 }; 3868 }; 3869 3870 port@1 { 3871 reg = <1>; 3872 dpu_intf2_out: endpoint { 3873 remote-endpoint = <&dsi1_in>; 3874 }; 3875 }; 3876 }; 3877 3878 mdp_opp_table: mdp-opp-table { 3879 compatible = "operating-points-v2"; 3880 3881 opp-19200000 { 3882 opp-hz = /bits/ 64 <19200000>; 3883 required-opps = <&rpmhpd_opp_min_svs>; 3884 }; 3885 3886 opp-171428571 { 3887 opp-hz = /bits/ 64 <171428571>; 3888 required-opps = <&rpmhpd_opp_low_svs>; 3889 }; 3890 3891 opp-344000000 { 3892 opp-hz = /bits/ 64 <344000000>; 3893 required-opps = <&rpmhpd_opp_svs_l1>; 3894 }; 3895 3896 opp-430000000 { 3897 opp-hz = /bits/ 64 <430000000>; 3898 required-opps = <&rpmhpd_opp_nom>; 3899 }; 3900 }; 3901 }; 3902 3903 dsi0: dsi@ae94000 { 3904 compatible = "qcom,mdss-dsi-ctrl"; 3905 reg = <0 0x0ae94000 0 0x400>; 3906 reg-names = "dsi_ctrl"; 3907 3908 interrupt-parent = <&mdss>; 3909 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; 3910 3911 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 3912 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 3913 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 3914 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 3915 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3916 <&dispcc DISP_CC_MDSS_AXI_CLK>; 3917 clock-names = "byte", 3918 "byte_intf", 3919 "pixel", 3920 "core", 3921 "iface", 3922 "bus"; 3923 operating-points-v2 = <&dsi_opp_table>; 3924 power-domains = <&rpmhpd SDM845_CX>; 3925 3926 phys = <&dsi0_phy>; 3927 phy-names = "dsi"; 3928 3929 status = "disabled"; 3930 3931 ports { 3932 #address-cells = <1>; 3933 #size-cells = <0>; 3934 3935 port@0 { 3936 reg = <0>; 3937 dsi0_in: endpoint { 3938 remote-endpoint = <&dpu_intf1_out>; 3939 }; 3940 }; 3941 3942 port@1 { 3943 reg = <1>; 3944 dsi0_out: endpoint { 3945 }; 3946 }; 3947 }; 3948 }; 3949 3950 dsi0_phy: dsi-phy@ae94400 { 3951 compatible = "qcom,dsi-phy-10nm"; 3952 reg = <0 0x0ae94400 0 0x200>, 3953 <0 0x0ae94600 0 0x280>, 3954 <0 0x0ae94a00 0 0x1e0>; 3955 reg-names = "dsi_phy", 3956 "dsi_phy_lane", 3957 "dsi_pll"; 3958 3959 #clock-cells = <1>; 3960 #phy-cells = <0>; 3961 3962 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3963 <&rpmhcc RPMH_CXO_CLK>; 3964 clock-names = "iface", "ref"; 3965 3966 status = "disabled"; 3967 }; 3968 3969 dsi1: dsi@ae96000 { 3970 compatible = "qcom,mdss-dsi-ctrl"; 3971 reg = <0 0x0ae96000 0 0x400>; 3972 reg-names = "dsi_ctrl"; 3973 3974 interrupt-parent = <&mdss>; 3975 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; 3976 3977 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 3978 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 3979 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 3980 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 3981 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3982 <&dispcc DISP_CC_MDSS_AXI_CLK>; 3983 clock-names = "byte", 3984 "byte_intf", 3985 "pixel", 3986 "core", 3987 "iface", 3988 "bus"; 3989 operating-points-v2 = <&dsi_opp_table>; 3990 power-domains = <&rpmhpd SDM845_CX>; 3991 3992 phys = <&dsi1_phy>; 3993 phy-names = "dsi"; 3994 3995 status = "disabled"; 3996 3997 ports { 3998 #address-cells = <1>; 3999 #size-cells = <0>; 4000 4001 port@0 { 4002 reg = <0>; 4003 dsi1_in: endpoint { 4004 remote-endpoint = <&dpu_intf2_out>; 4005 }; 4006 }; 4007 4008 port@1 { 4009 reg = <1>; 4010 dsi1_out: endpoint { 4011 }; 4012 }; 4013 }; 4014 }; 4015 4016 dsi1_phy: dsi-phy@ae96400 { 4017 compatible = "qcom,dsi-phy-10nm"; 4018 reg = <0 0x0ae96400 0 0x200>, 4019 <0 0x0ae96600 0 0x280>, 4020 <0 0x0ae96a00 0 0x10e>; 4021 reg-names = "dsi_phy", 4022 "dsi_phy_lane", 4023 "dsi_pll"; 4024 4025 #clock-cells = <1>; 4026 #phy-cells = <0>; 4027 4028 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4029 <&rpmhcc RPMH_CXO_CLK>; 4030 clock-names = "iface", "ref"; 4031 4032 status = "disabled"; 4033 }; 4034 }; 4035 4036 gpu: gpu@5000000 { 4037 compatible = "qcom,adreno-630.2", "qcom,adreno"; 4038 #stream-id-cells = <16>; 4039 4040 reg = <0 0x5000000 0 0x40000>, <0 0x509e000 0 0x10>; 4041 reg-names = "kgsl_3d0_reg_memory", "cx_mem"; 4042 4043 /* 4044 * Look ma, no clocks! The GPU clocks and power are 4045 * controlled entirely by the GMU 4046 */ 4047 4048 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 4049 4050 iommus = <&adreno_smmu 0>; 4051 4052 operating-points-v2 = <&gpu_opp_table>; 4053 4054 qcom,gmu = <&gmu>; 4055 4056 interconnects = <&mem_noc MASTER_GFX3D 0 &mem_noc SLAVE_EBI1 0>; 4057 interconnect-names = "gfx-mem"; 4058 4059 gpu_opp_table: opp-table { 4060 compatible = "operating-points-v2"; 4061 4062 opp-710000000 { 4063 opp-hz = /bits/ 64 <710000000>; 4064 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 4065 opp-peak-kBps = <7216000>; 4066 }; 4067 4068 opp-675000000 { 4069 opp-hz = /bits/ 64 <675000000>; 4070 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 4071 opp-peak-kBps = <7216000>; 4072 }; 4073 4074 opp-596000000 { 4075 opp-hz = /bits/ 64 <596000000>; 4076 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 4077 opp-peak-kBps = <6220000>; 4078 }; 4079 4080 opp-520000000 { 4081 opp-hz = /bits/ 64 <520000000>; 4082 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 4083 opp-peak-kBps = <6220000>; 4084 }; 4085 4086 opp-414000000 { 4087 opp-hz = /bits/ 64 <414000000>; 4088 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4089 opp-peak-kBps = <4068000>; 4090 }; 4091 4092 opp-342000000 { 4093 opp-hz = /bits/ 64 <342000000>; 4094 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4095 opp-peak-kBps = <2724000>; 4096 }; 4097 4098 opp-257000000 { 4099 opp-hz = /bits/ 64 <257000000>; 4100 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 4101 opp-peak-kBps = <1648000>; 4102 }; 4103 }; 4104 }; 4105 4106 adreno_smmu: iommu@5040000 { 4107 compatible = "qcom,sdm845-smmu-v2", "qcom,smmu-v2"; 4108 reg = <0 0x5040000 0 0x10000>; 4109 #iommu-cells = <1>; 4110 #global-interrupts = <2>; 4111 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 4112 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 4113 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>, 4114 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>, 4115 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>, 4116 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>, 4117 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>, 4118 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>, 4119 <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>, 4120 <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>; 4121 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 4122 <&gcc GCC_GPU_CFG_AHB_CLK>; 4123 clock-names = "bus", "iface"; 4124 4125 power-domains = <&gpucc GPU_CX_GDSC>; 4126 }; 4127 4128 gmu: gmu@506a000 { 4129 compatible="qcom,adreno-gmu-630.2", "qcom,adreno-gmu"; 4130 4131 reg = <0 0x506a000 0 0x30000>, 4132 <0 0xb280000 0 0x10000>, 4133 <0 0xb480000 0 0x10000>; 4134 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; 4135 4136 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 4137 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 4138 interrupt-names = "hfi", "gmu"; 4139 4140 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 4141 <&gpucc GPU_CC_CXO_CLK>, 4142 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 4143 <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 4144 clock-names = "gmu", "cxo", "axi", "memnoc"; 4145 4146 power-domains = <&gpucc GPU_CX_GDSC>, 4147 <&gpucc GPU_GX_GDSC>; 4148 power-domain-names = "cx", "gx"; 4149 4150 iommus = <&adreno_smmu 5>; 4151 4152 operating-points-v2 = <&gmu_opp_table>; 4153 4154 gmu_opp_table: opp-table { 4155 compatible = "operating-points-v2"; 4156 4157 opp-400000000 { 4158 opp-hz = /bits/ 64 <400000000>; 4159 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4160 }; 4161 4162 opp-200000000 { 4163 opp-hz = /bits/ 64 <200000000>; 4164 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 4165 }; 4166 }; 4167 }; 4168 4169 dispcc: clock-controller@af00000 { 4170 compatible = "qcom,sdm845-dispcc"; 4171 reg = <0 0x0af00000 0 0x10000>; 4172 clocks = <&rpmhcc RPMH_CXO_CLK>, 4173 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 4174 <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, 4175 <&dsi0_phy 0>, 4176 <&dsi0_phy 1>, 4177 <&dsi1_phy 0>, 4178 <&dsi1_phy 1>, 4179 <0>, 4180 <0>; 4181 clock-names = "bi_tcxo", 4182 "gcc_disp_gpll0_clk_src", 4183 "gcc_disp_gpll0_div_clk_src", 4184 "dsi0_phy_pll_out_byteclk", 4185 "dsi0_phy_pll_out_dsiclk", 4186 "dsi1_phy_pll_out_byteclk", 4187 "dsi1_phy_pll_out_dsiclk", 4188 "dp_link_clk_divsel_ten", 4189 "dp_vco_divided_clk_src_mux"; 4190 #clock-cells = <1>; 4191 #reset-cells = <1>; 4192 #power-domain-cells = <1>; 4193 }; 4194 4195 pdc_intc: interrupt-controller@b220000 { 4196 compatible = "qcom,sdm845-pdc", "qcom,pdc"; 4197 reg = <0 0x0b220000 0 0x30000>; 4198 qcom,pdc-ranges = <0 480 94>, <94 609 15>, <115 630 7>; 4199 #interrupt-cells = <2>; 4200 interrupt-parent = <&intc>; 4201 interrupt-controller; 4202 }; 4203 4204 pdc_reset: reset-controller@b2e0000 { 4205 compatible = "qcom,sdm845-pdc-global"; 4206 reg = <0 0x0b2e0000 0 0x20000>; 4207 #reset-cells = <1>; 4208 }; 4209 4210 tsens0: thermal-sensor@c263000 { 4211 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2"; 4212 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 4213 <0 0x0c222000 0 0x1ff>; /* SROT */ 4214 #qcom,sensors = <13>; 4215 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 4216 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 4217 interrupt-names = "uplow", "critical"; 4218 #thermal-sensor-cells = <1>; 4219 }; 4220 4221 tsens1: thermal-sensor@c265000 { 4222 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2"; 4223 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 4224 <0 0x0c223000 0 0x1ff>; /* SROT */ 4225 #qcom,sensors = <8>; 4226 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 4227 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 4228 interrupt-names = "uplow", "critical"; 4229 #thermal-sensor-cells = <1>; 4230 }; 4231 4232 aoss_reset: reset-controller@c2a0000 { 4233 compatible = "qcom,sdm845-aoss-cc"; 4234 reg = <0 0x0c2a0000 0 0x31000>; 4235 #reset-cells = <1>; 4236 }; 4237 4238 aoss_qmp: qmp@c300000 { 4239 compatible = "qcom,sdm845-aoss-qmp"; 4240 reg = <0 0x0c300000 0 0x100000>; 4241 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; 4242 mboxes = <&apss_shared 0>; 4243 4244 #clock-cells = <0>; 4245 #power-domain-cells = <1>; 4246 4247 cx_cdev: cx { 4248 #cooling-cells = <2>; 4249 }; 4250 4251 ebi_cdev: ebi { 4252 #cooling-cells = <2>; 4253 }; 4254 }; 4255 4256 spmi_bus: spmi@c440000 { 4257 compatible = "qcom,spmi-pmic-arb"; 4258 reg = <0 0x0c440000 0 0x1100>, 4259 <0 0x0c600000 0 0x2000000>, 4260 <0 0x0e600000 0 0x100000>, 4261 <0 0x0e700000 0 0xa0000>, 4262 <0 0x0c40a000 0 0x26000>; 4263 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 4264 interrupt-names = "periph_irq"; 4265 interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>; 4266 qcom,ee = <0>; 4267 qcom,channel = <0>; 4268 #address-cells = <2>; 4269 #size-cells = <0>; 4270 interrupt-controller; 4271 #interrupt-cells = <4>; 4272 cell-index = <0>; 4273 }; 4274 4275 imem@146bf000 { 4276 compatible = "simple-mfd"; 4277 reg = <0 0x146bf000 0 0x1000>; 4278 4279 #address-cells = <1>; 4280 #size-cells = <1>; 4281 4282 ranges = <0 0 0x146bf000 0x1000>; 4283 4284 pil-reloc@94c { 4285 compatible = "qcom,pil-reloc-info"; 4286 reg = <0x94c 0xc8>; 4287 }; 4288 }; 4289 4290 apps_smmu: iommu@15000000 { 4291 compatible = "qcom,sdm845-smmu-500", "arm,mmu-500"; 4292 reg = <0 0x15000000 0 0x80000>; 4293 #iommu-cells = <2>; 4294 #global-interrupts = <1>; 4295 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 4296 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 4297 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 4298 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 4299 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 4300 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 4301 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 4302 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 4303 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 4304 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 4305 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 4306 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 4307 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 4308 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 4309 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 4310 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 4311 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 4312 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 4313 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 4314 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 4315 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 4316 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 4317 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 4318 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 4319 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 4320 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 4321 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 4322 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 4323 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 4324 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 4325 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 4326 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 4327 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 4328 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 4329 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 4330 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 4331 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 4332 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 4333 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 4334 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 4335 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 4336 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 4337 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 4338 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 4339 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 4340 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 4341 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 4342 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 4343 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 4344 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 4345 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 4346 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 4347 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 4348 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 4349 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 4350 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 4351 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 4352 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 4353 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 4354 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 4355 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 4356 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 4357 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 4358 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 4359 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>; 4360 }; 4361 4362 lpasscc: clock-controller@17014000 { 4363 compatible = "qcom,sdm845-lpasscc"; 4364 reg = <0 0x17014000 0 0x1f004>, <0 0x17300000 0 0x200>; 4365 reg-names = "cc", "qdsp6ss"; 4366 #clock-cells = <1>; 4367 status = "disabled"; 4368 }; 4369 4370 gladiator_noc: interconnect@17900000 { 4371 compatible = "qcom,sdm845-gladiator-noc"; 4372 reg = <0 0x17900000 0 0xd080>; 4373 #interconnect-cells = <2>; 4374 qcom,bcm-voters = <&apps_bcm_voter>; 4375 }; 4376 4377 watchdog@17980000 { 4378 compatible = "qcom,apss-wdt-sdm845", "qcom,kpss-wdt"; 4379 reg = <0 0x17980000 0 0x1000>; 4380 clocks = <&sleep_clk>; 4381 }; 4382 4383 apss_shared: mailbox@17990000 { 4384 compatible = "qcom,sdm845-apss-shared"; 4385 reg = <0 0x17990000 0 0x1000>; 4386 #mbox-cells = <1>; 4387 }; 4388 4389 apps_rsc: rsc@179c0000 { 4390 label = "apps_rsc"; 4391 compatible = "qcom,rpmh-rsc"; 4392 reg = <0 0x179c0000 0 0x10000>, 4393 <0 0x179d0000 0 0x10000>, 4394 <0 0x179e0000 0 0x10000>; 4395 reg-names = "drv-0", "drv-1", "drv-2"; 4396 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 4397 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 4398 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 4399 qcom,tcs-offset = <0xd00>; 4400 qcom,drv-id = <2>; 4401 qcom,tcs-config = <ACTIVE_TCS 2>, 4402 <SLEEP_TCS 3>, 4403 <WAKE_TCS 3>, 4404 <CONTROL_TCS 1>; 4405 4406 apps_bcm_voter: bcm-voter { 4407 compatible = "qcom,bcm-voter"; 4408 }; 4409 4410 rpmhcc: clock-controller { 4411 compatible = "qcom,sdm845-rpmh-clk"; 4412 #clock-cells = <1>; 4413 clock-names = "xo"; 4414 clocks = <&xo_board>; 4415 }; 4416 4417 rpmhpd: power-controller { 4418 compatible = "qcom,sdm845-rpmhpd"; 4419 #power-domain-cells = <1>; 4420 operating-points-v2 = <&rpmhpd_opp_table>; 4421 4422 rpmhpd_opp_table: opp-table { 4423 compatible = "operating-points-v2"; 4424 4425 rpmhpd_opp_ret: opp1 { 4426 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 4427 }; 4428 4429 rpmhpd_opp_min_svs: opp2 { 4430 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 4431 }; 4432 4433 rpmhpd_opp_low_svs: opp3 { 4434 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 4435 }; 4436 4437 rpmhpd_opp_svs: opp4 { 4438 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4439 }; 4440 4441 rpmhpd_opp_svs_l1: opp5 { 4442 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4443 }; 4444 4445 rpmhpd_opp_nom: opp6 { 4446 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 4447 }; 4448 4449 rpmhpd_opp_nom_l1: opp7 { 4450 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 4451 }; 4452 4453 rpmhpd_opp_nom_l2: opp8 { 4454 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 4455 }; 4456 4457 rpmhpd_opp_turbo: opp9 { 4458 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 4459 }; 4460 4461 rpmhpd_opp_turbo_l1: opp10 { 4462 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 4463 }; 4464 }; 4465 }; 4466 }; 4467 4468 intc: interrupt-controller@17a00000 { 4469 compatible = "arm,gic-v3"; 4470 #address-cells = <2>; 4471 #size-cells = <2>; 4472 ranges; 4473 #interrupt-cells = <3>; 4474 interrupt-controller; 4475 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 4476 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 4477 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 4478 4479 msi-controller@17a40000 { 4480 compatible = "arm,gic-v3-its"; 4481 msi-controller; 4482 #msi-cells = <1>; 4483 reg = <0 0x17a40000 0 0x20000>; 4484 status = "disabled"; 4485 }; 4486 }; 4487 4488 slimbam: dma@17184000 { 4489 compatible = "qcom,bam-v1.7.0"; 4490 qcom,controlled-remotely; 4491 reg = <0 0x17184000 0 0x2a000>; 4492 num-channels = <31>; 4493 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 4494 #dma-cells = <1>; 4495 qcom,ee = <1>; 4496 qcom,num-ees = <2>; 4497 iommus = <&apps_smmu 0x1806 0x0>; 4498 }; 4499 4500 timer@17c90000 { 4501 #address-cells = <2>; 4502 #size-cells = <2>; 4503 ranges; 4504 compatible = "arm,armv7-timer-mem"; 4505 reg = <0 0x17c90000 0 0x1000>; 4506 4507 frame@17ca0000 { 4508 frame-number = <0>; 4509 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 4510 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 4511 reg = <0 0x17ca0000 0 0x1000>, 4512 <0 0x17cb0000 0 0x1000>; 4513 }; 4514 4515 frame@17cc0000 { 4516 frame-number = <1>; 4517 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 4518 reg = <0 0x17cc0000 0 0x1000>; 4519 status = "disabled"; 4520 }; 4521 4522 frame@17cd0000 { 4523 frame-number = <2>; 4524 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 4525 reg = <0 0x17cd0000 0 0x1000>; 4526 status = "disabled"; 4527 }; 4528 4529 frame@17ce0000 { 4530 frame-number = <3>; 4531 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 4532 reg = <0 0x17ce0000 0 0x1000>; 4533 status = "disabled"; 4534 }; 4535 4536 frame@17cf0000 { 4537 frame-number = <4>; 4538 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 4539 reg = <0 0x17cf0000 0 0x1000>; 4540 status = "disabled"; 4541 }; 4542 4543 frame@17d00000 { 4544 frame-number = <5>; 4545 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 4546 reg = <0 0x17d00000 0 0x1000>; 4547 status = "disabled"; 4548 }; 4549 4550 frame@17d10000 { 4551 frame-number = <6>; 4552 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 4553 reg = <0 0x17d10000 0 0x1000>; 4554 status = "disabled"; 4555 }; 4556 }; 4557 4558 osm_l3: interconnect@17d41000 { 4559 compatible = "qcom,sdm845-osm-l3"; 4560 reg = <0 0x17d41000 0 0x1400>; 4561 4562 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 4563 clock-names = "xo", "alternate"; 4564 4565 #interconnect-cells = <1>; 4566 }; 4567 4568 cpufreq_hw: cpufreq@17d43000 { 4569 compatible = "qcom,cpufreq-hw"; 4570 reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>; 4571 reg-names = "freq-domain0", "freq-domain1"; 4572 4573 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 4574 clock-names = "xo", "alternate"; 4575 4576 #freq-domain-cells = <1>; 4577 }; 4578 4579 wifi: wifi@18800000 { 4580 compatible = "qcom,wcn3990-wifi"; 4581 status = "disabled"; 4582 reg = <0 0x18800000 0 0x800000>; 4583 reg-names = "membase"; 4584 memory-region = <&wlan_msa_mem>; 4585 clock-names = "cxo_ref_clk_pin"; 4586 clocks = <&rpmhcc RPMH_RF_CLK2>; 4587 interrupts = 4588 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 4589 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, 4590 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 4591 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 4592 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 4593 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 4594 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 4595 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 4596 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 4597 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 4598 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 4599 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; 4600 iommus = <&apps_smmu 0x0040 0x1>; 4601 }; 4602 }; 4603 4604 thermal-zones { 4605 cpu0-thermal { 4606 polling-delay-passive = <250>; 4607 polling-delay = <1000>; 4608 4609 thermal-sensors = <&tsens0 1>; 4610 4611 trips { 4612 cpu0_alert0: trip-point0 { 4613 temperature = <90000>; 4614 hysteresis = <2000>; 4615 type = "passive"; 4616 }; 4617 4618 cpu0_alert1: trip-point1 { 4619 temperature = <95000>; 4620 hysteresis = <2000>; 4621 type = "passive"; 4622 }; 4623 4624 cpu0_crit: cpu_crit { 4625 temperature = <110000>; 4626 hysteresis = <1000>; 4627 type = "critical"; 4628 }; 4629 }; 4630 4631 cooling-maps { 4632 map0 { 4633 trip = <&cpu0_alert0>; 4634 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4635 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4636 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4637 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4638 }; 4639 map1 { 4640 trip = <&cpu0_alert1>; 4641 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4642 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4643 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4644 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4645 }; 4646 }; 4647 }; 4648 4649 cpu1-thermal { 4650 polling-delay-passive = <250>; 4651 polling-delay = <1000>; 4652 4653 thermal-sensors = <&tsens0 2>; 4654 4655 trips { 4656 cpu1_alert0: trip-point0 { 4657 temperature = <90000>; 4658 hysteresis = <2000>; 4659 type = "passive"; 4660 }; 4661 4662 cpu1_alert1: trip-point1 { 4663 temperature = <95000>; 4664 hysteresis = <2000>; 4665 type = "passive"; 4666 }; 4667 4668 cpu1_crit: cpu_crit { 4669 temperature = <110000>; 4670 hysteresis = <1000>; 4671 type = "critical"; 4672 }; 4673 }; 4674 4675 cooling-maps { 4676 map0 { 4677 trip = <&cpu1_alert0>; 4678 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4679 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4680 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4681 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4682 }; 4683 map1 { 4684 trip = <&cpu1_alert1>; 4685 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4686 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4687 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4688 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4689 }; 4690 }; 4691 }; 4692 4693 cpu2-thermal { 4694 polling-delay-passive = <250>; 4695 polling-delay = <1000>; 4696 4697 thermal-sensors = <&tsens0 3>; 4698 4699 trips { 4700 cpu2_alert0: trip-point0 { 4701 temperature = <90000>; 4702 hysteresis = <2000>; 4703 type = "passive"; 4704 }; 4705 4706 cpu2_alert1: trip-point1 { 4707 temperature = <95000>; 4708 hysteresis = <2000>; 4709 type = "passive"; 4710 }; 4711 4712 cpu2_crit: cpu_crit { 4713 temperature = <110000>; 4714 hysteresis = <1000>; 4715 type = "critical"; 4716 }; 4717 }; 4718 4719 cooling-maps { 4720 map0 { 4721 trip = <&cpu2_alert0>; 4722 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4723 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4724 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4725 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4726 }; 4727 map1 { 4728 trip = <&cpu2_alert1>; 4729 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4730 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4731 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4732 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4733 }; 4734 }; 4735 }; 4736 4737 cpu3-thermal { 4738 polling-delay-passive = <250>; 4739 polling-delay = <1000>; 4740 4741 thermal-sensors = <&tsens0 4>; 4742 4743 trips { 4744 cpu3_alert0: trip-point0 { 4745 temperature = <90000>; 4746 hysteresis = <2000>; 4747 type = "passive"; 4748 }; 4749 4750 cpu3_alert1: trip-point1 { 4751 temperature = <95000>; 4752 hysteresis = <2000>; 4753 type = "passive"; 4754 }; 4755 4756 cpu3_crit: cpu_crit { 4757 temperature = <110000>; 4758 hysteresis = <1000>; 4759 type = "critical"; 4760 }; 4761 }; 4762 4763 cooling-maps { 4764 map0 { 4765 trip = <&cpu3_alert0>; 4766 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4767 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4768 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4769 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4770 }; 4771 map1 { 4772 trip = <&cpu3_alert1>; 4773 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4774 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4775 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4776 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4777 }; 4778 }; 4779 }; 4780 4781 cpu4-thermal { 4782 polling-delay-passive = <250>; 4783 polling-delay = <1000>; 4784 4785 thermal-sensors = <&tsens0 7>; 4786 4787 trips { 4788 cpu4_alert0: trip-point0 { 4789 temperature = <90000>; 4790 hysteresis = <2000>; 4791 type = "passive"; 4792 }; 4793 4794 cpu4_alert1: trip-point1 { 4795 temperature = <95000>; 4796 hysteresis = <2000>; 4797 type = "passive"; 4798 }; 4799 4800 cpu4_crit: cpu_crit { 4801 temperature = <110000>; 4802 hysteresis = <1000>; 4803 type = "critical"; 4804 }; 4805 }; 4806 4807 cooling-maps { 4808 map0 { 4809 trip = <&cpu4_alert0>; 4810 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4811 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4812 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4813 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4814 }; 4815 map1 { 4816 trip = <&cpu4_alert1>; 4817 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4818 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4819 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4820 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4821 }; 4822 }; 4823 }; 4824 4825 cpu5-thermal { 4826 polling-delay-passive = <250>; 4827 polling-delay = <1000>; 4828 4829 thermal-sensors = <&tsens0 8>; 4830 4831 trips { 4832 cpu5_alert0: trip-point0 { 4833 temperature = <90000>; 4834 hysteresis = <2000>; 4835 type = "passive"; 4836 }; 4837 4838 cpu5_alert1: trip-point1 { 4839 temperature = <95000>; 4840 hysteresis = <2000>; 4841 type = "passive"; 4842 }; 4843 4844 cpu5_crit: cpu_crit { 4845 temperature = <110000>; 4846 hysteresis = <1000>; 4847 type = "critical"; 4848 }; 4849 }; 4850 4851 cooling-maps { 4852 map0 { 4853 trip = <&cpu5_alert0>; 4854 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4855 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4856 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4857 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4858 }; 4859 map1 { 4860 trip = <&cpu5_alert1>; 4861 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4862 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4863 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4864 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4865 }; 4866 }; 4867 }; 4868 4869 cpu6-thermal { 4870 polling-delay-passive = <250>; 4871 polling-delay = <1000>; 4872 4873 thermal-sensors = <&tsens0 9>; 4874 4875 trips { 4876 cpu6_alert0: trip-point0 { 4877 temperature = <90000>; 4878 hysteresis = <2000>; 4879 type = "passive"; 4880 }; 4881 4882 cpu6_alert1: trip-point1 { 4883 temperature = <95000>; 4884 hysteresis = <2000>; 4885 type = "passive"; 4886 }; 4887 4888 cpu6_crit: cpu_crit { 4889 temperature = <110000>; 4890 hysteresis = <1000>; 4891 type = "critical"; 4892 }; 4893 }; 4894 4895 cooling-maps { 4896 map0 { 4897 trip = <&cpu6_alert0>; 4898 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4899 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4900 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4901 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4902 }; 4903 map1 { 4904 trip = <&cpu6_alert1>; 4905 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4906 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4907 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4908 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4909 }; 4910 }; 4911 }; 4912 4913 cpu7-thermal { 4914 polling-delay-passive = <250>; 4915 polling-delay = <1000>; 4916 4917 thermal-sensors = <&tsens0 10>; 4918 4919 trips { 4920 cpu7_alert0: trip-point0 { 4921 temperature = <90000>; 4922 hysteresis = <2000>; 4923 type = "passive"; 4924 }; 4925 4926 cpu7_alert1: trip-point1 { 4927 temperature = <95000>; 4928 hysteresis = <2000>; 4929 type = "passive"; 4930 }; 4931 4932 cpu7_crit: cpu_crit { 4933 temperature = <110000>; 4934 hysteresis = <1000>; 4935 type = "critical"; 4936 }; 4937 }; 4938 4939 cooling-maps { 4940 map0 { 4941 trip = <&cpu7_alert0>; 4942 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4943 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4944 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4945 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4946 }; 4947 map1 { 4948 trip = <&cpu7_alert1>; 4949 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4950 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4951 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4952 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4953 }; 4954 }; 4955 }; 4956 4957 aoss0-thermal { 4958 polling-delay-passive = <250>; 4959 polling-delay = <1000>; 4960 4961 thermal-sensors = <&tsens0 0>; 4962 4963 trips { 4964 aoss0_alert0: trip-point0 { 4965 temperature = <90000>; 4966 hysteresis = <2000>; 4967 type = "hot"; 4968 }; 4969 }; 4970 }; 4971 4972 cluster0-thermal { 4973 polling-delay-passive = <250>; 4974 polling-delay = <1000>; 4975 4976 thermal-sensors = <&tsens0 5>; 4977 4978 trips { 4979 cluster0_alert0: trip-point0 { 4980 temperature = <90000>; 4981 hysteresis = <2000>; 4982 type = "hot"; 4983 }; 4984 cluster0_crit: cluster0_crit { 4985 temperature = <110000>; 4986 hysteresis = <2000>; 4987 type = "critical"; 4988 }; 4989 }; 4990 }; 4991 4992 cluster1-thermal { 4993 polling-delay-passive = <250>; 4994 polling-delay = <1000>; 4995 4996 thermal-sensors = <&tsens0 6>; 4997 4998 trips { 4999 cluster1_alert0: trip-point0 { 5000 temperature = <90000>; 5001 hysteresis = <2000>; 5002 type = "hot"; 5003 }; 5004 cluster1_crit: cluster1_crit { 5005 temperature = <110000>; 5006 hysteresis = <2000>; 5007 type = "critical"; 5008 }; 5009 }; 5010 }; 5011 5012 gpu-thermal-top { 5013 polling-delay-passive = <250>; 5014 polling-delay = <1000>; 5015 5016 thermal-sensors = <&tsens0 11>; 5017 5018 trips { 5019 gpu1_alert0: trip-point0 { 5020 temperature = <90000>; 5021 hysteresis = <2000>; 5022 type = "hot"; 5023 }; 5024 }; 5025 }; 5026 5027 gpu-thermal-bottom { 5028 polling-delay-passive = <250>; 5029 polling-delay = <1000>; 5030 5031 thermal-sensors = <&tsens0 12>; 5032 5033 trips { 5034 gpu2_alert0: trip-point0 { 5035 temperature = <90000>; 5036 hysteresis = <2000>; 5037 type = "hot"; 5038 }; 5039 }; 5040 }; 5041 5042 aoss1-thermal { 5043 polling-delay-passive = <250>; 5044 polling-delay = <1000>; 5045 5046 thermal-sensors = <&tsens1 0>; 5047 5048 trips { 5049 aoss1_alert0: trip-point0 { 5050 temperature = <90000>; 5051 hysteresis = <2000>; 5052 type = "hot"; 5053 }; 5054 }; 5055 }; 5056 5057 q6-modem-thermal { 5058 polling-delay-passive = <250>; 5059 polling-delay = <1000>; 5060 5061 thermal-sensors = <&tsens1 1>; 5062 5063 trips { 5064 q6_modem_alert0: trip-point0 { 5065 temperature = <90000>; 5066 hysteresis = <2000>; 5067 type = "hot"; 5068 }; 5069 }; 5070 }; 5071 5072 mem-thermal { 5073 polling-delay-passive = <250>; 5074 polling-delay = <1000>; 5075 5076 thermal-sensors = <&tsens1 2>; 5077 5078 trips { 5079 mem_alert0: trip-point0 { 5080 temperature = <90000>; 5081 hysteresis = <2000>; 5082 type = "hot"; 5083 }; 5084 }; 5085 }; 5086 5087 wlan-thermal { 5088 polling-delay-passive = <250>; 5089 polling-delay = <1000>; 5090 5091 thermal-sensors = <&tsens1 3>; 5092 5093 trips { 5094 wlan_alert0: trip-point0 { 5095 temperature = <90000>; 5096 hysteresis = <2000>; 5097 type = "hot"; 5098 }; 5099 }; 5100 }; 5101 5102 q6-hvx-thermal { 5103 polling-delay-passive = <250>; 5104 polling-delay = <1000>; 5105 5106 thermal-sensors = <&tsens1 4>; 5107 5108 trips { 5109 q6_hvx_alert0: trip-point0 { 5110 temperature = <90000>; 5111 hysteresis = <2000>; 5112 type = "hot"; 5113 }; 5114 }; 5115 }; 5116 5117 camera-thermal { 5118 polling-delay-passive = <250>; 5119 polling-delay = <1000>; 5120 5121 thermal-sensors = <&tsens1 5>; 5122 5123 trips { 5124 camera_alert0: trip-point0 { 5125 temperature = <90000>; 5126 hysteresis = <2000>; 5127 type = "hot"; 5128 }; 5129 }; 5130 }; 5131 5132 video-thermal { 5133 polling-delay-passive = <250>; 5134 polling-delay = <1000>; 5135 5136 thermal-sensors = <&tsens1 6>; 5137 5138 trips { 5139 video_alert0: trip-point0 { 5140 temperature = <90000>; 5141 hysteresis = <2000>; 5142 type = "hot"; 5143 }; 5144 }; 5145 }; 5146 5147 modem-thermal { 5148 polling-delay-passive = <250>; 5149 polling-delay = <1000>; 5150 5151 thermal-sensors = <&tsens1 7>; 5152 5153 trips { 5154 modem_alert0: trip-point0 { 5155 temperature = <90000>; 5156 hysteresis = <2000>; 5157 type = "hot"; 5158 }; 5159 }; 5160 }; 5161 }; 5162}; 5163