1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * NAU88L24 ALSA SoC audio driver
4 *
5 * Copyright 2016 Nuvoton Technology Corp.
6 * Author: John Hsu <KCHSU0@nuvoton.com>
7 */
8
9 #include <linux/module.h>
10 #include <linux/delay.h>
11 #include <linux/dmi.h>
12 #include <linux/init.h>
13 #include <linux/i2c.h>
14 #include <linux/regmap.h>
15 #include <linux/slab.h>
16 #include <linux/clk.h>
17 #include <linux/acpi.h>
18 #include <linux/math64.h>
19 #include <linux/semaphore.h>
20
21 #include <sound/initval.h>
22 #include <sound/tlv.h>
23 #include <sound/core.h>
24 #include <sound/pcm.h>
25 #include <sound/pcm_params.h>
26 #include <sound/soc.h>
27 #include <sound/jack.h>
28
29 #include "nau8824.h"
30
31 #define NAU8824_JD_ACTIVE_HIGH BIT(0)
32
33 static int nau8824_quirk;
34 static int quirk_override = -1;
35 module_param_named(quirk, quirk_override, uint, 0444);
36 MODULE_PARM_DESC(quirk, "Board-specific quirk override");
37
38 static int nau8824_config_sysclk(struct nau8824 *nau8824,
39 int clk_id, unsigned int freq);
40 static bool nau8824_is_jack_inserted(struct nau8824 *nau8824);
41
42 /* the ADC threshold of headset */
43 #define DMIC_CLK 3072000
44
45 /* the ADC threshold of headset */
46 #define HEADSET_SARADC_THD 0x80
47
48 /* the parameter threshold of FLL */
49 #define NAU_FREF_MAX 13500000
50 #define NAU_FVCO_MAX 100000000
51 #define NAU_FVCO_MIN 90000000
52
53 /* scaling for mclk from sysclk_src output */
54 static const struct nau8824_fll_attr mclk_src_scaling[] = {
55 { 1, 0x0 },
56 { 2, 0x2 },
57 { 4, 0x3 },
58 { 8, 0x4 },
59 { 16, 0x5 },
60 { 32, 0x6 },
61 { 3, 0x7 },
62 { 6, 0xa },
63 { 12, 0xb },
64 { 24, 0xc },
65 };
66
67 /* ratio for input clk freq */
68 static const struct nau8824_fll_attr fll_ratio[] = {
69 { 512000, 0x01 },
70 { 256000, 0x02 },
71 { 128000, 0x04 },
72 { 64000, 0x08 },
73 { 32000, 0x10 },
74 { 8000, 0x20 },
75 { 4000, 0x40 },
76 };
77
78 static const struct nau8824_fll_attr fll_pre_scalar[] = {
79 { 1, 0x0 },
80 { 2, 0x1 },
81 { 4, 0x2 },
82 { 8, 0x3 },
83 };
84
85 /* the maximum frequency of CLK_ADC and CLK_DAC */
86 #define CLK_DA_AD_MAX 6144000
87
88 /* over sampling rate */
89 static const struct nau8824_osr_attr osr_dac_sel[] = {
90 { 64, 2 }, /* OSR 64, SRC 1/4 */
91 { 256, 0 }, /* OSR 256, SRC 1 */
92 { 128, 1 }, /* OSR 128, SRC 1/2 */
93 { 0, 0 },
94 { 32, 3 }, /* OSR 32, SRC 1/8 */
95 };
96
97 static const struct nau8824_osr_attr osr_adc_sel[] = {
98 { 32, 3 }, /* OSR 32, SRC 1/8 */
99 { 64, 2 }, /* OSR 64, SRC 1/4 */
100 { 128, 1 }, /* OSR 128, SRC 1/2 */
101 { 256, 0 }, /* OSR 256, SRC 1 */
102 };
103
104 static const struct reg_default nau8824_reg_defaults[] = {
105 { NAU8824_REG_ENA_CTRL, 0x0000 },
106 { NAU8824_REG_CLK_GATING_ENA, 0x0000 },
107 { NAU8824_REG_CLK_DIVIDER, 0x0000 },
108 { NAU8824_REG_FLL1, 0x0000 },
109 { NAU8824_REG_FLL2, 0x3126 },
110 { NAU8824_REG_FLL3, 0x0008 },
111 { NAU8824_REG_FLL4, 0x0010 },
112 { NAU8824_REG_FLL5, 0xC000 },
113 { NAU8824_REG_FLL6, 0x6000 },
114 { NAU8824_REG_FLL_VCO_RSV, 0xF13C },
115 { NAU8824_REG_JACK_DET_CTRL, 0x0000 },
116 { NAU8824_REG_INTERRUPT_SETTING_1, 0x0000 },
117 { NAU8824_REG_IRQ, 0x0000 },
118 { NAU8824_REG_CLEAR_INT_REG, 0x0000 },
119 { NAU8824_REG_INTERRUPT_SETTING, 0x1000 },
120 { NAU8824_REG_SAR_ADC, 0x0015 },
121 { NAU8824_REG_VDET_COEFFICIENT, 0x0110 },
122 { NAU8824_REG_VDET_THRESHOLD_1, 0x0000 },
123 { NAU8824_REG_VDET_THRESHOLD_2, 0x0000 },
124 { NAU8824_REG_VDET_THRESHOLD_3, 0x0000 },
125 { NAU8824_REG_VDET_THRESHOLD_4, 0x0000 },
126 { NAU8824_REG_GPIO_SEL, 0x0000 },
127 { NAU8824_REG_PORT0_I2S_PCM_CTRL_1, 0x000B },
128 { NAU8824_REG_PORT0_I2S_PCM_CTRL_2, 0x0010 },
129 { NAU8824_REG_PORT0_LEFT_TIME_SLOT, 0x0000 },
130 { NAU8824_REG_PORT0_RIGHT_TIME_SLOT, 0x0000 },
131 { NAU8824_REG_TDM_CTRL, 0x0000 },
132 { NAU8824_REG_ADC_HPF_FILTER, 0x0000 },
133 { NAU8824_REG_ADC_FILTER_CTRL, 0x0002 },
134 { NAU8824_REG_DAC_FILTER_CTRL_1, 0x0000 },
135 { NAU8824_REG_DAC_FILTER_CTRL_2, 0x0000 },
136 { NAU8824_REG_NOTCH_FILTER_1, 0x0000 },
137 { NAU8824_REG_NOTCH_FILTER_2, 0x0000 },
138 { NAU8824_REG_EQ1_LOW, 0x112C },
139 { NAU8824_REG_EQ2_EQ3, 0x2C2C },
140 { NAU8824_REG_EQ4_EQ5, 0x2C2C },
141 { NAU8824_REG_ADC_CH0_DGAIN_CTRL, 0x0100 },
142 { NAU8824_REG_ADC_CH1_DGAIN_CTRL, 0x0100 },
143 { NAU8824_REG_ADC_CH2_DGAIN_CTRL, 0x0100 },
144 { NAU8824_REG_ADC_CH3_DGAIN_CTRL, 0x0100 },
145 { NAU8824_REG_DAC_MUTE_CTRL, 0x0000 },
146 { NAU8824_REG_DAC_CH0_DGAIN_CTRL, 0x0100 },
147 { NAU8824_REG_DAC_CH1_DGAIN_CTRL, 0x0100 },
148 { NAU8824_REG_ADC_TO_DAC_ST, 0x0000 },
149 { NAU8824_REG_DRC_KNEE_IP12_ADC_CH01, 0x1486 },
150 { NAU8824_REG_DRC_KNEE_IP34_ADC_CH01, 0x0F12 },
151 { NAU8824_REG_DRC_SLOPE_ADC_CH01, 0x25FF },
152 { NAU8824_REG_DRC_ATKDCY_ADC_CH01, 0x3457 },
153 { NAU8824_REG_DRC_KNEE_IP12_ADC_CH23, 0x1486 },
154 { NAU8824_REG_DRC_KNEE_IP34_ADC_CH23, 0x0F12 },
155 { NAU8824_REG_DRC_SLOPE_ADC_CH23, 0x25FF },
156 { NAU8824_REG_DRC_ATKDCY_ADC_CH23, 0x3457 },
157 { NAU8824_REG_DRC_GAINL_ADC0, 0x0200 },
158 { NAU8824_REG_DRC_GAINL_ADC1, 0x0200 },
159 { NAU8824_REG_DRC_GAINL_ADC2, 0x0200 },
160 { NAU8824_REG_DRC_GAINL_ADC3, 0x0200 },
161 { NAU8824_REG_DRC_KNEE_IP12_DAC, 0x1486 },
162 { NAU8824_REG_DRC_KNEE_IP34_DAC, 0x0F12 },
163 { NAU8824_REG_DRC_SLOPE_DAC, 0x25F9 },
164 { NAU8824_REG_DRC_ATKDCY_DAC, 0x3457 },
165 { NAU8824_REG_DRC_GAIN_DAC_CH0, 0x0200 },
166 { NAU8824_REG_DRC_GAIN_DAC_CH1, 0x0200 },
167 { NAU8824_REG_MODE, 0x0000 },
168 { NAU8824_REG_MODE1, 0x0000 },
169 { NAU8824_REG_MODE2, 0x0000 },
170 { NAU8824_REG_CLASSG, 0x0000 },
171 { NAU8824_REG_OTP_EFUSE, 0x0000 },
172 { NAU8824_REG_OTPDOUT_1, 0x0000 },
173 { NAU8824_REG_OTPDOUT_2, 0x0000 },
174 { NAU8824_REG_MISC_CTRL, 0x0000 },
175 { NAU8824_REG_I2C_TIMEOUT, 0xEFFF },
176 { NAU8824_REG_TEST_MODE, 0x0000 },
177 { NAU8824_REG_I2C_DEVICE_ID, 0x1AF1 },
178 { NAU8824_REG_SAR_ADC_DATA_OUT, 0x00FF },
179 { NAU8824_REG_BIAS_ADJ, 0x0000 },
180 { NAU8824_REG_PGA_GAIN, 0x0000 },
181 { NAU8824_REG_TRIM_SETTINGS, 0x0000 },
182 { NAU8824_REG_ANALOG_CONTROL_1, 0x0000 },
183 { NAU8824_REG_ANALOG_CONTROL_2, 0x0000 },
184 { NAU8824_REG_ENABLE_LO, 0x0000 },
185 { NAU8824_REG_GAIN_LO, 0x0000 },
186 { NAU8824_REG_CLASSD_GAIN_1, 0x0000 },
187 { NAU8824_REG_CLASSD_GAIN_2, 0x0000 },
188 { NAU8824_REG_ANALOG_ADC_1, 0x0011 },
189 { NAU8824_REG_ANALOG_ADC_2, 0x0020 },
190 { NAU8824_REG_RDAC, 0x0008 },
191 { NAU8824_REG_MIC_BIAS, 0x0006 },
192 { NAU8824_REG_HS_VOLUME_CONTROL, 0x0000 },
193 { NAU8824_REG_BOOST, 0x0000 },
194 { NAU8824_REG_FEPGA, 0x0000 },
195 { NAU8824_REG_FEPGA_II, 0x0000 },
196 { NAU8824_REG_FEPGA_SE, 0x0000 },
197 { NAU8824_REG_FEPGA_ATTENUATION, 0x0000 },
198 { NAU8824_REG_ATT_PORT0, 0x0000 },
199 { NAU8824_REG_ATT_PORT1, 0x0000 },
200 { NAU8824_REG_POWER_UP_CONTROL, 0x0000 },
201 { NAU8824_REG_CHARGE_PUMP_CONTROL, 0x0300 },
202 { NAU8824_REG_CHARGE_PUMP_INPUT, 0x0013 },
203 };
204
nau8824_sema_acquire(struct nau8824 * nau8824,long timeout)205 static int nau8824_sema_acquire(struct nau8824 *nau8824, long timeout)
206 {
207 int ret;
208
209 if (timeout) {
210 ret = down_timeout(&nau8824->jd_sem, timeout);
211 if (ret < 0)
212 dev_warn(nau8824->dev, "Acquire semaphore timeout\n");
213 } else {
214 ret = down_interruptible(&nau8824->jd_sem);
215 if (ret < 0)
216 dev_warn(nau8824->dev, "Acquire semaphore fail\n");
217 }
218
219 return ret;
220 }
221
nau8824_sema_release(struct nau8824 * nau8824)222 static inline void nau8824_sema_release(struct nau8824 *nau8824)
223 {
224 up(&nau8824->jd_sem);
225 }
226
nau8824_readable_reg(struct device * dev,unsigned int reg)227 static bool nau8824_readable_reg(struct device *dev, unsigned int reg)
228 {
229 switch (reg) {
230 case NAU8824_REG_ENA_CTRL ... NAU8824_REG_FLL_VCO_RSV:
231 case NAU8824_REG_JACK_DET_CTRL:
232 case NAU8824_REG_INTERRUPT_SETTING_1:
233 case NAU8824_REG_IRQ:
234 case NAU8824_REG_CLEAR_INT_REG ... NAU8824_REG_VDET_THRESHOLD_4:
235 case NAU8824_REG_GPIO_SEL:
236 case NAU8824_REG_PORT0_I2S_PCM_CTRL_1 ... NAU8824_REG_TDM_CTRL:
237 case NAU8824_REG_ADC_HPF_FILTER ... NAU8824_REG_EQ4_EQ5:
238 case NAU8824_REG_ADC_CH0_DGAIN_CTRL ... NAU8824_REG_ADC_TO_DAC_ST:
239 case NAU8824_REG_DRC_KNEE_IP12_ADC_CH01 ... NAU8824_REG_DRC_GAINL_ADC3:
240 case NAU8824_REG_DRC_KNEE_IP12_DAC ... NAU8824_REG_DRC_GAIN_DAC_CH1:
241 case NAU8824_REG_CLASSG ... NAU8824_REG_OTP_EFUSE:
242 case NAU8824_REG_OTPDOUT_1 ... NAU8824_REG_OTPDOUT_2:
243 case NAU8824_REG_I2C_TIMEOUT:
244 case NAU8824_REG_I2C_DEVICE_ID ... NAU8824_REG_SAR_ADC_DATA_OUT:
245 case NAU8824_REG_BIAS_ADJ ... NAU8824_REG_CLASSD_GAIN_2:
246 case NAU8824_REG_ANALOG_ADC_1 ... NAU8824_REG_ATT_PORT1:
247 case NAU8824_REG_POWER_UP_CONTROL ... NAU8824_REG_CHARGE_PUMP_INPUT:
248 return true;
249 default:
250 return false;
251 }
252
253 }
254
nau8824_writeable_reg(struct device * dev,unsigned int reg)255 static bool nau8824_writeable_reg(struct device *dev, unsigned int reg)
256 {
257 switch (reg) {
258 case NAU8824_REG_RESET ... NAU8824_REG_FLL_VCO_RSV:
259 case NAU8824_REG_JACK_DET_CTRL:
260 case NAU8824_REG_INTERRUPT_SETTING_1:
261 case NAU8824_REG_CLEAR_INT_REG ... NAU8824_REG_VDET_THRESHOLD_4:
262 case NAU8824_REG_GPIO_SEL:
263 case NAU8824_REG_PORT0_I2S_PCM_CTRL_1 ... NAU8824_REG_TDM_CTRL:
264 case NAU8824_REG_ADC_HPF_FILTER ... NAU8824_REG_EQ4_EQ5:
265 case NAU8824_REG_ADC_CH0_DGAIN_CTRL ... NAU8824_REG_ADC_TO_DAC_ST:
266 case NAU8824_REG_DRC_KNEE_IP12_ADC_CH01:
267 case NAU8824_REG_DRC_KNEE_IP34_ADC_CH01:
268 case NAU8824_REG_DRC_SLOPE_ADC_CH01:
269 case NAU8824_REG_DRC_ATKDCY_ADC_CH01:
270 case NAU8824_REG_DRC_KNEE_IP12_ADC_CH23:
271 case NAU8824_REG_DRC_KNEE_IP34_ADC_CH23:
272 case NAU8824_REG_DRC_SLOPE_ADC_CH23:
273 case NAU8824_REG_DRC_ATKDCY_ADC_CH23:
274 case NAU8824_REG_DRC_KNEE_IP12_DAC ... NAU8824_REG_DRC_ATKDCY_DAC:
275 case NAU8824_REG_CLASSG ... NAU8824_REG_OTP_EFUSE:
276 case NAU8824_REG_I2C_TIMEOUT:
277 case NAU8824_REG_BIAS_ADJ ... NAU8824_REG_CLASSD_GAIN_2:
278 case NAU8824_REG_ANALOG_ADC_1 ... NAU8824_REG_ATT_PORT1:
279 case NAU8824_REG_POWER_UP_CONTROL ... NAU8824_REG_CHARGE_PUMP_CONTROL:
280 return true;
281 default:
282 return false;
283 }
284 }
285
nau8824_volatile_reg(struct device * dev,unsigned int reg)286 static bool nau8824_volatile_reg(struct device *dev, unsigned int reg)
287 {
288 switch (reg) {
289 case NAU8824_REG_RESET:
290 case NAU8824_REG_IRQ ... NAU8824_REG_CLEAR_INT_REG:
291 case NAU8824_REG_DRC_GAINL_ADC0 ... NAU8824_REG_DRC_GAINL_ADC3:
292 case NAU8824_REG_DRC_GAIN_DAC_CH0 ... NAU8824_REG_DRC_GAIN_DAC_CH1:
293 case NAU8824_REG_OTPDOUT_1 ... NAU8824_REG_OTPDOUT_2:
294 case NAU8824_REG_I2C_DEVICE_ID ... NAU8824_REG_SAR_ADC_DATA_OUT:
295 case NAU8824_REG_CHARGE_PUMP_INPUT:
296 return true;
297 default:
298 return false;
299 }
300 }
301
302 static const char * const nau8824_companding[] = {
303 "Off", "NC", "u-law", "A-law" };
304
305 static const struct soc_enum nau8824_companding_adc_enum =
306 SOC_ENUM_SINGLE(NAU8824_REG_PORT0_I2S_PCM_CTRL_1, 12,
307 ARRAY_SIZE(nau8824_companding), nau8824_companding);
308
309 static const struct soc_enum nau8824_companding_dac_enum =
310 SOC_ENUM_SINGLE(NAU8824_REG_PORT0_I2S_PCM_CTRL_1, 14,
311 ARRAY_SIZE(nau8824_companding), nau8824_companding);
312
313 static const char * const nau8824_adc_decimation[] = {
314 "32", "64", "128", "256" };
315
316 static const struct soc_enum nau8824_adc_decimation_enum =
317 SOC_ENUM_SINGLE(NAU8824_REG_ADC_FILTER_CTRL, 0,
318 ARRAY_SIZE(nau8824_adc_decimation), nau8824_adc_decimation);
319
320 static const char * const nau8824_dac_oversampl[] = {
321 "64", "256", "128", "", "32" };
322
323 static const struct soc_enum nau8824_dac_oversampl_enum =
324 SOC_ENUM_SINGLE(NAU8824_REG_DAC_FILTER_CTRL_1, 0,
325 ARRAY_SIZE(nau8824_dac_oversampl), nau8824_dac_oversampl);
326
327 static const char * const nau8824_input_channel[] = {
328 "Input CH0", "Input CH1", "Input CH2", "Input CH3" };
329
330 static const struct soc_enum nau8824_adc_ch0_enum =
331 SOC_ENUM_SINGLE(NAU8824_REG_ADC_CH0_DGAIN_CTRL, 9,
332 ARRAY_SIZE(nau8824_input_channel), nau8824_input_channel);
333
334 static const struct soc_enum nau8824_adc_ch1_enum =
335 SOC_ENUM_SINGLE(NAU8824_REG_ADC_CH1_DGAIN_CTRL, 9,
336 ARRAY_SIZE(nau8824_input_channel), nau8824_input_channel);
337
338 static const struct soc_enum nau8824_adc_ch2_enum =
339 SOC_ENUM_SINGLE(NAU8824_REG_ADC_CH2_DGAIN_CTRL, 9,
340 ARRAY_SIZE(nau8824_input_channel), nau8824_input_channel);
341
342 static const struct soc_enum nau8824_adc_ch3_enum =
343 SOC_ENUM_SINGLE(NAU8824_REG_ADC_CH3_DGAIN_CTRL, 9,
344 ARRAY_SIZE(nau8824_input_channel), nau8824_input_channel);
345
346 static const char * const nau8824_tdm_slot[] = {
347 "Slot 0", "Slot 1", "Slot 2", "Slot 3" };
348
349 static const struct soc_enum nau8824_dac_left_sel_enum =
350 SOC_ENUM_SINGLE(NAU8824_REG_TDM_CTRL, 6,
351 ARRAY_SIZE(nau8824_tdm_slot), nau8824_tdm_slot);
352
353 static const struct soc_enum nau8824_dac_right_sel_enum =
354 SOC_ENUM_SINGLE(NAU8824_REG_TDM_CTRL, 4,
355 ARRAY_SIZE(nau8824_tdm_slot), nau8824_tdm_slot);
356
357 static const DECLARE_TLV_DB_MINMAX_MUTE(spk_vol_tlv, 0, 2400);
358 static const DECLARE_TLV_DB_MINMAX(hp_vol_tlv, -3000, 0);
359 static const DECLARE_TLV_DB_SCALE(mic_vol_tlv, 0, 200, 0);
360 static const DECLARE_TLV_DB_SCALE(dmic_vol_tlv, -12800, 50, 0);
361
362 static const struct snd_kcontrol_new nau8824_snd_controls[] = {
363 SOC_ENUM("ADC Companding", nau8824_companding_adc_enum),
364 SOC_ENUM("DAC Companding", nau8824_companding_dac_enum),
365
366 SOC_ENUM("ADC Decimation Rate", nau8824_adc_decimation_enum),
367 SOC_ENUM("DAC Oversampling Rate", nau8824_dac_oversampl_enum),
368
369 SOC_SINGLE_TLV("Speaker Right DACR Volume",
370 NAU8824_REG_CLASSD_GAIN_1, 8, 0x1f, 0, spk_vol_tlv),
371 SOC_SINGLE_TLV("Speaker Left DACL Volume",
372 NAU8824_REG_CLASSD_GAIN_2, 0, 0x1f, 0, spk_vol_tlv),
373 SOC_SINGLE_TLV("Speaker Left DACR Volume",
374 NAU8824_REG_CLASSD_GAIN_1, 0, 0x1f, 0, spk_vol_tlv),
375 SOC_SINGLE_TLV("Speaker Right DACL Volume",
376 NAU8824_REG_CLASSD_GAIN_2, 8, 0x1f, 0, spk_vol_tlv),
377
378 SOC_SINGLE_TLV("Headphone Right DACR Volume",
379 NAU8824_REG_ATT_PORT0, 8, 0x1f, 0, hp_vol_tlv),
380 SOC_SINGLE_TLV("Headphone Left DACL Volume",
381 NAU8824_REG_ATT_PORT0, 0, 0x1f, 0, hp_vol_tlv),
382 SOC_SINGLE_TLV("Headphone Right DACL Volume",
383 NAU8824_REG_ATT_PORT1, 8, 0x1f, 0, hp_vol_tlv),
384 SOC_SINGLE_TLV("Headphone Left DACR Volume",
385 NAU8824_REG_ATT_PORT1, 0, 0x1f, 0, hp_vol_tlv),
386
387 SOC_SINGLE_TLV("MIC1 Volume", NAU8824_REG_FEPGA_II,
388 NAU8824_FEPGA_GAINL_SFT, 0x12, 0, mic_vol_tlv),
389 SOC_SINGLE_TLV("MIC2 Volume", NAU8824_REG_FEPGA_II,
390 NAU8824_FEPGA_GAINR_SFT, 0x12, 0, mic_vol_tlv),
391
392 SOC_SINGLE_TLV("DMIC1 Volume", NAU8824_REG_ADC_CH0_DGAIN_CTRL,
393 0, 0x164, 0, dmic_vol_tlv),
394 SOC_SINGLE_TLV("DMIC2 Volume", NAU8824_REG_ADC_CH1_DGAIN_CTRL,
395 0, 0x164, 0, dmic_vol_tlv),
396 SOC_SINGLE_TLV("DMIC3 Volume", NAU8824_REG_ADC_CH2_DGAIN_CTRL,
397 0, 0x164, 0, dmic_vol_tlv),
398 SOC_SINGLE_TLV("DMIC4 Volume", NAU8824_REG_ADC_CH3_DGAIN_CTRL,
399 0, 0x164, 0, dmic_vol_tlv),
400
401 SOC_ENUM("ADC CH0 Select", nau8824_adc_ch0_enum),
402 SOC_ENUM("ADC CH1 Select", nau8824_adc_ch1_enum),
403 SOC_ENUM("ADC CH2 Select", nau8824_adc_ch2_enum),
404 SOC_ENUM("ADC CH3 Select", nau8824_adc_ch3_enum),
405
406 SOC_SINGLE("ADC CH0 TX Switch", NAU8824_REG_TDM_CTRL, 0, 1, 0),
407 SOC_SINGLE("ADC CH1 TX Switch", NAU8824_REG_TDM_CTRL, 1, 1, 0),
408 SOC_SINGLE("ADC CH2 TX Switch", NAU8824_REG_TDM_CTRL, 2, 1, 0),
409 SOC_SINGLE("ADC CH3 TX Switch", NAU8824_REG_TDM_CTRL, 3, 1, 0),
410
411 SOC_ENUM("DACL Channel Source", nau8824_dac_left_sel_enum),
412 SOC_ENUM("DACR Channel Source", nau8824_dac_right_sel_enum),
413
414 SOC_SINGLE("DACL LR Mix", NAU8824_REG_DAC_MUTE_CTRL, 0, 1, 0),
415 SOC_SINGLE("DACR LR Mix", NAU8824_REG_DAC_MUTE_CTRL, 1, 1, 0),
416
417 SOC_SINGLE("THD for key media",
418 NAU8824_REG_VDET_THRESHOLD_1, 8, 0xff, 0),
419 SOC_SINGLE("THD for key voice command",
420 NAU8824_REG_VDET_THRESHOLD_1, 0, 0xff, 0),
421 SOC_SINGLE("THD for key volume up",
422 NAU8824_REG_VDET_THRESHOLD_2, 8, 0xff, 0),
423 SOC_SINGLE("THD for key volume down",
424 NAU8824_REG_VDET_THRESHOLD_2, 0, 0xff, 0),
425 };
426
nau8824_output_dac_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)427 static int nau8824_output_dac_event(struct snd_soc_dapm_widget *w,
428 struct snd_kcontrol *kcontrol, int event)
429 {
430 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
431 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component);
432
433 switch (event) {
434 case SND_SOC_DAPM_PRE_PMU:
435 /* Disables the TESTDAC to let DAC signal pass through. */
436 regmap_update_bits(nau8824->regmap, NAU8824_REG_ENABLE_LO,
437 NAU8824_TEST_DAC_EN, 0);
438 break;
439 case SND_SOC_DAPM_POST_PMD:
440 regmap_update_bits(nau8824->regmap, NAU8824_REG_ENABLE_LO,
441 NAU8824_TEST_DAC_EN, NAU8824_TEST_DAC_EN);
442 break;
443 default:
444 return -EINVAL;
445 }
446
447 return 0;
448 }
449
nau8824_spk_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)450 static int nau8824_spk_event(struct snd_soc_dapm_widget *w,
451 struct snd_kcontrol *kcontrol, int event)
452 {
453 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
454 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component);
455
456 switch (event) {
457 case SND_SOC_DAPM_PRE_PMU:
458 regmap_update_bits(nau8824->regmap,
459 NAU8824_REG_ANALOG_CONTROL_2,
460 NAU8824_CLASSD_CLAMP_DIS, NAU8824_CLASSD_CLAMP_DIS);
461 break;
462 case SND_SOC_DAPM_POST_PMD:
463 regmap_update_bits(nau8824->regmap,
464 NAU8824_REG_ANALOG_CONTROL_2,
465 NAU8824_CLASSD_CLAMP_DIS, 0);
466 break;
467 default:
468 return -EINVAL;
469 }
470
471 return 0;
472 }
473
nau8824_pump_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)474 static int nau8824_pump_event(struct snd_soc_dapm_widget *w,
475 struct snd_kcontrol *kcontrol, int event)
476 {
477 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
478 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component);
479
480 switch (event) {
481 case SND_SOC_DAPM_POST_PMU:
482 /* Prevent startup click by letting charge pump to ramp up */
483 msleep(10);
484 regmap_update_bits(nau8824->regmap,
485 NAU8824_REG_CHARGE_PUMP_CONTROL,
486 NAU8824_JAMNODCLOW, NAU8824_JAMNODCLOW);
487 break;
488 case SND_SOC_DAPM_PRE_PMD:
489 regmap_update_bits(nau8824->regmap,
490 NAU8824_REG_CHARGE_PUMP_CONTROL,
491 NAU8824_JAMNODCLOW, 0);
492 break;
493 default:
494 return -EINVAL;
495 }
496
497 return 0;
498 }
499
system_clock_control(struct snd_soc_dapm_widget * w,struct snd_kcontrol * k,int event)500 static int system_clock_control(struct snd_soc_dapm_widget *w,
501 struct snd_kcontrol *k, int event)
502 {
503 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
504 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component);
505 struct regmap *regmap = nau8824->regmap;
506 unsigned int value;
507 bool clk_fll, error;
508
509 if (SND_SOC_DAPM_EVENT_OFF(event)) {
510 dev_dbg(nau8824->dev, "system clock control : POWER OFF\n");
511 /* Set clock source to disable or internal clock before the
512 * playback or capture end. Codec needs clock for Jack
513 * detection and button press if jack inserted; otherwise,
514 * the clock should be closed.
515 */
516 if (nau8824_is_jack_inserted(nau8824)) {
517 nau8824_config_sysclk(nau8824,
518 NAU8824_CLK_INTERNAL, 0);
519 } else {
520 nau8824_config_sysclk(nau8824, NAU8824_CLK_DIS, 0);
521 }
522 } else {
523 dev_dbg(nau8824->dev, "system clock control : POWER ON\n");
524 /* Check the clock source setting is proper or not
525 * no matter the source is from FLL or MCLK.
526 */
527 regmap_read(regmap, NAU8824_REG_FLL1, &value);
528 clk_fll = value & NAU8824_FLL_RATIO_MASK;
529 /* It's error to use internal clock when playback */
530 regmap_read(regmap, NAU8824_REG_FLL6, &value);
531 error = value & NAU8824_DCO_EN;
532 if (!error) {
533 /* Check error depending on source is FLL or MCLK. */
534 regmap_read(regmap, NAU8824_REG_CLK_DIVIDER, &value);
535 if (clk_fll)
536 error = !(value & NAU8824_CLK_SRC_VCO);
537 else
538 error = value & NAU8824_CLK_SRC_VCO;
539 }
540 /* Recover the clock source setting if error. */
541 if (error) {
542 if (clk_fll) {
543 regmap_update_bits(regmap,
544 NAU8824_REG_FLL6, NAU8824_DCO_EN, 0);
545 regmap_update_bits(regmap,
546 NAU8824_REG_CLK_DIVIDER,
547 NAU8824_CLK_SRC_MASK,
548 NAU8824_CLK_SRC_VCO);
549 } else {
550 nau8824_config_sysclk(nau8824,
551 NAU8824_CLK_MCLK, 0);
552 }
553 }
554 }
555
556 return 0;
557 }
558
dmic_clock_control(struct snd_soc_dapm_widget * w,struct snd_kcontrol * k,int event)559 static int dmic_clock_control(struct snd_soc_dapm_widget *w,
560 struct snd_kcontrol *k, int event)
561 {
562 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
563 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component);
564 int src;
565
566 /* The DMIC clock is gotten from system clock (256fs) divided by
567 * DMIC_SRC (1, 2, 4, 8, 16, 32). The clock has to be equal or
568 * less than 3.072 MHz.
569 */
570 for (src = 0; src < 5; src++) {
571 if ((0x1 << (8 - src)) * nau8824->fs <= DMIC_CLK)
572 break;
573 }
574 dev_dbg(nau8824->dev, "dmic src %d for mclk %d\n", src, nau8824->fs * 256);
575 regmap_update_bits(nau8824->regmap, NAU8824_REG_CLK_DIVIDER,
576 NAU8824_CLK_DMIC_SRC_MASK, (src << NAU8824_CLK_DMIC_SRC_SFT));
577
578 return 0;
579 }
580
581 static const struct snd_kcontrol_new nau8824_adc_ch0_dmic =
582 SOC_DAPM_SINGLE("Switch", NAU8824_REG_ENA_CTRL,
583 NAU8824_ADC_CH0_DMIC_SFT, 1, 0);
584
585 static const struct snd_kcontrol_new nau8824_adc_ch1_dmic =
586 SOC_DAPM_SINGLE("Switch", NAU8824_REG_ENA_CTRL,
587 NAU8824_ADC_CH1_DMIC_SFT, 1, 0);
588
589 static const struct snd_kcontrol_new nau8824_adc_ch2_dmic =
590 SOC_DAPM_SINGLE("Switch", NAU8824_REG_ENA_CTRL,
591 NAU8824_ADC_CH2_DMIC_SFT, 1, 0);
592
593 static const struct snd_kcontrol_new nau8824_adc_ch3_dmic =
594 SOC_DAPM_SINGLE("Switch", NAU8824_REG_ENA_CTRL,
595 NAU8824_ADC_CH3_DMIC_SFT, 1, 0);
596
597 static const struct snd_kcontrol_new nau8824_adc_left_mixer[] = {
598 SOC_DAPM_SINGLE("MIC Switch", NAU8824_REG_FEPGA,
599 NAU8824_FEPGA_MODEL_MIC1_SFT, 1, 0),
600 SOC_DAPM_SINGLE("HSMIC Switch", NAU8824_REG_FEPGA,
601 NAU8824_FEPGA_MODEL_HSMIC_SFT, 1, 0),
602 };
603
604 static const struct snd_kcontrol_new nau8824_adc_right_mixer[] = {
605 SOC_DAPM_SINGLE("MIC Switch", NAU8824_REG_FEPGA,
606 NAU8824_FEPGA_MODER_MIC2_SFT, 1, 0),
607 SOC_DAPM_SINGLE("HSMIC Switch", NAU8824_REG_FEPGA,
608 NAU8824_FEPGA_MODER_HSMIC_SFT, 1, 0),
609 };
610
611 static const struct snd_kcontrol_new nau8824_hp_left_mixer[] = {
612 SOC_DAPM_SINGLE("DAC Right Switch", NAU8824_REG_ENABLE_LO,
613 NAU8824_DACR_HPL_EN_SFT, 1, 0),
614 SOC_DAPM_SINGLE("DAC Left Switch", NAU8824_REG_ENABLE_LO,
615 NAU8824_DACL_HPL_EN_SFT, 1, 0),
616 };
617
618 static const struct snd_kcontrol_new nau8824_hp_right_mixer[] = {
619 SOC_DAPM_SINGLE("DAC Left Switch", NAU8824_REG_ENABLE_LO,
620 NAU8824_DACL_HPR_EN_SFT, 1, 0),
621 SOC_DAPM_SINGLE("DAC Right Switch", NAU8824_REG_ENABLE_LO,
622 NAU8824_DACR_HPR_EN_SFT, 1, 0),
623 };
624
625 static const char * const nau8824_dac_src[] = { "DACL", "DACR" };
626
627 static SOC_ENUM_SINGLE_DECL(
628 nau8824_dacl_enum, NAU8824_REG_DAC_CH0_DGAIN_CTRL,
629 NAU8824_DAC_CH0_SEL_SFT, nau8824_dac_src);
630
631 static SOC_ENUM_SINGLE_DECL(
632 nau8824_dacr_enum, NAU8824_REG_DAC_CH1_DGAIN_CTRL,
633 NAU8824_DAC_CH1_SEL_SFT, nau8824_dac_src);
634
635 static const struct snd_kcontrol_new nau8824_dacl_mux =
636 SOC_DAPM_ENUM("DACL Source", nau8824_dacl_enum);
637
638 static const struct snd_kcontrol_new nau8824_dacr_mux =
639 SOC_DAPM_ENUM("DACR Source", nau8824_dacr_enum);
640
641
642 static const struct snd_soc_dapm_widget nau8824_dapm_widgets[] = {
643 SND_SOC_DAPM_SUPPLY("System Clock", SND_SOC_NOPM, 0, 0,
644 system_clock_control, SND_SOC_DAPM_POST_PMD |
645 SND_SOC_DAPM_POST_PMU),
646
647 SND_SOC_DAPM_INPUT("HSMIC1"),
648 SND_SOC_DAPM_INPUT("HSMIC2"),
649 SND_SOC_DAPM_INPUT("MIC1"),
650 SND_SOC_DAPM_INPUT("MIC2"),
651 SND_SOC_DAPM_INPUT("DMIC1"),
652 SND_SOC_DAPM_INPUT("DMIC2"),
653 SND_SOC_DAPM_INPUT("DMIC3"),
654 SND_SOC_DAPM_INPUT("DMIC4"),
655
656 SND_SOC_DAPM_SUPPLY("SAR", NAU8824_REG_SAR_ADC,
657 NAU8824_SAR_ADC_EN_SFT, 0, NULL, 0),
658 SND_SOC_DAPM_SUPPLY("MICBIAS", NAU8824_REG_MIC_BIAS,
659 NAU8824_MICBIAS_POWERUP_SFT, 0, NULL, 0),
660 SND_SOC_DAPM_SUPPLY("DMIC12 Power", NAU8824_REG_BIAS_ADJ,
661 NAU8824_DMIC1_EN_SFT, 0, NULL, 0),
662 SND_SOC_DAPM_SUPPLY("DMIC34 Power", NAU8824_REG_BIAS_ADJ,
663 NAU8824_DMIC2_EN_SFT, 0, NULL, 0),
664 SND_SOC_DAPM_SUPPLY("DMIC Clock", SND_SOC_NOPM, 0, 0,
665 dmic_clock_control, SND_SOC_DAPM_POST_PMU),
666
667 SND_SOC_DAPM_SWITCH("DMIC1 Enable", SND_SOC_NOPM,
668 0, 0, &nau8824_adc_ch0_dmic),
669 SND_SOC_DAPM_SWITCH("DMIC2 Enable", SND_SOC_NOPM,
670 0, 0, &nau8824_adc_ch1_dmic),
671 SND_SOC_DAPM_SWITCH("DMIC3 Enable", SND_SOC_NOPM,
672 0, 0, &nau8824_adc_ch2_dmic),
673 SND_SOC_DAPM_SWITCH("DMIC4 Enable", SND_SOC_NOPM,
674 0, 0, &nau8824_adc_ch3_dmic),
675
676 SND_SOC_DAPM_MIXER("Left ADC", NAU8824_REG_POWER_UP_CONTROL,
677 12, 0, nau8824_adc_left_mixer,
678 ARRAY_SIZE(nau8824_adc_left_mixer)),
679 SND_SOC_DAPM_MIXER("Right ADC", NAU8824_REG_POWER_UP_CONTROL,
680 13, 0, nau8824_adc_right_mixer,
681 ARRAY_SIZE(nau8824_adc_right_mixer)),
682
683 SND_SOC_DAPM_ADC("ADCL", NULL, NAU8824_REG_ANALOG_ADC_2,
684 NAU8824_ADCL_EN_SFT, 0),
685 SND_SOC_DAPM_ADC("ADCR", NULL, NAU8824_REG_ANALOG_ADC_2,
686 NAU8824_ADCR_EN_SFT, 0),
687
688 SND_SOC_DAPM_AIF_OUT("AIFTX", "Capture", 0, SND_SOC_NOPM, 0, 0),
689 SND_SOC_DAPM_AIF_IN("AIFRX", "Playback", 0, SND_SOC_NOPM, 0, 0),
690
691 SND_SOC_DAPM_DAC("DACL", NULL, NAU8824_REG_RDAC,
692 NAU8824_DACL_EN_SFT, 0),
693 SND_SOC_DAPM_SUPPLY("DACL Clock", NAU8824_REG_RDAC,
694 NAU8824_DACL_CLK_SFT, 0, NULL, 0),
695 SND_SOC_DAPM_DAC("DACR", NULL, NAU8824_REG_RDAC,
696 NAU8824_DACR_EN_SFT, 0),
697 SND_SOC_DAPM_SUPPLY("DACR Clock", NAU8824_REG_RDAC,
698 NAU8824_DACR_CLK_SFT, 0, NULL, 0),
699
700 SND_SOC_DAPM_MUX("DACL Mux", SND_SOC_NOPM, 0, 0, &nau8824_dacl_mux),
701 SND_SOC_DAPM_MUX("DACR Mux", SND_SOC_NOPM, 0, 0, &nau8824_dacr_mux),
702
703 SND_SOC_DAPM_PGA_S("Output DACL", 0, NAU8824_REG_CHARGE_PUMP_CONTROL,
704 8, 1, nau8824_output_dac_event,
705 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
706 SND_SOC_DAPM_PGA_S("Output DACR", 0, NAU8824_REG_CHARGE_PUMP_CONTROL,
707 9, 1, nau8824_output_dac_event,
708 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
709
710 SND_SOC_DAPM_PGA_S("ClassD", 0, NAU8824_REG_CLASSD_GAIN_1,
711 NAU8824_CLASSD_EN_SFT, 0, nau8824_spk_event,
712 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
713
714 SND_SOC_DAPM_MIXER("Left Headphone", NAU8824_REG_CLASSG,
715 NAU8824_CLASSG_LDAC_EN_SFT, 0, nau8824_hp_left_mixer,
716 ARRAY_SIZE(nau8824_hp_left_mixer)),
717 SND_SOC_DAPM_MIXER("Right Headphone", NAU8824_REG_CLASSG,
718 NAU8824_CLASSG_RDAC_EN_SFT, 0, nau8824_hp_right_mixer,
719 ARRAY_SIZE(nau8824_hp_right_mixer)),
720 SND_SOC_DAPM_PGA_S("Charge Pump", 1, NAU8824_REG_CHARGE_PUMP_CONTROL,
721 NAU8824_CHARGE_PUMP_EN_SFT, 0, nau8824_pump_event,
722 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
723 SND_SOC_DAPM_PGA("Output Driver L",
724 NAU8824_REG_POWER_UP_CONTROL, 3, 0, NULL, 0),
725 SND_SOC_DAPM_PGA("Output Driver R",
726 NAU8824_REG_POWER_UP_CONTROL, 2, 0, NULL, 0),
727 SND_SOC_DAPM_PGA("Main Driver L",
728 NAU8824_REG_POWER_UP_CONTROL, 1, 0, NULL, 0),
729 SND_SOC_DAPM_PGA("Main Driver R",
730 NAU8824_REG_POWER_UP_CONTROL, 0, 0, NULL, 0),
731 SND_SOC_DAPM_PGA("HP Boost Driver", NAU8824_REG_BOOST,
732 NAU8824_HP_BOOST_DIS_SFT, 1, NULL, 0),
733 SND_SOC_DAPM_PGA("Class G", NAU8824_REG_CLASSG,
734 NAU8824_CLASSG_EN_SFT, 0, NULL, 0),
735
736 SND_SOC_DAPM_OUTPUT("SPKOUTL"),
737 SND_SOC_DAPM_OUTPUT("SPKOUTR"),
738 SND_SOC_DAPM_OUTPUT("HPOL"),
739 SND_SOC_DAPM_OUTPUT("HPOR"),
740 };
741
742 static const struct snd_soc_dapm_route nau8824_dapm_routes[] = {
743 {"DMIC1 Enable", "Switch", "DMIC1"},
744 {"DMIC2 Enable", "Switch", "DMIC2"},
745 {"DMIC3 Enable", "Switch", "DMIC3"},
746 {"DMIC4 Enable", "Switch", "DMIC4"},
747
748 {"DMIC1", NULL, "DMIC12 Power"},
749 {"DMIC2", NULL, "DMIC12 Power"},
750 {"DMIC3", NULL, "DMIC34 Power"},
751 {"DMIC4", NULL, "DMIC34 Power"},
752 {"DMIC12 Power", NULL, "DMIC Clock"},
753 {"DMIC34 Power", NULL, "DMIC Clock"},
754
755 {"Left ADC", "MIC Switch", "MIC1"},
756 {"Left ADC", "HSMIC Switch", "HSMIC1"},
757 {"Right ADC", "MIC Switch", "MIC2"},
758 {"Right ADC", "HSMIC Switch", "HSMIC2"},
759
760 {"ADCL", NULL, "Left ADC"},
761 {"ADCR", NULL, "Right ADC"},
762
763 {"AIFTX", NULL, "MICBIAS"},
764 {"AIFTX", NULL, "ADCL"},
765 {"AIFTX", NULL, "ADCR"},
766 {"AIFTX", NULL, "DMIC1 Enable"},
767 {"AIFTX", NULL, "DMIC2 Enable"},
768 {"AIFTX", NULL, "DMIC3 Enable"},
769 {"AIFTX", NULL, "DMIC4 Enable"},
770
771 {"AIFTX", NULL, "System Clock"},
772 {"AIFRX", NULL, "System Clock"},
773
774 {"DACL", NULL, "AIFRX"},
775 {"DACL", NULL, "DACL Clock"},
776 {"DACR", NULL, "AIFRX"},
777 {"DACR", NULL, "DACR Clock"},
778
779 {"DACL Mux", "DACL", "DACL"},
780 {"DACL Mux", "DACR", "DACR"},
781 {"DACR Mux", "DACL", "DACL"},
782 {"DACR Mux", "DACR", "DACR"},
783
784 {"Output DACL", NULL, "DACL Mux"},
785 {"Output DACR", NULL, "DACR Mux"},
786
787 {"ClassD", NULL, "Output DACL"},
788 {"ClassD", NULL, "Output DACR"},
789
790 {"Left Headphone", "DAC Left Switch", "Output DACL"},
791 {"Left Headphone", "DAC Right Switch", "Output DACR"},
792 {"Right Headphone", "DAC Left Switch", "Output DACL"},
793 {"Right Headphone", "DAC Right Switch", "Output DACR"},
794
795 {"Charge Pump", NULL, "Left Headphone"},
796 {"Charge Pump", NULL, "Right Headphone"},
797 {"Output Driver L", NULL, "Charge Pump"},
798 {"Output Driver R", NULL, "Charge Pump"},
799 {"Main Driver L", NULL, "Output Driver L"},
800 {"Main Driver R", NULL, "Output Driver R"},
801 {"Class G", NULL, "Main Driver L"},
802 {"Class G", NULL, "Main Driver R"},
803 {"HP Boost Driver", NULL, "Class G"},
804
805 {"SPKOUTL", NULL, "ClassD"},
806 {"SPKOUTR", NULL, "ClassD"},
807 {"HPOL", NULL, "HP Boost Driver"},
808 {"HPOR", NULL, "HP Boost Driver"},
809 };
810
nau8824_is_jack_inserted(struct nau8824 * nau8824)811 static bool nau8824_is_jack_inserted(struct nau8824 *nau8824)
812 {
813 struct snd_soc_jack *jack = nau8824->jack;
814 bool insert = false;
815
816 if (nau8824->irq && jack)
817 insert = jack->status & SND_JACK_HEADPHONE;
818
819 return insert;
820 }
821
nau8824_int_status_clear_all(struct regmap * regmap)822 static void nau8824_int_status_clear_all(struct regmap *regmap)
823 {
824 int active_irq, clear_irq, i;
825
826 /* Reset the intrruption status from rightmost bit if the corres-
827 * ponding irq event occurs.
828 */
829 regmap_read(regmap, NAU8824_REG_IRQ, &active_irq);
830 for (i = 0; i < NAU8824_REG_DATA_LEN; i++) {
831 clear_irq = (0x1 << i);
832 if (active_irq & clear_irq)
833 regmap_write(regmap,
834 NAU8824_REG_CLEAR_INT_REG, clear_irq);
835 }
836 }
837
nau8824_dapm_disable_pin(struct nau8824 * nau8824,const char * pin)838 static void nau8824_dapm_disable_pin(struct nau8824 *nau8824, const char *pin)
839 {
840 struct snd_soc_dapm_context *dapm = nau8824->dapm;
841 const char *prefix = dapm->component->name_prefix;
842 char prefixed_pin[80];
843
844 if (prefix) {
845 snprintf(prefixed_pin, sizeof(prefixed_pin), "%s %s",
846 prefix, pin);
847 snd_soc_dapm_disable_pin(dapm, prefixed_pin);
848 } else {
849 snd_soc_dapm_disable_pin(dapm, pin);
850 }
851 }
852
nau8824_dapm_enable_pin(struct nau8824 * nau8824,const char * pin)853 static void nau8824_dapm_enable_pin(struct nau8824 *nau8824, const char *pin)
854 {
855 struct snd_soc_dapm_context *dapm = nau8824->dapm;
856 const char *prefix = dapm->component->name_prefix;
857 char prefixed_pin[80];
858
859 if (prefix) {
860 snprintf(prefixed_pin, sizeof(prefixed_pin), "%s %s",
861 prefix, pin);
862 snd_soc_dapm_force_enable_pin(dapm, prefixed_pin);
863 } else {
864 snd_soc_dapm_force_enable_pin(dapm, pin);
865 }
866 }
867
nau8824_eject_jack(struct nau8824 * nau8824)868 static void nau8824_eject_jack(struct nau8824 *nau8824)
869 {
870 struct snd_soc_dapm_context *dapm = nau8824->dapm;
871 struct regmap *regmap = nau8824->regmap;
872
873 /* Clear all interruption status */
874 nau8824_int_status_clear_all(regmap);
875
876 nau8824_dapm_disable_pin(nau8824, "SAR");
877 nau8824_dapm_disable_pin(nau8824, "MICBIAS");
878 snd_soc_dapm_sync(dapm);
879
880 /* Enable the insertion interruption, disable the ejection
881 * interruption, and then bypass de-bounce circuit.
882 */
883 regmap_update_bits(regmap, NAU8824_REG_INTERRUPT_SETTING,
884 NAU8824_IRQ_KEY_RELEASE_DIS | NAU8824_IRQ_KEY_SHORT_PRESS_DIS |
885 NAU8824_IRQ_EJECT_DIS | NAU8824_IRQ_INSERT_DIS,
886 NAU8824_IRQ_KEY_RELEASE_DIS | NAU8824_IRQ_KEY_SHORT_PRESS_DIS |
887 NAU8824_IRQ_EJECT_DIS);
888 regmap_update_bits(regmap, NAU8824_REG_INTERRUPT_SETTING_1,
889 NAU8824_IRQ_INSERT_EN | NAU8824_IRQ_EJECT_EN,
890 NAU8824_IRQ_INSERT_EN);
891 regmap_update_bits(regmap, NAU8824_REG_ENA_CTRL,
892 NAU8824_JD_SLEEP_MODE, NAU8824_JD_SLEEP_MODE);
893
894 /* Close clock for jack type detection at manual mode */
895 if (dapm->bias_level < SND_SOC_BIAS_PREPARE)
896 nau8824_config_sysclk(nau8824, NAU8824_CLK_DIS, 0);
897 }
898
nau8824_jdet_work(struct work_struct * work)899 static void nau8824_jdet_work(struct work_struct *work)
900 {
901 struct nau8824 *nau8824 = container_of(
902 work, struct nau8824, jdet_work);
903 struct snd_soc_dapm_context *dapm = nau8824->dapm;
904 struct regmap *regmap = nau8824->regmap;
905 int adc_value, event = 0, event_mask = 0;
906
907 nau8824_dapm_enable_pin(nau8824, "MICBIAS");
908 nau8824_dapm_enable_pin(nau8824, "SAR");
909 snd_soc_dapm_sync(dapm);
910
911 msleep(100);
912
913 regmap_read(regmap, NAU8824_REG_SAR_ADC_DATA_OUT, &adc_value);
914 adc_value = adc_value & NAU8824_SAR_ADC_DATA_MASK;
915 dev_dbg(nau8824->dev, "SAR ADC data 0x%02x\n", adc_value);
916 if (adc_value < HEADSET_SARADC_THD) {
917 event |= SND_JACK_HEADPHONE;
918
919 nau8824_dapm_disable_pin(nau8824, "SAR");
920 nau8824_dapm_disable_pin(nau8824, "MICBIAS");
921 snd_soc_dapm_sync(dapm);
922 } else {
923 event |= SND_JACK_HEADSET;
924 }
925 event_mask |= SND_JACK_HEADSET;
926 snd_soc_jack_report(nau8824->jack, event, event_mask);
927
928 /* Enable short key press and release interruption. */
929 regmap_update_bits(regmap, NAU8824_REG_INTERRUPT_SETTING,
930 NAU8824_IRQ_KEY_RELEASE_DIS |
931 NAU8824_IRQ_KEY_SHORT_PRESS_DIS, 0);
932
933 nau8824_sema_release(nau8824);
934 }
935
nau8824_setup_auto_irq(struct nau8824 * nau8824)936 static void nau8824_setup_auto_irq(struct nau8824 *nau8824)
937 {
938 struct regmap *regmap = nau8824->regmap;
939
940 /* Enable jack ejection interruption. */
941 regmap_update_bits(regmap, NAU8824_REG_INTERRUPT_SETTING_1,
942 NAU8824_IRQ_INSERT_EN | NAU8824_IRQ_EJECT_EN,
943 NAU8824_IRQ_EJECT_EN);
944 regmap_update_bits(regmap, NAU8824_REG_INTERRUPT_SETTING,
945 NAU8824_IRQ_EJECT_DIS, 0);
946 /* Enable internal VCO needed for interruptions */
947 if (nau8824->dapm->bias_level < SND_SOC_BIAS_PREPARE)
948 nau8824_config_sysclk(nau8824, NAU8824_CLK_INTERNAL, 0);
949 regmap_update_bits(regmap, NAU8824_REG_ENA_CTRL,
950 NAU8824_JD_SLEEP_MODE, 0);
951 }
952
nau8824_button_decode(int value)953 static int nau8824_button_decode(int value)
954 {
955 int buttons = 0;
956
957 /* The chip supports up to 8 buttons, but ALSA defines
958 * only 6 buttons.
959 */
960 if (value & BIT(0))
961 buttons |= SND_JACK_BTN_0;
962 if (value & BIT(1))
963 buttons |= SND_JACK_BTN_1;
964 if (value & BIT(2))
965 buttons |= SND_JACK_BTN_2;
966 if (value & BIT(3))
967 buttons |= SND_JACK_BTN_3;
968 if (value & BIT(4))
969 buttons |= SND_JACK_BTN_4;
970 if (value & BIT(5))
971 buttons |= SND_JACK_BTN_5;
972
973 return buttons;
974 }
975
976 #define NAU8824_BUTTONS (SND_JACK_BTN_0 | SND_JACK_BTN_1 | \
977 SND_JACK_BTN_2 | SND_JACK_BTN_3)
978
nau8824_interrupt(int irq,void * data)979 static irqreturn_t nau8824_interrupt(int irq, void *data)
980 {
981 struct nau8824 *nau8824 = (struct nau8824 *)data;
982 struct regmap *regmap = nau8824->regmap;
983 int active_irq, clear_irq = 0, event = 0, event_mask = 0;
984
985 if (regmap_read(regmap, NAU8824_REG_IRQ, &active_irq)) {
986 dev_err(nau8824->dev, "failed to read irq status\n");
987 return IRQ_NONE;
988 }
989 dev_dbg(nau8824->dev, "IRQ %x\n", active_irq);
990
991 if (active_irq & NAU8824_JACK_EJECTION_DETECTED) {
992 nau8824_eject_jack(nau8824);
993 event_mask |= SND_JACK_HEADSET;
994 clear_irq = NAU8824_JACK_EJECTION_DETECTED;
995 /* release semaphore held after resume,
996 * and cancel jack detection
997 */
998 nau8824_sema_release(nau8824);
999 cancel_work_sync(&nau8824->jdet_work);
1000 } else if (active_irq & NAU8824_KEY_SHORT_PRESS_IRQ) {
1001 int key_status, button_pressed;
1002
1003 regmap_read(regmap, NAU8824_REG_CLEAR_INT_REG,
1004 &key_status);
1005
1006 /* lower 8 bits of the register are for pressed keys */
1007 button_pressed = nau8824_button_decode(key_status);
1008
1009 event |= button_pressed;
1010 dev_dbg(nau8824->dev, "button %x pressed\n", event);
1011 event_mask |= NAU8824_BUTTONS;
1012 clear_irq = NAU8824_KEY_SHORT_PRESS_IRQ;
1013 } else if (active_irq & NAU8824_KEY_RELEASE_IRQ) {
1014 event_mask = NAU8824_BUTTONS;
1015 clear_irq = NAU8824_KEY_RELEASE_IRQ;
1016 } else if (active_irq & NAU8824_JACK_INSERTION_DETECTED) {
1017 /* Turn off insertion interruption at manual mode */
1018 regmap_update_bits(regmap,
1019 NAU8824_REG_INTERRUPT_SETTING,
1020 NAU8824_IRQ_INSERT_DIS,
1021 NAU8824_IRQ_INSERT_DIS);
1022 regmap_update_bits(regmap,
1023 NAU8824_REG_INTERRUPT_SETTING_1,
1024 NAU8824_IRQ_INSERT_EN, 0);
1025 /* detect microphone and jack type */
1026 cancel_work_sync(&nau8824->jdet_work);
1027 schedule_work(&nau8824->jdet_work);
1028
1029 /* Enable interruption for jack type detection at audo
1030 * mode which can detect microphone and jack type.
1031 */
1032 nau8824_setup_auto_irq(nau8824);
1033 }
1034
1035 if (!clear_irq)
1036 clear_irq = active_irq;
1037 /* clears the rightmost interruption */
1038 regmap_write(regmap, NAU8824_REG_CLEAR_INT_REG, clear_irq);
1039
1040 if (event_mask)
1041 snd_soc_jack_report(nau8824->jack, event, event_mask);
1042
1043 return IRQ_HANDLED;
1044 }
1045
nau8824_clock_check(struct nau8824 * nau8824,int stream,int rate,int osr)1046 static int nau8824_clock_check(struct nau8824 *nau8824,
1047 int stream, int rate, int osr)
1048 {
1049 int osrate;
1050
1051 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
1052 if (osr >= ARRAY_SIZE(osr_dac_sel))
1053 return -EINVAL;
1054 osrate = osr_dac_sel[osr].osr;
1055 } else {
1056 if (osr >= ARRAY_SIZE(osr_adc_sel))
1057 return -EINVAL;
1058 osrate = osr_adc_sel[osr].osr;
1059 }
1060
1061 if (!osrate || rate * osr > CLK_DA_AD_MAX) {
1062 dev_err(nau8824->dev, "exceed the maximum frequency of CLK_ADC or CLK_DAC\n");
1063 return -EINVAL;
1064 }
1065
1066 return 0;
1067 }
1068
nau8824_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)1069 static int nau8824_hw_params(struct snd_pcm_substream *substream,
1070 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
1071 {
1072 struct snd_soc_component *component = dai->component;
1073 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component);
1074 unsigned int val_len = 0, osr, ctrl_val, bclk_fs, bclk_div;
1075 int err = -EINVAL;
1076
1077 nau8824_sema_acquire(nau8824, HZ);
1078
1079 /* CLK_DAC or CLK_ADC = OSR * FS
1080 * DAC or ADC clock frequency is defined as Over Sampling Rate (OSR)
1081 * multiplied by the audio sample rate (Fs). Note that the OSR and Fs
1082 * values must be selected such that the maximum frequency is less
1083 * than 6.144 MHz.
1084 */
1085 nau8824->fs = params_rate(params);
1086 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1087 regmap_read(nau8824->regmap,
1088 NAU8824_REG_DAC_FILTER_CTRL_1, &osr);
1089 osr &= NAU8824_DAC_OVERSAMPLE_MASK;
1090 if (nau8824_clock_check(nau8824, substream->stream,
1091 nau8824->fs, osr))
1092 goto error;
1093 regmap_update_bits(nau8824->regmap, NAU8824_REG_CLK_DIVIDER,
1094 NAU8824_CLK_DAC_SRC_MASK,
1095 osr_dac_sel[osr].clk_src << NAU8824_CLK_DAC_SRC_SFT);
1096 } else {
1097 regmap_read(nau8824->regmap,
1098 NAU8824_REG_ADC_FILTER_CTRL, &osr);
1099 osr &= NAU8824_ADC_SYNC_DOWN_MASK;
1100 if (nau8824_clock_check(nau8824, substream->stream,
1101 nau8824->fs, osr))
1102 goto error;
1103 regmap_update_bits(nau8824->regmap, NAU8824_REG_CLK_DIVIDER,
1104 NAU8824_CLK_ADC_SRC_MASK,
1105 osr_adc_sel[osr].clk_src << NAU8824_CLK_ADC_SRC_SFT);
1106 }
1107
1108 /* make BCLK and LRC divde configuration if the codec as master. */
1109 regmap_read(nau8824->regmap,
1110 NAU8824_REG_PORT0_I2S_PCM_CTRL_2, &ctrl_val);
1111 if (ctrl_val & NAU8824_I2S_MS_MASTER) {
1112 /* get the bclk and fs ratio */
1113 bclk_fs = snd_soc_params_to_bclk(params) / nau8824->fs;
1114 if (bclk_fs <= 32)
1115 bclk_div = 0x3;
1116 else if (bclk_fs <= 64)
1117 bclk_div = 0x2;
1118 else if (bclk_fs <= 128)
1119 bclk_div = 0x1;
1120 else if (bclk_fs <= 256)
1121 bclk_div = 0;
1122 else
1123 goto error;
1124 regmap_update_bits(nau8824->regmap,
1125 NAU8824_REG_PORT0_I2S_PCM_CTRL_2,
1126 NAU8824_I2S_LRC_DIV_MASK | NAU8824_I2S_BLK_DIV_MASK,
1127 (bclk_div << NAU8824_I2S_LRC_DIV_SFT) | bclk_div);
1128 }
1129
1130 switch (params_width(params)) {
1131 case 16:
1132 val_len |= NAU8824_I2S_DL_16;
1133 break;
1134 case 20:
1135 val_len |= NAU8824_I2S_DL_20;
1136 break;
1137 case 24:
1138 val_len |= NAU8824_I2S_DL_24;
1139 break;
1140 case 32:
1141 val_len |= NAU8824_I2S_DL_32;
1142 break;
1143 default:
1144 goto error;
1145 }
1146
1147 regmap_update_bits(nau8824->regmap, NAU8824_REG_PORT0_I2S_PCM_CTRL_1,
1148 NAU8824_I2S_DL_MASK, val_len);
1149 err = 0;
1150
1151 error:
1152 nau8824_sema_release(nau8824);
1153
1154 return err;
1155 }
1156
nau8824_set_fmt(struct snd_soc_dai * dai,unsigned int fmt)1157 static int nau8824_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1158 {
1159 struct snd_soc_component *component = dai->component;
1160 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component);
1161 unsigned int ctrl1_val = 0, ctrl2_val = 0;
1162
1163 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1164 case SND_SOC_DAIFMT_CBM_CFM:
1165 ctrl2_val |= NAU8824_I2S_MS_MASTER;
1166 break;
1167 case SND_SOC_DAIFMT_CBS_CFS:
1168 break;
1169 default:
1170 return -EINVAL;
1171 }
1172
1173 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1174 case SND_SOC_DAIFMT_NB_NF:
1175 break;
1176 case SND_SOC_DAIFMT_IB_NF:
1177 ctrl1_val |= NAU8824_I2S_BP_INV;
1178 break;
1179 default:
1180 return -EINVAL;
1181 }
1182
1183 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1184 case SND_SOC_DAIFMT_I2S:
1185 ctrl1_val |= NAU8824_I2S_DF_I2S;
1186 break;
1187 case SND_SOC_DAIFMT_LEFT_J:
1188 ctrl1_val |= NAU8824_I2S_DF_LEFT;
1189 break;
1190 case SND_SOC_DAIFMT_RIGHT_J:
1191 ctrl1_val |= NAU8824_I2S_DF_RIGTH;
1192 break;
1193 case SND_SOC_DAIFMT_DSP_A:
1194 ctrl1_val |= NAU8824_I2S_DF_PCM_AB;
1195 break;
1196 case SND_SOC_DAIFMT_DSP_B:
1197 ctrl1_val |= NAU8824_I2S_DF_PCM_AB;
1198 ctrl1_val |= NAU8824_I2S_PCMB_EN;
1199 break;
1200 default:
1201 return -EINVAL;
1202 }
1203
1204 nau8824_sema_acquire(nau8824, HZ);
1205
1206 regmap_update_bits(nau8824->regmap, NAU8824_REG_PORT0_I2S_PCM_CTRL_1,
1207 NAU8824_I2S_DF_MASK | NAU8824_I2S_BP_MASK |
1208 NAU8824_I2S_PCMB_EN, ctrl1_val);
1209 regmap_update_bits(nau8824->regmap, NAU8824_REG_PORT0_I2S_PCM_CTRL_2,
1210 NAU8824_I2S_MS_MASK, ctrl2_val);
1211
1212 nau8824_sema_release(nau8824);
1213
1214 return 0;
1215 }
1216
1217 /**
1218 * nau8824_set_tdm_slot - configure DAI TDM.
1219 * @dai: DAI
1220 * @tx_mask: Bitmask representing active TX slots. Ex.
1221 * 0xf for normal 4 channel TDM.
1222 * 0xf0 for shifted 4 channel TDM
1223 * @rx_mask: Bitmask [0:1] representing active DACR RX slots.
1224 * Bitmask [2:3] representing active DACL RX slots.
1225 * 00=CH0,01=CH1,10=CH2,11=CH3. Ex.
1226 * 0xf for DACL/R selecting TDM CH3.
1227 * 0xf0 for DACL/R selecting shifted TDM CH3.
1228 * @slots: Number of slots in use.
1229 * @slot_width: Width in bits for each slot.
1230 *
1231 * Configures a DAI for TDM operation. Only support 4 slots TDM.
1232 */
nau8824_set_tdm_slot(struct snd_soc_dai * dai,unsigned int tx_mask,unsigned int rx_mask,int slots,int slot_width)1233 static int nau8824_set_tdm_slot(struct snd_soc_dai *dai,
1234 unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
1235 {
1236 struct snd_soc_component *component = dai->component;
1237 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component);
1238 unsigned int tslot_l = 0, ctrl_val = 0;
1239
1240 if (slots > 4 || ((tx_mask & 0xf0) && (tx_mask & 0xf)) ||
1241 ((rx_mask & 0xf0) && (rx_mask & 0xf)) ||
1242 ((rx_mask & 0xf0) && (tx_mask & 0xf)) ||
1243 ((rx_mask & 0xf) && (tx_mask & 0xf0)))
1244 return -EINVAL;
1245
1246 ctrl_val |= (NAU8824_TDM_MODE | NAU8824_TDM_OFFSET_EN);
1247 if (tx_mask & 0xf0) {
1248 tslot_l = 4 * slot_width;
1249 ctrl_val |= (tx_mask >> 4);
1250 } else {
1251 ctrl_val |= tx_mask;
1252 }
1253 if (rx_mask & 0xf0)
1254 ctrl_val |= ((rx_mask >> 4) << NAU8824_TDM_DACR_RX_SFT);
1255 else
1256 ctrl_val |= (rx_mask << NAU8824_TDM_DACR_RX_SFT);
1257
1258 regmap_update_bits(nau8824->regmap, NAU8824_REG_TDM_CTRL,
1259 NAU8824_TDM_MODE | NAU8824_TDM_OFFSET_EN |
1260 NAU8824_TDM_DACL_RX_MASK | NAU8824_TDM_DACR_RX_MASK |
1261 NAU8824_TDM_TX_MASK, ctrl_val);
1262 regmap_update_bits(nau8824->regmap, NAU8824_REG_PORT0_LEFT_TIME_SLOT,
1263 NAU8824_TSLOT_L_MASK, tslot_l);
1264
1265 return 0;
1266 }
1267
1268 /**
1269 * nau8824_calc_fll_param - Calculate FLL parameters.
1270 * @fll_in: external clock provided to codec.
1271 * @fs: sampling rate.
1272 * @fll_param: Pointer to structure of FLL parameters.
1273 *
1274 * Calculate FLL parameters to configure codec.
1275 *
1276 * Returns 0 for success or negative error code.
1277 */
nau8824_calc_fll_param(unsigned int fll_in,unsigned int fs,struct nau8824_fll * fll_param)1278 static int nau8824_calc_fll_param(unsigned int fll_in,
1279 unsigned int fs, struct nau8824_fll *fll_param)
1280 {
1281 u64 fvco, fvco_max;
1282 unsigned int fref, i, fvco_sel;
1283
1284 /* Ensure the reference clock frequency (FREF) is <= 13.5MHz by dividing
1285 * freq_in by 1, 2, 4, or 8 using FLL pre-scalar.
1286 * FREF = freq_in / NAU8824_FLL_REF_DIV_MASK
1287 */
1288 for (i = 0; i < ARRAY_SIZE(fll_pre_scalar); i++) {
1289 fref = fll_in / fll_pre_scalar[i].param;
1290 if (fref <= NAU_FREF_MAX)
1291 break;
1292 }
1293 if (i == ARRAY_SIZE(fll_pre_scalar))
1294 return -EINVAL;
1295 fll_param->clk_ref_div = fll_pre_scalar[i].val;
1296
1297 /* Choose the FLL ratio based on FREF */
1298 for (i = 0; i < ARRAY_SIZE(fll_ratio); i++) {
1299 if (fref >= fll_ratio[i].param)
1300 break;
1301 }
1302 if (i == ARRAY_SIZE(fll_ratio))
1303 return -EINVAL;
1304 fll_param->ratio = fll_ratio[i].val;
1305
1306 /* Calculate the frequency of DCO (FDCO) given freq_out = 256 * Fs.
1307 * FDCO must be within the 90MHz - 124MHz or the FFL cannot be
1308 * guaranteed across the full range of operation.
1309 * FDCO = freq_out * 2 * mclk_src_scaling
1310 */
1311 fvco_max = 0;
1312 fvco_sel = ARRAY_SIZE(mclk_src_scaling);
1313 for (i = 0; i < ARRAY_SIZE(mclk_src_scaling); i++) {
1314 fvco = 256ULL * fs * 2 * mclk_src_scaling[i].param;
1315 if (fvco > NAU_FVCO_MIN && fvco < NAU_FVCO_MAX &&
1316 fvco_max < fvco) {
1317 fvco_max = fvco;
1318 fvco_sel = i;
1319 }
1320 }
1321 if (ARRAY_SIZE(mclk_src_scaling) == fvco_sel)
1322 return -EINVAL;
1323 fll_param->mclk_src = mclk_src_scaling[fvco_sel].val;
1324
1325 /* Calculate the FLL 10-bit integer input and the FLL 16-bit fractional
1326 * input based on FDCO, FREF and FLL ratio.
1327 */
1328 fvco = div_u64(fvco_max << 16, fref * fll_param->ratio);
1329 fll_param->fll_int = (fvco >> 16) & 0x3FF;
1330 fll_param->fll_frac = fvco & 0xFFFF;
1331 return 0;
1332 }
1333
nau8824_fll_apply(struct regmap * regmap,struct nau8824_fll * fll_param)1334 static void nau8824_fll_apply(struct regmap *regmap,
1335 struct nau8824_fll *fll_param)
1336 {
1337 regmap_update_bits(regmap, NAU8824_REG_CLK_DIVIDER,
1338 NAU8824_CLK_SRC_MASK | NAU8824_CLK_MCLK_SRC_MASK,
1339 NAU8824_CLK_SRC_MCLK | fll_param->mclk_src);
1340 regmap_update_bits(regmap, NAU8824_REG_FLL1,
1341 NAU8824_FLL_RATIO_MASK, fll_param->ratio);
1342 /* FLL 16-bit fractional input */
1343 regmap_write(regmap, NAU8824_REG_FLL2, fll_param->fll_frac);
1344 /* FLL 10-bit integer input */
1345 regmap_update_bits(regmap, NAU8824_REG_FLL3,
1346 NAU8824_FLL_INTEGER_MASK, fll_param->fll_int);
1347 /* FLL pre-scaler */
1348 regmap_update_bits(regmap, NAU8824_REG_FLL4,
1349 NAU8824_FLL_REF_DIV_MASK,
1350 fll_param->clk_ref_div << NAU8824_FLL_REF_DIV_SFT);
1351 /* select divided VCO input */
1352 regmap_update_bits(regmap, NAU8824_REG_FLL5,
1353 NAU8824_FLL_CLK_SW_MASK, NAU8824_FLL_CLK_SW_REF);
1354 /* Disable free-running mode */
1355 regmap_update_bits(regmap,
1356 NAU8824_REG_FLL6, NAU8824_DCO_EN, 0);
1357 if (fll_param->fll_frac) {
1358 regmap_update_bits(regmap, NAU8824_REG_FLL5,
1359 NAU8824_FLL_PDB_DAC_EN | NAU8824_FLL_LOOP_FTR_EN |
1360 NAU8824_FLL_FTR_SW_MASK,
1361 NAU8824_FLL_PDB_DAC_EN | NAU8824_FLL_LOOP_FTR_EN |
1362 NAU8824_FLL_FTR_SW_FILTER);
1363 regmap_update_bits(regmap, NAU8824_REG_FLL6,
1364 NAU8824_SDM_EN, NAU8824_SDM_EN);
1365 } else {
1366 regmap_update_bits(regmap, NAU8824_REG_FLL5,
1367 NAU8824_FLL_PDB_DAC_EN | NAU8824_FLL_LOOP_FTR_EN |
1368 NAU8824_FLL_FTR_SW_MASK, NAU8824_FLL_FTR_SW_ACCU);
1369 regmap_update_bits(regmap,
1370 NAU8824_REG_FLL6, NAU8824_SDM_EN, 0);
1371 }
1372 }
1373
1374 /* freq_out must be 256*Fs in order to achieve the best performance */
nau8824_set_pll(struct snd_soc_component * component,int pll_id,int source,unsigned int freq_in,unsigned int freq_out)1375 static int nau8824_set_pll(struct snd_soc_component *component, int pll_id, int source,
1376 unsigned int freq_in, unsigned int freq_out)
1377 {
1378 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component);
1379 struct nau8824_fll fll_param;
1380 int ret, fs;
1381
1382 fs = freq_out / 256;
1383 ret = nau8824_calc_fll_param(freq_in, fs, &fll_param);
1384 if (ret < 0) {
1385 dev_err(nau8824->dev, "Unsupported input clock %d\n", freq_in);
1386 return ret;
1387 }
1388 dev_dbg(nau8824->dev, "mclk_src=%x ratio=%x fll_frac=%x fll_int=%x clk_ref_div=%x\n",
1389 fll_param.mclk_src, fll_param.ratio, fll_param.fll_frac,
1390 fll_param.fll_int, fll_param.clk_ref_div);
1391
1392 nau8824_fll_apply(nau8824->regmap, &fll_param);
1393 mdelay(2);
1394 regmap_update_bits(nau8824->regmap, NAU8824_REG_CLK_DIVIDER,
1395 NAU8824_CLK_SRC_MASK, NAU8824_CLK_SRC_VCO);
1396
1397 return 0;
1398 }
1399
nau8824_config_sysclk(struct nau8824 * nau8824,int clk_id,unsigned int freq)1400 static int nau8824_config_sysclk(struct nau8824 *nau8824,
1401 int clk_id, unsigned int freq)
1402 {
1403 struct regmap *regmap = nau8824->regmap;
1404
1405 switch (clk_id) {
1406 case NAU8824_CLK_DIS:
1407 regmap_update_bits(regmap, NAU8824_REG_CLK_DIVIDER,
1408 NAU8824_CLK_SRC_MASK, NAU8824_CLK_SRC_MCLK);
1409 regmap_update_bits(regmap, NAU8824_REG_FLL6,
1410 NAU8824_DCO_EN, 0);
1411 break;
1412
1413 case NAU8824_CLK_MCLK:
1414 nau8824_sema_acquire(nau8824, HZ);
1415 regmap_update_bits(regmap, NAU8824_REG_CLK_DIVIDER,
1416 NAU8824_CLK_SRC_MASK, NAU8824_CLK_SRC_MCLK);
1417 regmap_update_bits(regmap, NAU8824_REG_FLL6,
1418 NAU8824_DCO_EN, 0);
1419 nau8824_sema_release(nau8824);
1420 break;
1421
1422 case NAU8824_CLK_INTERNAL:
1423 regmap_update_bits(regmap, NAU8824_REG_FLL6,
1424 NAU8824_DCO_EN, NAU8824_DCO_EN);
1425 regmap_update_bits(regmap, NAU8824_REG_CLK_DIVIDER,
1426 NAU8824_CLK_SRC_MASK, NAU8824_CLK_SRC_VCO);
1427 break;
1428
1429 case NAU8824_CLK_FLL_MCLK:
1430 nau8824_sema_acquire(nau8824, HZ);
1431 regmap_update_bits(regmap, NAU8824_REG_FLL3,
1432 NAU8824_FLL_CLK_SRC_MASK, NAU8824_FLL_CLK_SRC_MCLK);
1433 nau8824_sema_release(nau8824);
1434 break;
1435
1436 case NAU8824_CLK_FLL_BLK:
1437 nau8824_sema_acquire(nau8824, HZ);
1438 regmap_update_bits(regmap, NAU8824_REG_FLL3,
1439 NAU8824_FLL_CLK_SRC_MASK, NAU8824_FLL_CLK_SRC_BLK);
1440 nau8824_sema_release(nau8824);
1441 break;
1442
1443 case NAU8824_CLK_FLL_FS:
1444 nau8824_sema_acquire(nau8824, HZ);
1445 regmap_update_bits(regmap, NAU8824_REG_FLL3,
1446 NAU8824_FLL_CLK_SRC_MASK, NAU8824_FLL_CLK_SRC_FS);
1447 nau8824_sema_release(nau8824);
1448 break;
1449
1450 default:
1451 dev_err(nau8824->dev, "Invalid clock id (%d)\n", clk_id);
1452 return -EINVAL;
1453 }
1454
1455 dev_dbg(nau8824->dev, "Sysclk is %dHz and clock id is %d\n", freq,
1456 clk_id);
1457
1458 return 0;
1459 }
1460
nau8824_set_sysclk(struct snd_soc_component * component,int clk_id,int source,unsigned int freq,int dir)1461 static int nau8824_set_sysclk(struct snd_soc_component *component,
1462 int clk_id, int source, unsigned int freq, int dir)
1463 {
1464 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component);
1465
1466 return nau8824_config_sysclk(nau8824, clk_id, freq);
1467 }
1468
nau8824_resume_setup(struct nau8824 * nau8824)1469 static void nau8824_resume_setup(struct nau8824 *nau8824)
1470 {
1471 nau8824_config_sysclk(nau8824, NAU8824_CLK_DIS, 0);
1472 if (nau8824->irq) {
1473 /* Clear all interruption status */
1474 nau8824_int_status_clear_all(nau8824->regmap);
1475 /* Enable jack detection at sleep mode, insertion detection,
1476 * and ejection detection.
1477 */
1478 regmap_update_bits(nau8824->regmap, NAU8824_REG_ENA_CTRL,
1479 NAU8824_JD_SLEEP_MODE, NAU8824_JD_SLEEP_MODE);
1480 regmap_update_bits(nau8824->regmap,
1481 NAU8824_REG_INTERRUPT_SETTING_1,
1482 NAU8824_IRQ_EJECT_EN | NAU8824_IRQ_INSERT_EN,
1483 NAU8824_IRQ_EJECT_EN | NAU8824_IRQ_INSERT_EN);
1484 regmap_update_bits(nau8824->regmap,
1485 NAU8824_REG_INTERRUPT_SETTING,
1486 NAU8824_IRQ_EJECT_DIS | NAU8824_IRQ_INSERT_DIS, 0);
1487 }
1488 }
1489
nau8824_set_bias_level(struct snd_soc_component * component,enum snd_soc_bias_level level)1490 static int nau8824_set_bias_level(struct snd_soc_component *component,
1491 enum snd_soc_bias_level level)
1492 {
1493 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component);
1494
1495 switch (level) {
1496 case SND_SOC_BIAS_ON:
1497 break;
1498
1499 case SND_SOC_BIAS_PREPARE:
1500 break;
1501
1502 case SND_SOC_BIAS_STANDBY:
1503 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
1504 /* Setup codec configuration after resume */
1505 nau8824_resume_setup(nau8824);
1506 }
1507 break;
1508
1509 case SND_SOC_BIAS_OFF:
1510 regmap_update_bits(nau8824->regmap,
1511 NAU8824_REG_INTERRUPT_SETTING, 0x3ff, 0x3ff);
1512 regmap_update_bits(nau8824->regmap,
1513 NAU8824_REG_INTERRUPT_SETTING_1,
1514 NAU8824_IRQ_EJECT_EN | NAU8824_IRQ_INSERT_EN, 0);
1515 break;
1516 }
1517
1518 return 0;
1519 }
1520
nau8824_component_probe(struct snd_soc_component * component)1521 static int nau8824_component_probe(struct snd_soc_component *component)
1522 {
1523 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component);
1524 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
1525
1526 nau8824->dapm = dapm;
1527
1528 return 0;
1529 }
1530
nau8824_suspend(struct snd_soc_component * component)1531 static int __maybe_unused nau8824_suspend(struct snd_soc_component *component)
1532 {
1533 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component);
1534
1535 if (nau8824->irq) {
1536 disable_irq(nau8824->irq);
1537 snd_soc_component_force_bias_level(component, SND_SOC_BIAS_OFF);
1538 }
1539 regcache_cache_only(nau8824->regmap, true);
1540 regcache_mark_dirty(nau8824->regmap);
1541
1542 return 0;
1543 }
1544
nau8824_resume(struct snd_soc_component * component)1545 static int __maybe_unused nau8824_resume(struct snd_soc_component *component)
1546 {
1547 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component);
1548
1549 regcache_cache_only(nau8824->regmap, false);
1550 regcache_sync(nau8824->regmap);
1551 if (nau8824->irq) {
1552 /* Hold semaphore to postpone playback happening
1553 * until jack detection done.
1554 */
1555 nau8824_sema_acquire(nau8824, 0);
1556 enable_irq(nau8824->irq);
1557 }
1558
1559 return 0;
1560 }
1561
1562 static const struct snd_soc_component_driver nau8824_component_driver = {
1563 .probe = nau8824_component_probe,
1564 .set_sysclk = nau8824_set_sysclk,
1565 .set_pll = nau8824_set_pll,
1566 .set_bias_level = nau8824_set_bias_level,
1567 .suspend = nau8824_suspend,
1568 .resume = nau8824_resume,
1569 .controls = nau8824_snd_controls,
1570 .num_controls = ARRAY_SIZE(nau8824_snd_controls),
1571 .dapm_widgets = nau8824_dapm_widgets,
1572 .num_dapm_widgets = ARRAY_SIZE(nau8824_dapm_widgets),
1573 .dapm_routes = nau8824_dapm_routes,
1574 .num_dapm_routes = ARRAY_SIZE(nau8824_dapm_routes),
1575 .suspend_bias_off = 1,
1576 .idle_bias_on = 1,
1577 .use_pmdown_time = 1,
1578 .endianness = 1,
1579 .non_legacy_dai_naming = 1,
1580 };
1581
1582 static const struct snd_soc_dai_ops nau8824_dai_ops = {
1583 .hw_params = nau8824_hw_params,
1584 .set_fmt = nau8824_set_fmt,
1585 .set_tdm_slot = nau8824_set_tdm_slot,
1586 };
1587
1588 #define NAU8824_RATES SNDRV_PCM_RATE_8000_192000
1589 #define NAU8824_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \
1590 | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
1591
1592 static struct snd_soc_dai_driver nau8824_dai = {
1593 .name = NAU8824_CODEC_DAI,
1594 .playback = {
1595 .stream_name = "Playback",
1596 .channels_min = 1,
1597 .channels_max = 2,
1598 .rates = NAU8824_RATES,
1599 .formats = NAU8824_FORMATS,
1600 },
1601 .capture = {
1602 .stream_name = "Capture",
1603 .channels_min = 1,
1604 .channels_max = 2,
1605 .rates = NAU8824_RATES,
1606 .formats = NAU8824_FORMATS,
1607 },
1608 .ops = &nau8824_dai_ops,
1609 };
1610
1611 static const struct regmap_config nau8824_regmap_config = {
1612 .val_bits = NAU8824_REG_ADDR_LEN,
1613 .reg_bits = NAU8824_REG_DATA_LEN,
1614
1615 .max_register = NAU8824_REG_MAX,
1616 .readable_reg = nau8824_readable_reg,
1617 .writeable_reg = nau8824_writeable_reg,
1618 .volatile_reg = nau8824_volatile_reg,
1619
1620 .cache_type = REGCACHE_RBTREE,
1621 .reg_defaults = nau8824_reg_defaults,
1622 .num_reg_defaults = ARRAY_SIZE(nau8824_reg_defaults),
1623 };
1624
1625 /**
1626 * nau8824_enable_jack_detect - Specify a jack for event reporting
1627 *
1628 * @component: component to register the jack with
1629 * @jack: jack to use to report headset and button events on
1630 *
1631 * After this function has been called the headset insert/remove and button
1632 * events will be routed to the given jack. Jack can be null to stop
1633 * reporting.
1634 */
nau8824_enable_jack_detect(struct snd_soc_component * component,struct snd_soc_jack * jack)1635 int nau8824_enable_jack_detect(struct snd_soc_component *component,
1636 struct snd_soc_jack *jack)
1637 {
1638 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component);
1639 int ret;
1640
1641 nau8824->jack = jack;
1642 /* Initiate jack detection work queue */
1643 INIT_WORK(&nau8824->jdet_work, nau8824_jdet_work);
1644 ret = devm_request_threaded_irq(nau8824->dev, nau8824->irq, NULL,
1645 nau8824_interrupt, IRQF_TRIGGER_LOW | IRQF_ONESHOT,
1646 "nau8824", nau8824);
1647 if (ret) {
1648 dev_err(nau8824->dev, "Cannot request irq %d (%d)\n",
1649 nau8824->irq, ret);
1650 }
1651
1652 return ret;
1653 }
1654 EXPORT_SYMBOL_GPL(nau8824_enable_jack_detect);
1655
nau8824_reset_chip(struct regmap * regmap)1656 static void nau8824_reset_chip(struct regmap *regmap)
1657 {
1658 regmap_write(regmap, NAU8824_REG_RESET, 0x00);
1659 regmap_write(regmap, NAU8824_REG_RESET, 0x00);
1660 }
1661
nau8824_setup_buttons(struct nau8824 * nau8824)1662 static void nau8824_setup_buttons(struct nau8824 *nau8824)
1663 {
1664 struct regmap *regmap = nau8824->regmap;
1665
1666 regmap_update_bits(regmap, NAU8824_REG_SAR_ADC,
1667 NAU8824_SAR_TRACKING_GAIN_MASK,
1668 nau8824->sar_voltage << NAU8824_SAR_TRACKING_GAIN_SFT);
1669 regmap_update_bits(regmap, NAU8824_REG_SAR_ADC,
1670 NAU8824_SAR_COMPARE_TIME_MASK,
1671 nau8824->sar_compare_time << NAU8824_SAR_COMPARE_TIME_SFT);
1672 regmap_update_bits(regmap, NAU8824_REG_SAR_ADC,
1673 NAU8824_SAR_SAMPLING_TIME_MASK,
1674 nau8824->sar_sampling_time << NAU8824_SAR_SAMPLING_TIME_SFT);
1675
1676 regmap_update_bits(regmap, NAU8824_REG_VDET_COEFFICIENT,
1677 NAU8824_LEVELS_NR_MASK,
1678 (nau8824->sar_threshold_num - 1) << NAU8824_LEVELS_NR_SFT);
1679 regmap_update_bits(regmap, NAU8824_REG_VDET_COEFFICIENT,
1680 NAU8824_HYSTERESIS_MASK,
1681 nau8824->sar_hysteresis << NAU8824_HYSTERESIS_SFT);
1682 regmap_update_bits(regmap, NAU8824_REG_VDET_COEFFICIENT,
1683 NAU8824_SHORTKEY_DEBOUNCE_MASK,
1684 nau8824->key_debounce << NAU8824_SHORTKEY_DEBOUNCE_SFT);
1685
1686 regmap_write(regmap, NAU8824_REG_VDET_THRESHOLD_1,
1687 (nau8824->sar_threshold[0] << 8) | nau8824->sar_threshold[1]);
1688 regmap_write(regmap, NAU8824_REG_VDET_THRESHOLD_2,
1689 (nau8824->sar_threshold[2] << 8) | nau8824->sar_threshold[3]);
1690 regmap_write(regmap, NAU8824_REG_VDET_THRESHOLD_3,
1691 (nau8824->sar_threshold[4] << 8) | nau8824->sar_threshold[5]);
1692 regmap_write(regmap, NAU8824_REG_VDET_THRESHOLD_4,
1693 (nau8824->sar_threshold[6] << 8) | nau8824->sar_threshold[7]);
1694 }
1695
nau8824_init_regs(struct nau8824 * nau8824)1696 static void nau8824_init_regs(struct nau8824 *nau8824)
1697 {
1698 struct regmap *regmap = nau8824->regmap;
1699
1700 /* Enable Bias/VMID/VMID Tieoff */
1701 regmap_update_bits(regmap, NAU8824_REG_BIAS_ADJ,
1702 NAU8824_VMID | NAU8824_VMID_SEL_MASK, NAU8824_VMID |
1703 (nau8824->vref_impedance << NAU8824_VMID_SEL_SFT));
1704 regmap_update_bits(regmap, NAU8824_REG_BOOST,
1705 NAU8824_GLOBAL_BIAS_EN, NAU8824_GLOBAL_BIAS_EN);
1706 mdelay(2);
1707 regmap_update_bits(regmap, NAU8824_REG_MIC_BIAS,
1708 NAU8824_MICBIAS_VOLTAGE_MASK, nau8824->micbias_voltage);
1709 /* Disable Boost Driver, Automatic Short circuit protection enable */
1710 regmap_update_bits(regmap, NAU8824_REG_BOOST,
1711 NAU8824_PRECHARGE_DIS | NAU8824_HP_BOOST_DIS |
1712 NAU8824_HP_BOOST_G_DIS | NAU8824_SHORT_SHUTDOWN_EN,
1713 NAU8824_PRECHARGE_DIS | NAU8824_HP_BOOST_DIS |
1714 NAU8824_HP_BOOST_G_DIS | NAU8824_SHORT_SHUTDOWN_EN);
1715 /* Scaling for ADC and DAC clock */
1716 regmap_update_bits(regmap, NAU8824_REG_CLK_DIVIDER,
1717 NAU8824_CLK_ADC_SRC_MASK | NAU8824_CLK_DAC_SRC_MASK,
1718 (0x1 << NAU8824_CLK_ADC_SRC_SFT) |
1719 (0x1 << NAU8824_CLK_DAC_SRC_SFT));
1720 regmap_update_bits(regmap, NAU8824_REG_DAC_MUTE_CTRL,
1721 NAU8824_DAC_ZC_EN, NAU8824_DAC_ZC_EN);
1722 regmap_update_bits(regmap, NAU8824_REG_ENA_CTRL,
1723 NAU8824_DAC_CH1_EN | NAU8824_DAC_CH0_EN |
1724 NAU8824_ADC_CH0_EN | NAU8824_ADC_CH1_EN |
1725 NAU8824_ADC_CH2_EN | NAU8824_ADC_CH3_EN,
1726 NAU8824_DAC_CH1_EN | NAU8824_DAC_CH0_EN |
1727 NAU8824_ADC_CH0_EN | NAU8824_ADC_CH1_EN |
1728 NAU8824_ADC_CH2_EN | NAU8824_ADC_CH3_EN);
1729 regmap_update_bits(regmap, NAU8824_REG_CLK_GATING_ENA,
1730 NAU8824_CLK_ADC_CH23_EN | NAU8824_CLK_ADC_CH01_EN |
1731 NAU8824_CLK_DAC_CH1_EN | NAU8824_CLK_DAC_CH0_EN |
1732 NAU8824_CLK_I2S_EN | NAU8824_CLK_GAIN_EN |
1733 NAU8824_CLK_SAR_EN | NAU8824_CLK_DMIC_CH23_EN,
1734 NAU8824_CLK_ADC_CH23_EN | NAU8824_CLK_ADC_CH01_EN |
1735 NAU8824_CLK_DAC_CH1_EN | NAU8824_CLK_DAC_CH0_EN |
1736 NAU8824_CLK_I2S_EN | NAU8824_CLK_GAIN_EN |
1737 NAU8824_CLK_SAR_EN | NAU8824_CLK_DMIC_CH23_EN);
1738 /* Class G timer 64ms */
1739 regmap_update_bits(regmap, NAU8824_REG_CLASSG,
1740 NAU8824_CLASSG_TIMER_MASK,
1741 0x20 << NAU8824_CLASSG_TIMER_SFT);
1742 regmap_update_bits(regmap, NAU8824_REG_TRIM_SETTINGS,
1743 NAU8824_DRV_CURR_INC, NAU8824_DRV_CURR_INC);
1744 /* Disable DACR/L power */
1745 regmap_update_bits(regmap, NAU8824_REG_CHARGE_PUMP_CONTROL,
1746 NAU8824_SPKR_PULL_DOWN | NAU8824_SPKL_PULL_DOWN |
1747 NAU8824_POWER_DOWN_DACR | NAU8824_POWER_DOWN_DACL,
1748 NAU8824_SPKR_PULL_DOWN | NAU8824_SPKL_PULL_DOWN |
1749 NAU8824_POWER_DOWN_DACR | NAU8824_POWER_DOWN_DACL);
1750 /* Enable TESTDAC. This sets the analog DAC inputs to a '0' input
1751 * signal to avoid any glitches due to power up transients in both
1752 * the analog and digital DAC circuit.
1753 */
1754 regmap_update_bits(regmap, NAU8824_REG_ENABLE_LO,
1755 NAU8824_TEST_DAC_EN, NAU8824_TEST_DAC_EN);
1756 /* Config L/R channel */
1757 regmap_update_bits(regmap, NAU8824_REG_DAC_CH0_DGAIN_CTRL,
1758 NAU8824_DAC_CH0_SEL_MASK, NAU8824_DAC_CH0_SEL_I2S0);
1759 regmap_update_bits(regmap, NAU8824_REG_DAC_CH1_DGAIN_CTRL,
1760 NAU8824_DAC_CH1_SEL_MASK, NAU8824_DAC_CH1_SEL_I2S1);
1761 regmap_update_bits(regmap, NAU8824_REG_ENABLE_LO,
1762 NAU8824_DACR_HPR_EN | NAU8824_DACL_HPL_EN,
1763 NAU8824_DACR_HPR_EN | NAU8824_DACL_HPL_EN);
1764 /* Default oversampling/decimations settings are unusable
1765 * (audible hiss). Set it to something better.
1766 */
1767 regmap_update_bits(regmap, NAU8824_REG_ADC_FILTER_CTRL,
1768 NAU8824_ADC_SYNC_DOWN_MASK, NAU8824_ADC_SYNC_DOWN_64);
1769 regmap_update_bits(regmap, NAU8824_REG_DAC_FILTER_CTRL_1,
1770 NAU8824_DAC_CICCLP_OFF | NAU8824_DAC_OVERSAMPLE_MASK,
1771 NAU8824_DAC_CICCLP_OFF | NAU8824_DAC_OVERSAMPLE_64);
1772 /* DAC clock delay 2ns, VREF */
1773 regmap_update_bits(regmap, NAU8824_REG_RDAC,
1774 NAU8824_RDAC_CLK_DELAY_MASK | NAU8824_RDAC_VREF_MASK,
1775 (0x2 << NAU8824_RDAC_CLK_DELAY_SFT) |
1776 (0x3 << NAU8824_RDAC_VREF_SFT));
1777 /* PGA input mode selection */
1778 regmap_update_bits(regmap, NAU8824_REG_FEPGA,
1779 NAU8824_FEPGA_MODEL_SHORT_EN | NAU8824_FEPGA_MODER_SHORT_EN,
1780 NAU8824_FEPGA_MODEL_SHORT_EN | NAU8824_FEPGA_MODER_SHORT_EN);
1781 /* Digital microphone control */
1782 regmap_update_bits(regmap, NAU8824_REG_ANALOG_CONTROL_1,
1783 NAU8824_DMIC_CLK_DRV_STRG | NAU8824_DMIC_CLK_SLEW_FAST,
1784 NAU8824_DMIC_CLK_DRV_STRG | NAU8824_DMIC_CLK_SLEW_FAST);
1785 regmap_update_bits(regmap, NAU8824_REG_JACK_DET_CTRL,
1786 NAU8824_JACK_LOGIC,
1787 /* jkdet_polarity - 1 is for active-low */
1788 nau8824->jkdet_polarity ? 0 : NAU8824_JACK_LOGIC);
1789 regmap_update_bits(regmap,
1790 NAU8824_REG_JACK_DET_CTRL, NAU8824_JACK_EJECT_DT_MASK,
1791 (nau8824->jack_eject_debounce << NAU8824_JACK_EJECT_DT_SFT));
1792 if (nau8824->sar_threshold_num)
1793 nau8824_setup_buttons(nau8824);
1794 }
1795
nau8824_setup_irq(struct nau8824 * nau8824)1796 static int nau8824_setup_irq(struct nau8824 *nau8824)
1797 {
1798 /* Disable interruption before codec initiation done */
1799 regmap_update_bits(nau8824->regmap, NAU8824_REG_ENA_CTRL,
1800 NAU8824_JD_SLEEP_MODE, NAU8824_JD_SLEEP_MODE);
1801 regmap_update_bits(nau8824->regmap,
1802 NAU8824_REG_INTERRUPT_SETTING, 0x3ff, 0x3ff);
1803 regmap_update_bits(nau8824->regmap, NAU8824_REG_INTERRUPT_SETTING_1,
1804 NAU8824_IRQ_EJECT_EN | NAU8824_IRQ_INSERT_EN, 0);
1805
1806 return 0;
1807 }
1808
nau8824_print_device_properties(struct nau8824 * nau8824)1809 static void nau8824_print_device_properties(struct nau8824 *nau8824)
1810 {
1811 struct device *dev = nau8824->dev;
1812 int i;
1813
1814 dev_dbg(dev, "jkdet-polarity: %d\n", nau8824->jkdet_polarity);
1815 dev_dbg(dev, "micbias-voltage: %d\n", nau8824->micbias_voltage);
1816 dev_dbg(dev, "vref-impedance: %d\n", nau8824->vref_impedance);
1817
1818 dev_dbg(dev, "sar-threshold-num: %d\n", nau8824->sar_threshold_num);
1819 for (i = 0; i < nau8824->sar_threshold_num; i++)
1820 dev_dbg(dev, "sar-threshold[%d]=%x\n", i,
1821 nau8824->sar_threshold[i]);
1822
1823 dev_dbg(dev, "sar-hysteresis: %d\n", nau8824->sar_hysteresis);
1824 dev_dbg(dev, "sar-voltage: %d\n", nau8824->sar_voltage);
1825 dev_dbg(dev, "sar-compare-time: %d\n", nau8824->sar_compare_time);
1826 dev_dbg(dev, "sar-sampling-time: %d\n", nau8824->sar_sampling_time);
1827 dev_dbg(dev, "short-key-debounce: %d\n", nau8824->key_debounce);
1828 dev_dbg(dev, "jack-eject-debounce: %d\n",
1829 nau8824->jack_eject_debounce);
1830 }
1831
nau8824_read_device_properties(struct device * dev,struct nau8824 * nau8824)1832 static int nau8824_read_device_properties(struct device *dev,
1833 struct nau8824 *nau8824) {
1834 int ret;
1835
1836 ret = device_property_read_u32(dev, "nuvoton,jkdet-polarity",
1837 &nau8824->jkdet_polarity);
1838 if (ret)
1839 nau8824->jkdet_polarity = 1;
1840 ret = device_property_read_u32(dev, "nuvoton,micbias-voltage",
1841 &nau8824->micbias_voltage);
1842 if (ret)
1843 nau8824->micbias_voltage = 6;
1844 ret = device_property_read_u32(dev, "nuvoton,vref-impedance",
1845 &nau8824->vref_impedance);
1846 if (ret)
1847 nau8824->vref_impedance = 2;
1848 ret = device_property_read_u32(dev, "nuvoton,sar-threshold-num",
1849 &nau8824->sar_threshold_num);
1850 if (ret)
1851 nau8824->sar_threshold_num = 4;
1852 ret = device_property_read_u32_array(dev, "nuvoton,sar-threshold",
1853 nau8824->sar_threshold, nau8824->sar_threshold_num);
1854 if (ret) {
1855 nau8824->sar_threshold[0] = 0x0a;
1856 nau8824->sar_threshold[1] = 0x14;
1857 nau8824->sar_threshold[2] = 0x26;
1858 nau8824->sar_threshold[3] = 0x73;
1859 }
1860 ret = device_property_read_u32(dev, "nuvoton,sar-hysteresis",
1861 &nau8824->sar_hysteresis);
1862 if (ret)
1863 nau8824->sar_hysteresis = 0;
1864 ret = device_property_read_u32(dev, "nuvoton,sar-voltage",
1865 &nau8824->sar_voltage);
1866 if (ret)
1867 nau8824->sar_voltage = 6;
1868 ret = device_property_read_u32(dev, "nuvoton,sar-compare-time",
1869 &nau8824->sar_compare_time);
1870 if (ret)
1871 nau8824->sar_compare_time = 1;
1872 ret = device_property_read_u32(dev, "nuvoton,sar-sampling-time",
1873 &nau8824->sar_sampling_time);
1874 if (ret)
1875 nau8824->sar_sampling_time = 1;
1876 ret = device_property_read_u32(dev, "nuvoton,short-key-debounce",
1877 &nau8824->key_debounce);
1878 if (ret)
1879 nau8824->key_debounce = 0;
1880 ret = device_property_read_u32(dev, "nuvoton,jack-eject-debounce",
1881 &nau8824->jack_eject_debounce);
1882 if (ret)
1883 nau8824->jack_eject_debounce = 1;
1884
1885 return 0;
1886 }
1887
1888 /* Please keep this list alphabetically sorted */
1889 static const struct dmi_system_id nau8824_quirk_table[] = {
1890 {
1891 /* Cyberbook T116 rugged tablet */
1892 .matches = {
1893 DMI_EXACT_MATCH(DMI_BOARD_VENDOR, "Default string"),
1894 DMI_EXACT_MATCH(DMI_BOARD_NAME, "Cherry Trail CR"),
1895 DMI_EXACT_MATCH(DMI_PRODUCT_SKU, "20170531"),
1896 },
1897 .driver_data = (void *)(NAU8824_JD_ACTIVE_HIGH),
1898 },
1899 {}
1900 };
1901
nau8824_check_quirks(void)1902 static void nau8824_check_quirks(void)
1903 {
1904 const struct dmi_system_id *dmi_id;
1905
1906 if (quirk_override != -1) {
1907 nau8824_quirk = quirk_override;
1908 return;
1909 }
1910
1911 dmi_id = dmi_first_match(nau8824_quirk_table);
1912 if (dmi_id)
1913 nau8824_quirk = (unsigned long)dmi_id->driver_data;
1914 }
1915
nau8824_i2c_probe(struct i2c_client * i2c,const struct i2c_device_id * id)1916 static int nau8824_i2c_probe(struct i2c_client *i2c,
1917 const struct i2c_device_id *id)
1918 {
1919 struct device *dev = &i2c->dev;
1920 struct nau8824 *nau8824 = dev_get_platdata(dev);
1921 int ret, value;
1922
1923 if (!nau8824) {
1924 nau8824 = devm_kzalloc(dev, sizeof(*nau8824), GFP_KERNEL);
1925 if (!nau8824)
1926 return -ENOMEM;
1927 ret = nau8824_read_device_properties(dev, nau8824);
1928 if (ret)
1929 return ret;
1930 }
1931 i2c_set_clientdata(i2c, nau8824);
1932
1933 nau8824->regmap = devm_regmap_init_i2c(i2c, &nau8824_regmap_config);
1934 if (IS_ERR(nau8824->regmap))
1935 return PTR_ERR(nau8824->regmap);
1936 nau8824->dev = dev;
1937 nau8824->irq = i2c->irq;
1938 sema_init(&nau8824->jd_sem, 1);
1939
1940 nau8824_check_quirks();
1941
1942 if (nau8824_quirk & NAU8824_JD_ACTIVE_HIGH)
1943 nau8824->jkdet_polarity = 0;
1944
1945 nau8824_print_device_properties(nau8824);
1946
1947 ret = regmap_read(nau8824->regmap, NAU8824_REG_I2C_DEVICE_ID, &value);
1948 if (ret < 0) {
1949 dev_err(dev, "Failed to read device id from the NAU8824: %d\n",
1950 ret);
1951 return ret;
1952 }
1953 nau8824_reset_chip(nau8824->regmap);
1954 nau8824_init_regs(nau8824);
1955
1956 if (i2c->irq)
1957 nau8824_setup_irq(nau8824);
1958
1959 return devm_snd_soc_register_component(dev,
1960 &nau8824_component_driver, &nau8824_dai, 1);
1961 }
1962
1963 static const struct i2c_device_id nau8824_i2c_ids[] = {
1964 { "nau8824", 0 },
1965 { }
1966 };
1967 MODULE_DEVICE_TABLE(i2c, nau8824_i2c_ids);
1968
1969 #ifdef CONFIG_OF
1970 static const struct of_device_id nau8824_of_ids[] = {
1971 { .compatible = "nuvoton,nau8824", },
1972 {}
1973 };
1974 MODULE_DEVICE_TABLE(of, nau8824_of_ids);
1975 #endif
1976
1977 #ifdef CONFIG_ACPI
1978 static const struct acpi_device_id nau8824_acpi_match[] = {
1979 { "10508824", 0 },
1980 {},
1981 };
1982 MODULE_DEVICE_TABLE(acpi, nau8824_acpi_match);
1983 #endif
1984
1985 static struct i2c_driver nau8824_i2c_driver = {
1986 .driver = {
1987 .name = "nau8824",
1988 .of_match_table = of_match_ptr(nau8824_of_ids),
1989 .acpi_match_table = ACPI_PTR(nau8824_acpi_match),
1990 },
1991 .probe = nau8824_i2c_probe,
1992 .id_table = nau8824_i2c_ids,
1993 };
1994 module_i2c_driver(nau8824_i2c_driver);
1995
1996
1997 MODULE_DESCRIPTION("ASoC NAU88L24 driver");
1998 MODULE_AUTHOR("John Hsu <KCHSU0@nuvoton.com>");
1999 MODULE_LICENSE("GPL v2");
2000