1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * skl-pcm.c -ASoC HDA Platform driver file implementing PCM functionality
4 *
5 * Copyright (C) 2014-2015 Intel Corp
6 * Author: Jeeja KP <jeeja.kp@intel.com>
7 *
8 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
9 *
10 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
11 */
12
13 #include <linux/pci.h>
14 #include <linux/pm_runtime.h>
15 #include <linux/delay.h>
16 #include <sound/pcm_params.h>
17 #include <sound/soc.h>
18 #include "skl.h"
19 #include "skl-topology.h"
20 #include "skl-sst-dsp.h"
21 #include "skl-sst-ipc.h"
22
23 #define HDA_MONO 1
24 #define HDA_STEREO 2
25 #define HDA_QUAD 4
26 #define HDA_MAX 8
27
28 static const struct snd_pcm_hardware azx_pcm_hw = {
29 .info = (SNDRV_PCM_INFO_MMAP |
30 SNDRV_PCM_INFO_INTERLEAVED |
31 SNDRV_PCM_INFO_BLOCK_TRANSFER |
32 SNDRV_PCM_INFO_MMAP_VALID |
33 SNDRV_PCM_INFO_PAUSE |
34 SNDRV_PCM_INFO_RESUME |
35 SNDRV_PCM_INFO_SYNC_START |
36 SNDRV_PCM_INFO_HAS_WALL_CLOCK | /* legacy */
37 SNDRV_PCM_INFO_HAS_LINK_ATIME |
38 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
39 .formats = SNDRV_PCM_FMTBIT_S16_LE |
40 SNDRV_PCM_FMTBIT_S32_LE |
41 SNDRV_PCM_FMTBIT_S24_LE,
42 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000 |
43 SNDRV_PCM_RATE_8000,
44 .rate_min = 8000,
45 .rate_max = 48000,
46 .channels_min = 1,
47 .channels_max = 8,
48 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
49 .period_bytes_min = 128,
50 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
51 .periods_min = 2,
52 .periods_max = AZX_MAX_FRAG,
53 .fifo_size = 0,
54 };
55
56 static inline
get_hdac_ext_stream(struct snd_pcm_substream * substream)57 struct hdac_ext_stream *get_hdac_ext_stream(struct snd_pcm_substream *substream)
58 {
59 return substream->runtime->private_data;
60 }
61
get_bus_ctx(struct snd_pcm_substream * substream)62 static struct hdac_bus *get_bus_ctx(struct snd_pcm_substream *substream)
63 {
64 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
65 struct hdac_stream *hstream = hdac_stream(stream);
66 struct hdac_bus *bus = hstream->bus;
67 return bus;
68 }
69
skl_substream_alloc_pages(struct hdac_bus * bus,struct snd_pcm_substream * substream,size_t size)70 static int skl_substream_alloc_pages(struct hdac_bus *bus,
71 struct snd_pcm_substream *substream,
72 size_t size)
73 {
74 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
75
76 hdac_stream(stream)->bufsize = 0;
77 hdac_stream(stream)->period_bytes = 0;
78 hdac_stream(stream)->format_val = 0;
79
80 return 0;
81 }
82
skl_set_pcm_constrains(struct hdac_bus * bus,struct snd_pcm_runtime * runtime)83 static void skl_set_pcm_constrains(struct hdac_bus *bus,
84 struct snd_pcm_runtime *runtime)
85 {
86 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
87
88 /* avoid wrap-around with wall-clock */
89 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_TIME,
90 20, 178000000);
91 }
92
skl_get_host_stream_type(struct hdac_bus * bus)93 static enum hdac_ext_stream_type skl_get_host_stream_type(struct hdac_bus *bus)
94 {
95 if (bus->ppcap)
96 return HDAC_EXT_STREAM_TYPE_HOST;
97 else
98 return HDAC_EXT_STREAM_TYPE_COUPLED;
99 }
100
101 /*
102 * check if the stream opened is marked as ignore_suspend by machine, if so
103 * then enable suspend_active refcount
104 *
105 * The count supend_active does not need lock as it is used in open/close
106 * and suspend context
107 */
skl_set_suspend_active(struct snd_pcm_substream * substream,struct snd_soc_dai * dai,bool enable)108 static void skl_set_suspend_active(struct snd_pcm_substream *substream,
109 struct snd_soc_dai *dai, bool enable)
110 {
111 struct hdac_bus *bus = dev_get_drvdata(dai->dev);
112 struct snd_soc_dapm_widget *w;
113 struct skl_dev *skl = bus_to_skl(bus);
114
115 w = snd_soc_dai_get_widget(dai, substream->stream);
116
117 if (w->ignore_suspend && enable)
118 skl->supend_active++;
119 else if (w->ignore_suspend && !enable)
120 skl->supend_active--;
121 }
122
skl_pcm_host_dma_prepare(struct device * dev,struct skl_pipe_params * params)123 int skl_pcm_host_dma_prepare(struct device *dev, struct skl_pipe_params *params)
124 {
125 struct hdac_bus *bus = dev_get_drvdata(dev);
126 struct skl_dev *skl = bus_to_skl(bus);
127 unsigned int format_val;
128 struct hdac_stream *hstream;
129 struct hdac_ext_stream *stream;
130 int err;
131
132 hstream = snd_hdac_get_stream(bus, params->stream,
133 params->host_dma_id + 1);
134 if (!hstream)
135 return -EINVAL;
136
137 stream = stream_to_hdac_ext_stream(hstream);
138 snd_hdac_ext_stream_decouple(bus, stream, true);
139
140 format_val = snd_hdac_calc_stream_format(params->s_freq,
141 params->ch, params->format, params->host_bps, 0);
142
143 dev_dbg(dev, "format_val=%d, rate=%d, ch=%d, format=%d\n",
144 format_val, params->s_freq, params->ch, params->format);
145
146 snd_hdac_stream_reset(hdac_stream(stream));
147 err = snd_hdac_stream_set_params(hdac_stream(stream), format_val);
148 if (err < 0)
149 return err;
150
151 /*
152 * The recommended SDxFMT programming sequence for BXT
153 * platforms is to couple the stream before writing the format
154 */
155 if (IS_BXT(skl->pci)) {
156 snd_hdac_ext_stream_decouple(bus, stream, false);
157 err = snd_hdac_stream_setup(hdac_stream(stream));
158 snd_hdac_ext_stream_decouple(bus, stream, true);
159 } else {
160 err = snd_hdac_stream_setup(hdac_stream(stream));
161 }
162
163 if (err < 0)
164 return err;
165
166 hdac_stream(stream)->prepared = 1;
167
168 return 0;
169 }
170
skl_pcm_link_dma_prepare(struct device * dev,struct skl_pipe_params * params)171 int skl_pcm_link_dma_prepare(struct device *dev, struct skl_pipe_params *params)
172 {
173 struct hdac_bus *bus = dev_get_drvdata(dev);
174 unsigned int format_val;
175 struct hdac_stream *hstream;
176 struct hdac_ext_stream *stream;
177 struct hdac_ext_link *link;
178 unsigned char stream_tag;
179
180 hstream = snd_hdac_get_stream(bus, params->stream,
181 params->link_dma_id + 1);
182 if (!hstream)
183 return -EINVAL;
184
185 stream = stream_to_hdac_ext_stream(hstream);
186 snd_hdac_ext_stream_decouple(bus, stream, true);
187 format_val = snd_hdac_calc_stream_format(params->s_freq, params->ch,
188 params->format, params->link_bps, 0);
189
190 dev_dbg(dev, "format_val=%d, rate=%d, ch=%d, format=%d\n",
191 format_val, params->s_freq, params->ch, params->format);
192
193 snd_hdac_ext_link_stream_reset(stream);
194
195 snd_hdac_ext_link_stream_setup(stream, format_val);
196
197 stream_tag = hstream->stream_tag;
198 if (stream->hstream.direction == SNDRV_PCM_STREAM_PLAYBACK) {
199 list_for_each_entry(link, &bus->hlink_list, list) {
200 if (link->index == params->link_index)
201 snd_hdac_ext_link_set_stream_id(link,
202 stream_tag);
203 }
204 }
205
206 stream->link_prepared = 1;
207
208 return 0;
209 }
210
skl_pcm_open(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)211 static int skl_pcm_open(struct snd_pcm_substream *substream,
212 struct snd_soc_dai *dai)
213 {
214 struct hdac_bus *bus = dev_get_drvdata(dai->dev);
215 struct hdac_ext_stream *stream;
216 struct snd_pcm_runtime *runtime = substream->runtime;
217 struct skl_dma_params *dma_params;
218 struct skl_dev *skl = get_skl_ctx(dai->dev);
219 struct skl_module_cfg *mconfig;
220
221 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
222
223 stream = snd_hdac_ext_stream_assign(bus, substream,
224 skl_get_host_stream_type(bus));
225 if (stream == NULL)
226 return -EBUSY;
227
228 skl_set_pcm_constrains(bus, runtime);
229
230 /*
231 * disable WALLCLOCK timestamps for capture streams
232 * until we figure out how to handle digital inputs
233 */
234 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
235 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_WALL_CLOCK; /* legacy */
236 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_LINK_ATIME;
237 }
238
239 runtime->private_data = stream;
240
241 dma_params = kzalloc(sizeof(*dma_params), GFP_KERNEL);
242 if (!dma_params)
243 return -ENOMEM;
244
245 dma_params->stream_tag = hdac_stream(stream)->stream_tag;
246 snd_soc_dai_set_dma_data(dai, substream, dma_params);
247
248 dev_dbg(dai->dev, "stream tag set in dma params=%d\n",
249 dma_params->stream_tag);
250 skl_set_suspend_active(substream, dai, true);
251 snd_pcm_set_sync(substream);
252
253 mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream);
254 if (!mconfig)
255 return -EINVAL;
256
257 skl_tplg_d0i3_get(skl, mconfig->d0i3_caps);
258
259 return 0;
260 }
261
skl_pcm_prepare(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)262 static int skl_pcm_prepare(struct snd_pcm_substream *substream,
263 struct snd_soc_dai *dai)
264 {
265 struct skl_dev *skl = get_skl_ctx(dai->dev);
266 struct skl_module_cfg *mconfig;
267 int ret;
268
269 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
270
271 mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream);
272
273 /*
274 * In case of XRUN recovery or in the case when the application
275 * calls prepare another time, reset the FW pipe to clean state
276 */
277 if (mconfig &&
278 (substream->runtime->status->state == SNDRV_PCM_STATE_XRUN ||
279 mconfig->pipe->state == SKL_PIPE_CREATED ||
280 mconfig->pipe->state == SKL_PIPE_PAUSED)) {
281
282 ret = skl_reset_pipe(skl, mconfig->pipe);
283
284 if (ret < 0)
285 return ret;
286
287 ret = skl_pcm_host_dma_prepare(dai->dev,
288 mconfig->pipe->p_params);
289 if (ret < 0)
290 return ret;
291 }
292
293 return 0;
294 }
295
skl_pcm_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)296 static int skl_pcm_hw_params(struct snd_pcm_substream *substream,
297 struct snd_pcm_hw_params *params,
298 struct snd_soc_dai *dai)
299 {
300 struct hdac_bus *bus = dev_get_drvdata(dai->dev);
301 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
302 struct snd_pcm_runtime *runtime = substream->runtime;
303 struct skl_pipe_params p_params = {0};
304 struct skl_module_cfg *m_cfg;
305 int ret, dma_id;
306
307 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
308 ret = skl_substream_alloc_pages(bus, substream,
309 params_buffer_bytes(params));
310 if (ret < 0)
311 return ret;
312
313 dev_dbg(dai->dev, "format_val, rate=%d, ch=%d, format=%d\n",
314 runtime->rate, runtime->channels, runtime->format);
315
316 dma_id = hdac_stream(stream)->stream_tag - 1;
317 dev_dbg(dai->dev, "dma_id=%d\n", dma_id);
318
319 p_params.s_fmt = snd_pcm_format_width(params_format(params));
320 p_params.ch = params_channels(params);
321 p_params.s_freq = params_rate(params);
322 p_params.host_dma_id = dma_id;
323 p_params.stream = substream->stream;
324 p_params.format = params_format(params);
325 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
326 p_params.host_bps = dai->driver->playback.sig_bits;
327 else
328 p_params.host_bps = dai->driver->capture.sig_bits;
329
330
331 m_cfg = skl_tplg_fe_get_cpr_module(dai, p_params.stream);
332 if (m_cfg)
333 skl_tplg_update_pipe_params(dai->dev, m_cfg, &p_params);
334
335 return 0;
336 }
337
skl_pcm_close(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)338 static void skl_pcm_close(struct snd_pcm_substream *substream,
339 struct snd_soc_dai *dai)
340 {
341 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
342 struct hdac_bus *bus = dev_get_drvdata(dai->dev);
343 struct skl_dma_params *dma_params = NULL;
344 struct skl_dev *skl = bus_to_skl(bus);
345 struct skl_module_cfg *mconfig;
346
347 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
348
349 snd_hdac_ext_stream_release(stream, skl_get_host_stream_type(bus));
350
351 dma_params = snd_soc_dai_get_dma_data(dai, substream);
352 /*
353 * now we should set this to NULL as we are freeing by the
354 * dma_params
355 */
356 snd_soc_dai_set_dma_data(dai, substream, NULL);
357 skl_set_suspend_active(substream, dai, false);
358
359 /*
360 * check if close is for "Reference Pin" and set back the
361 * CGCTL.MISCBDCGE if disabled by driver
362 */
363 if (!strncmp(dai->name, "Reference Pin", 13) &&
364 skl->miscbdcg_disabled) {
365 skl->enable_miscbdcge(dai->dev, true);
366 skl->miscbdcg_disabled = false;
367 }
368
369 mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream);
370 if (mconfig)
371 skl_tplg_d0i3_put(skl, mconfig->d0i3_caps);
372
373 kfree(dma_params);
374 }
375
skl_pcm_hw_free(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)376 static int skl_pcm_hw_free(struct snd_pcm_substream *substream,
377 struct snd_soc_dai *dai)
378 {
379 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
380 struct skl_dev *skl = get_skl_ctx(dai->dev);
381 struct skl_module_cfg *mconfig;
382 int ret;
383
384 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
385
386 mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream);
387
388 if (mconfig) {
389 ret = skl_reset_pipe(skl, mconfig->pipe);
390 if (ret < 0)
391 dev_err(dai->dev, "%s:Reset failed ret =%d",
392 __func__, ret);
393 }
394
395 snd_hdac_stream_cleanup(hdac_stream(stream));
396 hdac_stream(stream)->prepared = 0;
397
398 return 0;
399 }
400
skl_be_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)401 static int skl_be_hw_params(struct snd_pcm_substream *substream,
402 struct snd_pcm_hw_params *params,
403 struct snd_soc_dai *dai)
404 {
405 struct skl_pipe_params p_params = {0};
406
407 p_params.s_fmt = snd_pcm_format_width(params_format(params));
408 p_params.ch = params_channels(params);
409 p_params.s_freq = params_rate(params);
410 p_params.stream = substream->stream;
411
412 return skl_tplg_be_update_params(dai, &p_params);
413 }
414
skl_decoupled_trigger(struct snd_pcm_substream * substream,int cmd)415 static int skl_decoupled_trigger(struct snd_pcm_substream *substream,
416 int cmd)
417 {
418 struct hdac_bus *bus = get_bus_ctx(substream);
419 struct hdac_ext_stream *stream;
420 int start;
421 unsigned long cookie;
422 struct hdac_stream *hstr;
423
424 stream = get_hdac_ext_stream(substream);
425 hstr = hdac_stream(stream);
426
427 if (!hstr->prepared)
428 return -EPIPE;
429
430 switch (cmd) {
431 case SNDRV_PCM_TRIGGER_START:
432 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
433 case SNDRV_PCM_TRIGGER_RESUME:
434 start = 1;
435 break;
436
437 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
438 case SNDRV_PCM_TRIGGER_SUSPEND:
439 case SNDRV_PCM_TRIGGER_STOP:
440 start = 0;
441 break;
442
443 default:
444 return -EINVAL;
445 }
446
447 spin_lock_irqsave(&bus->reg_lock, cookie);
448
449 if (start) {
450 snd_hdac_stream_start(hdac_stream(stream), true);
451 snd_hdac_stream_timecounter_init(hstr, 0);
452 } else {
453 snd_hdac_stream_stop(hdac_stream(stream));
454 }
455
456 spin_unlock_irqrestore(&bus->reg_lock, cookie);
457
458 return 0;
459 }
460
skl_pcm_trigger(struct snd_pcm_substream * substream,int cmd,struct snd_soc_dai * dai)461 static int skl_pcm_trigger(struct snd_pcm_substream *substream, int cmd,
462 struct snd_soc_dai *dai)
463 {
464 struct skl_dev *skl = get_skl_ctx(dai->dev);
465 struct skl_module_cfg *mconfig;
466 struct hdac_bus *bus = get_bus_ctx(substream);
467 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
468 struct snd_soc_dapm_widget *w;
469 int ret;
470
471 mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream);
472 if (!mconfig)
473 return -EIO;
474
475 w = snd_soc_dai_get_widget(dai, substream->stream);
476
477 switch (cmd) {
478 case SNDRV_PCM_TRIGGER_RESUME:
479 if (!w->ignore_suspend) {
480 /*
481 * enable DMA Resume enable bit for the stream, set the
482 * dpib & lpib position to resume before starting the
483 * DMA
484 */
485 snd_hdac_ext_stream_drsm_enable(bus, true,
486 hdac_stream(stream)->index);
487 snd_hdac_ext_stream_set_dpibr(bus, stream,
488 stream->lpib);
489 snd_hdac_ext_stream_set_lpib(stream, stream->lpib);
490 }
491 fallthrough;
492
493 case SNDRV_PCM_TRIGGER_START:
494 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
495 /*
496 * Start HOST DMA and Start FE Pipe.This is to make sure that
497 * there are no underrun/overrun in the case when the FE
498 * pipeline is started but there is a delay in starting the
499 * DMA channel on the host.
500 */
501 ret = skl_decoupled_trigger(substream, cmd);
502 if (ret < 0)
503 return ret;
504 return skl_run_pipe(skl, mconfig->pipe);
505 break;
506
507 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
508 case SNDRV_PCM_TRIGGER_SUSPEND:
509 case SNDRV_PCM_TRIGGER_STOP:
510 /*
511 * Stop FE Pipe first and stop DMA. This is to make sure that
512 * there are no underrun/overrun in the case if there is a delay
513 * between the two operations.
514 */
515 ret = skl_stop_pipe(skl, mconfig->pipe);
516 if (ret < 0)
517 return ret;
518
519 ret = skl_decoupled_trigger(substream, cmd);
520 if ((cmd == SNDRV_PCM_TRIGGER_SUSPEND) && !w->ignore_suspend) {
521 /* save the dpib and lpib positions */
522 stream->dpib = readl(bus->remap_addr +
523 AZX_REG_VS_SDXDPIB_XBASE +
524 (AZX_REG_VS_SDXDPIB_XINTERVAL *
525 hdac_stream(stream)->index));
526
527 stream->lpib = snd_hdac_stream_get_pos_lpib(
528 hdac_stream(stream));
529 snd_hdac_ext_stream_decouple(bus, stream, false);
530 }
531 break;
532
533 default:
534 return -EINVAL;
535 }
536
537 return 0;
538 }
539
540
skl_link_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)541 static int skl_link_hw_params(struct snd_pcm_substream *substream,
542 struct snd_pcm_hw_params *params,
543 struct snd_soc_dai *dai)
544 {
545 struct hdac_bus *bus = dev_get_drvdata(dai->dev);
546 struct hdac_ext_stream *link_dev;
547 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
548 struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
549 struct skl_pipe_params p_params = {0};
550 struct hdac_ext_link *link;
551 int stream_tag;
552
553 link_dev = snd_hdac_ext_stream_assign(bus, substream,
554 HDAC_EXT_STREAM_TYPE_LINK);
555 if (!link_dev)
556 return -EBUSY;
557
558 snd_soc_dai_set_dma_data(dai, substream, (void *)link_dev);
559
560 link = snd_hdac_ext_bus_get_link(bus, codec_dai->component->name);
561 if (!link)
562 return -EINVAL;
563
564 stream_tag = hdac_stream(link_dev)->stream_tag;
565
566 /* set the hdac_stream in the codec dai */
567 snd_soc_dai_set_stream(codec_dai, hdac_stream(link_dev), substream->stream);
568
569 p_params.s_fmt = snd_pcm_format_width(params_format(params));
570 p_params.ch = params_channels(params);
571 p_params.s_freq = params_rate(params);
572 p_params.stream = substream->stream;
573 p_params.link_dma_id = stream_tag - 1;
574 p_params.link_index = link->index;
575 p_params.format = params_format(params);
576
577 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
578 p_params.link_bps = codec_dai->driver->playback.sig_bits;
579 else
580 p_params.link_bps = codec_dai->driver->capture.sig_bits;
581
582 return skl_tplg_be_update_params(dai, &p_params);
583 }
584
skl_link_pcm_prepare(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)585 static int skl_link_pcm_prepare(struct snd_pcm_substream *substream,
586 struct snd_soc_dai *dai)
587 {
588 struct skl_dev *skl = get_skl_ctx(dai->dev);
589 struct skl_module_cfg *mconfig = NULL;
590
591 /* In case of XRUN recovery, reset the FW pipe to clean state */
592 mconfig = skl_tplg_be_get_cpr_module(dai, substream->stream);
593 if (mconfig && !mconfig->pipe->passthru &&
594 (substream->runtime->status->state == SNDRV_PCM_STATE_XRUN))
595 skl_reset_pipe(skl, mconfig->pipe);
596
597 return 0;
598 }
599
skl_link_pcm_trigger(struct snd_pcm_substream * substream,int cmd,struct snd_soc_dai * dai)600 static int skl_link_pcm_trigger(struct snd_pcm_substream *substream,
601 int cmd, struct snd_soc_dai *dai)
602 {
603 struct hdac_ext_stream *link_dev =
604 snd_soc_dai_get_dma_data(dai, substream);
605 struct hdac_bus *bus = get_bus_ctx(substream);
606 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
607
608 dev_dbg(dai->dev, "In %s cmd=%d\n", __func__, cmd);
609 switch (cmd) {
610 case SNDRV_PCM_TRIGGER_RESUME:
611 case SNDRV_PCM_TRIGGER_START:
612 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
613 snd_hdac_ext_link_stream_start(link_dev);
614 break;
615
616 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
617 case SNDRV_PCM_TRIGGER_SUSPEND:
618 case SNDRV_PCM_TRIGGER_STOP:
619 snd_hdac_ext_link_stream_clear(link_dev);
620 if (cmd == SNDRV_PCM_TRIGGER_SUSPEND)
621 snd_hdac_ext_stream_decouple(bus, stream, false);
622 break;
623
624 default:
625 return -EINVAL;
626 }
627 return 0;
628 }
629
skl_link_hw_free(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)630 static int skl_link_hw_free(struct snd_pcm_substream *substream,
631 struct snd_soc_dai *dai)
632 {
633 struct hdac_bus *bus = dev_get_drvdata(dai->dev);
634 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
635 struct hdac_ext_stream *link_dev =
636 snd_soc_dai_get_dma_data(dai, substream);
637 struct hdac_ext_link *link;
638 unsigned char stream_tag;
639
640 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
641
642 link_dev->link_prepared = 0;
643
644 link = snd_hdac_ext_bus_get_link(bus, asoc_rtd_to_codec(rtd, 0)->component->name);
645 if (!link)
646 return -EINVAL;
647
648 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
649 stream_tag = hdac_stream(link_dev)->stream_tag;
650 snd_hdac_ext_link_clear_stream_id(link, stream_tag);
651 }
652
653 snd_hdac_ext_stream_release(link_dev, HDAC_EXT_STREAM_TYPE_LINK);
654 return 0;
655 }
656
657 static const struct snd_soc_dai_ops skl_pcm_dai_ops = {
658 .startup = skl_pcm_open,
659 .shutdown = skl_pcm_close,
660 .prepare = skl_pcm_prepare,
661 .hw_params = skl_pcm_hw_params,
662 .hw_free = skl_pcm_hw_free,
663 .trigger = skl_pcm_trigger,
664 };
665
666 static const struct snd_soc_dai_ops skl_dmic_dai_ops = {
667 .hw_params = skl_be_hw_params,
668 };
669
670 static const struct snd_soc_dai_ops skl_be_ssp_dai_ops = {
671 .hw_params = skl_be_hw_params,
672 };
673
674 static const struct snd_soc_dai_ops skl_link_dai_ops = {
675 .prepare = skl_link_pcm_prepare,
676 .hw_params = skl_link_hw_params,
677 .hw_free = skl_link_hw_free,
678 .trigger = skl_link_pcm_trigger,
679 };
680
681 static struct snd_soc_dai_driver skl_fe_dai[] = {
682 {
683 .name = "System Pin",
684 .ops = &skl_pcm_dai_ops,
685 .playback = {
686 .stream_name = "System Playback",
687 .channels_min = HDA_MONO,
688 .channels_max = HDA_STEREO,
689 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_8000,
690 .formats = SNDRV_PCM_FMTBIT_S16_LE |
691 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,
692 .sig_bits = 32,
693 },
694 .capture = {
695 .stream_name = "System Capture",
696 .channels_min = HDA_MONO,
697 .channels_max = HDA_STEREO,
698 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000,
699 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
700 .sig_bits = 32,
701 },
702 },
703 {
704 .name = "System Pin2",
705 .ops = &skl_pcm_dai_ops,
706 .playback = {
707 .stream_name = "Headset Playback",
708 .channels_min = HDA_MONO,
709 .channels_max = HDA_STEREO,
710 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000 |
711 SNDRV_PCM_RATE_8000,
712 .formats = SNDRV_PCM_FMTBIT_S16_LE |
713 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,
714 },
715 },
716 {
717 .name = "Echoref Pin",
718 .ops = &skl_pcm_dai_ops,
719 .capture = {
720 .stream_name = "Echoreference Capture",
721 .channels_min = HDA_STEREO,
722 .channels_max = HDA_STEREO,
723 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000 |
724 SNDRV_PCM_RATE_8000,
725 .formats = SNDRV_PCM_FMTBIT_S16_LE |
726 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,
727 },
728 },
729 {
730 .name = "Reference Pin",
731 .ops = &skl_pcm_dai_ops,
732 .capture = {
733 .stream_name = "Reference Capture",
734 .channels_min = HDA_MONO,
735 .channels_max = HDA_QUAD,
736 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000,
737 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
738 .sig_bits = 32,
739 },
740 },
741 {
742 .name = "Deepbuffer Pin",
743 .ops = &skl_pcm_dai_ops,
744 .playback = {
745 .stream_name = "Deepbuffer Playback",
746 .channels_min = HDA_STEREO,
747 .channels_max = HDA_STEREO,
748 .rates = SNDRV_PCM_RATE_48000,
749 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
750 .sig_bits = 32,
751 },
752 },
753 {
754 .name = "LowLatency Pin",
755 .ops = &skl_pcm_dai_ops,
756 .playback = {
757 .stream_name = "Low Latency Playback",
758 .channels_min = HDA_STEREO,
759 .channels_max = HDA_STEREO,
760 .rates = SNDRV_PCM_RATE_48000,
761 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
762 .sig_bits = 32,
763 },
764 },
765 {
766 .name = "DMIC Pin",
767 .ops = &skl_pcm_dai_ops,
768 .capture = {
769 .stream_name = "DMIC Capture",
770 .channels_min = HDA_MONO,
771 .channels_max = HDA_QUAD,
772 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000,
773 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
774 .sig_bits = 32,
775 },
776 },
777 {
778 .name = "HDMI1 Pin",
779 .ops = &skl_pcm_dai_ops,
780 .playback = {
781 .stream_name = "HDMI1 Playback",
782 .channels_min = HDA_STEREO,
783 .channels_max = 8,
784 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
785 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
786 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
787 SNDRV_PCM_RATE_192000,
788 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
789 SNDRV_PCM_FMTBIT_S32_LE,
790 .sig_bits = 32,
791 },
792 },
793 {
794 .name = "HDMI2 Pin",
795 .ops = &skl_pcm_dai_ops,
796 .playback = {
797 .stream_name = "HDMI2 Playback",
798 .channels_min = HDA_STEREO,
799 .channels_max = 8,
800 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
801 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
802 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
803 SNDRV_PCM_RATE_192000,
804 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
805 SNDRV_PCM_FMTBIT_S32_LE,
806 .sig_bits = 32,
807 },
808 },
809 {
810 .name = "HDMI3 Pin",
811 .ops = &skl_pcm_dai_ops,
812 .playback = {
813 .stream_name = "HDMI3 Playback",
814 .channels_min = HDA_STEREO,
815 .channels_max = 8,
816 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
817 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
818 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
819 SNDRV_PCM_RATE_192000,
820 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
821 SNDRV_PCM_FMTBIT_S32_LE,
822 .sig_bits = 32,
823 },
824 },
825 };
826
827 /* BE CPU Dais */
828 static struct snd_soc_dai_driver skl_platform_dai[] = {
829 {
830 .name = "SSP0 Pin",
831 .ops = &skl_be_ssp_dai_ops,
832 .playback = {
833 .stream_name = "ssp0 Tx",
834 .channels_min = HDA_STEREO,
835 .channels_max = HDA_STEREO,
836 .rates = SNDRV_PCM_RATE_48000,
837 .formats = SNDRV_PCM_FMTBIT_S16_LE,
838 },
839 .capture = {
840 .stream_name = "ssp0 Rx",
841 .channels_min = HDA_STEREO,
842 .channels_max = HDA_STEREO,
843 .rates = SNDRV_PCM_RATE_48000,
844 .formats = SNDRV_PCM_FMTBIT_S16_LE,
845 },
846 },
847 {
848 .name = "SSP1 Pin",
849 .ops = &skl_be_ssp_dai_ops,
850 .playback = {
851 .stream_name = "ssp1 Tx",
852 .channels_min = HDA_STEREO,
853 .channels_max = HDA_STEREO,
854 .rates = SNDRV_PCM_RATE_48000,
855 .formats = SNDRV_PCM_FMTBIT_S16_LE,
856 },
857 .capture = {
858 .stream_name = "ssp1 Rx",
859 .channels_min = HDA_STEREO,
860 .channels_max = HDA_STEREO,
861 .rates = SNDRV_PCM_RATE_48000,
862 .formats = SNDRV_PCM_FMTBIT_S16_LE,
863 },
864 },
865 {
866 .name = "SSP2 Pin",
867 .ops = &skl_be_ssp_dai_ops,
868 .playback = {
869 .stream_name = "ssp2 Tx",
870 .channels_min = HDA_STEREO,
871 .channels_max = HDA_STEREO,
872 .rates = SNDRV_PCM_RATE_48000,
873 .formats = SNDRV_PCM_FMTBIT_S16_LE,
874 },
875 .capture = {
876 .stream_name = "ssp2 Rx",
877 .channels_min = HDA_STEREO,
878 .channels_max = HDA_STEREO,
879 .rates = SNDRV_PCM_RATE_48000,
880 .formats = SNDRV_PCM_FMTBIT_S16_LE,
881 },
882 },
883 {
884 .name = "SSP3 Pin",
885 .ops = &skl_be_ssp_dai_ops,
886 .playback = {
887 .stream_name = "ssp3 Tx",
888 .channels_min = HDA_STEREO,
889 .channels_max = HDA_STEREO,
890 .rates = SNDRV_PCM_RATE_48000,
891 .formats = SNDRV_PCM_FMTBIT_S16_LE,
892 },
893 .capture = {
894 .stream_name = "ssp3 Rx",
895 .channels_min = HDA_STEREO,
896 .channels_max = HDA_STEREO,
897 .rates = SNDRV_PCM_RATE_48000,
898 .formats = SNDRV_PCM_FMTBIT_S16_LE,
899 },
900 },
901 {
902 .name = "SSP4 Pin",
903 .ops = &skl_be_ssp_dai_ops,
904 .playback = {
905 .stream_name = "ssp4 Tx",
906 .channels_min = HDA_STEREO,
907 .channels_max = HDA_STEREO,
908 .rates = SNDRV_PCM_RATE_48000,
909 .formats = SNDRV_PCM_FMTBIT_S16_LE,
910 },
911 .capture = {
912 .stream_name = "ssp4 Rx",
913 .channels_min = HDA_STEREO,
914 .channels_max = HDA_STEREO,
915 .rates = SNDRV_PCM_RATE_48000,
916 .formats = SNDRV_PCM_FMTBIT_S16_LE,
917 },
918 },
919 {
920 .name = "SSP5 Pin",
921 .ops = &skl_be_ssp_dai_ops,
922 .playback = {
923 .stream_name = "ssp5 Tx",
924 .channels_min = HDA_STEREO,
925 .channels_max = HDA_STEREO,
926 .rates = SNDRV_PCM_RATE_48000,
927 .formats = SNDRV_PCM_FMTBIT_S16_LE,
928 },
929 .capture = {
930 .stream_name = "ssp5 Rx",
931 .channels_min = HDA_STEREO,
932 .channels_max = HDA_STEREO,
933 .rates = SNDRV_PCM_RATE_48000,
934 .formats = SNDRV_PCM_FMTBIT_S16_LE,
935 },
936 },
937 {
938 .name = "iDisp1 Pin",
939 .ops = &skl_link_dai_ops,
940 .playback = {
941 .stream_name = "iDisp1 Tx",
942 .channels_min = HDA_STEREO,
943 .channels_max = 8,
944 .rates = SNDRV_PCM_RATE_8000|SNDRV_PCM_RATE_16000|SNDRV_PCM_RATE_48000,
945 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE |
946 SNDRV_PCM_FMTBIT_S24_LE,
947 },
948 },
949 {
950 .name = "iDisp2 Pin",
951 .ops = &skl_link_dai_ops,
952 .playback = {
953 .stream_name = "iDisp2 Tx",
954 .channels_min = HDA_STEREO,
955 .channels_max = 8,
956 .rates = SNDRV_PCM_RATE_8000|SNDRV_PCM_RATE_16000|
957 SNDRV_PCM_RATE_48000,
958 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE |
959 SNDRV_PCM_FMTBIT_S24_LE,
960 },
961 },
962 {
963 .name = "iDisp3 Pin",
964 .ops = &skl_link_dai_ops,
965 .playback = {
966 .stream_name = "iDisp3 Tx",
967 .channels_min = HDA_STEREO,
968 .channels_max = 8,
969 .rates = SNDRV_PCM_RATE_8000|SNDRV_PCM_RATE_16000|
970 SNDRV_PCM_RATE_48000,
971 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE |
972 SNDRV_PCM_FMTBIT_S24_LE,
973 },
974 },
975 {
976 .name = "DMIC01 Pin",
977 .ops = &skl_dmic_dai_ops,
978 .capture = {
979 .stream_name = "DMIC01 Rx",
980 .channels_min = HDA_MONO,
981 .channels_max = HDA_QUAD,
982 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000,
983 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
984 },
985 },
986 {
987 .name = "DMIC16k Pin",
988 .ops = &skl_dmic_dai_ops,
989 .capture = {
990 .stream_name = "DMIC16k Rx",
991 .channels_min = HDA_MONO,
992 .channels_max = HDA_QUAD,
993 .rates = SNDRV_PCM_RATE_16000,
994 .formats = SNDRV_PCM_FMTBIT_S16_LE,
995 },
996 },
997 {
998 .name = "Analog CPU DAI",
999 .ops = &skl_link_dai_ops,
1000 .playback = {
1001 .stream_name = "Analog CPU Playback",
1002 .channels_min = HDA_MONO,
1003 .channels_max = HDA_MAX,
1004 .rates = SNDRV_PCM_RATE_8000_192000,
1005 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
1006 SNDRV_PCM_FMTBIT_S32_LE,
1007 },
1008 .capture = {
1009 .stream_name = "Analog CPU Capture",
1010 .channels_min = HDA_MONO,
1011 .channels_max = HDA_MAX,
1012 .rates = SNDRV_PCM_RATE_8000_192000,
1013 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
1014 SNDRV_PCM_FMTBIT_S32_LE,
1015 },
1016 },
1017 {
1018 .name = "Alt Analog CPU DAI",
1019 .ops = &skl_link_dai_ops,
1020 .playback = {
1021 .stream_name = "Alt Analog CPU Playback",
1022 .channels_min = HDA_MONO,
1023 .channels_max = HDA_MAX,
1024 .rates = SNDRV_PCM_RATE_8000_192000,
1025 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
1026 SNDRV_PCM_FMTBIT_S32_LE,
1027 },
1028 .capture = {
1029 .stream_name = "Alt Analog CPU Capture",
1030 .channels_min = HDA_MONO,
1031 .channels_max = HDA_MAX,
1032 .rates = SNDRV_PCM_RATE_8000_192000,
1033 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
1034 SNDRV_PCM_FMTBIT_S32_LE,
1035 },
1036 },
1037 {
1038 .name = "Digital CPU DAI",
1039 .ops = &skl_link_dai_ops,
1040 .playback = {
1041 .stream_name = "Digital CPU Playback",
1042 .channels_min = HDA_MONO,
1043 .channels_max = HDA_MAX,
1044 .rates = SNDRV_PCM_RATE_8000_192000,
1045 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
1046 SNDRV_PCM_FMTBIT_S32_LE,
1047 },
1048 .capture = {
1049 .stream_name = "Digital CPU Capture",
1050 .channels_min = HDA_MONO,
1051 .channels_max = HDA_MAX,
1052 .rates = SNDRV_PCM_RATE_8000_192000,
1053 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
1054 SNDRV_PCM_FMTBIT_S32_LE,
1055 },
1056 },
1057 };
1058
skl_dai_load(struct snd_soc_component * cmp,int index,struct snd_soc_dai_driver * dai_drv,struct snd_soc_tplg_pcm * pcm,struct snd_soc_dai * dai)1059 int skl_dai_load(struct snd_soc_component *cmp, int index,
1060 struct snd_soc_dai_driver *dai_drv,
1061 struct snd_soc_tplg_pcm *pcm, struct snd_soc_dai *dai)
1062 {
1063 dai_drv->ops = &skl_pcm_dai_ops;
1064
1065 return 0;
1066 }
1067
skl_platform_soc_open(struct snd_soc_component * component,struct snd_pcm_substream * substream)1068 static int skl_platform_soc_open(struct snd_soc_component *component,
1069 struct snd_pcm_substream *substream)
1070 {
1071 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
1072 struct snd_soc_dai_link *dai_link = rtd->dai_link;
1073
1074 dev_dbg(asoc_rtd_to_cpu(rtd, 0)->dev, "In %s:%s\n", __func__,
1075 dai_link->cpus->dai_name);
1076
1077 snd_soc_set_runtime_hwparams(substream, &azx_pcm_hw);
1078
1079 return 0;
1080 }
1081
skl_coupled_trigger(struct snd_pcm_substream * substream,int cmd)1082 static int skl_coupled_trigger(struct snd_pcm_substream *substream,
1083 int cmd)
1084 {
1085 struct hdac_bus *bus = get_bus_ctx(substream);
1086 struct hdac_ext_stream *stream;
1087 struct snd_pcm_substream *s;
1088 bool start;
1089 int sbits = 0;
1090 unsigned long cookie;
1091 struct hdac_stream *hstr;
1092
1093 stream = get_hdac_ext_stream(substream);
1094 hstr = hdac_stream(stream);
1095
1096 dev_dbg(bus->dev, "In %s cmd=%d\n", __func__, cmd);
1097
1098 if (!hstr->prepared)
1099 return -EPIPE;
1100
1101 switch (cmd) {
1102 case SNDRV_PCM_TRIGGER_START:
1103 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1104 case SNDRV_PCM_TRIGGER_RESUME:
1105 start = true;
1106 break;
1107
1108 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1109 case SNDRV_PCM_TRIGGER_SUSPEND:
1110 case SNDRV_PCM_TRIGGER_STOP:
1111 start = false;
1112 break;
1113
1114 default:
1115 return -EINVAL;
1116 }
1117
1118 snd_pcm_group_for_each_entry(s, substream) {
1119 if (s->pcm->card != substream->pcm->card)
1120 continue;
1121 stream = get_hdac_ext_stream(s);
1122 sbits |= 1 << hdac_stream(stream)->index;
1123 snd_pcm_trigger_done(s, substream);
1124 }
1125
1126 spin_lock_irqsave(&bus->reg_lock, cookie);
1127
1128 /* first, set SYNC bits of corresponding streams */
1129 snd_hdac_stream_sync_trigger(hstr, true, sbits, AZX_REG_SSYNC);
1130
1131 snd_pcm_group_for_each_entry(s, substream) {
1132 if (s->pcm->card != substream->pcm->card)
1133 continue;
1134 stream = get_hdac_ext_stream(s);
1135 if (start)
1136 snd_hdac_stream_start(hdac_stream(stream), true);
1137 else
1138 snd_hdac_stream_stop(hdac_stream(stream));
1139 }
1140 spin_unlock_irqrestore(&bus->reg_lock, cookie);
1141
1142 snd_hdac_stream_sync(hstr, start, sbits);
1143
1144 spin_lock_irqsave(&bus->reg_lock, cookie);
1145
1146 /* reset SYNC bits */
1147 snd_hdac_stream_sync_trigger(hstr, false, sbits, AZX_REG_SSYNC);
1148 if (start)
1149 snd_hdac_stream_timecounter_init(hstr, sbits);
1150 spin_unlock_irqrestore(&bus->reg_lock, cookie);
1151
1152 return 0;
1153 }
1154
skl_platform_soc_trigger(struct snd_soc_component * component,struct snd_pcm_substream * substream,int cmd)1155 static int skl_platform_soc_trigger(struct snd_soc_component *component,
1156 struct snd_pcm_substream *substream,
1157 int cmd)
1158 {
1159 struct hdac_bus *bus = get_bus_ctx(substream);
1160
1161 if (!bus->ppcap)
1162 return skl_coupled_trigger(substream, cmd);
1163
1164 return 0;
1165 }
1166
skl_platform_soc_pointer(struct snd_soc_component * component,struct snd_pcm_substream * substream)1167 static snd_pcm_uframes_t skl_platform_soc_pointer(
1168 struct snd_soc_component *component,
1169 struct snd_pcm_substream *substream)
1170 {
1171 struct hdac_ext_stream *hstream = get_hdac_ext_stream(substream);
1172 struct hdac_bus *bus = get_bus_ctx(substream);
1173 unsigned int pos;
1174
1175 /*
1176 * Use DPIB for Playback stream as the periodic DMA Position-in-
1177 * Buffer Writes may be scheduled at the same time or later than
1178 * the MSI and does not guarantee to reflect the Position of the
1179 * last buffer that was transferred. Whereas DPIB register in
1180 * HAD space reflects the actual data that is transferred.
1181 * Use the position buffer for capture, as DPIB write gets
1182 * completed earlier than the actual data written to the DDR.
1183 *
1184 * For capture stream following workaround is required to fix the
1185 * incorrect position reporting.
1186 *
1187 * 1. Wait for 20us before reading the DMA position in buffer once
1188 * the interrupt is generated for stream completion as update happens
1189 * on the HDA frame boundary i.e. 20.833uSec.
1190 * 2. Read DPIB register to flush the DMA position value. This dummy
1191 * read is required to flush DMA position value.
1192 * 3. Read the DMA Position-in-Buffer. This value now will be equal to
1193 * or greater than period boundary.
1194 */
1195
1196 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1197 pos = readl(bus->remap_addr + AZX_REG_VS_SDXDPIB_XBASE +
1198 (AZX_REG_VS_SDXDPIB_XINTERVAL *
1199 hdac_stream(hstream)->index));
1200 } else {
1201 udelay(20);
1202 readl(bus->remap_addr +
1203 AZX_REG_VS_SDXDPIB_XBASE +
1204 (AZX_REG_VS_SDXDPIB_XINTERVAL *
1205 hdac_stream(hstream)->index));
1206 pos = snd_hdac_stream_get_pos_posbuf(hdac_stream(hstream));
1207 }
1208
1209 if (pos >= hdac_stream(hstream)->bufsize)
1210 pos = 0;
1211
1212 return bytes_to_frames(substream->runtime, pos);
1213 }
1214
skl_platform_soc_mmap(struct snd_soc_component * component,struct snd_pcm_substream * substream,struct vm_area_struct * area)1215 static int skl_platform_soc_mmap(struct snd_soc_component *component,
1216 struct snd_pcm_substream *substream,
1217 struct vm_area_struct *area)
1218 {
1219 return snd_pcm_lib_default_mmap(substream, area);
1220 }
1221
skl_adjust_codec_delay(struct snd_pcm_substream * substream,u64 nsec)1222 static u64 skl_adjust_codec_delay(struct snd_pcm_substream *substream,
1223 u64 nsec)
1224 {
1225 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
1226 struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
1227 u64 codec_frames, codec_nsecs;
1228
1229 if (!codec_dai->driver->ops->delay)
1230 return nsec;
1231
1232 codec_frames = codec_dai->driver->ops->delay(substream, codec_dai);
1233 codec_nsecs = div_u64(codec_frames * 1000000000LL,
1234 substream->runtime->rate);
1235
1236 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
1237 return nsec + codec_nsecs;
1238
1239 return (nsec > codec_nsecs) ? nsec - codec_nsecs : 0;
1240 }
1241
skl_platform_soc_get_time_info(struct snd_soc_component * component,struct snd_pcm_substream * substream,struct timespec64 * system_ts,struct timespec64 * audio_ts,struct snd_pcm_audio_tstamp_config * audio_tstamp_config,struct snd_pcm_audio_tstamp_report * audio_tstamp_report)1242 static int skl_platform_soc_get_time_info(
1243 struct snd_soc_component *component,
1244 struct snd_pcm_substream *substream,
1245 struct timespec64 *system_ts, struct timespec64 *audio_ts,
1246 struct snd_pcm_audio_tstamp_config *audio_tstamp_config,
1247 struct snd_pcm_audio_tstamp_report *audio_tstamp_report)
1248 {
1249 struct hdac_ext_stream *sstream = get_hdac_ext_stream(substream);
1250 struct hdac_stream *hstr = hdac_stream(sstream);
1251 u64 nsec;
1252
1253 if ((substream->runtime->hw.info & SNDRV_PCM_INFO_HAS_LINK_ATIME) &&
1254 (audio_tstamp_config->type_requested == SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK)) {
1255
1256 snd_pcm_gettime(substream->runtime, system_ts);
1257
1258 nsec = timecounter_read(&hstr->tc);
1259 nsec = div_u64(nsec, 3); /* can be optimized */
1260 if (audio_tstamp_config->report_delay)
1261 nsec = skl_adjust_codec_delay(substream, nsec);
1262
1263 *audio_ts = ns_to_timespec64(nsec);
1264
1265 audio_tstamp_report->actual_type = SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK;
1266 audio_tstamp_report->accuracy_report = 1; /* rest of struct is valid */
1267 audio_tstamp_report->accuracy = 42; /* 24MHzWallClk == 42ns resolution */
1268
1269 } else {
1270 audio_tstamp_report->actual_type = SNDRV_PCM_AUDIO_TSTAMP_TYPE_DEFAULT;
1271 }
1272
1273 return 0;
1274 }
1275
1276 #define MAX_PREALLOC_SIZE (32 * 1024 * 1024)
1277
skl_platform_soc_new(struct snd_soc_component * component,struct snd_soc_pcm_runtime * rtd)1278 static int skl_platform_soc_new(struct snd_soc_component *component,
1279 struct snd_soc_pcm_runtime *rtd)
1280 {
1281 struct snd_soc_dai *dai = asoc_rtd_to_cpu(rtd, 0);
1282 struct hdac_bus *bus = dev_get_drvdata(dai->dev);
1283 struct snd_pcm *pcm = rtd->pcm;
1284 unsigned int size;
1285 struct skl_dev *skl = bus_to_skl(bus);
1286
1287 if (dai->driver->playback.channels_min ||
1288 dai->driver->capture.channels_min) {
1289 /* buffer pre-allocation */
1290 size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024;
1291 if (size > MAX_PREALLOC_SIZE)
1292 size = MAX_PREALLOC_SIZE;
1293 snd_pcm_set_managed_buffer_all(pcm,
1294 SNDRV_DMA_TYPE_DEV_SG,
1295 &skl->pci->dev,
1296 size, MAX_PREALLOC_SIZE);
1297 }
1298
1299 return 0;
1300 }
1301
skl_get_module_info(struct skl_dev * skl,struct skl_module_cfg * mconfig)1302 static int skl_get_module_info(struct skl_dev *skl,
1303 struct skl_module_cfg *mconfig)
1304 {
1305 struct skl_module_inst_id *pin_id;
1306 guid_t *uuid_mod, *uuid_tplg;
1307 struct skl_module *skl_module;
1308 struct uuid_module *module;
1309 int i, ret = -EIO;
1310
1311 uuid_mod = (guid_t *)mconfig->guid;
1312
1313 if (list_empty(&skl->uuid_list)) {
1314 dev_err(skl->dev, "Module list is empty\n");
1315 return -EIO;
1316 }
1317
1318 for (i = 0; i < skl->nr_modules; i++) {
1319 skl_module = skl->modules[i];
1320 uuid_tplg = &skl_module->uuid;
1321 if (guid_equal(uuid_mod, uuid_tplg)) {
1322 mconfig->module = skl_module;
1323 ret = 0;
1324 break;
1325 }
1326 }
1327
1328 if (skl->nr_modules && ret)
1329 return ret;
1330
1331 ret = -EIO;
1332 list_for_each_entry(module, &skl->uuid_list, list) {
1333 if (guid_equal(uuid_mod, &module->uuid)) {
1334 mconfig->id.module_id = module->id;
1335 mconfig->module->loadable = module->is_loadable;
1336 ret = 0;
1337 }
1338
1339 for (i = 0; i < MAX_IN_QUEUE; i++) {
1340 pin_id = &mconfig->m_in_pin[i].id;
1341 if (guid_equal(&pin_id->mod_uuid, &module->uuid))
1342 pin_id->module_id = module->id;
1343 }
1344
1345 for (i = 0; i < MAX_OUT_QUEUE; i++) {
1346 pin_id = &mconfig->m_out_pin[i].id;
1347 if (guid_equal(&pin_id->mod_uuid, &module->uuid))
1348 pin_id->module_id = module->id;
1349 }
1350 }
1351
1352 return ret;
1353 }
1354
skl_populate_modules(struct skl_dev * skl)1355 static int skl_populate_modules(struct skl_dev *skl)
1356 {
1357 struct skl_pipeline *p;
1358 struct skl_pipe_module *m;
1359 struct snd_soc_dapm_widget *w;
1360 struct skl_module_cfg *mconfig;
1361 int ret = 0;
1362
1363 list_for_each_entry(p, &skl->ppl_list, node) {
1364 list_for_each_entry(m, &p->pipe->w_list, node) {
1365 w = m->w;
1366 mconfig = w->priv;
1367
1368 ret = skl_get_module_info(skl, mconfig);
1369 if (ret < 0) {
1370 dev_err(skl->dev,
1371 "query module info failed\n");
1372 return ret;
1373 }
1374
1375 skl_tplg_add_moduleid_in_bind_params(skl, w);
1376 }
1377 }
1378
1379 return ret;
1380 }
1381
skl_platform_soc_probe(struct snd_soc_component * component)1382 static int skl_platform_soc_probe(struct snd_soc_component *component)
1383 {
1384 struct hdac_bus *bus = dev_get_drvdata(component->dev);
1385 struct skl_dev *skl = bus_to_skl(bus);
1386 const struct skl_dsp_ops *ops;
1387 int ret;
1388
1389 pm_runtime_get_sync(component->dev);
1390 if (bus->ppcap) {
1391 skl->component = component;
1392
1393 /* init debugfs */
1394 skl->debugfs = skl_debugfs_init(skl);
1395
1396 ret = skl_tplg_init(component, bus);
1397 if (ret < 0) {
1398 dev_err(component->dev, "Failed to init topology!\n");
1399 return ret;
1400 }
1401
1402 /* load the firmwares, since all is set */
1403 ops = skl_get_dsp_ops(skl->pci->device);
1404 if (!ops)
1405 return -EIO;
1406
1407 /*
1408 * Disable dynamic clock and power gating during firmware
1409 * and library download
1410 */
1411 skl->enable_miscbdcge(component->dev, false);
1412 skl->clock_power_gating(component->dev, false);
1413
1414 ret = ops->init_fw(component->dev, skl);
1415 skl->enable_miscbdcge(component->dev, true);
1416 skl->clock_power_gating(component->dev, true);
1417 if (ret < 0) {
1418 dev_err(component->dev, "Failed to boot first fw: %d\n", ret);
1419 return ret;
1420 }
1421 skl_populate_modules(skl);
1422 skl->update_d0i3c = skl_update_d0i3c;
1423
1424 if (skl->cfg.astate_cfg != NULL) {
1425 skl_dsp_set_astate_cfg(skl,
1426 skl->cfg.astate_cfg->count,
1427 skl->cfg.astate_cfg);
1428 }
1429 }
1430 pm_runtime_mark_last_busy(component->dev);
1431 pm_runtime_put_autosuspend(component->dev);
1432
1433 return 0;
1434 }
1435
skl_platform_soc_remove(struct snd_soc_component * component)1436 static void skl_platform_soc_remove(struct snd_soc_component *component)
1437 {
1438 struct hdac_bus *bus = dev_get_drvdata(component->dev);
1439 struct skl_dev *skl = bus_to_skl(bus);
1440
1441 skl_tplg_exit(component, bus);
1442
1443 skl_debugfs_exit(skl);
1444 }
1445
1446 static const struct snd_soc_component_driver skl_component = {
1447 .name = "pcm",
1448 .probe = skl_platform_soc_probe,
1449 .remove = skl_platform_soc_remove,
1450 .open = skl_platform_soc_open,
1451 .trigger = skl_platform_soc_trigger,
1452 .pointer = skl_platform_soc_pointer,
1453 .get_time_info = skl_platform_soc_get_time_info,
1454 .mmap = skl_platform_soc_mmap,
1455 .pcm_construct = skl_platform_soc_new,
1456 .module_get_upon_open = 1, /* increment refcount when a pcm is opened */
1457 };
1458
skl_platform_register(struct device * dev)1459 int skl_platform_register(struct device *dev)
1460 {
1461 int ret;
1462 struct snd_soc_dai_driver *dais;
1463 int num_dais = ARRAY_SIZE(skl_platform_dai);
1464 struct hdac_bus *bus = dev_get_drvdata(dev);
1465 struct skl_dev *skl = bus_to_skl(bus);
1466
1467 skl->dais = kmemdup(skl_platform_dai, sizeof(skl_platform_dai),
1468 GFP_KERNEL);
1469 if (!skl->dais) {
1470 ret = -ENOMEM;
1471 goto err;
1472 }
1473
1474 if (!skl->use_tplg_pcm) {
1475 dais = krealloc(skl->dais, sizeof(skl_fe_dai) +
1476 sizeof(skl_platform_dai), GFP_KERNEL);
1477 if (!dais) {
1478 ret = -ENOMEM;
1479 goto err;
1480 }
1481
1482 skl->dais = dais;
1483 memcpy(&skl->dais[ARRAY_SIZE(skl_platform_dai)], skl_fe_dai,
1484 sizeof(skl_fe_dai));
1485 num_dais += ARRAY_SIZE(skl_fe_dai);
1486 }
1487
1488 ret = devm_snd_soc_register_component(dev, &skl_component,
1489 skl->dais, num_dais);
1490 if (ret)
1491 dev_err(dev, "soc component registration failed %d\n", ret);
1492 err:
1493 return ret;
1494 }
1495
skl_platform_unregister(struct device * dev)1496 int skl_platform_unregister(struct device *dev)
1497 {
1498 struct hdac_bus *bus = dev_get_drvdata(dev);
1499 struct skl_dev *skl = bus_to_skl(bus);
1500 struct skl_module_deferred_bind *modules, *tmp;
1501
1502 list_for_each_entry_safe(modules, tmp, &skl->bind_list, node) {
1503 list_del(&modules->node);
1504 kfree(modules);
1505 }
1506
1507 kfree(skl->dais);
1508
1509 return 0;
1510 }
1511