1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2010-2011,2013-2015 The Linux Foundation. All rights reserved.
4 *
5 * lpass-cpu.c -- ALSA SoC CPU DAI driver for QTi LPASS
6 */
7
8 #include <linux/clk.h>
9 #include <linux/kernel.h>
10 #include <linux/module.h>
11 #include <linux/of.h>
12 #include <linux/of_device.h>
13 #include <linux/platform_device.h>
14 #include <sound/pcm.h>
15 #include <sound/pcm_params.h>
16 #include <linux/regmap.h>
17 #include <sound/soc.h>
18 #include <sound/soc-dai.h>
19 #include "lpass-lpaif-reg.h"
20 #include "lpass.h"
21
22 #define LPASS_CPU_MAX_MI2S_LINES 4
23 #define LPASS_CPU_I2S_SD0_MASK BIT(0)
24 #define LPASS_CPU_I2S_SD1_MASK BIT(1)
25 #define LPASS_CPU_I2S_SD2_MASK BIT(2)
26 #define LPASS_CPU_I2S_SD3_MASK BIT(3)
27 #define LPASS_CPU_I2S_SD0_1_MASK GENMASK(1, 0)
28 #define LPASS_CPU_I2S_SD2_3_MASK GENMASK(3, 2)
29 #define LPASS_CPU_I2S_SD0_1_2_MASK GENMASK(2, 0)
30 #define LPASS_CPU_I2S_SD0_1_2_3_MASK GENMASK(3, 0)
31
lpass_cpu_init_i2sctl_bitfields(struct device * dev,struct lpaif_i2sctl * i2sctl,struct regmap * map)32 static int lpass_cpu_init_i2sctl_bitfields(struct device *dev,
33 struct lpaif_i2sctl *i2sctl, struct regmap *map)
34 {
35 struct lpass_data *drvdata = dev_get_drvdata(dev);
36 struct lpass_variant *v = drvdata->variant;
37
38 i2sctl->loopback = devm_regmap_field_alloc(dev, map, v->loopback);
39 i2sctl->spken = devm_regmap_field_alloc(dev, map, v->spken);
40 i2sctl->spkmode = devm_regmap_field_alloc(dev, map, v->spkmode);
41 i2sctl->spkmono = devm_regmap_field_alloc(dev, map, v->spkmono);
42 i2sctl->micen = devm_regmap_field_alloc(dev, map, v->micen);
43 i2sctl->micmode = devm_regmap_field_alloc(dev, map, v->micmode);
44 i2sctl->micmono = devm_regmap_field_alloc(dev, map, v->micmono);
45 i2sctl->wssrc = devm_regmap_field_alloc(dev, map, v->wssrc);
46 i2sctl->bitwidth = devm_regmap_field_alloc(dev, map, v->bitwidth);
47
48 if (IS_ERR(i2sctl->loopback) || IS_ERR(i2sctl->spken) ||
49 IS_ERR(i2sctl->spkmode) || IS_ERR(i2sctl->spkmono) ||
50 IS_ERR(i2sctl->micen) || IS_ERR(i2sctl->micmode) ||
51 IS_ERR(i2sctl->micmono) || IS_ERR(i2sctl->wssrc) ||
52 IS_ERR(i2sctl->bitwidth))
53 return -EINVAL;
54
55 return 0;
56 }
57
lpass_cpu_daiops_set_sysclk(struct snd_soc_dai * dai,int clk_id,unsigned int freq,int dir)58 static int lpass_cpu_daiops_set_sysclk(struct snd_soc_dai *dai, int clk_id,
59 unsigned int freq, int dir)
60 {
61 struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
62 int ret;
63
64 ret = clk_set_rate(drvdata->mi2s_osr_clk[dai->driver->id], freq);
65 if (ret)
66 dev_err(dai->dev, "error setting mi2s osrclk to %u: %d\n",
67 freq, ret);
68
69 return ret;
70 }
71
lpass_cpu_daiops_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)72 static int lpass_cpu_daiops_startup(struct snd_pcm_substream *substream,
73 struct snd_soc_dai *dai)
74 {
75 struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
76 int ret;
77
78 ret = clk_prepare_enable(drvdata->mi2s_osr_clk[dai->driver->id]);
79 if (ret) {
80 dev_err(dai->dev, "error in enabling mi2s osr clk: %d\n", ret);
81 return ret;
82 }
83 ret = clk_prepare(drvdata->mi2s_bit_clk[dai->driver->id]);
84 if (ret) {
85 dev_err(dai->dev, "error in enabling mi2s bit clk: %d\n", ret);
86 clk_disable_unprepare(drvdata->mi2s_osr_clk[dai->driver->id]);
87 return ret;
88 }
89 return 0;
90 }
91
lpass_cpu_daiops_shutdown(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)92 static void lpass_cpu_daiops_shutdown(struct snd_pcm_substream *substream,
93 struct snd_soc_dai *dai)
94 {
95 struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
96 struct lpaif_i2sctl *i2sctl = drvdata->i2sctl;
97 unsigned int id = dai->driver->id;
98
99 clk_disable_unprepare(drvdata->mi2s_osr_clk[dai->driver->id]);
100 /*
101 * Ensure LRCLK is disabled even in device node validation.
102 * Will not impact if disabled in lpass_cpu_daiops_trigger()
103 * suspend.
104 */
105 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
106 regmap_fields_write(i2sctl->spken, id, LPAIF_I2SCTL_SPKEN_DISABLE);
107 else
108 regmap_fields_write(i2sctl->micen, id, LPAIF_I2SCTL_MICEN_DISABLE);
109
110 /*
111 * BCLK may not be enabled if lpass_cpu_daiops_prepare is called before
112 * lpass_cpu_daiops_shutdown. It's paired with the clk_enable in
113 * lpass_cpu_daiops_prepare.
114 */
115 if (drvdata->mi2s_was_prepared[dai->driver->id]) {
116 drvdata->mi2s_was_prepared[dai->driver->id] = false;
117 clk_disable(drvdata->mi2s_bit_clk[dai->driver->id]);
118 }
119
120 clk_unprepare(drvdata->mi2s_bit_clk[dai->driver->id]);
121 }
122
lpass_cpu_daiops_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)123 static int lpass_cpu_daiops_hw_params(struct snd_pcm_substream *substream,
124 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
125 {
126 struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
127 struct lpaif_i2sctl *i2sctl = drvdata->i2sctl;
128 unsigned int id = dai->driver->id;
129 snd_pcm_format_t format = params_format(params);
130 unsigned int channels = params_channels(params);
131 unsigned int rate = params_rate(params);
132 unsigned int mode;
133 unsigned int regval;
134 int bitwidth, ret;
135
136 bitwidth = snd_pcm_format_width(format);
137 if (bitwidth < 0) {
138 dev_err(dai->dev, "invalid bit width given: %d\n", bitwidth);
139 return bitwidth;
140 }
141
142 ret = regmap_fields_write(i2sctl->loopback, id,
143 LPAIF_I2SCTL_LOOPBACK_DISABLE);
144 if (ret) {
145 dev_err(dai->dev, "error updating loopback field: %d\n", ret);
146 return ret;
147 }
148
149 ret = regmap_fields_write(i2sctl->wssrc, id,
150 LPAIF_I2SCTL_WSSRC_INTERNAL);
151 if (ret) {
152 dev_err(dai->dev, "error updating wssrc field: %d\n", ret);
153 return ret;
154 }
155
156 switch (bitwidth) {
157 case 16:
158 regval = LPAIF_I2SCTL_BITWIDTH_16;
159 break;
160 case 24:
161 regval = LPAIF_I2SCTL_BITWIDTH_24;
162 break;
163 case 32:
164 regval = LPAIF_I2SCTL_BITWIDTH_32;
165 break;
166 default:
167 dev_err(dai->dev, "invalid bitwidth given: %d\n", bitwidth);
168 return -EINVAL;
169 }
170
171 ret = regmap_fields_write(i2sctl->bitwidth, id, regval);
172 if (ret) {
173 dev_err(dai->dev, "error updating bitwidth field: %d\n", ret);
174 return ret;
175 }
176
177 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
178 mode = drvdata->mi2s_playback_sd_mode[id];
179 else
180 mode = drvdata->mi2s_capture_sd_mode[id];
181
182 if (!mode) {
183 dev_err(dai->dev, "no line is assigned\n");
184 return -EINVAL;
185 }
186
187 switch (channels) {
188 case 1:
189 case 2:
190 switch (mode) {
191 case LPAIF_I2SCTL_MODE_QUAD01:
192 case LPAIF_I2SCTL_MODE_6CH:
193 case LPAIF_I2SCTL_MODE_8CH:
194 mode = LPAIF_I2SCTL_MODE_SD0;
195 break;
196 case LPAIF_I2SCTL_MODE_QUAD23:
197 mode = LPAIF_I2SCTL_MODE_SD2;
198 break;
199 }
200
201 break;
202 case 4:
203 if (mode < LPAIF_I2SCTL_MODE_QUAD01) {
204 dev_err(dai->dev, "cannot configure 4 channels with mode %d\n",
205 mode);
206 return -EINVAL;
207 }
208
209 switch (mode) {
210 case LPAIF_I2SCTL_MODE_6CH:
211 case LPAIF_I2SCTL_MODE_8CH:
212 mode = LPAIF_I2SCTL_MODE_QUAD01;
213 break;
214 }
215 break;
216 case 6:
217 if (mode < LPAIF_I2SCTL_MODE_6CH) {
218 dev_err(dai->dev, "cannot configure 6 channels with mode %d\n",
219 mode);
220 return -EINVAL;
221 }
222
223 switch (mode) {
224 case LPAIF_I2SCTL_MODE_8CH:
225 mode = LPAIF_I2SCTL_MODE_6CH;
226 break;
227 }
228 break;
229 case 8:
230 if (mode < LPAIF_I2SCTL_MODE_8CH) {
231 dev_err(dai->dev, "cannot configure 8 channels with mode %d\n",
232 mode);
233 return -EINVAL;
234 }
235 break;
236 default:
237 dev_err(dai->dev, "invalid channels given: %u\n", channels);
238 return -EINVAL;
239 }
240
241 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
242 ret = regmap_fields_write(i2sctl->spkmode, id,
243 LPAIF_I2SCTL_SPKMODE(mode));
244 if (ret) {
245 dev_err(dai->dev, "error writing to i2sctl spkr mode: %d\n",
246 ret);
247 return ret;
248 }
249 if (channels >= 2)
250 ret = regmap_fields_write(i2sctl->spkmono, id,
251 LPAIF_I2SCTL_SPKMONO_STEREO);
252 else
253 ret = regmap_fields_write(i2sctl->spkmono, id,
254 LPAIF_I2SCTL_SPKMONO_MONO);
255 } else {
256 ret = regmap_fields_write(i2sctl->micmode, id,
257 LPAIF_I2SCTL_MICMODE(mode));
258 if (ret) {
259 dev_err(dai->dev, "error writing to i2sctl mic mode: %d\n",
260 ret);
261 return ret;
262 }
263 if (channels >= 2)
264 ret = regmap_fields_write(i2sctl->micmono, id,
265 LPAIF_I2SCTL_MICMONO_STEREO);
266 else
267 ret = regmap_fields_write(i2sctl->micmono, id,
268 LPAIF_I2SCTL_MICMONO_MONO);
269 }
270
271 if (ret) {
272 dev_err(dai->dev, "error writing to i2sctl channels mode: %d\n",
273 ret);
274 return ret;
275 }
276
277 ret = clk_set_rate(drvdata->mi2s_bit_clk[id],
278 rate * bitwidth * 2);
279 if (ret) {
280 dev_err(dai->dev, "error setting mi2s bitclk to %u: %d\n",
281 rate * bitwidth * 2, ret);
282 return ret;
283 }
284
285 return 0;
286 }
287
lpass_cpu_daiops_trigger(struct snd_pcm_substream * substream,int cmd,struct snd_soc_dai * dai)288 static int lpass_cpu_daiops_trigger(struct snd_pcm_substream *substream,
289 int cmd, struct snd_soc_dai *dai)
290 {
291 struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
292 struct lpaif_i2sctl *i2sctl = drvdata->i2sctl;
293 unsigned int id = dai->driver->id;
294 int ret = -EINVAL;
295
296 switch (cmd) {
297 case SNDRV_PCM_TRIGGER_START:
298 case SNDRV_PCM_TRIGGER_RESUME:
299 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
300 /*
301 * Ensure lpass BCLK/LRCLK is enabled during
302 * device resume as lpass_cpu_daiops_prepare() is not called
303 * after the device resumes. We don't check mi2s_was_prepared before
304 * enable/disable BCLK in trigger events because:
305 * 1. These trigger events are paired, so the BCLK
306 * enable_count is balanced.
307 * 2. the BCLK can be shared (ex: headset and headset mic),
308 * we need to increase the enable_count so that we don't
309 * turn off the shared BCLK while other devices are using
310 * it.
311 */
312 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
313 ret = regmap_fields_write(i2sctl->spken, id,
314 LPAIF_I2SCTL_SPKEN_ENABLE);
315 } else {
316 ret = regmap_fields_write(i2sctl->micen, id,
317 LPAIF_I2SCTL_MICEN_ENABLE);
318 }
319 if (ret)
320 dev_err(dai->dev, "error writing to i2sctl reg: %d\n",
321 ret);
322
323 ret = clk_enable(drvdata->mi2s_bit_clk[id]);
324 if (ret) {
325 dev_err(dai->dev, "error in enabling mi2s bit clk: %d\n", ret);
326 clk_disable(drvdata->mi2s_osr_clk[id]);
327 return ret;
328 }
329 break;
330 case SNDRV_PCM_TRIGGER_STOP:
331 case SNDRV_PCM_TRIGGER_SUSPEND:
332 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
333 /*
334 * To ensure lpass BCLK/LRCLK is disabled during
335 * device suspend.
336 */
337 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
338 ret = regmap_fields_write(i2sctl->spken, id,
339 LPAIF_I2SCTL_SPKEN_DISABLE);
340 } else {
341 ret = regmap_fields_write(i2sctl->micen, id,
342 LPAIF_I2SCTL_MICEN_DISABLE);
343 }
344 if (ret)
345 dev_err(dai->dev, "error writing to i2sctl reg: %d\n",
346 ret);
347
348 clk_disable(drvdata->mi2s_bit_clk[dai->driver->id]);
349
350 break;
351 }
352
353 return ret;
354 }
355
lpass_cpu_daiops_prepare(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)356 static int lpass_cpu_daiops_prepare(struct snd_pcm_substream *substream,
357 struct snd_soc_dai *dai)
358 {
359 struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
360 struct lpaif_i2sctl *i2sctl = drvdata->i2sctl;
361 unsigned int id = dai->driver->id;
362 int ret;
363
364 /*
365 * Ensure lpass BCLK/LRCLK is enabled bit before playback/capture
366 * data flow starts. This allows other codec to have some delay before
367 * the data flow.
368 * (ex: to drop start up pop noise before capture starts).
369 */
370 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
371 ret = regmap_fields_write(i2sctl->spken, id, LPAIF_I2SCTL_SPKEN_ENABLE);
372 else
373 ret = regmap_fields_write(i2sctl->micen, id, LPAIF_I2SCTL_MICEN_ENABLE);
374
375 if (ret) {
376 dev_err(dai->dev, "error writing to i2sctl reg: %d\n", ret);
377 return ret;
378 }
379
380 /*
381 * Check mi2s_was_prepared before enabling BCLK as lpass_cpu_daiops_prepare can
382 * be called multiple times. It's paired with the clk_disable in
383 * lpass_cpu_daiops_shutdown.
384 */
385 if (!drvdata->mi2s_was_prepared[dai->driver->id]) {
386 ret = clk_enable(drvdata->mi2s_bit_clk[id]);
387 if (ret) {
388 dev_err(dai->dev, "error in enabling mi2s bit clk: %d\n", ret);
389 return ret;
390 }
391 drvdata->mi2s_was_prepared[dai->driver->id] = true;
392 }
393 return 0;
394 }
395
396 const struct snd_soc_dai_ops asoc_qcom_lpass_cpu_dai_ops = {
397 .set_sysclk = lpass_cpu_daiops_set_sysclk,
398 .startup = lpass_cpu_daiops_startup,
399 .shutdown = lpass_cpu_daiops_shutdown,
400 .hw_params = lpass_cpu_daiops_hw_params,
401 .trigger = lpass_cpu_daiops_trigger,
402 .prepare = lpass_cpu_daiops_prepare,
403 };
404 EXPORT_SYMBOL_GPL(asoc_qcom_lpass_cpu_dai_ops);
405
asoc_qcom_lpass_cpu_dai_probe(struct snd_soc_dai * dai)406 int asoc_qcom_lpass_cpu_dai_probe(struct snd_soc_dai *dai)
407 {
408 struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
409 int ret;
410
411 /* ensure audio hardware is disabled */
412 ret = regmap_write(drvdata->lpaif_map,
413 LPAIF_I2SCTL_REG(drvdata->variant, dai->driver->id), 0);
414 if (ret)
415 dev_err(dai->dev, "error writing to i2sctl reg: %d\n", ret);
416
417 return ret;
418 }
419 EXPORT_SYMBOL_GPL(asoc_qcom_lpass_cpu_dai_probe);
420
asoc_qcom_of_xlate_dai_name(struct snd_soc_component * component,struct of_phandle_args * args,const char ** dai_name)421 static int asoc_qcom_of_xlate_dai_name(struct snd_soc_component *component,
422 struct of_phandle_args *args,
423 const char **dai_name)
424 {
425 struct lpass_data *drvdata = snd_soc_component_get_drvdata(component);
426 struct lpass_variant *variant = drvdata->variant;
427 int id = args->args[0];
428 int ret = -EINVAL;
429 int i;
430
431 for (i = 0; i < variant->num_dai; i++) {
432 if (variant->dai_driver[i].id == id) {
433 *dai_name = variant->dai_driver[i].name;
434 ret = 0;
435 break;
436 }
437 }
438
439 return ret;
440 }
441
442 static const struct snd_soc_component_driver lpass_cpu_comp_driver = {
443 .name = "lpass-cpu",
444 .of_xlate_dai_name = asoc_qcom_of_xlate_dai_name,
445 };
446
lpass_cpu_regmap_writeable(struct device * dev,unsigned int reg)447 static bool lpass_cpu_regmap_writeable(struct device *dev, unsigned int reg)
448 {
449 struct lpass_data *drvdata = dev_get_drvdata(dev);
450 struct lpass_variant *v = drvdata->variant;
451 int i;
452
453 for (i = 0; i < v->i2s_ports; ++i)
454 if (reg == LPAIF_I2SCTL_REG(v, i))
455 return true;
456
457 for (i = 0; i < v->irq_ports; ++i) {
458 if (reg == LPAIF_IRQEN_REG(v, i))
459 return true;
460 if (reg == LPAIF_IRQCLEAR_REG(v, i))
461 return true;
462 }
463
464 for (i = 0; i < v->rdma_channels; ++i) {
465 if (reg == LPAIF_RDMACTL_REG(v, i))
466 return true;
467 if (reg == LPAIF_RDMABASE_REG(v, i))
468 return true;
469 if (reg == LPAIF_RDMABUFF_REG(v, i))
470 return true;
471 if (reg == LPAIF_RDMAPER_REG(v, i))
472 return true;
473 }
474
475 for (i = 0; i < v->wrdma_channels; ++i) {
476 if (reg == LPAIF_WRDMACTL_REG(v, i + v->wrdma_channel_start))
477 return true;
478 if (reg == LPAIF_WRDMABASE_REG(v, i + v->wrdma_channel_start))
479 return true;
480 if (reg == LPAIF_WRDMABUFF_REG(v, i + v->wrdma_channel_start))
481 return true;
482 if (reg == LPAIF_WRDMAPER_REG(v, i + v->wrdma_channel_start))
483 return true;
484 }
485
486 return false;
487 }
488
lpass_cpu_regmap_readable(struct device * dev,unsigned int reg)489 static bool lpass_cpu_regmap_readable(struct device *dev, unsigned int reg)
490 {
491 struct lpass_data *drvdata = dev_get_drvdata(dev);
492 struct lpass_variant *v = drvdata->variant;
493 int i;
494
495 for (i = 0; i < v->i2s_ports; ++i)
496 if (reg == LPAIF_I2SCTL_REG(v, i))
497 return true;
498
499 for (i = 0; i < v->irq_ports; ++i) {
500 if (reg == LPAIF_IRQEN_REG(v, i))
501 return true;
502 if (reg == LPAIF_IRQSTAT_REG(v, i))
503 return true;
504 }
505
506 for (i = 0; i < v->rdma_channels; ++i) {
507 if (reg == LPAIF_RDMACTL_REG(v, i))
508 return true;
509 if (reg == LPAIF_RDMABASE_REG(v, i))
510 return true;
511 if (reg == LPAIF_RDMABUFF_REG(v, i))
512 return true;
513 if (reg == LPAIF_RDMACURR_REG(v, i))
514 return true;
515 if (reg == LPAIF_RDMAPER_REG(v, i))
516 return true;
517 }
518
519 for (i = 0; i < v->wrdma_channels; ++i) {
520 if (reg == LPAIF_WRDMACTL_REG(v, i + v->wrdma_channel_start))
521 return true;
522 if (reg == LPAIF_WRDMABASE_REG(v, i + v->wrdma_channel_start))
523 return true;
524 if (reg == LPAIF_WRDMABUFF_REG(v, i + v->wrdma_channel_start))
525 return true;
526 if (reg == LPAIF_WRDMACURR_REG(v, i + v->wrdma_channel_start))
527 return true;
528 if (reg == LPAIF_WRDMAPER_REG(v, i + v->wrdma_channel_start))
529 return true;
530 }
531
532 return false;
533 }
534
lpass_cpu_regmap_volatile(struct device * dev,unsigned int reg)535 static bool lpass_cpu_regmap_volatile(struct device *dev, unsigned int reg)
536 {
537 struct lpass_data *drvdata = dev_get_drvdata(dev);
538 struct lpass_variant *v = drvdata->variant;
539 int i;
540
541 for (i = 0; i < v->irq_ports; ++i)
542 if (reg == LPAIF_IRQSTAT_REG(v, i))
543 return true;
544
545 for (i = 0; i < v->rdma_channels; ++i)
546 if (reg == LPAIF_RDMACURR_REG(v, i))
547 return true;
548
549 for (i = 0; i < v->wrdma_channels; ++i)
550 if (reg == LPAIF_WRDMACURR_REG(v, i + v->wrdma_channel_start))
551 return true;
552
553 return false;
554 }
555
556 static struct regmap_config lpass_cpu_regmap_config = {
557 .reg_bits = 32,
558 .reg_stride = 4,
559 .val_bits = 32,
560 .writeable_reg = lpass_cpu_regmap_writeable,
561 .readable_reg = lpass_cpu_regmap_readable,
562 .volatile_reg = lpass_cpu_regmap_volatile,
563 .cache_type = REGCACHE_FLAT,
564 };
565
lpass_hdmi_init_bitfields(struct device * dev,struct regmap * map)566 static int lpass_hdmi_init_bitfields(struct device *dev, struct regmap *map)
567 {
568 struct lpass_data *drvdata = dev_get_drvdata(dev);
569 struct lpass_variant *v = drvdata->variant;
570 unsigned int i;
571 struct lpass_hdmi_tx_ctl *tx_ctl;
572 struct regmap_field *legacy_en;
573 struct lpass_vbit_ctrl *vbit_ctl;
574 struct regmap_field *tx_parity;
575 struct lpass_dp_metadata_ctl *meta_ctl;
576 struct lpass_sstream_ctl *sstream_ctl;
577 struct regmap_field *ch_msb;
578 struct regmap_field *ch_lsb;
579 struct lpass_hdmitx_dmactl *tx_dmactl;
580 int rval;
581
582 tx_ctl = devm_kzalloc(dev, sizeof(*tx_ctl), GFP_KERNEL);
583 if (!tx_ctl)
584 return -ENOMEM;
585
586 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->soft_reset, tx_ctl->soft_reset);
587 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->force_reset, tx_ctl->force_reset);
588 drvdata->tx_ctl = tx_ctl;
589
590 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->legacy_en, legacy_en);
591 drvdata->hdmitx_legacy_en = legacy_en;
592
593 vbit_ctl = devm_kzalloc(dev, sizeof(*vbit_ctl), GFP_KERNEL);
594 if (!vbit_ctl)
595 return -ENOMEM;
596
597 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->replace_vbit, vbit_ctl->replace_vbit);
598 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->vbit_stream, vbit_ctl->vbit_stream);
599 drvdata->vbit_ctl = vbit_ctl;
600
601
602 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->calc_en, tx_parity);
603 drvdata->hdmitx_parity_calc_en = tx_parity;
604
605 meta_ctl = devm_kzalloc(dev, sizeof(*meta_ctl), GFP_KERNEL);
606 if (!meta_ctl)
607 return -ENOMEM;
608
609 rval = devm_regmap_field_bulk_alloc(dev, map, &meta_ctl->mute, &v->mute, 7);
610 if (rval)
611 return rval;
612 drvdata->meta_ctl = meta_ctl;
613
614 sstream_ctl = devm_kzalloc(dev, sizeof(*sstream_ctl), GFP_KERNEL);
615 if (!sstream_ctl)
616 return -ENOMEM;
617
618 rval = devm_regmap_field_bulk_alloc(dev, map, &sstream_ctl->sstream_en, &v->sstream_en, 9);
619 if (rval)
620 return rval;
621
622 drvdata->sstream_ctl = sstream_ctl;
623
624 for (i = 0; i < LPASS_MAX_HDMI_DMA_CHANNELS; i++) {
625 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->msb_bits, ch_msb);
626 drvdata->hdmitx_ch_msb[i] = ch_msb;
627
628 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->lsb_bits, ch_lsb);
629 drvdata->hdmitx_ch_lsb[i] = ch_lsb;
630
631 tx_dmactl = devm_kzalloc(dev, sizeof(*tx_dmactl), GFP_KERNEL);
632 if (!tx_dmactl)
633 return -ENOMEM;
634
635 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->use_hw_chs, tx_dmactl->use_hw_chs);
636 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->use_hw_usr, tx_dmactl->use_hw_usr);
637 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->hw_chs_sel, tx_dmactl->hw_chs_sel);
638 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->hw_usr_sel, tx_dmactl->hw_usr_sel);
639 drvdata->hdmi_tx_dmactl[i] = tx_dmactl;
640 }
641 return 0;
642 }
643
lpass_hdmi_regmap_writeable(struct device * dev,unsigned int reg)644 static bool lpass_hdmi_regmap_writeable(struct device *dev, unsigned int reg)
645 {
646 struct lpass_data *drvdata = dev_get_drvdata(dev);
647 struct lpass_variant *v = drvdata->variant;
648 int i;
649
650 if (reg == LPASS_HDMI_TX_CTL_ADDR(v))
651 return true;
652 if (reg == LPASS_HDMI_TX_LEGACY_ADDR(v))
653 return true;
654 if (reg == LPASS_HDMI_TX_VBIT_CTL_ADDR(v))
655 return true;
656 if (reg == LPASS_HDMI_TX_PARITY_ADDR(v))
657 return true;
658 if (reg == LPASS_HDMI_TX_DP_ADDR(v))
659 return true;
660 if (reg == LPASS_HDMI_TX_SSTREAM_ADDR(v))
661 return true;
662 if (reg == LPASS_HDMITX_APP_IRQEN_REG(v))
663 return true;
664 if (reg == LPASS_HDMITX_APP_IRQCLEAR_REG(v))
665 return true;
666
667 for (i = 0; i < v->hdmi_rdma_channels; i++) {
668 if (reg == LPASS_HDMI_TX_CH_LSB_ADDR(v, i))
669 return true;
670 if (reg == LPASS_HDMI_TX_CH_MSB_ADDR(v, i))
671 return true;
672 if (reg == LPASS_HDMI_TX_DMA_ADDR(v, i))
673 return true;
674 }
675
676 for (i = 0; i < v->hdmi_rdma_channels; ++i) {
677 if (reg == LPAIF_HDMI_RDMACTL_REG(v, i))
678 return true;
679 if (reg == LPAIF_HDMI_RDMABASE_REG(v, i))
680 return true;
681 if (reg == LPAIF_HDMI_RDMABUFF_REG(v, i))
682 return true;
683 if (reg == LPAIF_HDMI_RDMAPER_REG(v, i))
684 return true;
685 }
686 return false;
687 }
688
lpass_hdmi_regmap_readable(struct device * dev,unsigned int reg)689 static bool lpass_hdmi_regmap_readable(struct device *dev, unsigned int reg)
690 {
691 struct lpass_data *drvdata = dev_get_drvdata(dev);
692 struct lpass_variant *v = drvdata->variant;
693 int i;
694
695 if (reg == LPASS_HDMI_TX_CTL_ADDR(v))
696 return true;
697 if (reg == LPASS_HDMI_TX_LEGACY_ADDR(v))
698 return true;
699 if (reg == LPASS_HDMI_TX_VBIT_CTL_ADDR(v))
700 return true;
701
702 for (i = 0; i < v->hdmi_rdma_channels; i++) {
703 if (reg == LPASS_HDMI_TX_CH_LSB_ADDR(v, i))
704 return true;
705 if (reg == LPASS_HDMI_TX_CH_MSB_ADDR(v, i))
706 return true;
707 if (reg == LPASS_HDMI_TX_DMA_ADDR(v, i))
708 return true;
709 }
710
711 if (reg == LPASS_HDMI_TX_PARITY_ADDR(v))
712 return true;
713 if (reg == LPASS_HDMI_TX_DP_ADDR(v))
714 return true;
715 if (reg == LPASS_HDMI_TX_SSTREAM_ADDR(v))
716 return true;
717 if (reg == LPASS_HDMITX_APP_IRQEN_REG(v))
718 return true;
719 if (reg == LPASS_HDMITX_APP_IRQSTAT_REG(v))
720 return true;
721
722 for (i = 0; i < v->hdmi_rdma_channels; ++i) {
723 if (reg == LPAIF_HDMI_RDMACTL_REG(v, i))
724 return true;
725 if (reg == LPAIF_HDMI_RDMABASE_REG(v, i))
726 return true;
727 if (reg == LPAIF_HDMI_RDMABUFF_REG(v, i))
728 return true;
729 if (reg == LPAIF_HDMI_RDMAPER_REG(v, i))
730 return true;
731 if (reg == LPAIF_HDMI_RDMACURR_REG(v, i))
732 return true;
733 }
734
735 return false;
736 }
737
lpass_hdmi_regmap_volatile(struct device * dev,unsigned int reg)738 static bool lpass_hdmi_regmap_volatile(struct device *dev, unsigned int reg)
739 {
740 struct lpass_data *drvdata = dev_get_drvdata(dev);
741 struct lpass_variant *v = drvdata->variant;
742 int i;
743
744 if (reg == LPASS_HDMITX_APP_IRQSTAT_REG(v))
745 return true;
746 if (reg == LPASS_HDMI_TX_LEGACY_ADDR(v))
747 return true;
748 if (reg == LPASS_HDMI_TX_VBIT_CTL_ADDR(v))
749 return true;
750 if (reg == LPASS_HDMI_TX_PARITY_ADDR(v))
751 return true;
752
753 for (i = 0; i < v->hdmi_rdma_channels; ++i) {
754 if (reg == LPAIF_HDMI_RDMACURR_REG(v, i))
755 return true;
756 if (reg == LPASS_HDMI_TX_DMA_ADDR(v, i))
757 return true;
758 if (reg == LPASS_HDMI_TX_CH_LSB_ADDR(v, i))
759 return true;
760 if (reg == LPASS_HDMI_TX_CH_MSB_ADDR(v, i))
761 return true;
762 }
763 return false;
764 }
765
766 struct regmap_config lpass_hdmi_regmap_config = {
767 .reg_bits = 32,
768 .reg_stride = 4,
769 .val_bits = 32,
770 .writeable_reg = lpass_hdmi_regmap_writeable,
771 .readable_reg = lpass_hdmi_regmap_readable,
772 .volatile_reg = lpass_hdmi_regmap_volatile,
773 .cache_type = REGCACHE_FLAT,
774 };
775
of_lpass_cpu_parse_sd_lines(struct device * dev,struct device_node * node,const char * name)776 static unsigned int of_lpass_cpu_parse_sd_lines(struct device *dev,
777 struct device_node *node,
778 const char *name)
779 {
780 unsigned int lines[LPASS_CPU_MAX_MI2S_LINES];
781 unsigned int sd_line_mask = 0;
782 int num_lines, i;
783
784 num_lines = of_property_read_variable_u32_array(node, name, lines, 0,
785 LPASS_CPU_MAX_MI2S_LINES);
786 if (num_lines < 0)
787 return LPAIF_I2SCTL_MODE_NONE;
788
789 for (i = 0; i < num_lines; i++)
790 sd_line_mask |= BIT(lines[i]);
791
792 switch (sd_line_mask) {
793 case LPASS_CPU_I2S_SD0_MASK:
794 return LPAIF_I2SCTL_MODE_SD0;
795 case LPASS_CPU_I2S_SD1_MASK:
796 return LPAIF_I2SCTL_MODE_SD1;
797 case LPASS_CPU_I2S_SD2_MASK:
798 return LPAIF_I2SCTL_MODE_SD2;
799 case LPASS_CPU_I2S_SD3_MASK:
800 return LPAIF_I2SCTL_MODE_SD3;
801 case LPASS_CPU_I2S_SD0_1_MASK:
802 return LPAIF_I2SCTL_MODE_QUAD01;
803 case LPASS_CPU_I2S_SD2_3_MASK:
804 return LPAIF_I2SCTL_MODE_QUAD23;
805 case LPASS_CPU_I2S_SD0_1_2_MASK:
806 return LPAIF_I2SCTL_MODE_6CH;
807 case LPASS_CPU_I2S_SD0_1_2_3_MASK:
808 return LPAIF_I2SCTL_MODE_8CH;
809 default:
810 dev_err(dev, "Unsupported SD line mask: %#x\n", sd_line_mask);
811 return LPAIF_I2SCTL_MODE_NONE;
812 }
813 }
814
of_lpass_cpu_parse_dai_data(struct device * dev,struct lpass_data * data)815 static void of_lpass_cpu_parse_dai_data(struct device *dev,
816 struct lpass_data *data)
817 {
818 struct device_node *node;
819 int ret, i, id;
820
821 /* Allow all channels by default for backwards compatibility */
822 for (i = 0; i < data->variant->num_dai; i++) {
823 id = data->variant->dai_driver[i].id;
824 data->mi2s_playback_sd_mode[id] = LPAIF_I2SCTL_MODE_8CH;
825 data->mi2s_capture_sd_mode[id] = LPAIF_I2SCTL_MODE_8CH;
826 }
827
828 for_each_child_of_node(dev->of_node, node) {
829 ret = of_property_read_u32(node, "reg", &id);
830 if (ret || id < 0) {
831 dev_err(dev, "valid dai id not found: %d\n", ret);
832 continue;
833 }
834 if (id == LPASS_DP_RX) {
835 data->hdmi_port_enable = 1;
836 } else {
837 data->mi2s_playback_sd_mode[id] =
838 of_lpass_cpu_parse_sd_lines(dev, node,
839 "qcom,playback-sd-lines");
840 data->mi2s_capture_sd_mode[id] =
841 of_lpass_cpu_parse_sd_lines(dev, node,
842 "qcom,capture-sd-lines");
843 }
844 }
845 }
846
asoc_qcom_lpass_cpu_platform_probe(struct platform_device * pdev)847 int asoc_qcom_lpass_cpu_platform_probe(struct platform_device *pdev)
848 {
849 struct lpass_data *drvdata;
850 struct device_node *dsp_of_node;
851 struct resource *res;
852 struct lpass_variant *variant;
853 struct device *dev = &pdev->dev;
854 const struct of_device_id *match;
855 int ret, i, dai_id;
856
857 dsp_of_node = of_parse_phandle(pdev->dev.of_node, "qcom,adsp", 0);
858 if (dsp_of_node) {
859 dev_err(dev, "DSP exists and holds audio resources\n");
860 of_node_put(dsp_of_node);
861 return -EBUSY;
862 }
863
864 drvdata = devm_kzalloc(dev, sizeof(struct lpass_data), GFP_KERNEL);
865 if (!drvdata)
866 return -ENOMEM;
867 platform_set_drvdata(pdev, drvdata);
868
869 match = of_match_device(dev->driver->of_match_table, dev);
870 if (!match || !match->data)
871 return -EINVAL;
872
873 drvdata->variant = (struct lpass_variant *)match->data;
874 variant = drvdata->variant;
875
876 of_lpass_cpu_parse_dai_data(dev, drvdata);
877
878 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "lpass-lpaif");
879
880 drvdata->lpaif = devm_ioremap_resource(dev, res);
881 if (IS_ERR((void const __force *)drvdata->lpaif)) {
882 dev_err(dev, "error mapping reg resource: %ld\n",
883 PTR_ERR((void const __force *)drvdata->lpaif));
884 return PTR_ERR((void const __force *)drvdata->lpaif);
885 }
886
887 lpass_cpu_regmap_config.max_register = LPAIF_WRDMAPER_REG(variant,
888 variant->wrdma_channels +
889 variant->wrdma_channel_start);
890
891 drvdata->lpaif_map = devm_regmap_init_mmio(dev, drvdata->lpaif,
892 &lpass_cpu_regmap_config);
893 if (IS_ERR(drvdata->lpaif_map)) {
894 dev_err(dev, "error initializing regmap: %ld\n",
895 PTR_ERR(drvdata->lpaif_map));
896 return PTR_ERR(drvdata->lpaif_map);
897 }
898
899 if (drvdata->hdmi_port_enable) {
900 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "lpass-hdmiif");
901
902 drvdata->hdmiif = devm_ioremap_resource(dev, res);
903 if (IS_ERR((void const __force *)drvdata->hdmiif)) {
904 dev_err(dev, "error mapping reg resource: %ld\n",
905 PTR_ERR((void const __force *)drvdata->hdmiif));
906 return PTR_ERR((void const __force *)drvdata->hdmiif);
907 }
908
909 lpass_hdmi_regmap_config.max_register = LPAIF_HDMI_RDMAPER_REG(variant,
910 variant->hdmi_rdma_channels - 1);
911 drvdata->hdmiif_map = devm_regmap_init_mmio(dev, drvdata->hdmiif,
912 &lpass_hdmi_regmap_config);
913 if (IS_ERR(drvdata->hdmiif_map)) {
914 dev_err(dev, "error initializing regmap: %ld\n",
915 PTR_ERR(drvdata->hdmiif_map));
916 return PTR_ERR(drvdata->hdmiif_map);
917 }
918 }
919
920 if (variant->init) {
921 ret = variant->init(pdev);
922 if (ret) {
923 dev_err(dev, "error initializing variant: %d\n", ret);
924 return ret;
925 }
926 }
927
928 for (i = 0; i < variant->num_dai; i++) {
929 dai_id = variant->dai_driver[i].id;
930 if (dai_id == LPASS_DP_RX)
931 continue;
932
933 drvdata->mi2s_osr_clk[dai_id] = devm_clk_get_optional(dev,
934 variant->dai_osr_clk_names[i]);
935 drvdata->mi2s_bit_clk[dai_id] = devm_clk_get(dev,
936 variant->dai_bit_clk_names[i]);
937 if (IS_ERR(drvdata->mi2s_bit_clk[dai_id])) {
938 dev_err(dev,
939 "error getting %s: %ld\n",
940 variant->dai_bit_clk_names[i],
941 PTR_ERR(drvdata->mi2s_bit_clk[dai_id]));
942 return PTR_ERR(drvdata->mi2s_bit_clk[dai_id]);
943 }
944 }
945
946 /* Allocation for i2sctl regmap fields */
947 drvdata->i2sctl = devm_kzalloc(&pdev->dev, sizeof(struct lpaif_i2sctl),
948 GFP_KERNEL);
949
950 /* Initialize bitfields for dai I2SCTL register */
951 ret = lpass_cpu_init_i2sctl_bitfields(dev, drvdata->i2sctl,
952 drvdata->lpaif_map);
953 if (ret) {
954 dev_err(dev, "error init i2sctl field: %d\n", ret);
955 return ret;
956 }
957
958 if (drvdata->hdmi_port_enable) {
959 ret = lpass_hdmi_init_bitfields(dev, drvdata->hdmiif_map);
960 if (ret) {
961 dev_err(dev, "%s error hdmi init failed\n", __func__);
962 return ret;
963 }
964 }
965 ret = devm_snd_soc_register_component(dev,
966 &lpass_cpu_comp_driver,
967 variant->dai_driver,
968 variant->num_dai);
969 if (ret) {
970 dev_err(dev, "error registering cpu driver: %d\n", ret);
971 goto err;
972 }
973
974 ret = asoc_qcom_lpass_platform_register(pdev);
975 if (ret) {
976 dev_err(dev, "error registering platform driver: %d\n", ret);
977 goto err;
978 }
979
980 err:
981 return ret;
982 }
983 EXPORT_SYMBOL_GPL(asoc_qcom_lpass_cpu_platform_probe);
984
asoc_qcom_lpass_cpu_platform_remove(struct platform_device * pdev)985 int asoc_qcom_lpass_cpu_platform_remove(struct platform_device *pdev)
986 {
987 struct lpass_data *drvdata = platform_get_drvdata(pdev);
988
989 if (drvdata->variant->exit)
990 drvdata->variant->exit(pdev);
991
992
993 return 0;
994 }
995 EXPORT_SYMBOL_GPL(asoc_qcom_lpass_cpu_platform_remove);
996
997 MODULE_DESCRIPTION("QTi LPASS CPU Driver");
998 MODULE_LICENSE("GPL v2");
999