1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * TXx9 ACLC AC97 driver
4 *
5 * Copyright (C) 2009 Atsushi Nemoto
6 *
7 * Based on RBTX49xx patch from CELF patch archive.
8 * (C) Copyright TOSHIBA CORPORATION 2004-2006
9 */
10
11 #include <linux/init.h>
12 #include <linux/module.h>
13 #include <linux/delay.h>
14 #include <linux/interrupt.h>
15 #include <linux/io.h>
16 #include <linux/gfp.h>
17 #include <asm/mach-tx39xx/ioremap.h> /* for TXX9_DIRECTMAP_BASE */
18 #include <sound/core.h>
19 #include <sound/pcm.h>
20 #include <sound/soc.h>
21 #include "txx9aclc.h"
22
23 #define AC97_DIR \
24 (SND_SOC_DAIDIR_PLAYBACK | SND_SOC_DAIDIR_CAPTURE)
25
26 #define AC97_RATES \
27 SNDRV_PCM_RATE_8000_48000
28
29 #ifdef __BIG_ENDIAN
30 #define AC97_FMTS SNDRV_PCM_FMTBIT_S16_BE
31 #else
32 #define AC97_FMTS SNDRV_PCM_FMTBIT_S16_LE
33 #endif
34
35 static DECLARE_WAIT_QUEUE_HEAD(ac97_waitq);
36
37 /* REVISIT: How to find txx9aclc_drvdata from snd_ac97? */
38 static struct txx9aclc_plat_drvdata *txx9aclc_drvdata;
39
txx9aclc_regready(struct txx9aclc_plat_drvdata * drvdata)40 static int txx9aclc_regready(struct txx9aclc_plat_drvdata *drvdata)
41 {
42 return __raw_readl(drvdata->base + ACINTSTS) & ACINT_REGACCRDY;
43 }
44
45 /* AC97 controller reads codec register */
txx9aclc_ac97_read(struct snd_ac97 * ac97,unsigned short reg)46 static unsigned short txx9aclc_ac97_read(struct snd_ac97 *ac97,
47 unsigned short reg)
48 {
49 struct txx9aclc_plat_drvdata *drvdata = txx9aclc_drvdata;
50 void __iomem *base = drvdata->base;
51 u32 dat;
52
53 if (!(__raw_readl(base + ACINTSTS) & ACINT_CODECRDY(ac97->num)))
54 return 0xffff;
55 reg |= ac97->num << 7;
56 dat = (reg << ACREGACC_REG_SHIFT) | ACREGACC_READ;
57 __raw_writel(dat, base + ACREGACC);
58 __raw_writel(ACINT_REGACCRDY, base + ACINTEN);
59 if (!wait_event_timeout(ac97_waitq, txx9aclc_regready(txx9aclc_drvdata), HZ)) {
60 __raw_writel(ACINT_REGACCRDY, base + ACINTDIS);
61 printk(KERN_ERR "ac97 read timeout (reg %#x)\n", reg);
62 dat = 0xffff;
63 goto done;
64 }
65 dat = __raw_readl(base + ACREGACC);
66 if (((dat >> ACREGACC_REG_SHIFT) & 0xff) != reg) {
67 printk(KERN_ERR "reg mismatch %x with %x\n",
68 dat, reg);
69 dat = 0xffff;
70 goto done;
71 }
72 dat = (dat >> ACREGACC_DAT_SHIFT) & 0xffff;
73 done:
74 __raw_writel(ACINT_REGACCRDY, base + ACINTDIS);
75 return dat;
76 }
77
78 /* AC97 controller writes to codec register */
txx9aclc_ac97_write(struct snd_ac97 * ac97,unsigned short reg,unsigned short val)79 static void txx9aclc_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
80 unsigned short val)
81 {
82 struct txx9aclc_plat_drvdata *drvdata = txx9aclc_drvdata;
83 void __iomem *base = drvdata->base;
84
85 __raw_writel(((reg | (ac97->num << 7)) << ACREGACC_REG_SHIFT) |
86 (val << ACREGACC_DAT_SHIFT),
87 base + ACREGACC);
88 __raw_writel(ACINT_REGACCRDY, base + ACINTEN);
89 if (!wait_event_timeout(ac97_waitq, txx9aclc_regready(txx9aclc_drvdata), HZ)) {
90 printk(KERN_ERR
91 "ac97 write timeout (reg %#x)\n", reg);
92 }
93 __raw_writel(ACINT_REGACCRDY, base + ACINTDIS);
94 }
95
txx9aclc_ac97_cold_reset(struct snd_ac97 * ac97)96 static void txx9aclc_ac97_cold_reset(struct snd_ac97 *ac97)
97 {
98 struct txx9aclc_plat_drvdata *drvdata = txx9aclc_drvdata;
99 void __iomem *base = drvdata->base;
100 u32 ready = ACINT_CODECRDY(ac97->num) | ACINT_REGACCRDY;
101
102 __raw_writel(ACCTL_ENLINK, base + ACCTLDIS);
103 udelay(1);
104 __raw_writel(ACCTL_ENLINK, base + ACCTLEN);
105 /* wait for primary codec ready status */
106 __raw_writel(ready, base + ACINTEN);
107 if (!wait_event_timeout(ac97_waitq,
108 (__raw_readl(base + ACINTSTS) & ready) == ready,
109 HZ)) {
110 dev_err(&ac97->dev, "primary codec is not ready "
111 "(status %#x)\n",
112 __raw_readl(base + ACINTSTS));
113 }
114 __raw_writel(ACINT_REGACCRDY, base + ACINTSTS);
115 __raw_writel(ready, base + ACINTDIS);
116 }
117
118 /* AC97 controller operations */
119 static struct snd_ac97_bus_ops txx9aclc_ac97_ops = {
120 .read = txx9aclc_ac97_read,
121 .write = txx9aclc_ac97_write,
122 .reset = txx9aclc_ac97_cold_reset,
123 };
124
txx9aclc_ac97_irq(int irq,void * dev_id)125 static irqreturn_t txx9aclc_ac97_irq(int irq, void *dev_id)
126 {
127 struct txx9aclc_plat_drvdata *drvdata = dev_id;
128 void __iomem *base = drvdata->base;
129
130 __raw_writel(__raw_readl(base + ACINTMSTS), base + ACINTDIS);
131 wake_up(&ac97_waitq);
132 return IRQ_HANDLED;
133 }
134
txx9aclc_ac97_probe(struct snd_soc_dai * dai)135 static int txx9aclc_ac97_probe(struct snd_soc_dai *dai)
136 {
137 txx9aclc_drvdata = snd_soc_dai_get_drvdata(dai);
138 return 0;
139 }
140
txx9aclc_ac97_remove(struct snd_soc_dai * dai)141 static int txx9aclc_ac97_remove(struct snd_soc_dai *dai)
142 {
143 struct txx9aclc_plat_drvdata *drvdata = snd_soc_dai_get_drvdata(dai);
144
145 /* disable AC-link */
146 __raw_writel(ACCTL_ENLINK, drvdata->base + ACCTLDIS);
147 txx9aclc_drvdata = NULL;
148 return 0;
149 }
150
151 static struct snd_soc_dai_driver txx9aclc_ac97_dai = {
152 .probe = txx9aclc_ac97_probe,
153 .remove = txx9aclc_ac97_remove,
154 .playback = {
155 .rates = AC97_RATES,
156 .formats = AC97_FMTS,
157 .channels_min = 2,
158 .channels_max = 2,
159 },
160 .capture = {
161 .rates = AC97_RATES,
162 .formats = AC97_FMTS,
163 .channels_min = 2,
164 .channels_max = 2,
165 },
166 };
167
168 static const struct snd_soc_component_driver txx9aclc_ac97_component = {
169 .name = "txx9aclc-ac97",
170 };
171
txx9aclc_ac97_dev_probe(struct platform_device * pdev)172 static int txx9aclc_ac97_dev_probe(struct platform_device *pdev)
173 {
174 struct txx9aclc_plat_drvdata *drvdata;
175 struct resource *r;
176 int err;
177 int irq;
178
179 irq = platform_get_irq(pdev, 0);
180 if (irq < 0)
181 return irq;
182
183 drvdata = devm_kzalloc(&pdev->dev, sizeof(*drvdata), GFP_KERNEL);
184 if (!drvdata)
185 return -ENOMEM;
186
187 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
188 drvdata->base = devm_ioremap_resource(&pdev->dev, r);
189 if (IS_ERR(drvdata->base))
190 return PTR_ERR(drvdata->base);
191
192 platform_set_drvdata(pdev, drvdata);
193 drvdata->physbase = r->start;
194 if (sizeof(drvdata->physbase) > sizeof(r->start) &&
195 r->start >= TXX9_DIRECTMAP_BASE &&
196 r->start < TXX9_DIRECTMAP_BASE + 0x400000)
197 drvdata->physbase |= 0xf00000000ull;
198 err = devm_request_irq(&pdev->dev, irq, txx9aclc_ac97_irq,
199 0, dev_name(&pdev->dev), drvdata);
200 if (err < 0)
201 return err;
202
203 err = snd_soc_set_ac97_ops(&txx9aclc_ac97_ops);
204 if (err < 0)
205 return err;
206
207 return devm_snd_soc_register_component(&pdev->dev, &txx9aclc_ac97_component,
208 &txx9aclc_ac97_dai, 1);
209 }
210
txx9aclc_ac97_dev_remove(struct platform_device * pdev)211 static int txx9aclc_ac97_dev_remove(struct platform_device *pdev)
212 {
213 snd_soc_set_ac97_ops(NULL);
214 return 0;
215 }
216
217 static struct platform_driver txx9aclc_ac97_driver = {
218 .probe = txx9aclc_ac97_dev_probe,
219 .remove = txx9aclc_ac97_dev_remove,
220 .driver = {
221 .name = "txx9aclc-ac97",
222 },
223 };
224
225 module_platform_driver(txx9aclc_ac97_driver);
226
227 MODULE_AUTHOR("Atsushi Nemoto <anemo@mba.ocn.ne.jp>");
228 MODULE_DESCRIPTION("TXx9 ACLC AC97 driver");
229 MODULE_LICENSE("GPL");
230 MODULE_ALIAS("platform:txx9aclc-ac97");
231