1 /* 2 * This header was generated from the Linux kernel headers by update_headers.py, 3 * to provide necessary information from kernel to userspace, such as constants, 4 * structures, and macros, and thus, contains no copyrightable information. 5 */ 6 #ifndef __MSM_DRM_H__ 7 #define __MSM_DRM_H__ 8 #include "drm.h" 9 #if defined(__cplusplus) 10 extern "C" { 11 #endif 12 #define MSM_PIPE_NONE 0x00 13 #define MSM_PIPE_2D0 0x01 14 #define MSM_PIPE_2D1 0x02 15 #define MSM_PIPE_3D0 0x10 16 #define MSM_PIPE_ID_MASK 0xffff 17 #define MSM_PIPE_ID(x) ((x) & MSM_PIPE_ID_MASK) 18 #define MSM_PIPE_FLAGS(x) ((x) & ~MSM_PIPE_ID_MASK) 19 struct drm_msm_timespec { 20 __s64 tv_sec; 21 __s64 tv_nsec; 22 }; 23 #define MSM_PARAM_GPU_ID 0x01 24 #define MSM_PARAM_GMEM_SIZE 0x02 25 #define MSM_PARAM_CHIP_ID 0x03 26 #define MSM_PARAM_MAX_FREQ 0x04 27 #define MSM_PARAM_TIMESTAMP 0x05 28 #define MSM_PARAM_GMEM_BASE 0x06 29 #define MSM_PARAM_NR_RINGS 0x07 30 struct drm_msm_param { 31 __u32 pipe; 32 __u32 param; 33 __u64 value; 34 }; 35 #define MSM_BO_SCANOUT 0x00000001 36 #define MSM_BO_GPU_READONLY 0x00000002 37 #define MSM_BO_CACHE_MASK 0x000f0000 38 #define MSM_BO_CACHED 0x00010000 39 #define MSM_BO_WC 0x00020000 40 #define MSM_BO_UNCACHED 0x00040000 41 #define MSM_BO_FLAGS (MSM_BO_SCANOUT | \ 42 MSM_BO_GPU_READONLY | \ 43 MSM_BO_CACHED | \ 44 MSM_BO_WC | \ 45 MSM_BO_UNCACHED) 46 struct drm_msm_gem_new { 47 __u64 size; 48 __u32 flags; 49 __u32 handle; 50 }; 51 #define MSM_INFO_IOVA 0x01 52 #define MSM_INFO_FLAGS (MSM_INFO_IOVA) 53 struct drm_msm_gem_info { 54 __u32 handle; 55 __u32 flags; 56 __u64 offset; 57 }; 58 #define MSM_PREP_READ 0x01 59 #define MSM_PREP_WRITE 0x02 60 #define MSM_PREP_NOSYNC 0x04 61 #define MSM_PREP_FLAGS (MSM_PREP_READ | MSM_PREP_WRITE | MSM_PREP_NOSYNC) 62 struct drm_msm_gem_cpu_prep { 63 __u32 handle; 64 __u32 op; 65 struct drm_msm_timespec timeout; 66 }; 67 struct drm_msm_gem_cpu_fini { 68 __u32 handle; 69 }; 70 struct drm_msm_gem_submit_reloc { 71 __u32 submit_offset; 72 __u32 or; 73 __s32 shift; 74 __u32 reloc_idx; 75 __u64 reloc_offset; 76 }; 77 #define MSM_SUBMIT_CMD_BUF 0x0001 78 #define MSM_SUBMIT_CMD_IB_TARGET_BUF 0x0002 79 #define MSM_SUBMIT_CMD_CTX_RESTORE_BUF 0x0003 80 struct drm_msm_gem_submit_cmd { 81 __u32 type; 82 __u32 submit_idx; 83 __u32 submit_offset; 84 __u32 size; 85 __u32 pad; 86 __u32 nr_relocs; 87 __u64 relocs; 88 }; 89 #define MSM_SUBMIT_BO_READ 0x0001 90 #define MSM_SUBMIT_BO_WRITE 0x0002 91 #define MSM_SUBMIT_BO_FLAGS (MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE) 92 struct drm_msm_gem_submit_bo { 93 __u32 flags; 94 __u32 handle; 95 __u64 presumed; 96 }; 97 #define MSM_SUBMIT_NO_IMPLICIT 0x80000000 98 #define MSM_SUBMIT_FENCE_FD_IN 0x40000000 99 #define MSM_SUBMIT_FENCE_FD_OUT 0x20000000 100 #define MSM_SUBMIT_SUDO 0x10000000 101 #define MSM_SUBMIT_FLAGS ( \ 102 MSM_SUBMIT_NO_IMPLICIT | \ 103 MSM_SUBMIT_FENCE_FD_IN | \ 104 MSM_SUBMIT_FENCE_FD_OUT | \ 105 MSM_SUBMIT_SUDO | \ 106 0) 107 struct drm_msm_gem_submit { 108 __u32 flags; 109 __u32 fence; 110 __u32 nr_bos; 111 __u32 nr_cmds; 112 __u64 bos; 113 __u64 cmds; 114 __s32 fence_fd; 115 __u32 queueid; 116 }; 117 struct drm_msm_wait_fence { 118 __u32 fence; 119 __u32 pad; 120 struct drm_msm_timespec timeout; 121 __u32 queueid; 122 }; 123 #define MSM_MADV_WILLNEED 0 124 #define MSM_MADV_DONTNEED 1 125 #define __MSM_MADV_PURGED 2 126 struct drm_msm_gem_madvise { 127 __u32 handle; 128 __u32 madv; 129 __u32 retained; 130 }; 131 #define MSM_SUBMITQUEUE_FLAGS (0) 132 struct drm_msm_submitqueue { 133 __u32 flags; 134 __u32 prio; 135 __u32 id; 136 }; 137 #define DRM_MSM_GET_PARAM 0x00 138 #define DRM_MSM_GEM_NEW 0x02 139 #define DRM_MSM_GEM_INFO 0x03 140 #define DRM_MSM_GEM_CPU_PREP 0x04 141 #define DRM_MSM_GEM_CPU_FINI 0x05 142 #define DRM_MSM_GEM_SUBMIT 0x06 143 #define DRM_MSM_WAIT_FENCE 0x07 144 #define DRM_MSM_GEM_MADVISE 0x08 145 #define DRM_MSM_SUBMITQUEUE_NEW 0x0A 146 #define DRM_MSM_SUBMITQUEUE_CLOSE 0x0B 147 #define DRM_IOCTL_MSM_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GET_PARAM, struct drm_msm_param) 148 #define DRM_IOCTL_MSM_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_NEW, struct drm_msm_gem_new) 149 #define DRM_IOCTL_MSM_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_INFO, struct drm_msm_gem_info) 150 #define DRM_IOCTL_MSM_GEM_CPU_PREP DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_PREP, struct drm_msm_gem_cpu_prep) 151 #define DRM_IOCTL_MSM_GEM_CPU_FINI DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_FINI, struct drm_msm_gem_cpu_fini) 152 #define DRM_IOCTL_MSM_GEM_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_SUBMIT, struct drm_msm_gem_submit) 153 #define DRM_IOCTL_MSM_WAIT_FENCE DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_WAIT_FENCE, struct drm_msm_wait_fence) 154 #define DRM_IOCTL_MSM_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_MADVISE, struct drm_msm_gem_madvise) 155 #define DRM_IOCTL_MSM_SUBMITQUEUE_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_NEW, struct drm_msm_submitqueue) 156 #define DRM_IOCTL_MSM_SUBMITQUEUE_CLOSE DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_CLOSE, __u32) 157 #if defined(__cplusplus) 158 } 159 #endif 160 #endif 161