1 /*
2 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
3 * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without modification,
6 * are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice, this list of
9 * conditions and the following disclaimer.
10 *
11 * 2. Redistributions in binary form must reproduce the above copyright notice, this list
12 * of conditions and the following disclaimer in the documentation and/or other materials
13 * provided with the distribution.
14 *
15 * 3. Neither the name of the copyright holder nor the names of its contributors may be used
16 * to endorse or promote products derived from this software without specific prior written
17 * permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
20 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
21 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
23 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
24 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
25 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
26 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
27 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
28 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
29 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 #include "los_timer.h"
33 #include "los_config.h"
34 #include "los_arch_context.h"
35 #include "los_arch_interrupt.h"
36 #include "los_reg.h"
37
38 #define OS_TIMER_CLKDIV_POS 3
39 #define OS_TIMER_CLKDIV_MASK 7
40 #define OS_TIMER_INT_POS 7
41 #define OS_TIMER_INT_MASK 7
42 #define OS_TIMER_IRQ_NUM 8
43 #define OS_TIMER_ENABLE (1U << 0)
44 #define OS_TIMER_32K_CLK_BIT (1U << 21)
45 #define OS_TIMER_CNT_READ_BIT (1U << 0)
46
47 #define OS_TIMER_REG_BASE 0x00802A40UL
48 #define OS_TIMER_CLK_PWD_ADDR 0x00802008UL
49 #define OS_TIMER_PERIOD_REG_ADDR (OS_TIMER_REG_BASE)
50 #define OS_TIMER_CTL_REG_ADDR (OS_TIMER_REG_BASE + 12)
51 #define OS_TIMER_READ_CTL_ADDR (OS_TIMER_REG_BASE + 16)
52 #define OS_TIMER_READ_VAL_ADDR (OS_TIMER_REG_BASE + 20)
53
54 STATIC UINT32 SysTickStart(HWI_PROC_FUNC handler);
55 STATIC UINT64 SysTickReload(UINT64 nextResponseTime);
56 STATIC UINT64 SysTickCycleGet(UINT32 *period);
57 STATIC VOID SysTickLock(VOID);
58 STATIC VOID SysTickUnlock(VOID);
59
60 STATIC ArchTickTimer g_archTickTimer = {
61 .freq = 0,
62 .irqNum = OS_TIMER_IRQ_NUM,
63 .periodMax = LOSCFG_BASE_CORE_TICK_RESPONSE_MAX,
64 .init = SysTickStart,
65 .getCycle = SysTickCycleGet,
66 .reload = SysTickReload,
67 .lock = SysTickLock,
68 .unlock = SysTickUnlock,
69 .tickHandler = NULL,
70 };
71
SysTickStart(HWI_PROC_FUNC handler)72 STATIC UINT32 SysTickStart(HWI_PROC_FUNC handler)
73 {
74 UINT32 intSave = LOS_IntLock();
75 UINT32 value;
76
77 ArchTickTimer *tick = &g_archTickTimer;
78 tick->freq = OS_SYS_CLOCK;
79
80 READ_UINT32(value, OS_TIMER_CLK_PWD_ADDR);
81 value &= ~(OS_TIMER_32K_CLK_BIT);
82 WRITE_UINT32(value, OS_TIMER_CLK_PWD_ADDR);
83
84 value = LOSCFG_BASE_CORE_TICK_RESPONSE_MAX;
85 WRITE_UINT32(value, OS_TIMER_PERIOD_REG_ADDR);
86
87 READ_UINT32(value, OS_TIMER_CTL_REG_ADDR);
88 value &= ~(OS_TIMER_CLKDIV_MASK << OS_TIMER_CLKDIV_POS); // The default is 1, and the clock does not divide.
89 value &= ~(OS_TIMER_INT_MASK << OS_TIMER_INT_POS); // Clearing interruption.
90 value |= 0x1 << OS_TIMER_INT_POS;
91 value |= OS_TIMER_ENABLE; // Enable timer.
92 WRITE_UINT32(value, OS_TIMER_CTL_REG_ADDR);
93
94 (VOID)ArchHwiCreate(OS_TIMER_IRQ_NUM, 0, 0, (HWI_PROC_FUNC)handler, 0);
95 LOS_IntRestore(intSave);
96
97 return LOS_OK;
98 }
99
SysTickClockIrqClear(VOID)100 STATIC VOID SysTickClockIrqClear(VOID)
101 {
102 UINT32 mask = OS_TIMER_INT_MASK << OS_TIMER_INT_POS;
103 UINT32 status;
104
105 do {
106 WRITE_UINT32(mask, OS_TIMER_CTL_REG_ADDR);
107 READ_UINT32(status, OS_TIMER_CTL_REG_ADDR);
108 } while (status & mask);
109 }
110
SysTickReload(UINT64 nextResponseTime)111 STATIC UINT64 SysTickReload(UINT64 nextResponseTime)
112 {
113 if (nextResponseTime > g_archTickTimer.periodMax) {
114 nextResponseTime = g_archTickTimer.periodMax;
115 }
116
117 SysTickLock();
118 WRITE_UINT32((UINT32)nextResponseTime, OS_TIMER_PERIOD_REG_ADDR);
119 SysTickClockIrqClear();
120 SysTickUnlock();
121 return nextResponseTime;
122 }
123
SysTickCycleGet(UINT32 * period)124 STATIC UINT64 SysTickCycleGet(UINT32 *period)
125 {
126 UINT32 val;
127
128 READ_UINT32(*period, OS_TIMER_PERIOD_REG_ADDR);
129
130 WRITE_UINT32(OS_TIMER_CNT_READ_BIT, OS_TIMER_READ_CTL_ADDR);
131 do {
132 READ_UINT32(val, OS_TIMER_READ_CTL_ADDR);
133 } while (val & OS_TIMER_CNT_READ_BIT); // Wait for the setting to take effect.
134
135 READ_UINT32(val, OS_TIMER_READ_VAL_ADDR);
136
137 return (UINT64)val;
138 }
139
SysTickLock(VOID)140 STATIC VOID SysTickLock(VOID)
141 {
142 UINT32 value;
143
144 READ_UINT32(value, OS_TIMER_CTL_REG_ADDR);
145 value &= ~OS_TIMER_ENABLE;
146 value &= ~(OS_TIMER_INT_MASK << OS_TIMER_INT_POS);
147 value |= 0x1 << OS_TIMER_INT_POS;
148 WRITE_UINT32(value, OS_TIMER_CTL_REG_ADDR);
149 }
150
SysTickUnlock(VOID)151 STATIC VOID SysTickUnlock(VOID)
152 {
153 UINT32 value;
154
155 READ_UINT32(value, OS_TIMER_CTL_REG_ADDR);
156 value |= OS_TIMER_ENABLE;
157 value &= ~(OS_TIMER_INT_MASK << OS_TIMER_INT_POS);
158 value |= 0x1 << OS_TIMER_INT_POS;
159 WRITE_UINT32(value, OS_TIMER_CTL_REG_ADDR);
160 }
161
ArchSysTickTimerGet(VOID)162 ArchTickTimer *ArchSysTickTimerGet(VOID)
163 {
164 return &g_archTickTimer;
165 }
166
ArchEnterSleep(VOID)167 UINT32 ArchEnterSleep(VOID)
168 {
169 dsb();
170 wfi();
171 isb();
172
173 return LOS_OK;
174 }
175