1; 2; Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved. 3; Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved. 4; 5; Redistribution and use in source and binary forms, with or without modification, 6; are permitted provided that the following conditions are met: 7; 8; 1. Redistributions of source code must retain the above copyright notice, this list of 9; conditions and the following disclaimer. 10; 11; 2. Redistributions in binary form must reproduce the above copyright notice, this list 12; of conditions and the following disclaimer in the documentation and/or other materials 13; provided with the distribution. 14; 15; 3. Neither the name of the copyright holder nor the names of its contributors may be used 16; to endorse or promote products derived from this software without specific prior written 17; permission. 18; 19; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 20; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 21; THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22; PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 23; CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 24; EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 25; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 26; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 27; WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 28; OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 29; ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30; 31 32 PRESERVE8 33 34 EXPORT ArchIntLock 35 EXPORT ArchIntUnLock 36 EXPORT ArchIntRestore 37 EXPORT HalStartToRun 38 EXPORT ArchTaskSchedule 39 EXPORT HalPendSV 40 IMPORT OsSchedTaskSwitch 41 IMPORT OsSignalTaskContextRestore 42 IMPORT g_losTask 43 44OS_FPU_CPACR EQU 0xE000ED88 45OS_FPU_CPACR_ENABLE EQU 0x00F00000 46OS_NVIC_INT_CTRL EQU 0xE000ED04 47OS_NVIC_SYSPRI2 EQU 0xE000ED20 48OS_NVIC_PENDSV_PRI EQU 0xF0F00000 49OS_NVIC_PENDSVSET EQU 0x10000000 50OS_TASK_STATUS_RUNNING EQU 0x0010 51 52 SECTION .text:CODE(2) 53 THUMB 54 REQUIRE8 55 56 MACRO SIGNAL_CONTEXT_RESTORE 57 PUSH {R12, LR} 58 BLX OsSignalTaskContextRestore 59 POP {R12, LR} 60 CMP R0, #0 61 MOV R1, R0 62 BNE SignalContextRestore 63 ENDM 64 65HalStartToRun 66 LDR R4, =OS_NVIC_SYSPRI2 67 LDR R5, =OS_NVIC_PENDSV_PRI 68 STR R5, [R4] 69 70 MOV R0, #2 71 MSR CONTROL, R0 72 73 LDR R1, =g_losTask 74 LDR R0, [R1, #4] 75 LDR R12, [R0] 76 77 LDR.W R1, =OS_FPU_CPACR 78 LDR R1, [R1] 79 AND R1, R1, #OS_FPU_CPACR_ENABLE 80 CMP R1, #OS_FPU_CPACR_ENABLE 81 BNE __DisabledFPU 82 ADD R12, R12, #100 83 84 LDMFD R12!, {R0-R7} 85 ADD R12, R12, #72 86 MSR PSP, R12 87 VPUSH S0; 88 VPOP S0; 89 MOV LR, R5 90 CPSIE I 91 BX R6 92 93__DisabledFPU 94 ADD R12, R12, #36 95 96 LDMFD R12!, {R0-R7} 97 MSR PSP, R12 98 MOV LR, R5 99 CPSIE I 100 BX R6 101 102 103ArchIntLock 104 MRS R0, PRIMASK 105 CPSID I 106 BX LR 107 108ArchIntUnLock 109 MRS R0, PRIMASK 110 CPSIE I 111 BX LR 112 113ArchIntRestore 114 MSR PRIMASK, R0 115 BX LR 116 117ArchTaskSchedule 118 LDR R0, =OS_NVIC_INT_CTRL 119 LDR R1, =OS_NVIC_PENDSVSET 120 STR R1, [R0] 121 DSB 122 ISB 123 BX LR 124 125HalPendSV 126 MRS R12, PRIMASK 127 CPSID I 128 129HalTaskSwitch 130 SIGNAL_CONTEXT_RESTORE 131 132 PUSH {R12, LR} 133 BLX OsSchedTaskSwitch 134 POP {R12, LR} 135 CMP R0, #0 136 MOV R0, LR 137 BNE TaskContextSwitch 138 MSR PRIMASK, R12 139 BX LR 140 141TaskContextSwitch 142 MOV LR, R0 143 144 MRS R0, PSP 145 STMFD R0!, {R4-R12} 146 LDR.W R3, =OS_FPU_CPACR 147 LDR R3, [R3] 148 AND R3, R3, #OS_FPU_CPACR_ENABLE 149 CMP R3, #OS_FPU_CPACR_ENABLE 150 BNE __DisabledFPU1 151 VSTMDB R0!, {D8-D15} 152 153__DisabledFPU1 154 LDR R5, =g_losTask 155 LDR R6, [R5] 156 STR R0, [R6] 157 158 LDR R0, [R5, #4] 159 STR R0, [R5] 160 LDR R1, [R0] 161 162SignalContextRestore 163 LDR.W R3, =OS_FPU_CPACR 164 LDR R3, [R3] 165 AND R3, R3, #OS_FPU_CPACR_ENABLE 166 CMP R3, #OS_FPU_CPACR_ENABLE 167 BNE __DisabledFPU2 168 VLDMIA R1!, {D8-D15} 169 170__DisabledFPU2 171 LDMFD R1!, {R4-R12} 172 MSR PSP, R1 173 174 MSR PRIMASK, R12 175 BX LR 176 177 END 178