1 /*
2 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
3 * Copyright (c) 2020-2023 Huawei Device Co., Ltd. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without modification,
6 * are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice, this list of
9 * conditions and the following disclaimer.
10 *
11 * 2. Redistributions in binary form must reproduce the above copyright notice, this list
12 * of conditions and the following disclaimer in the documentation and/or other materials
13 * provided with the distribution.
14 *
15 * 3. Neither the name of the copyright holder nor the names of its contributors may be used
16 * to endorse or promote products derived from this software without specific prior written
17 * permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
20 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
21 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
23 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
24 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
25 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
26 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
27 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
28 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
29 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 #include <stdarg.h>
33 #include "securec.h"
34 #include "los_context.h"
35 #include "los_arch_interrupt.h"
36 #include "los_hook.h"
37 #include "los_task.h"
38 #include "los_sched.h"
39 #include "los_memory.h"
40 #include "los_membox.h"
41 #if (LOSCFG_CPUP_INCLUDE_IRQ == 1)
42 #include "los_cpup.h"
43 #endif
44
45 #pragma location = ".data.vector"
46 #pragma data_alignment = LOSCFG_ARCH_HWI_VECTOR_ALIGN
47
48 /* ****************************************************************************
49 Function : HwiNumGet
50 Description : Get an interrupt number
51 Input : None
52 Output : None
53 Return : Interrupt Indexes number
54 **************************************************************************** */
HwiNumGet(VOID)55 STATIC UINT32 HwiNumGet(VOID)
56 {
57 return __get_IPSR();
58 }
59
HwiUnmask(HWI_HANDLE_T hwiNum)60 STATIC UINT32 HwiUnmask(HWI_HANDLE_T hwiNum)
61 {
62 NVIC_EnableIRQ((IRQn_Type)hwiNum);
63 return LOS_OK;
64 }
65
HwiMask(HWI_HANDLE_T hwiNum)66 STATIC UINT32 HwiMask(HWI_HANDLE_T hwiNum)
67 {
68 NVIC_DisableIRQ((IRQn_Type)hwiNum);
69 return LOS_OK;
70 }
71
HwiSetPriority(HWI_HANDLE_T hwiNum,UINT8 priority)72 STATIC UINT32 HwiSetPriority(HWI_HANDLE_T hwiNum, UINT8 priority)
73 {
74 NVIC_SetPriority((IRQn_Type)hwiNum, priority);
75 return LOS_OK;
76 }
77
HwiPending(HWI_HANDLE_T hwiNum)78 STATIC UINT32 HwiPending(HWI_HANDLE_T hwiNum)
79 {
80 NVIC_SetPendingIRQ((IRQn_Type)hwiNum);
81 return LOS_OK;
82 }
83
HwiClear(HWI_HANDLE_T hwiNum)84 STATIC UINT32 HwiClear(HWI_HANDLE_T hwiNum)
85 {
86 NVIC_ClearPendingIRQ((IRQn_Type)hwiNum);
87 return LOS_OK;
88 }
89
HwiCreate(HWI_HANDLE_T hwiNum,HWI_PRIOR_T hwiPrio)90 STATIC UINT32 HwiCreate(HWI_HANDLE_T hwiNum, HWI_PRIOR_T hwiPrio)
91 {
92 HwiSetPriority(hwiNum, hwiPrio);
93 HwiUnmask(hwiNum);
94 return LOS_OK;
95 }
96
97 STATIC HwiControllerOps g_archHwiOps = {
98 .enableIrq = HwiUnmask,
99 .disableIrq = HwiMask,
100 .setIrqPriority = HwiSetPriority,
101 .getCurIrqNum = HwiNumGet,
102 .triggerIrq = HwiPending,
103 .clearIrq = HwiClear,
104 .createIrq = HwiCreate,
105 };
106
ArchIntOpsGet(VOID)107 HwiControllerOps *ArchIntOpsGet(VOID)
108 {
109 return &g_archHwiOps;
110 }
111
112 /* ****************************************************************************
113 Function : HalInterrupt
114 Description : Hardware interrupt entry function
115 Input : None
116 Output : None
117 Return : None
118 **************************************************************************** */
HalInterrupt(VOID)119 LITE_OS_SEC_TEXT VOID HalInterrupt(VOID)
120 {
121 UINT32 hwiIndex;
122 UINT32 intSave;
123
124 #if (LOSCFG_KERNEL_RUNSTOP == 1)
125 SCB->SCR &= (UINT32) ~((UINT32)SCB_SCR_SLEEPDEEP_Msk);
126 #endif
127
128 intSave = LOS_IntLock();
129 g_intCount++;
130 LOS_IntRestore(intSave);
131
132 hwiIndex = HwiNumGet();
133
134 OsHookCall(LOS_HOOK_TYPE_ISR_ENTER, hwiIndex);
135 #if (LOSCFG_CPUP_INCLUDE_IRQ == 1)
136 OsCpupIrqStart(hwiIndex);
137 #endif
138
139 HalPreInterruptHandler(hwiIndex);
140
141 #if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
142 if (g_hwiHandlerForm[hwiIndex].pfnHandler != 0) {
143 g_hwiHandlerForm[hwiIndex].pfnHandler((VOID *)g_hwiHandlerForm[hwiIndex].pParm);
144 }
145 #else
146 if (g_hwiHandlerForm[hwiIndex] != 0) {
147 g_hwiHandlerForm[hwiIndex]();
148 }
149 #endif
150
151 #if (LOSCFG_DEBUG_TOOLS == 1)
152 ++g_hwiFormCnt[hwiIndex];
153 #endif
154
155 HalAftInterruptHandler(hwiIndex);
156
157 #if (LOSCFG_CPUP_INCLUDE_IRQ == 1)
158 OsCpupIrqEnd(hwiIndex);
159 #endif
160
161 OsHookCall(LOS_HOOK_TYPE_ISR_EXIT, hwiIndex);
162
163 intSave = LOS_IntLock();
164 g_intCount--;
165 LOS_IntRestore(intSave);
166 }
167
168 #define FAULT_STATUS_REG_BIT 32
169 #define USGFAULT (1 << 18)
170 #define BUSFAULT (1 << 17)
171 #define MEMFAULT (1 << 16)
172 #define DIV0FAULT (1 << 4)
173 #define UNALIGNFAULT (1 << 3)
174 #define HARDFAULT_IRQN (-13)
175
176 ExcInfo g_excInfo = {0};
177
178 UINT8 g_uwExcTbl[FAULT_STATUS_REG_BIT] = {
179 0, 0, 0, 0, 0, 0, OS_EXC_UF_DIVBYZERO, OS_EXC_UF_UNALIGNED,
180 0, 0, 0, 0, OS_EXC_UF_NOCP, OS_EXC_UF_INVPC, OS_EXC_UF_INVSTATE, OS_EXC_UF_UNDEFINSTR,
181 0, 0, 0, OS_EXC_BF_STKERR, OS_EXC_BF_UNSTKERR, OS_EXC_BF_IMPRECISERR, OS_EXC_BF_PRECISERR, OS_EXC_BF_IBUSERR,
182 0, 0, 0, OS_EXC_MF_MSTKERR, OS_EXC_MF_MUNSTKERR, 0, OS_EXC_MF_DACCVIOL, OS_EXC_MF_IACCVIOL
183 };
184
185 #if (LOSCFG_KERNEL_PRINTF != 0)
OsExcNvicDump(VOID)186 STATIC VOID OsExcNvicDump(VOID)
187 {
188 #define OS_NR_NVIC_EXC_DUMP_TYPES 7
189 UINT32 *base = NULL;
190 UINT32 len, i, j;
191 UINT32 rgNvicBases[OS_NR_NVIC_EXC_DUMP_TYPES] = {
192 OS_NVIC_SETENA_BASE, OS_NVIC_SETPEND_BASE, OS_NVIC_INT_ACT_BASE,
193 OS_NVIC_PRI_BASE, OS_NVIC_EXCPRI_BASE, OS_NVIC_SHCSR, OS_NVIC_INT_CTRL
194 };
195 UINT32 rgNvicLens[OS_NR_NVIC_EXC_DUMP_TYPES] = {
196 OS_NVIC_INT_ENABLE_SIZE, OS_NVIC_INT_PEND_SIZE, OS_NVIC_INT_ACT_SIZE,
197 OS_NVIC_INT_PRI_SIZE, OS_NVIC_EXCPRI_SIZE, OS_NVIC_SHCSR_SIZE,
198 OS_NVIC_INT_CTRL_SIZE
199 };
200 CHAR strRgEnable[] = "enable";
201 CHAR strRgPending[] = "pending";
202 CHAR strRgActive[] = "active";
203 CHAR strRgPriority[] = "priority";
204 CHAR strRgException[] = "exception";
205 CHAR strRgShcsr[] = "shcsr";
206 CHAR strRgIntCtrl[] = "control";
207 CHAR *strRgs[] = {
208 strRgEnable, strRgPending, strRgActive, strRgPriority,
209 strRgException, strRgShcsr, strRgIntCtrl
210 };
211
212 PRINTK("\r\nOS exception NVIC dump:\n");
213 for (i = 0; i < OS_NR_NVIC_EXC_DUMP_TYPES; i++) {
214 base = (UINT32 *)rgNvicBases[i];
215 len = rgNvicLens[i];
216 PRINTK("interrupt %s register, base address: %p, size: 0x%x\n", strRgs[i], base, len);
217 len = (len >> 2); /* 2: Gets the next register offset */
218 for (j = 0; j < len; j++) {
219 PRINTK("0x%x ", *(base + j));
220 if ((j != 0) && ((j % 16) == 0)) { /* 16: print wrap line */
221 PRINTK("\n");
222 }
223 }
224 PRINTK("\n");
225 }
226 }
227
OsExcTypeInfo(const ExcInfo * excInfo)228 STATIC VOID OsExcTypeInfo(const ExcInfo *excInfo)
229 {
230 CHAR *phaseStr[] = {"exc in init", "exc in task", "exc in hwi"};
231
232 PRINTK("Type = %d\n", excInfo->type);
233 PRINTK("ThrdPid = %d\n", excInfo->thrdPid);
234 PRINTK("Phase = %s\n", phaseStr[excInfo->phase]);
235 PRINTK("FaultAddr = 0x%x\n", excInfo->faultAddr);
236 }
237
OsExcCurTaskInfo(const ExcInfo * excInfo)238 STATIC VOID OsExcCurTaskInfo(const ExcInfo *excInfo)
239 {
240 PRINTK("Current task info:\n");
241 if (excInfo->phase == OS_EXC_IN_TASK) {
242 LosTaskCB *taskCB = OS_TCB_FROM_TID(LOS_CurTaskIDGet());
243 PRINTK("Task name = %s\n", taskCB->taskName);
244 PRINTK("Task ID = %d\n", taskCB->taskID);
245 PRINTK("Task SP = %p\n", taskCB->stackPointer);
246 PRINTK("Task ST = 0x%x\n", taskCB->topOfStack);
247 PRINTK("Task SS = 0x%x\n", taskCB->stackSize);
248 } else if (excInfo->phase == OS_EXC_IN_HWI) {
249 PRINTK("Exception occur in interrupt phase!\n");
250 } else {
251 PRINTK("Exception occur in system init phase!\n");
252 }
253 }
254
OsExcRegInfo(const ExcInfo * excInfo)255 STATIC VOID OsExcRegInfo(const ExcInfo *excInfo)
256 {
257 PRINTK("Exception reg dump:\n");
258 PRINTK("PC = 0x%x\n", excInfo->context->uwPC);
259 PRINTK("LR = 0x%x\n", excInfo->context->uwLR);
260 PRINTK("SP = 0x%x\n", excInfo->context->uwSP);
261 PRINTK("R0 = 0x%x\n", excInfo->context->uwR0);
262 PRINTK("R1 = 0x%x\n", excInfo->context->uwR1);
263 PRINTK("R2 = 0x%x\n", excInfo->context->uwR2);
264 PRINTK("R3 = 0x%x\n", excInfo->context->uwR3);
265 PRINTK("R4 = 0x%x\n", excInfo->context->uwR4);
266 PRINTK("R5 = 0x%x\n", excInfo->context->uwR5);
267 PRINTK("R6 = 0x%x\n", excInfo->context->uwR6);
268 PRINTK("R7 = 0x%x\n", excInfo->context->uwR7);
269 PRINTK("R8 = 0x%x\n", excInfo->context->uwR8);
270 PRINTK("R9 = 0x%x\n", excInfo->context->uwR9);
271 PRINTK("R10 = 0x%x\n", excInfo->context->uwR10);
272 PRINTK("R11 = 0x%x\n", excInfo->context->uwR11);
273 PRINTK("R12 = 0x%x\n", excInfo->context->uwR12);
274 PRINTK("PriMask = 0x%x\n", excInfo->context->uwPriMask);
275 PRINTK("xPSR = 0x%x\n", excInfo->context->uwxPSR);
276 }
277
278 #if (LOSCFG_KERNEL_BACKTRACE == 1)
OsExcBackTraceInfo(const ExcInfo * excInfo)279 STATIC VOID OsExcBackTraceInfo(const ExcInfo *excInfo)
280 {
281 UINTPTR LR[LOSCFG_BACKTRACE_DEPTH] = {0};
282 UINT32 index;
283
284 OsBackTraceHookCall(LR, LOSCFG_BACKTRACE_DEPTH, 0, excInfo->context->uwSP);
285
286 PRINTK("----- backtrace start -----\n");
287 for (index = 0; index < LOSCFG_BACKTRACE_DEPTH; index++) {
288 if (LR[index] == 0) {
289 break;
290 }
291 PRINTK("backtrace %d -- lr = 0x%x\n", index, LR[index]);
292 }
293 PRINTK("----- backtrace end -----\n");
294 }
295 #endif
296
OsExcMemPoolCheckInfo(VOID)297 STATIC VOID OsExcMemPoolCheckInfo(VOID)
298 {
299 PRINTK("\r\nmemory pools check:\n");
300 #if (LOSCFG_PLATFORM_EXC == 1)
301 MemInfoCB memExcInfo[OS_SYS_MEM_NUM];
302 UINT32 errCnt;
303 UINT32 i;
304
305 (VOID)memset_s(memExcInfo, sizeof(memExcInfo), 0, sizeof(memExcInfo));
306
307 errCnt = OsMemExcInfoGet(OS_SYS_MEM_NUM, memExcInfo);
308 if (errCnt < OS_SYS_MEM_NUM) {
309 errCnt += OsMemboxExcInfoGet(OS_SYS_MEM_NUM - errCnt, memExcInfo + errCnt);
310 }
311
312 if (errCnt == 0) {
313 PRINTK("all memory pool check passed!\n");
314 return;
315 }
316
317 for (i = 0; i < errCnt; i++) {
318 PRINTK("pool num = %d\n", i);
319 PRINTK("pool type = %d\n", memExcInfo[i].type);
320 PRINTK("pool addr = 0x%x\n", memExcInfo[i].startAddr);
321 PRINTK("pool size = 0x%x\n", memExcInfo[i].size);
322 PRINTK("pool free = 0x%x\n", memExcInfo[i].free);
323 PRINTK("pool blkNum = %d\n", memExcInfo[i].blockSize);
324 PRINTK("pool error node addr = 0x%x\n", memExcInfo[i].errorAddr);
325 PRINTK("pool error node len = 0x%x\n", memExcInfo[i].errorLen);
326 PRINTK("pool error node owner = %d\n", memExcInfo[i].errorOwner);
327 }
328 #endif
329 UINT32 ret = LOS_MemIntegrityCheck(LOSCFG_SYS_HEAP_ADDR);
330 if (ret == LOS_OK) {
331 PRINTK("system heap memcheck over, all passed!\n");
332 }
333
334 PRINTK("memory pool check end!\n");
335 }
336 #endif
337
OsExcInfoDisplay(const ExcInfo * excInfo)338 STATIC VOID OsExcInfoDisplay(const ExcInfo *excInfo)
339 {
340 #if (LOSCFG_KERNEL_PRINTF != 0)
341 PRINTK("*************Exception Information**************\n");
342 OsExcTypeInfo(excInfo);
343 OsExcCurTaskInfo(excInfo);
344 OsExcRegInfo(excInfo);
345 #if (LOSCFG_KERNEL_BACKTRACE == 1)
346 OsExcBackTraceInfo(excInfo);
347 #endif
348 OsGetAllTskInfo();
349 OsExcNvicDump();
350 OsExcMemPoolCheckInfo();
351 #endif
352 }
353
HalExcHandleEntry(UINT32 excType,UINT32 faultAddr,UINT32 pid,EXC_CONTEXT_S * excBufAddr)354 LITE_OS_SEC_TEXT_INIT VOID HalExcHandleEntry(UINT32 excType, UINT32 faultAddr, UINT32 pid, EXC_CONTEXT_S *excBufAddr)
355 {
356 UINT16 tmpFlag = (excType >> 16) & OS_NULL_SHORT; /* 16: Get Exception Type */
357 g_intCount++;
358 g_excInfo.nestCnt++;
359
360 g_excInfo.type = excType & OS_NULL_SHORT;
361
362 if (tmpFlag & OS_EXC_FLAG_FAULTADDR_VALID) {
363 g_excInfo.faultAddr = faultAddr;
364 } else {
365 g_excInfo.faultAddr = OS_EXC_IMPRECISE_ACCESS_ADDR;
366 }
367 if (g_losTask.runTask != NULL) {
368 if (tmpFlag & OS_EXC_FLAG_IN_HWI) {
369 g_excInfo.phase = OS_EXC_IN_HWI;
370 g_excInfo.thrdPid = pid;
371 } else {
372 g_excInfo.phase = OS_EXC_IN_TASK;
373 g_excInfo.thrdPid = g_losTask.runTask->taskID;
374 }
375 } else {
376 g_excInfo.phase = OS_EXC_IN_INIT;
377 g_excInfo.thrdPid = OS_NULL_INT;
378 }
379 if (excType & OS_EXC_FLAG_NO_FLOAT) {
380 g_excInfo.context = (EXC_CONTEXT_S *)((CHAR *)excBufAddr - LOS_OFF_SET_OF(EXC_CONTEXT_S, uwR4));
381 } else {
382 g_excInfo.context = excBufAddr;
383 }
384
385 OsDoExcHook(EXC_INTERRUPT);
386 OsExcInfoDisplay(&g_excInfo);
387 ArchSysExit();
388 }
389
SysTick_Handler(VOID)390 WEAK VOID SysTick_Handler(VOID)
391 {
392 return;
393 }
394
395 /* ****************************************************************************
396 Function : HalHwiInit
397 Description : initialization of the hardware interrupt
398 Input : None
399 Output : None
400 Return : None
401 **************************************************************************** */
HalHwiInit(VOID)402 LITE_OS_SEC_TEXT_INIT VOID HalHwiInit(VOID)
403 {
404 #if (LOSCFG_USE_SYSTEM_DEFINED_INTERRUPT == 1)
405 UINT32 index;
406 HWI_PROC_FUNC *hwiForm = (HWI_PROC_FUNC *)ArchGetHwiFrom();
407 hwiForm[0] = 0; /* [0] Top of Stack */
408 hwiForm[1] = (HWI_PROC_FUNC)Reset_Handler; /* [1] reset */
409 for (index = 2; index < OS_VECTOR_CNT; index++) { /* 2: The starting position of the interrupt */
410 hwiForm[index] = (HWI_PROC_FUNC)HalHwiDefaultHandler;
411 }
412 /* Exception handler register */
413 hwiForm[NonMaskableInt_IRQn + OS_SYS_VECTOR_CNT] = (HWI_PROC_FUNC)HalExcNMI;
414 hwiForm[HARDFAULT_IRQN + OS_SYS_VECTOR_CNT] = (HWI_PROC_FUNC)HalExcHardFault;
415 hwiForm[MemoryManagement_IRQn + OS_SYS_VECTOR_CNT] = (HWI_PROC_FUNC)HalExcMemFault;
416 hwiForm[BusFault_IRQn + OS_SYS_VECTOR_CNT] = (HWI_PROC_FUNC)HalExcBusFault;
417 hwiForm[UsageFault_IRQn + OS_SYS_VECTOR_CNT] = (HWI_PROC_FUNC)HalExcUsageFault;
418 hwiForm[SVCall_IRQn + OS_SYS_VECTOR_CNT] = (HWI_PROC_FUNC)HalExcSvcCall;
419 hwiForm[PendSV_IRQn + OS_SYS_VECTOR_CNT] = (HWI_PROC_FUNC)HalPendSV;
420 hwiForm[SysTick_IRQn + OS_SYS_VECTOR_CNT] = (HWI_PROC_FUNC)SysTick_Handler;
421
422 /* Interrupt vector table location */
423 SCB->VTOR = (UINT32)(UINTPTR)hwiForm;
424 #endif
425 #if (__CORTEX_M >= 0x03U) /* only for Cortex-M3 and above */
426 NVIC_SetPriorityGrouping(OS_NVIC_AIRCR_PRIGROUP);
427 #endif
428
429 /* Enable USGFAULT, BUSFAULT, MEMFAULT */
430 *(volatile UINT32 *)OS_NVIC_SHCSR |= (USGFAULT | BUSFAULT | MEMFAULT);
431
432 /* Enable DIV 0 and unaligned exception */
433 *(volatile UINT32 *)OS_NVIC_CCR |= (DIV0FAULT | UNALIGNFAULT);
434
435 return;
436 }
437