1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2013-2014 Kevin Lo 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 31 #define AXE_FLAG_178A 0x10000 /* AX88178A */ 32 33 #define AXGE_ACCESS_MAC 0x01 34 #define AXGE_ACCESS_PHY 0x02 35 #define AXGE_ACCESS_WAKEUP 0x03 36 #define AXGE_ACCESS_EEPROM 0x04 37 #define AXGE_ACCESS_EFUSE 0x05 38 #define AXGE_RELOAD_EEPROM_EFUSE 0x06 39 #define AXGE_WRITE_EFUSE_EN 0x09 40 #define AXGE_WRITE_EFUSE_DIS 0x0A 41 #define AXGE_ACCESS_MFAB 0x10 42 43 /* Physical link status register */ 44 #define AXGE_PLSR 0x02 45 #define PLSR_USB_FS 0x01 46 #define PLSR_USB_HS 0x02 47 #define PLSR_USB_SS 0x04 48 49 /* EEPROM address register */ 50 #define AXGE_EAR 0x07 51 52 /* EEPROM data low register */ 53 #define AXGE_EDLR 0x08 54 55 /* EEPROM data high register */ 56 #define AXGE_EDHR 0x09 57 58 /* EEPROM command register */ 59 #define AXGE_ECR 0x0a 60 61 /* Rx control register */ 62 #define AXGE_RCR 0x0b 63 #define RCR_STOP 0x0000 64 #define RCR_PRO 0x0001 65 #define RCR_AMALL 0x0002 66 #define RCR_AB 0x0008 67 #define RCR_AM 0x0010 68 #define RCR_AP 0x0020 69 #define RCR_SO 0x0080 70 #define RCR_DROP_CRCE 0x0100 71 #define RCR_IPE 0x0200 72 #define RCR_TX_CRC_PAD 0x0400 73 74 /* Node id register */ 75 #define AXGE_NIDR 0x10 76 77 /* Multicast filter array */ 78 #define AXGE_MFA 0x16 79 80 /* Medium status register */ 81 #define AXGE_MSR 0x22 82 #define MSR_GM 0x0001 83 #define MSR_FD 0x0002 84 #define MSR_EN_125MHZ 0x0008 85 #define MSR_RFC 0x0010 86 #define MSR_TFC 0x0020 87 #define MSR_RE 0x0100 88 #define MSR_PS 0x0200 89 90 /* Monitor mode status register */ 91 #define AXGE_MMSR 0x24 92 #define MMSR_RWLC 0x02 93 #define MMSR_RWMP 0x04 94 #define MMSR_RWWF 0x08 95 #define MMSR_RW_FLAG 0x10 96 #define MMSR_PME_POL 0x20 97 #define MMSR_PME_TYPE 0x40 98 #define MMSR_PME_IND 0x80 99 100 /* GPIO control/status register */ 101 #define AXGE_GPIOCR 0x25 102 103 /* Ethernet PHY power & reset control register */ 104 #define AXGE_EPPRCR 0x26 105 #define EPPRCR_BZ 0x0010 106 #define EPPRCR_IPRL 0x0020 107 #define EPPRCR_AUTODETACH 0x1000 108 109 #define AXGE_RX_BULKIN_QCTRL 0x2e 110 111 #define AXGE_CLK_SELECT 0x33 112 #define AXGE_CLK_SELECT_BCS 0x01 113 #define AXGE_CLK_SELECT_ACS 0x02 114 #define AXGE_CLK_SELECT_ACSREQ 0x10 115 #define AXGE_CLK_SELECT_ULR 0x08 116 117 /* COE Rx control register */ 118 #define AXGE_CRCR 0x34 119 #define CRCR_IP 0x01 120 #define CRCR_TCP 0x02 121 #define CRCR_UDP 0x04 122 #define CRCR_ICMP 0x08 123 #define CRCR_IGMP 0x10 124 #define CRCR_TCPV6 0x20 125 #define CRCR_UDPV6 0x40 126 #define CRCR_ICMPV6 0x80 127 128 /* COE Tx control register */ 129 #define AXGE_CTCR 0x35 130 #define CTCR_IP 0x01 131 #define CTCR_TCP 0x02 132 #define CTCR_UDP 0x04 133 #define CTCR_ICMP 0x08 134 #define CTCR_IGMP 0x10 135 #define CTCR_TCPV6 0x20 136 #define CTCR_UDPV6 0x40 137 #define CTCR_ICMPV6 0x80 138 139 /* Pause water level high register */ 140 #define AXGE_PWLHR 0x54 141 142 /* Pause water level low register */ 143 #define AXGE_PWLLR 0x55 144 145 #define AXGE_CONFIG_IDX 0 /* config number 1 */ 146 #define AXGE_IFACE_IDX 0 147 148 #define AXGE_RXHDR_L4_TYPE_MASK 0x1c 149 #define AXGE_RXHDR_L4CSUM_ERR 1 150 #define AXGE_RXHDR_L3CSUM_ERR 2 151 #define AXGE_RXHDR_L4_TYPE_UDP 4 152 #define AXGE_RXHDR_L4_TYPE_TCP 16 153 #define AXGE_RXHDR_CRC_ERR 0x20000000 154 #define AXGE_RXHDR_DROP_ERR 0x80000000 155 156 /* The interrupt endpoint is currently unused by the ASIX part. */ 157 enum { 158 AXGE_BULK_DT_WR, 159 AXGE_BULK_DT_RD, 160 AXGE_N_TRANSFER, 161 }; 162 163 struct axge_softc { 164 struct usb_ether sc_ue; 165 struct mtx sc_mtx; 166 struct usb_xfer *sc_xfer[AXGE_N_TRANSFER]; 167 int sc_phyno; 168 169 int sc_flags; 170 uint8_t sc_link_status; 171 #define AXE_FLAG_LINK 0x0001 172 #define AXE_FLAG_STD_FRAME 0x0010 173 #define AXE_FLAG_CSUM_FRAME 0x0020 174 175 uint8_t sc_ipgs[3]; 176 uint8_t sc_phyaddrs[2]; 177 uint16_t sc_pwrcfg; 178 uint16_t sc_lenmask; 179 uint8_t rx_chklink_cnt; 180 #define EVENT_LINK 0x00000001 181 }; 182 183 #define ETHER_TYPE_LEN 2 /* length of the Ethernet type field */ 184 #define ETHER_HDR_LEN (NETIF_MAX_HWADDR_LEN * 2 + ETHER_TYPE_LEN) 185 186 #define IFM_1000_T 0x40 187 #define IFM_100_TX 0x20 188 #define IFM_10_T 0x10 189 190 #define AXGE_LINK_MASK 0xf0 191 192 #define AXGE_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 193 #define AXGE_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 194 #define AXGE_LOCK_ASSERT(_sc, t) mtx_assert(&(_sc)->sc_mtx, t) 195