1 /**************************************************************************//**
2 * @file cmsis_armclang.h
3 * @brief CMSIS compiler armclang (Arm Compiler 6) header file
4 * @version V5.5.0
5 * @date 20. January 2023
6 ******************************************************************************/
7 /*
8 * Copyright (c) 2009-2023 Arm Limited. All rights reserved.
9 *
10 * SPDX-License-Identifier: Apache-2.0
11 *
12 * Licensed under the Apache License, Version 2.0 (the License); you may
13 * not use this file except in compliance with the License.
14 * You may obtain a copy of the License at
15 *
16 * www.apache.org/licenses/LICENSE-2.0
17 *
18 * Unless required by applicable law or agreed to in writing, software
19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 * See the License for the specific language governing permissions and
22 * limitations under the License.
23 */
24
25 /*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */
26
27 #ifndef __CMSIS_ARMCLANG_H
28 #define __CMSIS_ARMCLANG_H
29
30 #pragma clang system_header /* treat file as system include file */
31
32 /* CMSIS compiler specific defines */
33 #ifndef __ASM
34 #define __ASM __asm
35 #endif
36 #ifndef __INLINE
37 #define __INLINE __inline
38 #endif
39 #ifndef __STATIC_INLINE
40 #define __STATIC_INLINE static __inline
41 #endif
42 #ifndef __STATIC_FORCEINLINE
43 #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline
44 #endif
45 #ifndef __NO_RETURN
46 #define __NO_RETURN __attribute__((__noreturn__))
47 #endif
48 #ifndef __USED
49 #define __USED __attribute__((used))
50 #endif
51 #ifndef __WEAK
52 #define __WEAK __attribute__((weak))
53 #endif
54 #ifndef __PACKED
55 #define __PACKED __attribute__((packed, aligned(1)))
56 #endif
57 #ifndef __PACKED_STRUCT
58 #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
59 #endif
60 #ifndef __PACKED_UNION
61 #define __PACKED_UNION union __attribute__((packed, aligned(1)))
62 #endif
63 #ifndef __UNALIGNED_UINT32 /* deprecated */
64 #pragma clang diagnostic push
65 #pragma clang diagnostic ignored "-Wpacked"
66 /*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */
67 struct __attribute__((packed)) T_UINT32 { uint32_t v; };
68 #pragma clang diagnostic pop
69 #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
70 #endif
71 #ifndef __UNALIGNED_UINT16_WRITE
72 #pragma clang diagnostic push
73 #pragma clang diagnostic ignored "-Wpacked"
74 /*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */
75 __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
76 #pragma clang diagnostic pop
77 #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
78 #endif
79 #ifndef __UNALIGNED_UINT16_READ
80 #pragma clang diagnostic push
81 #pragma clang diagnostic ignored "-Wpacked"
82 /*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */
83 __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
84 #pragma clang diagnostic pop
85 #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
86 #endif
87 #ifndef __UNALIGNED_UINT32_WRITE
88 #pragma clang diagnostic push
89 #pragma clang diagnostic ignored "-Wpacked"
90 /*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */
91 __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
92 #pragma clang diagnostic pop
93 #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
94 #endif
95 #ifndef __UNALIGNED_UINT32_READ
96 #pragma clang diagnostic push
97 #pragma clang diagnostic ignored "-Wpacked"
98 /*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */
99 __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
100 #pragma clang diagnostic pop
101 #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
102 #endif
103 #ifndef __ALIGNED
104 #define __ALIGNED(x) __attribute__((aligned(x)))
105 #endif
106 #ifndef __RESTRICT
107 #define __RESTRICT __restrict
108 #endif
109 #ifndef __COMPILER_BARRIER
110 #define __COMPILER_BARRIER() __ASM volatile("":::"memory")
111 #endif
112 #ifndef __NO_INIT
113 #define __NO_INIT __attribute__ ((section (".bss.noinit")))
114 #endif
115 #ifndef __ALIAS
116 #define __ALIAS(x) __attribute__ ((alias(x)))
117 #endif
118
119
120 /* ######################### Startup and Lowlevel Init ######################## */
121
122 #ifndef __PROGRAM_START
123 #define __PROGRAM_START __main
124 #endif
125
126 #ifndef __INITIAL_SP
127 #define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit
128 #endif
129
130 #ifndef __STACK_LIMIT
131 #define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base
132 #endif
133
134 #ifndef __VECTOR_TABLE
135 #define __VECTOR_TABLE __Vectors
136 #endif
137
138 #ifndef __VECTOR_TABLE_ATTRIBUTE
139 #define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET")))
140 #endif
141
142 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
143 #ifndef __STACK_SEAL
144 #define __STACK_SEAL Image$$STACKSEAL$$ZI$$Base
145 #endif
146
147 #ifndef __TZ_STACK_SEAL_SIZE
148 #define __TZ_STACK_SEAL_SIZE 8U
149 #endif
150
151 #ifndef __TZ_STACK_SEAL_VALUE
152 #define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL
153 #endif
154
155
__TZ_set_STACKSEAL_S(uint32_t * stackTop)156 __STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) {
157 *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE;
158 }
159 #endif
160
161
162 /* ########################## Core Instruction Access ######################### */
163 /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
164 Access to dedicated instructions
165 @{
166 */
167
168 /* Define macros for porting to both thumb1 and thumb2.
169 * For thumb1, use low register (r0-r7), specified by constraint "l"
170 * Otherwise, use general registers, specified by constraint "r" */
171 #if defined (__thumb__) && !defined (__thumb2__)
172 #define __CMSIS_GCC_OUT_REG(r) "=l" (r)
173 #define __CMSIS_GCC_RW_REG(r) "+l" (r)
174 #define __CMSIS_GCC_USE_REG(r) "l" (r)
175 #else
176 #define __CMSIS_GCC_OUT_REG(r) "=r" (r)
177 #define __CMSIS_GCC_RW_REG(r) "+r" (r)
178 #define __CMSIS_GCC_USE_REG(r) "r" (r)
179 #endif
180
181 /**
182 \brief No Operation
183 \details No Operation does nothing. This instruction can be used for code alignment purposes.
184 */
185 #define __NOP __builtin_arm_nop
186
187 /**
188 \brief Wait For Interrupt
189 \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
190 */
191 #define __WFI __builtin_arm_wfi
192
193
194 /**
195 \brief Wait For Event
196 \details Wait For Event is a hint instruction that permits the processor to enter
197 a low-power state until one of a number of events occurs.
198 */
199 #define __WFE __builtin_arm_wfe
200
201
202 /**
203 \brief Send Event
204 \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
205 */
206 #define __SEV __builtin_arm_sev
207
208
209 /**
210 \brief Instruction Synchronization Barrier
211 \details Instruction Synchronization Barrier flushes the pipeline in the processor,
212 so that all instructions following the ISB are fetched from cache or memory,
213 after the instruction has been completed.
214 */
215 #define __ISB() __builtin_arm_isb(0xF)
216
217 /**
218 \brief Data Synchronization Barrier
219 \details Acts as a special kind of Data Memory Barrier.
220 It completes when all explicit memory accesses before this instruction complete.
221 */
222 #define __DSB() __builtin_arm_dsb(0xF)
223
224
225 /**
226 \brief Data Memory Barrier
227 \details Ensures the apparent order of the explicit memory operations before
228 and after the instruction, without ensuring their completion.
229 */
230 #define __DMB() __builtin_arm_dmb(0xF)
231
232
233 /**
234 \brief Reverse byte order (32 bit)
235 \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
236 \param [in] value Value to reverse
237 \return Reversed value
238 */
239 #define __REV(value) __builtin_bswap32(value)
240
241
242 /**
243 \brief Reverse byte order (16 bit)
244 \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
245 \param [in] value Value to reverse
246 \return Reversed value
247 */
248 #define __REV16(value) __ROR(__REV(value), 16)
249
250
251 /**
252 \brief Reverse byte order (16 bit)
253 \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
254 \param [in] value Value to reverse
255 \return Reversed value
256 */
257 #define __REVSH(value) (int16_t)__builtin_bswap16(value)
258
259
260 /**
261 \brief Rotate Right in unsigned value (32 bit)
262 \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
263 \param [in] op1 Value to rotate
264 \param [in] op2 Number of Bits to rotate
265 \return Rotated value
266 */
__ROR(uint32_t op1,uint32_t op2)267 __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
268 {
269 op2 %= 32U;
270 if (op2 == 0U)
271 {
272 return op1;
273 }
274 return (op1 >> op2) | (op1 << (32U - op2));
275 }
276
277
278 /**
279 \brief Breakpoint
280 \details Causes the processor to enter Debug state.
281 Debug tools can use this to investigate system state when the instruction at a particular address is reached.
282 \param [in] value is ignored by the processor.
283 If required, a debugger can use it to store additional information about the breakpoint.
284 */
285 #define __BKPT(value) __ASM volatile ("bkpt "#value)
286
287
288 /**
289 \brief Reverse bit order of value
290 \details Reverses the bit order of the given value.
291 \param [in] value Value to reverse
292 \return Reversed value
293 */
294 #define __RBIT __builtin_arm_rbit
295
296 /**
297 \brief Count leading zeros
298 \details Counts the number of leading zeros of a data value.
299 \param [in] value Value to count the leading zeros
300 \return number of leading zeros in value
301 */
__CLZ(uint32_t value)302 __STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)
303 {
304 /* Even though __builtin_clz produces a CLZ instruction on ARM, formally
305 __builtin_clz(0) is undefined behaviour, so handle this case specially.
306 This guarantees ARM-compatible results if happening to compile on a non-ARM
307 target, and ensures the compiler doesn't decide to activate any
308 optimisations using the logic "value was passed to __builtin_clz, so it
309 is non-zero".
310 ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a
311 single CLZ instruction.
312 */
313 if (value == 0U)
314 {
315 return 32U;
316 }
317 return __builtin_clz(value);
318 }
319
320
321 #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
322 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
323 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
324 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \
325 (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) )
326
327 /**
328 \brief LDR Exclusive (8 bit)
329 \details Executes a exclusive LDR instruction for 8 bit value.
330 \param [in] ptr Pointer to data
331 \return value of type uint8_t at (*ptr)
332 */
333 #define __LDREXB (uint8_t)__builtin_arm_ldrex
334
335
336 /**
337 \brief LDR Exclusive (16 bit)
338 \details Executes a exclusive LDR instruction for 16 bit values.
339 \param [in] ptr Pointer to data
340 \return value of type uint16_t at (*ptr)
341 */
342 #define __LDREXH (uint16_t)__builtin_arm_ldrex
343
344
345 /**
346 \brief LDR Exclusive (32 bit)
347 \details Executes a exclusive LDR instruction for 32 bit values.
348 \param [in] ptr Pointer to data
349 \return value of type uint32_t at (*ptr)
350 */
351 #define __LDREXW (uint32_t)__builtin_arm_ldrex
352
353
354 /**
355 \brief STR Exclusive (8 bit)
356 \details Executes a exclusive STR instruction for 8 bit values.
357 \param [in] value Value to store
358 \param [in] ptr Pointer to location
359 \return 0 Function succeeded
360 \return 1 Function failed
361 */
362 #define __STREXB (uint32_t)__builtin_arm_strex
363
364
365 /**
366 \brief STR Exclusive (16 bit)
367 \details Executes a exclusive STR instruction for 16 bit values.
368 \param [in] value Value to store
369 \param [in] ptr Pointer to location
370 \return 0 Function succeeded
371 \return 1 Function failed
372 */
373 #define __STREXH (uint32_t)__builtin_arm_strex
374
375
376 /**
377 \brief STR Exclusive (32 bit)
378 \details Executes a exclusive STR instruction for 32 bit values.
379 \param [in] value Value to store
380 \param [in] ptr Pointer to location
381 \return 0 Function succeeded
382 \return 1 Function failed
383 */
384 #define __STREXW (uint32_t)__builtin_arm_strex
385
386
387 /**
388 \brief Remove the exclusive lock
389 \details Removes the exclusive lock which is created by LDREX.
390 */
391 #define __CLREX __builtin_arm_clrex
392
393 #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
394 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
395 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
396 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \
397 (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */
398
399
400 #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
401 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
402 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
403 (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) )
404
405 /**
406 \brief Signed Saturate
407 \details Saturates a signed value.
408 \param [in] value Value to be saturated
409 \param [in] sat Bit position to saturate to (1..32)
410 \return Saturated value
411 */
412 #define __SSAT __builtin_arm_ssat
413
414
415 /**
416 \brief Unsigned Saturate
417 \details Saturates an unsigned value.
418 \param [in] value Value to be saturated
419 \param [in] sat Bit position to saturate to (0..31)
420 \return Saturated value
421 */
422 #define __USAT __builtin_arm_usat
423
424
425 /**
426 \brief Rotate Right with Extend (32 bit)
427 \details Moves each bit of a bitstring right by one bit.
428 The carry input is shifted in at the left end of the bitstring.
429 \param [in] value Value to rotate
430 \return Rotated value
431 */
__RRX(uint32_t value)432 __STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
433 {
434 uint32_t result;
435
436 __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
437 return(result);
438 }
439
440
441 /**
442 \brief LDRT Unprivileged (8 bit)
443 \details Executes a Unprivileged LDRT instruction for 8 bit value.
444 \param [in] ptr Pointer to data
445 \return value of type uint8_t at (*ptr)
446 */
__LDRBT(volatile uint8_t * ptr)447 __STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
448 {
449 uint32_t result;
450
451 __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
452 return ((uint8_t) result); /* Add explicit type cast here */
453 }
454
455
456 /**
457 \brief LDRT Unprivileged (16 bit)
458 \details Executes a Unprivileged LDRT instruction for 16 bit values.
459 \param [in] ptr Pointer to data
460 \return value of type uint16_t at (*ptr)
461 */
__LDRHT(volatile uint16_t * ptr)462 __STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
463 {
464 uint32_t result;
465
466 __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
467 return ((uint16_t) result); /* Add explicit type cast here */
468 }
469
470
471 /**
472 \brief LDRT Unprivileged (32 bit)
473 \details Executes a Unprivileged LDRT instruction for 32 bit values.
474 \param [in] ptr Pointer to data
475 \return value of type uint32_t at (*ptr)
476 */
__LDRT(volatile uint32_t * ptr)477 __STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
478 {
479 uint32_t result;
480
481 __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
482 return(result);
483 }
484
485
486 /**
487 \brief STRT Unprivileged (8 bit)
488 \details Executes a Unprivileged STRT instruction for 8 bit values.
489 \param [in] value Value to store
490 \param [in] ptr Pointer to location
491 */
__STRBT(uint8_t value,volatile uint8_t * ptr)492 __STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
493 {
494 __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
495 }
496
497
498 /**
499 \brief STRT Unprivileged (16 bit)
500 \details Executes a Unprivileged STRT instruction for 16 bit values.
501 \param [in] value Value to store
502 \param [in] ptr Pointer to location
503 */
__STRHT(uint16_t value,volatile uint16_t * ptr)504 __STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
505 {
506 __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
507 }
508
509
510 /**
511 \brief STRT Unprivileged (32 bit)
512 \details Executes a Unprivileged STRT instruction for 32 bit values.
513 \param [in] value Value to store
514 \param [in] ptr Pointer to location
515 */
__STRT(uint32_t value,volatile uint32_t * ptr)516 __STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
517 {
518 __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
519 }
520
521 #else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
522 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
523 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
524 (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */
525
526 /**
527 \brief Signed Saturate
528 \details Saturates a signed value.
529 \param [in] value Value to be saturated
530 \param [in] sat Bit position to saturate to (1..32)
531 \return Saturated value
532 */
__SSAT(int32_t val,uint32_t sat)533 __STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
534 {
535 if ((sat >= 1U) && (sat <= 32U))
536 {
537 const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
538 const int32_t min = -1 - max ;
539 if (val > max)
540 {
541 return max;
542 }
543 else if (val < min)
544 {
545 return min;
546 }
547 }
548 return val;
549 }
550
551 /**
552 \brief Unsigned Saturate
553 \details Saturates an unsigned value.
554 \param [in] value Value to be saturated
555 \param [in] sat Bit position to saturate to (0..31)
556 \return Saturated value
557 */
__USAT(int32_t val,uint32_t sat)558 __STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
559 {
560 if (sat <= 31U)
561 {
562 const uint32_t max = ((1U << sat) - 1U);
563 if (val > (int32_t)max)
564 {
565 return max;
566 }
567 else if (val < 0)
568 {
569 return 0U;
570 }
571 }
572 return (uint32_t)val;
573 }
574
575 #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
576 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
577 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
578 (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */
579
580
581 #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
582 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \
583 (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) )
584
585 /**
586 \brief Load-Acquire (8 bit)
587 \details Executes a LDAB instruction for 8 bit value.
588 \param [in] ptr Pointer to data
589 \return value of type uint8_t at (*ptr)
590 */
__LDAB(volatile uint8_t * ptr)591 __STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
592 {
593 uint32_t result;
594
595 __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
596 return ((uint8_t) result);
597 }
598
599
600 /**
601 \brief Load-Acquire (16 bit)
602 \details Executes a LDAH instruction for 16 bit values.
603 \param [in] ptr Pointer to data
604 \return value of type uint16_t at (*ptr)
605 */
__LDAH(volatile uint16_t * ptr)606 __STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
607 {
608 uint32_t result;
609
610 __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
611 return ((uint16_t) result);
612 }
613
614
615 /**
616 \brief Load-Acquire (32 bit)
617 \details Executes a LDA instruction for 32 bit values.
618 \param [in] ptr Pointer to data
619 \return value of type uint32_t at (*ptr)
620 */
__LDA(volatile uint32_t * ptr)621 __STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
622 {
623 uint32_t result;
624
625 __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
626 return(result);
627 }
628
629
630 /**
631 \brief Store-Release (8 bit)
632 \details Executes a STLB instruction for 8 bit values.
633 \param [in] value Value to store
634 \param [in] ptr Pointer to location
635 */
__STLB(uint8_t value,volatile uint8_t * ptr)636 __STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
637 {
638 __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
639 }
640
641
642 /**
643 \brief Store-Release (16 bit)
644 \details Executes a STLH instruction for 16 bit values.
645 \param [in] value Value to store
646 \param [in] ptr Pointer to location
647 */
__STLH(uint16_t value,volatile uint16_t * ptr)648 __STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
649 {
650 __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
651 }
652
653
654 /**
655 \brief Store-Release (32 bit)
656 \details Executes a STL instruction for 32 bit values.
657 \param [in] value Value to store
658 \param [in] ptr Pointer to location
659 */
__STL(uint32_t value,volatile uint32_t * ptr)660 __STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
661 {
662 __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
663 }
664
665
666 /**
667 \brief Load-Acquire Exclusive (8 bit)
668 \details Executes a LDAB exclusive instruction for 8 bit value.
669 \param [in] ptr Pointer to data
670 \return value of type uint8_t at (*ptr)
671 */
672 #define __LDAEXB (uint8_t)__builtin_arm_ldaex
673
674
675 /**
676 \brief Load-Acquire Exclusive (16 bit)
677 \details Executes a LDAH exclusive instruction for 16 bit values.
678 \param [in] ptr Pointer to data
679 \return value of type uint16_t at (*ptr)
680 */
681 #define __LDAEXH (uint16_t)__builtin_arm_ldaex
682
683
684 /**
685 \brief Load-Acquire Exclusive (32 bit)
686 \details Executes a LDA exclusive instruction for 32 bit values.
687 \param [in] ptr Pointer to data
688 \return value of type uint32_t at (*ptr)
689 */
690 #define __LDAEX (uint32_t)__builtin_arm_ldaex
691
692
693 /**
694 \brief Store-Release Exclusive (8 bit)
695 \details Executes a STLB exclusive instruction for 8 bit values.
696 \param [in] value Value to store
697 \param [in] ptr Pointer to location
698 \return 0 Function succeeded
699 \return 1 Function failed
700 */
701 #define __STLEXB (uint32_t)__builtin_arm_stlex
702
703
704 /**
705 \brief Store-Release Exclusive (16 bit)
706 \details Executes a STLH exclusive instruction for 16 bit values.
707 \param [in] value Value to store
708 \param [in] ptr Pointer to location
709 \return 0 Function succeeded
710 \return 1 Function failed
711 */
712 #define __STLEXH (uint32_t)__builtin_arm_stlex
713
714
715 /**
716 \brief Store-Release Exclusive (32 bit)
717 \details Executes a STL exclusive instruction for 32 bit values.
718 \param [in] value Value to store
719 \param [in] ptr Pointer to location
720 \return 0 Function succeeded
721 \return 1 Function failed
722 */
723 #define __STLEX (uint32_t)__builtin_arm_stlex
724
725 #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
726 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \
727 (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */
728
729 /** @}*/ /* end of group CMSIS_Core_InstructionInterface */
730
731
732 /* ########################### Core Function Access ########################### */
733 /** \ingroup CMSIS_Core_FunctionInterface
734 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
735 @{
736 */
737
738 /**
739 \brief Enable IRQ Interrupts
740 \details Enables IRQ interrupts by clearing special-purpose register PRIMASK.
741 Can only be executed in Privileged modes.
742 */
743 #ifndef __ARM_COMPAT_H
__enable_irq(void)744 __STATIC_FORCEINLINE void __enable_irq(void)
745 {
746 __ASM volatile ("cpsie i" : : : "memory");
747 }
748 #endif
749
750
751 /**
752 \brief Disable IRQ Interrupts
753 \details Disables IRQ interrupts by setting special-purpose register PRIMASK.
754 Can only be executed in Privileged modes.
755 */
756 #ifndef __ARM_COMPAT_H
__disable_irq(void)757 __STATIC_FORCEINLINE void __disable_irq(void)
758 {
759 __ASM volatile ("cpsid i" : : : "memory");
760 }
761 #endif
762
763
764 /**
765 \brief Get Control Register
766 \details Returns the content of the Control Register.
767 \return Control Register value
768 */
__get_CONTROL(void)769 __STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
770 {
771 uint32_t result;
772
773 __ASM volatile ("MRS %0, control" : "=r" (result) );
774 return(result);
775 }
776
777
778 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
779 /**
780 \brief Get Control Register (non-secure)
781 \details Returns the content of the non-secure Control Register when in secure mode.
782 \return non-secure Control Register value
783 */
__TZ_get_CONTROL_NS(void)784 __STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
785 {
786 uint32_t result;
787
788 __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
789 return(result);
790 }
791 #endif
792
793
794 /**
795 \brief Set Control Register
796 \details Writes the given value to the Control Register.
797 \param [in] control Control Register value to set
798 */
__set_CONTROL(uint32_t control)799 __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
800 {
801 __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
802 __ISB();
803 }
804
805
806 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
807 /**
808 \brief Set Control Register (non-secure)
809 \details Writes the given value to the non-secure Control Register when in secure state.
810 \param [in] control Control Register value to set
811 */
__TZ_set_CONTROL_NS(uint32_t control)812 __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
813 {
814 __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
815 __ISB();
816 }
817 #endif
818
819
820 /**
821 \brief Get IPSR Register
822 \details Returns the content of the IPSR Register.
823 \return IPSR Register value
824 */
__get_IPSR(void)825 __STATIC_FORCEINLINE uint32_t __get_IPSR(void)
826 {
827 uint32_t result;
828
829 __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
830 return(result);
831 }
832
833
834 /**
835 \brief Get APSR Register
836 \details Returns the content of the APSR Register.
837 \return APSR Register value
838 */
__get_APSR(void)839 __STATIC_FORCEINLINE uint32_t __get_APSR(void)
840 {
841 uint32_t result;
842
843 __ASM volatile ("MRS %0, apsr" : "=r" (result) );
844 return(result);
845 }
846
847
848 /**
849 \brief Get xPSR Register
850 \details Returns the content of the xPSR Register.
851 \return xPSR Register value
852 */
__get_xPSR(void)853 __STATIC_FORCEINLINE uint32_t __get_xPSR(void)
854 {
855 uint32_t result;
856
857 __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
858 return(result);
859 }
860
861
862 /**
863 \brief Get Process Stack Pointer
864 \details Returns the current value of the Process Stack Pointer (PSP).
865 \return PSP Register value
866 */
__get_PSP(void)867 __STATIC_FORCEINLINE uint32_t __get_PSP(void)
868 {
869 uint32_t result;
870
871 __ASM volatile ("MRS %0, psp" : "=r" (result) );
872 return(result);
873 }
874
875
876 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
877 /**
878 \brief Get Process Stack Pointer (non-secure)
879 \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
880 \return PSP Register value
881 */
__TZ_get_PSP_NS(void)882 __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
883 {
884 uint32_t result;
885
886 __ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
887 return(result);
888 }
889 #endif
890
891
892 /**
893 \brief Set Process Stack Pointer
894 \details Assigns the given value to the Process Stack Pointer (PSP).
895 \param [in] topOfProcStack Process Stack Pointer value to set
896 */
__set_PSP(uint32_t topOfProcStack)897 __STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
898 {
899 __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
900 }
901
902
903 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
904 /**
905 \brief Set Process Stack Pointer (non-secure)
906 \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
907 \param [in] topOfProcStack Process Stack Pointer value to set
908 */
__TZ_set_PSP_NS(uint32_t topOfProcStack)909 __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
910 {
911 __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
912 }
913 #endif
914
915
916 /**
917 \brief Get Main Stack Pointer
918 \details Returns the current value of the Main Stack Pointer (MSP).
919 \return MSP Register value
920 */
__get_MSP(void)921 __STATIC_FORCEINLINE uint32_t __get_MSP(void)
922 {
923 uint32_t result;
924
925 __ASM volatile ("MRS %0, msp" : "=r" (result) );
926 return(result);
927 }
928
929
930 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
931 /**
932 \brief Get Main Stack Pointer (non-secure)
933 \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
934 \return MSP Register value
935 */
__TZ_get_MSP_NS(void)936 __STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
937 {
938 uint32_t result;
939
940 __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
941 return(result);
942 }
943 #endif
944
945
946 /**
947 \brief Set Main Stack Pointer
948 \details Assigns the given value to the Main Stack Pointer (MSP).
949 \param [in] topOfMainStack Main Stack Pointer value to set
950 */
__set_MSP(uint32_t topOfMainStack)951 __STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
952 {
953 __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
954 }
955
956
957 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
958 /**
959 \brief Set Main Stack Pointer (non-secure)
960 \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
961 \param [in] topOfMainStack Main Stack Pointer value to set
962 */
__TZ_set_MSP_NS(uint32_t topOfMainStack)963 __STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
964 {
965 __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
966 }
967 #endif
968
969
970 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
971 /**
972 \brief Get Stack Pointer (non-secure)
973 \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
974 \return SP Register value
975 */
__TZ_get_SP_NS(void)976 __STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
977 {
978 uint32_t result;
979
980 __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
981 return(result);
982 }
983
984
985 /**
986 \brief Set Stack Pointer (non-secure)
987 \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
988 \param [in] topOfStack Stack Pointer value to set
989 */
__TZ_set_SP_NS(uint32_t topOfStack)990 __STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
991 {
992 __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
993 }
994 #endif
995
996
997 /**
998 \brief Get Priority Mask
999 \details Returns the current state of the priority mask bit from the Priority Mask Register.
1000 \return Priority Mask value
1001 */
__get_PRIMASK(void)1002 __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
1003 {
1004 uint32_t result;
1005
1006 __ASM volatile ("MRS %0, primask" : "=r" (result) );
1007 return(result);
1008 }
1009
1010
1011 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
1012 /**
1013 \brief Get Priority Mask (non-secure)
1014 \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
1015 \return Priority Mask value
1016 */
__TZ_get_PRIMASK_NS(void)1017 __STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
1018 {
1019 uint32_t result;
1020
1021 __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
1022 return(result);
1023 }
1024 #endif
1025
1026
1027 /**
1028 \brief Set Priority Mask
1029 \details Assigns the given value to the Priority Mask Register.
1030 \param [in] priMask Priority Mask
1031 */
__set_PRIMASK(uint32_t priMask)1032 __STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
1033 {
1034 __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
1035 }
1036
1037
1038 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
1039 /**
1040 \brief Set Priority Mask (non-secure)
1041 \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
1042 \param [in] priMask Priority Mask
1043 */
__TZ_set_PRIMASK_NS(uint32_t priMask)1044 __STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
1045 {
1046 __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
1047 }
1048 #endif
1049
1050
1051 #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
1052 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
1053 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
1054 (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) )
1055 /**
1056 \brief Enable FIQ
1057 \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK.
1058 Can only be executed in Privileged modes.
1059 */
__enable_fault_irq(void)1060 __STATIC_FORCEINLINE void __enable_fault_irq(void)
1061 {
1062 __ASM volatile ("cpsie f" : : : "memory");
1063 }
1064
1065
1066 /**
1067 \brief Disable FIQ
1068 \details Disables FIQ interrupts by setting special-purpose register FAULTMASK.
1069 Can only be executed in Privileged modes.
1070 */
__disable_fault_irq(void)1071 __STATIC_FORCEINLINE void __disable_fault_irq(void)
1072 {
1073 __ASM volatile ("cpsid f" : : : "memory");
1074 }
1075
1076
1077 /**
1078 \brief Get Base Priority
1079 \details Returns the current value of the Base Priority register.
1080 \return Base Priority register value
1081 */
__get_BASEPRI(void)1082 __STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
1083 {
1084 uint32_t result;
1085
1086 __ASM volatile ("MRS %0, basepri" : "=r" (result) );
1087 return(result);
1088 }
1089
1090
1091 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
1092 /**
1093 \brief Get Base Priority (non-secure)
1094 \details Returns the current value of the non-secure Base Priority register when in secure state.
1095 \return Base Priority register value
1096 */
__TZ_get_BASEPRI_NS(void)1097 __STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
1098 {
1099 uint32_t result;
1100
1101 __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
1102 return(result);
1103 }
1104 #endif
1105
1106
1107 /**
1108 \brief Set Base Priority
1109 \details Assigns the given value to the Base Priority register.
1110 \param [in] basePri Base Priority value to set
1111 */
__set_BASEPRI(uint32_t basePri)1112 __STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
1113 {
1114 __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
1115 }
1116
1117
1118 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
1119 /**
1120 \brief Set Base Priority (non-secure)
1121 \details Assigns the given value to the non-secure Base Priority register when in secure state.
1122 \param [in] basePri Base Priority value to set
1123 */
__TZ_set_BASEPRI_NS(uint32_t basePri)1124 __STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
1125 {
1126 __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
1127 }
1128 #endif
1129
1130
1131 /**
1132 \brief Set Base Priority with condition
1133 \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
1134 or the new value increases the BASEPRI priority level.
1135 \param [in] basePri Base Priority value to set
1136 */
__set_BASEPRI_MAX(uint32_t basePri)1137 __STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
1138 {
1139 __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
1140 }
1141
1142
1143 /**
1144 \brief Get Fault Mask
1145 \details Returns the current value of the Fault Mask register.
1146 \return Fault Mask register value
1147 */
__get_FAULTMASK(void)1148 __STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
1149 {
1150 uint32_t result;
1151
1152 __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
1153 return(result);
1154 }
1155
1156
1157 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
1158 /**
1159 \brief Get Fault Mask (non-secure)
1160 \details Returns the current value of the non-secure Fault Mask register when in secure state.
1161 \return Fault Mask register value
1162 */
__TZ_get_FAULTMASK_NS(void)1163 __STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
1164 {
1165 uint32_t result;
1166
1167 __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
1168 return(result);
1169 }
1170 #endif
1171
1172
1173 /**
1174 \brief Set Fault Mask
1175 \details Assigns the given value to the Fault Mask register.
1176 \param [in] faultMask Fault Mask value to set
1177 */
__set_FAULTMASK(uint32_t faultMask)1178 __STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
1179 {
1180 __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
1181 }
1182
1183
1184 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
1185 /**
1186 \brief Set Fault Mask (non-secure)
1187 \details Assigns the given value to the non-secure Fault Mask register when in secure state.
1188 \param [in] faultMask Fault Mask value to set
1189 */
__TZ_set_FAULTMASK_NS(uint32_t faultMask)1190 __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
1191 {
1192 __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
1193 }
1194 #endif
1195
1196 #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
1197 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
1198 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
1199 (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */
1200
1201
1202 #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
1203 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \
1204 (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) )
1205
1206 /**
1207 \brief Get Process Stack Pointer Limit
1208 Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
1209 Stack Pointer Limit register hence zero is returned always in non-secure
1210 mode.
1211
1212 \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
1213 \return PSPLIM Register value
1214 */
__get_PSPLIM(void)1215 __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
1216 {
1217 #if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
1218 (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \
1219 (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
1220 // without main extensions, the non-secure PSPLIM is RAZ/WI
1221 return 0U;
1222 #else
1223 uint32_t result;
1224 __ASM volatile ("MRS %0, psplim" : "=r" (result) );
1225 return result;
1226 #endif
1227 }
1228
1229 #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
1230 /**
1231 \brief Get Process Stack Pointer Limit (non-secure)
1232 Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
1233 Stack Pointer Limit register hence zero is returned always in non-secure
1234 mode.
1235
1236 \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
1237 \return PSPLIM Register value
1238 */
__TZ_get_PSPLIM_NS(void)1239 __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
1240 {
1241 #if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
1242 (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) )
1243 // without main extensions, the non-secure PSPLIM is RAZ/WI
1244 return 0U;
1245 #else
1246 uint32_t result;
1247 __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
1248 return result;
1249 #endif
1250 }
1251 #endif
1252
1253
1254 /**
1255 \brief Set Process Stack Pointer Limit
1256 Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
1257 Stack Pointer Limit register hence the write is silently ignored in non-secure
1258 mode.
1259
1260 \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
1261 \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
1262 */
__set_PSPLIM(uint32_t ProcStackPtrLimit)1263 __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
1264 {
1265 #if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
1266 (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \
1267 (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
1268 // without main extensions, the non-secure PSPLIM is RAZ/WI
1269 (void)ProcStackPtrLimit;
1270 #else
1271 __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
1272 #endif
1273 }
1274
1275
1276 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
1277 /**
1278 \brief Set Process Stack Pointer (non-secure)
1279 Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
1280 Stack Pointer Limit register hence the write is silently ignored in non-secure
1281 mode.
1282
1283 \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
1284 \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
1285 */
__TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)1286 __STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
1287 {
1288 #if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
1289 (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) )
1290 // without main extensions, the non-secure PSPLIM is RAZ/WI
1291 (void)ProcStackPtrLimit;
1292 #else
1293 __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
1294 #endif
1295 }
1296 #endif
1297
1298
1299 /**
1300 \brief Get Main Stack Pointer Limit
1301 Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
1302 Stack Pointer Limit register hence zero is returned always.
1303
1304 \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
1305 \return MSPLIM Register value
1306 */
__get_MSPLIM(void)1307 __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
1308 {
1309 #if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
1310 (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \
1311 (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
1312 // without main extensions, the non-secure MSPLIM is RAZ/WI
1313 return 0U;
1314 #else
1315 uint32_t result;
1316 __ASM volatile ("MRS %0, msplim" : "=r" (result) );
1317 return result;
1318 #endif
1319 }
1320
1321
1322 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
1323 /**
1324 \brief Get Main Stack Pointer Limit (non-secure)
1325 Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
1326 Stack Pointer Limit register hence zero is returned always.
1327
1328 \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
1329 \return MSPLIM Register value
1330 */
__TZ_get_MSPLIM_NS(void)1331 __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
1332 {
1333 #if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
1334 (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) )
1335 // without main extensions, the non-secure MSPLIM is RAZ/WI
1336 return 0U;
1337 #else
1338 uint32_t result;
1339 __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
1340 return result;
1341 #endif
1342 }
1343 #endif
1344
1345
1346 /**
1347 \brief Set Main Stack Pointer Limit
1348 Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
1349 Stack Pointer Limit register hence the write is silently ignored.
1350
1351 \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
1352 \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
1353 */
__set_MSPLIM(uint32_t MainStackPtrLimit)1354 __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
1355 {
1356 #if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
1357 (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \
1358 (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
1359 // without main extensions, the non-secure MSPLIM is RAZ/WI
1360 (void)MainStackPtrLimit;
1361 #else
1362 __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
1363 #endif
1364 }
1365
1366
1367 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
1368 /**
1369 \brief Set Main Stack Pointer Limit (non-secure)
1370 Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
1371 Stack Pointer Limit register hence the write is silently ignored.
1372
1373 \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
1374 \param [in] MainStackPtrLimit Main Stack Pointer value to set
1375 */
__TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)1376 __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
1377 {
1378 #if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
1379 (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) )
1380 // without main extensions, the non-secure MSPLIM is RAZ/WI
1381 (void)MainStackPtrLimit;
1382 #else
1383 __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
1384 #endif
1385 }
1386 #endif
1387
1388 #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
1389 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \
1390 (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */
1391
1392 /**
1393 \brief Get FPSCR
1394 \details Returns the current value of the Floating Point Status/Control register.
1395 \return Floating Point Status/Control register value
1396 */
1397 #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
1398 (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
1399 #define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr
1400 #else
1401 #define __get_FPSCR() ((uint32_t)0U)
1402 #endif
1403
1404 /**
1405 \brief Set FPSCR
1406 \details Assigns the given value to the Floating Point Status/Control register.
1407 \param [in] fpscr Floating Point Status/Control value to set
1408 */
1409 #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
1410 (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
1411 #define __set_FPSCR __builtin_arm_set_fpscr
1412 #else
1413 #define __set_FPSCR(fpscr) ((void)(fpscr))
1414 #endif
1415
1416
1417 /** @} end of CMSIS_Core_RegAccFunctions */
1418
1419
1420 /* ################### Compiler specific Intrinsics ########################### */
1421 /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
1422 Access to dedicated SIMD instructions
1423 @{
1424 */
1425
1426 #if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
1427
1428 #define __SADD8 __builtin_arm_sadd8
1429 #define __QADD8 __builtin_arm_qadd8
1430 #define __SHADD8 __builtin_arm_shadd8
1431 #define __UADD8 __builtin_arm_uadd8
1432 #define __UQADD8 __builtin_arm_uqadd8
1433 #define __UHADD8 __builtin_arm_uhadd8
1434 #define __SSUB8 __builtin_arm_ssub8
1435 #define __QSUB8 __builtin_arm_qsub8
1436 #define __SHSUB8 __builtin_arm_shsub8
1437 #define __USUB8 __builtin_arm_usub8
1438 #define __UQSUB8 __builtin_arm_uqsub8
1439 #define __UHSUB8 __builtin_arm_uhsub8
1440 #define __SADD16 __builtin_arm_sadd16
1441 #define __QADD16 __builtin_arm_qadd16
1442 #define __SHADD16 __builtin_arm_shadd16
1443 #define __UADD16 __builtin_arm_uadd16
1444 #define __UQADD16 __builtin_arm_uqadd16
1445 #define __UHADD16 __builtin_arm_uhadd16
1446 #define __SSUB16 __builtin_arm_ssub16
1447 #define __QSUB16 __builtin_arm_qsub16
1448 #define __SHSUB16 __builtin_arm_shsub16
1449 #define __USUB16 __builtin_arm_usub16
1450 #define __UQSUB16 __builtin_arm_uqsub16
1451 #define __UHSUB16 __builtin_arm_uhsub16
1452 #define __SASX __builtin_arm_sasx
1453 #define __QASX __builtin_arm_qasx
1454 #define __SHASX __builtin_arm_shasx
1455 #define __UASX __builtin_arm_uasx
1456 #define __UQASX __builtin_arm_uqasx
1457 #define __UHASX __builtin_arm_uhasx
1458 #define __SSAX __builtin_arm_ssax
1459 #define __QSAX __builtin_arm_qsax
1460 #define __SHSAX __builtin_arm_shsax
1461 #define __USAX __builtin_arm_usax
1462 #define __UQSAX __builtin_arm_uqsax
1463 #define __UHSAX __builtin_arm_uhsax
1464 #define __USAD8 __builtin_arm_usad8
1465 #define __USADA8 __builtin_arm_usada8
1466 #define __SSAT16 __builtin_arm_ssat16
1467 #define __USAT16 __builtin_arm_usat16
1468 #define __UXTB16 __builtin_arm_uxtb16
1469 #define __UXTAB16 __builtin_arm_uxtab16
1470 #define __SXTB16 __builtin_arm_sxtb16
1471 #define __SXTAB16 __builtin_arm_sxtab16
1472 #define __SMUAD __builtin_arm_smuad
1473 #define __SMUADX __builtin_arm_smuadx
1474 #define __SMLAD __builtin_arm_smlad
1475 #define __SMLADX __builtin_arm_smladx
1476 #define __SMLALD __builtin_arm_smlald
1477 #define __SMLALDX __builtin_arm_smlaldx
1478 #define __SMUSD __builtin_arm_smusd
1479 #define __SMUSDX __builtin_arm_smusdx
1480 #define __SMLSD __builtin_arm_smlsd
1481 #define __SMLSDX __builtin_arm_smlsdx
1482 #define __SMLSLD __builtin_arm_smlsld
1483 #define __SMLSLDX __builtin_arm_smlsldx
1484 #define __SEL __builtin_arm_sel
1485 #define __QADD __builtin_arm_qadd
1486 #define __QSUB __builtin_arm_qsub
1487
1488 #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
1489 ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
1490
1491 #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
1492 ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
1493
1494 #define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2))
1495
1496 #define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3))
1497
__SMMLA(int32_t op1,int32_t op2,int32_t op3)1498 __STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
1499 {
1500 int32_t result;
1501
1502 __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
1503 return(result);
1504 }
1505
1506 #endif /* (__ARM_FEATURE_DSP == 1) */
1507 /** @} end of group CMSIS_SIMD_intrinsics */
1508
1509
1510 #endif /* __CMSIS_ARMCLANG_H */
1511