1 /**************************************************************************//**
2 * @file core_cm0.h
3 * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
4 * @version V5.1.0
5 * @date 04. April 2023
6 ******************************************************************************/
7 /*
8 * Copyright (c) 2009-2023 Arm Limited. All rights reserved.
9 *
10 * SPDX-License-Identifier: Apache-2.0
11 *
12 * Licensed under the Apache License, Version 2.0 (the License); you may
13 * not use this file except in compliance with the License.
14 * You may obtain a copy of the License at
15 *
16 * www.apache.org/licenses/LICENSE-2.0
17 *
18 * Unless required by applicable law or agreed to in writing, software
19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 * See the License for the specific language governing permissions and
22 * limitations under the License.
23 */
24
25 #if defined ( __ICCARM__ )
26 #pragma system_include /* treat file as system include file for MISRA check */
27 #elif defined (__clang__)
28 #pragma clang system_header /* treat file as system include file */
29 #endif
30
31 #ifndef __CORE_CM0_H_GENERIC
32 #define __CORE_CM0_H_GENERIC
33
34 #include <stdint.h>
35
36 #ifdef __cplusplus
37 extern "C" {
38 #endif
39
40 /**
41 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
42 CMSIS violates the following MISRA-C:2004 rules:
43
44 \li Required Rule 8.5, object/function definition in header file.<br>
45 Function definitions in header files are used to allow 'inlining'.
46
47 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
48 Unions are used for effective representation of core registers.
49
50 \li Advisory Rule 19.7, Function-like macro defined.<br>
51 Function-like macros are used to allow more efficient code.
52 */
53
54
55 /*******************************************************************************
56 * CMSIS definitions
57 ******************************************************************************/
58 /**
59 \ingroup Cortex_M0
60 @{
61 */
62
63 #include "cmsis_version.h"
64
65 /* CMSIS CM0 definitions */
66 #define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
67 #define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
68 #define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
69 __CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
70
71 #define __CORTEX_M (0U) /*!< Cortex-M Core */
72
73 /** __FPU_USED indicates whether an FPU is used or not.
74 This core does not support an FPU at all
75 */
76 #define __FPU_USED 0U
77
78 #if defined ( __CC_ARM )
79 #if defined __TARGET_FPU_VFP
80 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
81 #endif
82
83 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
84 #if defined __ARM_FP
85 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
86 #endif
87
88 #elif defined (__ti__)
89 #if defined __ARM_FP
90 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
91 #endif
92
93 #elif defined ( __GNUC__ )
94 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
95 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
96 #endif
97
98 #elif defined ( __ICCARM__ )
99 #if defined __ARMVFP__
100 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
101 #endif
102
103 #elif defined ( __TI_ARM__ )
104 #if defined __TI_VFP_SUPPORT__
105 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
106 #endif
107
108 #elif defined ( __TASKING__ )
109 #if defined __FPU_VFP__
110 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
111 #endif
112
113 #elif defined ( __CSMC__ )
114 #if ( __CSMC__ & 0x400U)
115 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
116 #endif
117
118 #endif
119
120 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
121
122
123 #ifdef __cplusplus
124 }
125 #endif
126
127 #endif /* __CORE_CM0_H_GENERIC */
128
129 #ifndef __CMSIS_GENERIC
130
131 #ifndef __CORE_CM0_H_DEPENDANT
132 #define __CORE_CM0_H_DEPENDANT
133
134 #ifdef __cplusplus
135 extern "C" {
136 #endif
137
138 /* check device defines and use defaults */
139 #if defined __CHECK_DEVICE_DEFINES
140 #ifndef __CM0_REV
141 #define __CM0_REV 0x0000U
142 #warning "__CM0_REV not defined in device header file; using default!"
143 #endif
144
145 #ifndef __NVIC_PRIO_BITS
146 #define __NVIC_PRIO_BITS 2U
147 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
148 #endif
149
150 #ifndef __Vendor_SysTickConfig
151 #define __Vendor_SysTickConfig 0U
152 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
153 #endif
154 #endif
155
156 /* IO definitions (access restrictions to peripheral registers) */
157 /**
158 \defgroup CMSIS_glob_defs CMSIS Global Defines
159
160 <strong>IO Type Qualifiers</strong> are used
161 \li to specify the access to peripheral variables.
162 \li for automatic generation of peripheral register debug information.
163 */
164 #ifdef __cplusplus
165 #define __I volatile /*!< Defines 'read only' permissions */
166 #else
167 #define __I volatile const /*!< Defines 'read only' permissions */
168 #endif
169 #define __O volatile /*!< Defines 'write only' permissions */
170 #define __IO volatile /*!< Defines 'read / write' permissions */
171
172 /* following defines should be used for structure members */
173 #define __IM volatile const /*! Defines 'read only' structure member permissions */
174 #define __OM volatile /*! Defines 'write only' structure member permissions */
175 #define __IOM volatile /*! Defines 'read / write' structure member permissions */
176
177 /*@} end of group Cortex_M0 */
178
179
180
181 /*******************************************************************************
182 * Register Abstraction
183 Core Register contain:
184 - Core Register
185 - Core NVIC Register
186 - Core SCB Register
187 - Core SysTick Register
188 ******************************************************************************/
189 /**
190 \defgroup CMSIS_core_register Defines and Type Definitions
191 \brief Type definitions and defines for Cortex-M processor based devices.
192 */
193
194 /**
195 \ingroup CMSIS_core_register
196 \defgroup CMSIS_CORE Status and Control Registers
197 \brief Core Register type definitions.
198 @{
199 */
200
201 /**
202 \brief Union type to access the Application Program Status Register (APSR).
203 */
204 typedef union
205 {
206 struct
207 {
208 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
209 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
210 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
211 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
212 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
213 } b; /*!< Structure used for bit access */
214 uint32_t w; /*!< Type used for word access */
215 } APSR_Type;
216
217 /* APSR Register Definitions */
218 #define APSR_N_Pos 31U /*!< APSR: N Position */
219 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
220
221 #define APSR_Z_Pos 30U /*!< APSR: Z Position */
222 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
223
224 #define APSR_C_Pos 29U /*!< APSR: C Position */
225 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
226
227 #define APSR_V_Pos 28U /*!< APSR: V Position */
228 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
229
230
231 /**
232 \brief Union type to access the Interrupt Program Status Register (IPSR).
233 */
234 typedef union
235 {
236 struct
237 {
238 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
239 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
240 } b; /*!< Structure used for bit access */
241 uint32_t w; /*!< Type used for word access */
242 } IPSR_Type;
243
244 /* IPSR Register Definitions */
245 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
246 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
247
248
249 /**
250 \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
251 */
252 typedef union
253 {
254 struct
255 {
256 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
257 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
258 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
259 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
260 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
261 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
262 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
263 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
264 } b; /*!< Structure used for bit access */
265 uint32_t w; /*!< Type used for word access */
266 } xPSR_Type;
267
268 /* xPSR Register Definitions */
269 #define xPSR_N_Pos 31U /*!< xPSR: N Position */
270 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
271
272 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
273 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
274
275 #define xPSR_C_Pos 29U /*!< xPSR: C Position */
276 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
277
278 #define xPSR_V_Pos 28U /*!< xPSR: V Position */
279 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
280
281 #define xPSR_T_Pos 24U /*!< xPSR: T Position */
282 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
283
284 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
285 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
286
287
288 /**
289 \brief Union type to access the Control Registers (CONTROL).
290 */
291 typedef union
292 {
293 struct
294 {
295 uint32_t _reserved0:1; /*!< bit: 0 Reserved */
296 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
297 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
298 } b; /*!< Structure used for bit access */
299 uint32_t w; /*!< Type used for word access */
300 } CONTROL_Type;
301
302 /* CONTROL Register Definitions */
303 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
304 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
305
306 /*@} end of group CMSIS_CORE */
307
308
309 /**
310 \ingroup CMSIS_core_register
311 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
312 \brief Type definitions for the NVIC Registers
313 @{
314 */
315
316 /**
317 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
318 */
319 typedef struct
320 {
321 __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
322 uint32_t RESERVED0[31U];
323 __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
324 uint32_t RESERVED1[31U];
325 __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
326 uint32_t RESERVED2[31U];
327 __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
328 uint32_t RESERVED3[31U];
329 uint32_t RESERVED4[64U];
330 __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
331 } NVIC_Type;
332
333 /*@} end of group CMSIS_NVIC */
334
335
336 /**
337 \ingroup CMSIS_core_register
338 \defgroup CMSIS_SCB System Control Block (SCB)
339 \brief Type definitions for the System Control Block Registers
340 @{
341 */
342
343 /**
344 \brief Structure type to access the System Control Block (SCB).
345 */
346 typedef struct
347 {
348 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
349 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
350 uint32_t RESERVED0;
351 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
352 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
353 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
354 uint32_t RESERVED1;
355 __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
356 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
357 } SCB_Type;
358
359 /* SCB CPUID Register Definitions */
360 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
361 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
362
363 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
364 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
365
366 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
367 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
368
369 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
370 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
371
372 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
373 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
374
375 /* SCB Interrupt Control State Register Definitions */
376 #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
377 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
378
379 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
380 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
381
382 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
383 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
384
385 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
386 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
387
388 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
389 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
390
391 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
392 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
393
394 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
395 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
396
397 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
398 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
399
400 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
401 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
402
403 /* SCB Application Interrupt and Reset Control Register Definitions */
404 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
405 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
406
407 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
408 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
409
410 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
411 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
412
413 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
414 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
415
416 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
417 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
418
419 /* SCB System Control Register Definitions */
420 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
421 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
422
423 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
424 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
425
426 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
427 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
428
429 /* SCB Configuration Control Register Definitions */
430 #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
431 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
432
433 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
434 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
435
436 /* SCB System Handler Control and State Register Definitions */
437 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
438 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
439
440 /*@} end of group CMSIS_SCB */
441
442
443 /**
444 \ingroup CMSIS_core_register
445 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
446 \brief Type definitions for the System Timer Registers.
447 @{
448 */
449
450 /**
451 \brief Structure type to access the System Timer (SysTick).
452 */
453 typedef struct
454 {
455 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
456 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
457 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
458 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
459 } SysTick_Type;
460
461 /* SysTick Control / Status Register Definitions */
462 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
463 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
464
465 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
466 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
467
468 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
469 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
470
471 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
472 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
473
474 /* SysTick Reload Register Definitions */
475 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
476 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
477
478 /* SysTick Current Register Definitions */
479 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
480 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
481
482 /* SysTick Calibration Register Definitions */
483 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
484 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
485
486 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
487 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
488
489 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
490 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
491
492 /*@} end of group CMSIS_SysTick */
493
494
495 /**
496 \ingroup CMSIS_core_register
497 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
498 \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
499 Therefore they are not covered by the Cortex-M0 header file.
500 @{
501 */
502 /*@} end of group CMSIS_CoreDebug */
503
504
505 /**
506 \ingroup CMSIS_core_register
507 \defgroup CMSIS_core_bitfield Core register bit field macros
508 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
509 @{
510 */
511
512 /**
513 \brief Mask and shift a bit field value for use in a register bit range.
514 \param[in] field Name of the register bit field.
515 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
516 \return Masked and shifted value.
517 */
518 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
519
520 /**
521 \brief Mask and shift a register value to extract a bit filed value.
522 \param[in] field Name of the register bit field.
523 \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
524 \return Masked and shifted bit field value.
525 */
526 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
527
528 /*@} end of group CMSIS_core_bitfield */
529
530
531 /**
532 \ingroup CMSIS_core_register
533 \defgroup CMSIS_core_base Core Definitions
534 \brief Definitions for base addresses, unions, and structures.
535 @{
536 */
537
538 /* Memory mapping of Core Hardware */
539 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
540 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
541 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
542 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
543
544 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
545 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
546 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
547
548
549 /*@} */
550
551
552
553 /*******************************************************************************
554 * Hardware Abstraction Layer
555 Core Function Interface contains:
556 - Core NVIC Functions
557 - Core SysTick Functions
558 - Core Register Access Functions
559 ******************************************************************************/
560 /**
561 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
562 */
563
564
565
566 /* ########################## NVIC functions #################################### */
567 /**
568 \ingroup CMSIS_Core_FunctionInterface
569 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
570 \brief Functions that manage interrupts and exceptions via the NVIC.
571 @{
572 */
573
574 #ifdef CMSIS_NVIC_VIRTUAL
575 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
576 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
577 #endif
578 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
579 #else
580 #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
581 #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
582 #define NVIC_EnableIRQ __NVIC_EnableIRQ
583 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
584 #define NVIC_DisableIRQ __NVIC_DisableIRQ
585 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
586 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
587 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
588 /*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */
589 #define NVIC_SetPriority __NVIC_SetPriority
590 #define NVIC_GetPriority __NVIC_GetPriority
591 #define NVIC_SystemReset __NVIC_SystemReset
592 #endif /* CMSIS_NVIC_VIRTUAL */
593
594 #ifdef CMSIS_VECTAB_VIRTUAL
595 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
596 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
597 #endif
598 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
599 #else
600 #define NVIC_SetVector __NVIC_SetVector
601 #define NVIC_GetVector __NVIC_GetVector
602 #endif /* (CMSIS_VECTAB_VIRTUAL) */
603
604 #define NVIC_USER_IRQ_OFFSET 16
605
606
607 /* The following EXC_RETURN values are saved the LR on exception entry */
608 #define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
609 #define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
610 #define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
611
612
613 /* Interrupt Priorities are WORD accessible only under Armv6-M */
614 /* The following MACROS handle generation of the register offset and byte masks */
615 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
616 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
617 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
618
619 #define __NVIC_SetPriorityGrouping(X) (void)(X)
620 #define __NVIC_GetPriorityGrouping() (0U)
621
622 /**
623 \brief Enable Interrupt
624 \details Enables a device specific interrupt in the NVIC interrupt controller.
625 \param [in] IRQn Device specific interrupt number.
626 \note IRQn must not be negative.
627 */
__NVIC_EnableIRQ(IRQn_Type IRQn)628 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
629 {
630 if ((int32_t)(IRQn) >= 0)
631 {
632 __COMPILER_BARRIER();
633 NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
634 __COMPILER_BARRIER();
635 }
636 }
637
638
639 /**
640 \brief Get Interrupt Enable status
641 \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
642 \param [in] IRQn Device specific interrupt number.
643 \return 0 Interrupt is not enabled.
644 \return 1 Interrupt is enabled.
645 \note IRQn must not be negative.
646 */
__NVIC_GetEnableIRQ(IRQn_Type IRQn)647 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
648 {
649 if ((int32_t)(IRQn) >= 0)
650 {
651 return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
652 }
653 else
654 {
655 return(0U);
656 }
657 }
658
659
660 /**
661 \brief Disable Interrupt
662 \details Disables a device specific interrupt in the NVIC interrupt controller.
663 \param [in] IRQn Device specific interrupt number.
664 \note IRQn must not be negative.
665 */
__NVIC_DisableIRQ(IRQn_Type IRQn)666 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
667 {
668 if ((int32_t)(IRQn) >= 0)
669 {
670 NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
671 __DSB();
672 __ISB();
673 }
674 }
675
676
677 /**
678 \brief Get Pending Interrupt
679 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
680 \param [in] IRQn Device specific interrupt number.
681 \return 0 Interrupt status is not pending.
682 \return 1 Interrupt status is pending.
683 \note IRQn must not be negative.
684 */
__NVIC_GetPendingIRQ(IRQn_Type IRQn)685 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
686 {
687 if ((int32_t)(IRQn) >= 0)
688 {
689 return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
690 }
691 else
692 {
693 return(0U);
694 }
695 }
696
697
698 /**
699 \brief Set Pending Interrupt
700 \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
701 \param [in] IRQn Device specific interrupt number.
702 \note IRQn must not be negative.
703 */
__NVIC_SetPendingIRQ(IRQn_Type IRQn)704 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
705 {
706 if ((int32_t)(IRQn) >= 0)
707 {
708 NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
709 }
710 }
711
712
713 /**
714 \brief Clear Pending Interrupt
715 \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
716 \param [in] IRQn Device specific interrupt number.
717 \note IRQn must not be negative.
718 */
__NVIC_ClearPendingIRQ(IRQn_Type IRQn)719 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
720 {
721 if ((int32_t)(IRQn) >= 0)
722 {
723 NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
724 }
725 }
726
727
728 /**
729 \brief Set Interrupt Priority
730 \details Sets the priority of a device specific interrupt or a processor exception.
731 The interrupt number can be positive to specify a device specific interrupt,
732 or negative to specify a processor exception.
733 \param [in] IRQn Interrupt number.
734 \param [in] priority Priority to set.
735 \note The priority cannot be set for every processor exception.
736 */
__NVIC_SetPriority(IRQn_Type IRQn,uint32_t priority)737 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
738 {
739 if ((int32_t)(IRQn) >= 0)
740 {
741 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
742 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
743 }
744 else
745 {
746 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
747 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
748 }
749 }
750
751
752 /**
753 \brief Get Interrupt Priority
754 \details Reads the priority of a device specific interrupt or a processor exception.
755 The interrupt number can be positive to specify a device specific interrupt,
756 or negative to specify a processor exception.
757 \param [in] IRQn Interrupt number.
758 \return Interrupt Priority.
759 Value is aligned automatically to the implemented priority bits of the microcontroller.
760 */
__NVIC_GetPriority(IRQn_Type IRQn)761 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
762 {
763
764 if ((int32_t)(IRQn) >= 0)
765 {
766 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
767 }
768 else
769 {
770 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
771 }
772 }
773
774
775 /**
776 \brief Encode Priority
777 \details Encodes the priority for an interrupt with the given priority group,
778 preemptive priority value, and subpriority value.
779 In case of a conflict between priority grouping and available
780 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
781 \param [in] PriorityGroup Used priority group.
782 \param [in] PreemptPriority Preemptive priority value (starting from 0).
783 \param [in] SubPriority Subpriority value (starting from 0).
784 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
785 */
NVIC_EncodePriority(uint32_t PriorityGroup,uint32_t PreemptPriority,uint32_t SubPriority)786 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
787 {
788 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
789 uint32_t PreemptPriorityBits;
790 uint32_t SubPriorityBits;
791
792 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
793 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
794
795 return (
796 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
797 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
798 );
799 }
800
801
802 /**
803 \brief Decode Priority
804 \details Decodes an interrupt priority value with a given priority group to
805 preemptive priority value and subpriority value.
806 In case of a conflict between priority grouping and available
807 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
808 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
809 \param [in] PriorityGroup Used priority group.
810 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
811 \param [out] pSubPriority Subpriority value (starting from 0).
812 */
NVIC_DecodePriority(uint32_t Priority,uint32_t PriorityGroup,uint32_t * const pPreemptPriority,uint32_t * const pSubPriority)813 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
814 {
815 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
816 uint32_t PreemptPriorityBits;
817 uint32_t SubPriorityBits;
818
819 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
820 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
821
822 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
823 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
824 }
825
826
827
828 /**
829 \brief Set Interrupt Vector
830 \details Sets an interrupt vector in SRAM based interrupt vector table.
831 The interrupt number can be positive to specify a device specific interrupt,
832 or negative to specify a processor exception.
833 Address 0 must be mapped to SRAM.
834 \param [in] IRQn Interrupt number
835 \param [in] vector Address of interrupt handler function
836 */
__NVIC_SetVector(IRQn_Type IRQn,uint32_t vector)837 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
838 {
839 uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */
840 *(vectors + (int32_t)IRQn) = vector; /* use pointer arithmetic to access vector */
841 /* ARM Application Note 321 states that the M0 does not require the architectural barrier */
842 }
843
844
845 /**
846 \brief Get Interrupt Vector
847 \details Reads an interrupt vector from interrupt vector table.
848 The interrupt number can be positive to specify a device specific interrupt,
849 or negative to specify a processor exception.
850 \param [in] IRQn Interrupt number.
851 \return Address of interrupt handler function
852 */
__NVIC_GetVector(IRQn_Type IRQn)853 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
854 {
855 uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */
856 return *(vectors + (int32_t)IRQn); /* use pointer arithmetic to access vector */
857 }
858
859
860 /**
861 \brief System Reset
862 \details Initiates a system reset request to reset the MCU.
863 */
__NVIC_SystemReset(void)864 __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
865 {
866 __DSB(); /* Ensure all outstanding memory accesses included
867 buffered write are completed before reset */
868 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
869 SCB_AIRCR_SYSRESETREQ_Msk);
870 __DSB(); /* Ensure completion of memory access */
871
872 for(;;) /* wait until reset */
873 {
874 __NOP();
875 }
876 }
877
878 /*@} end of CMSIS_Core_NVICFunctions */
879
880
881 /* ########################## FPU functions #################################### */
882 /**
883 \ingroup CMSIS_Core_FunctionInterface
884 \defgroup CMSIS_Core_FpuFunctions FPU Functions
885 \brief Function that provides FPU type.
886 @{
887 */
888
889 /**
890 \brief get FPU type
891 \details returns the FPU type
892 \returns
893 - \b 0: No FPU
894 - \b 1: Single precision FPU
895 - \b 2: Double + Single precision FPU
896 */
SCB_GetFPUType(void)897 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
898 {
899 return 0U; /* No FPU */
900 }
901
902
903 /*@} end of CMSIS_Core_FpuFunctions */
904
905
906
907 /* ################################## SysTick function ############################################ */
908 /**
909 \ingroup CMSIS_Core_FunctionInterface
910 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
911 \brief Functions that configure the System.
912 @{
913 */
914
915 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
916
917 /**
918 \brief System Tick Configuration
919 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
920 Counter is in free running mode to generate periodic interrupts.
921 \param [in] ticks Number of ticks between two interrupts.
922 \return 0 Function succeeded.
923 \return 1 Function failed.
924 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
925 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
926 must contain a vendor-specific implementation of this function.
927 */
SysTick_Config(uint32_t ticks)928 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
929 {
930 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
931 {
932 return (1UL); /* Reload value impossible */
933 }
934
935 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
936 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
937 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
938 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
939 SysTick_CTRL_TICKINT_Msk |
940 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
941 return (0UL); /* Function successful */
942 }
943
944 #endif
945
946 /*@} end of CMSIS_Core_SysTickFunctions */
947
948
949
950
951 #ifdef __cplusplus
952 }
953 #endif
954
955 #endif /* __CORE_CM0_H_DEPENDANT */
956
957 #endif /* __CMSIS_GENERIC */
958