1 /**************************************************************************//**
2 * @file core_cm4.h
3 * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File
4 * @version V5.2.0
5 * @date 04. April 2023
6 ******************************************************************************/
7 /*
8 * Copyright (c) 2009-2023 Arm Limited. All rights reserved.
9 *
10 * SPDX-License-Identifier: Apache-2.0
11 *
12 * Licensed under the Apache License, Version 2.0 (the License); you may
13 * not use this file except in compliance with the License.
14 * You may obtain a copy of the License at
15 *
16 * www.apache.org/licenses/LICENSE-2.0
17 *
18 * Unless required by applicable law or agreed to in writing, software
19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 * See the License for the specific language governing permissions and
22 * limitations under the License.
23 */
24
25 #if defined ( __ICCARM__ )
26 #pragma system_include /* treat file as system include file for MISRA check */
27 #elif defined (__clang__)
28 #pragma clang system_header /* treat file as system include file */
29 #endif
30
31 #ifndef __CORE_CM4_H_GENERIC
32 #define __CORE_CM4_H_GENERIC
33
34 #include <stdint.h>
35
36 #ifdef __cplusplus
37 extern "C" {
38 #endif
39
40 /**
41 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
42 CMSIS violates the following MISRA-C:2004 rules:
43
44 \li Required Rule 8.5, object/function definition in header file.<br>
45 Function definitions in header files are used to allow 'inlining'.
46
47 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
48 Unions are used for effective representation of core registers.
49
50 \li Advisory Rule 19.7, Function-like macro defined.<br>
51 Function-like macros are used to allow more efficient code.
52 */
53
54
55 /*******************************************************************************
56 * CMSIS definitions
57 ******************************************************************************/
58 /**
59 \ingroup Cortex_M4
60 @{
61 */
62
63 #include "cmsis_version.h"
64
65 /* CMSIS CM4 definitions */
66 #define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
67 #define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
68 #define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \
69 __CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
70
71 #define __CORTEX_M (4U) /*!< Cortex-M Core */
72
73 /** __FPU_USED indicates whether an FPU is used or not.
74 For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
75 */
76 #if defined ( __CC_ARM )
77 #if defined __TARGET_FPU_VFP
78 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
79 #define __FPU_USED 1U
80 #else
81 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
82 #define __FPU_USED 0U
83 #endif
84 #else
85 #define __FPU_USED 0U
86 #endif
87
88 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
89 #if defined __ARM_FP
90 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
91 #define __FPU_USED 1U
92 #else
93 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
94 #define __FPU_USED 0U
95 #endif
96 #else
97 #define __FPU_USED 0U
98 #endif
99
100 #elif defined (__ti__)
101 #if defined (__ARM_FP)
102 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
103 #define __FPU_USED 1U
104 #else
105 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
106 #define __FPU_USED 0U
107 #endif
108 #else
109 #define __FPU_USED 0U
110 #endif
111
112 #elif defined ( __GNUC__ )
113 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
114 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
115 #define __FPU_USED 1U
116 #else
117 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
118 #define __FPU_USED 0U
119 #endif
120 #else
121 #define __FPU_USED 0U
122 #endif
123
124 #elif defined ( __ICCARM__ )
125 #if defined __ARMVFP__
126 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
127 #define __FPU_USED 1U
128 #else
129 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
130 #define __FPU_USED 0U
131 #endif
132 #else
133 #define __FPU_USED 0U
134 #endif
135
136 #elif defined ( __TI_ARM__ )
137 #if defined __TI_VFP_SUPPORT__
138 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
139 #define __FPU_USED 1U
140 #else
141 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
142 #define __FPU_USED 0U
143 #endif
144 #else
145 #define __FPU_USED 0U
146 #endif
147
148 #elif defined ( __TASKING__ )
149 #if defined __FPU_VFP__
150 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
151 #define __FPU_USED 1U
152 #else
153 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
154 #define __FPU_USED 0U
155 #endif
156 #else
157 #define __FPU_USED 0U
158 #endif
159
160 #elif defined ( __CSMC__ )
161 #if ( __CSMC__ & 0x400U)
162 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
163 #define __FPU_USED 1U
164 #else
165 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
166 #define __FPU_USED 0U
167 #endif
168 #else
169 #define __FPU_USED 0U
170 #endif
171
172 #endif
173
174 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
175
176
177 #ifdef __cplusplus
178 }
179 #endif
180
181 #endif /* __CORE_CM4_H_GENERIC */
182
183 #ifndef __CMSIS_GENERIC
184
185 #ifndef __CORE_CM4_H_DEPENDANT
186 #define __CORE_CM4_H_DEPENDANT
187
188 #ifdef __cplusplus
189 extern "C" {
190 #endif
191
192 /* check device defines and use defaults */
193 #if defined __CHECK_DEVICE_DEFINES
194 #ifndef __CM4_REV
195 #define __CM4_REV 0x0000U
196 #warning "__CM4_REV not defined in device header file; using default!"
197 #endif
198
199 #ifndef __FPU_PRESENT
200 #define __FPU_PRESENT 0U
201 #warning "__FPU_PRESENT not defined in device header file; using default!"
202 #endif
203
204 #ifndef __MPU_PRESENT
205 #define __MPU_PRESENT 0U
206 #warning "__MPU_PRESENT not defined in device header file; using default!"
207 #endif
208
209 #ifndef __VTOR_PRESENT
210 #define __VTOR_PRESENT 1U
211 #warning "__VTOR_PRESENT not defined in device header file; using default!"
212 #endif
213
214 #ifndef __NVIC_PRIO_BITS
215 #define __NVIC_PRIO_BITS 3U
216 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
217 #endif
218
219 #ifndef __Vendor_SysTickConfig
220 #define __Vendor_SysTickConfig 0U
221 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
222 #endif
223 #endif
224
225 /* IO definitions (access restrictions to peripheral registers) */
226 /**
227 \defgroup CMSIS_glob_defs CMSIS Global Defines
228
229 <strong>IO Type Qualifiers</strong> are used
230 \li to specify the access to peripheral variables.
231 \li for automatic generation of peripheral register debug information.
232 */
233 #ifdef __cplusplus
234 #define __I volatile /*!< Defines 'read only' permissions */
235 #else
236 #define __I volatile const /*!< Defines 'read only' permissions */
237 #endif
238 #define __O volatile /*!< Defines 'write only' permissions */
239 #define __IO volatile /*!< Defines 'read / write' permissions */
240
241 /* following defines should be used for structure members */
242 #define __IM volatile const /*! Defines 'read only' structure member permissions */
243 #define __OM volatile /*! Defines 'write only' structure member permissions */
244 #define __IOM volatile /*! Defines 'read / write' structure member permissions */
245
246 /*@} end of group Cortex_M4 */
247
248
249
250 /*******************************************************************************
251 * Register Abstraction
252 Core Register contain:
253 - Core Register
254 - Core NVIC Register
255 - Core SCB Register
256 - Core SysTick Register
257 - Core Debug Register
258 - Core MPU Register
259 - Core FPU Register
260 ******************************************************************************/
261 /**
262 \defgroup CMSIS_core_register Defines and Type Definitions
263 \brief Type definitions and defines for Cortex-M processor based devices.
264 */
265
266 /**
267 \ingroup CMSIS_core_register
268 \defgroup CMSIS_CORE Status and Control Registers
269 \brief Core Register type definitions.
270 @{
271 */
272
273 /**
274 \brief Union type to access the Application Program Status Register (APSR).
275 */
276 typedef union
277 {
278 struct
279 {
280 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
281 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
282 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
283 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
284 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
285 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
286 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
287 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
288 } b; /*!< Structure used for bit access */
289 uint32_t w; /*!< Type used for word access */
290 } APSR_Type;
291
292 /* APSR Register Definitions */
293 #define APSR_N_Pos 31U /*!< APSR: N Position */
294 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
295
296 #define APSR_Z_Pos 30U /*!< APSR: Z Position */
297 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
298
299 #define APSR_C_Pos 29U /*!< APSR: C Position */
300 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
301
302 #define APSR_V_Pos 28U /*!< APSR: V Position */
303 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
304
305 #define APSR_Q_Pos 27U /*!< APSR: Q Position */
306 #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
307
308 #define APSR_GE_Pos 16U /*!< APSR: GE Position */
309 #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
310
311
312 /**
313 \brief Union type to access the Interrupt Program Status Register (IPSR).
314 */
315 typedef union
316 {
317 struct
318 {
319 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
320 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
321 } b; /*!< Structure used for bit access */
322 uint32_t w; /*!< Type used for word access */
323 } IPSR_Type;
324
325 /* IPSR Register Definitions */
326 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
327 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
328
329
330 /**
331 \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
332 */
333 typedef union
334 {
335 struct
336 {
337 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
338 uint32_t _reserved0:1; /*!< bit: 9 Reserved */
339 uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */
340 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
341 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
342 uint32_t T:1; /*!< bit: 24 Thumb bit */
343 uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */
344 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
345 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
346 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
347 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
348 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
349 } b; /*!< Structure used for bit access */
350 uint32_t w; /*!< Type used for word access */
351 } xPSR_Type;
352
353 /* xPSR Register Definitions */
354 #define xPSR_N_Pos 31U /*!< xPSR: N Position */
355 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
356
357 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
358 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
359
360 #define xPSR_C_Pos 29U /*!< xPSR: C Position */
361 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
362
363 #define xPSR_V_Pos 28U /*!< xPSR: V Position */
364 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
365
366 #define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
367 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
368
369 #define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */
370 #define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */
371
372 #define xPSR_T_Pos 24U /*!< xPSR: T Position */
373 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
374
375 #define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
376 #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
377
378 #define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */
379 #define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */
380
381 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
382 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
383
384
385 /**
386 \brief Union type to access the Control Registers (CONTROL).
387 */
388 typedef union
389 {
390 struct
391 {
392 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
393 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
394 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
395 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
396 } b; /*!< Structure used for bit access */
397 uint32_t w; /*!< Type used for word access */
398 } CONTROL_Type;
399
400 /* CONTROL Register Definitions */
401 #define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
402 #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
403
404 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
405 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
406
407 #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
408 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
409
410 /*@} end of group CMSIS_CORE */
411
412
413 /**
414 \ingroup CMSIS_core_register
415 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
416 \brief Type definitions for the NVIC Registers
417 @{
418 */
419
420 /**
421 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
422 */
423 typedef struct
424 {
425 __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
426 uint32_t RESERVED0[24U];
427 __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
428 uint32_t RESERVED1[24U];
429 __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
430 uint32_t RESERVED2[24U];
431 __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
432 uint32_t RESERVED3[24U];
433 __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
434 uint32_t RESERVED4[56U];
435 __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
436 uint32_t RESERVED5[644U];
437 __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
438 } NVIC_Type;
439
440 /* Software Triggered Interrupt Register Definitions */
441 #define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
442 #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
443
444 /*@} end of group CMSIS_NVIC */
445
446
447 /**
448 \ingroup CMSIS_core_register
449 \defgroup CMSIS_SCB System Control Block (SCB)
450 \brief Type definitions for the System Control Block Registers
451 @{
452 */
453
454 /**
455 \brief Structure type to access the System Control Block (SCB).
456 */
457 typedef struct
458 {
459 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
460 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
461 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
462 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
463 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
464 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
465 __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
466 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
467 __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
468 __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
469 __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
470 __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
471 __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
472 __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
473 __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
474 __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
475 __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
476 __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
477 __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
478 uint32_t RESERVED0[5U];
479 __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
480 } SCB_Type;
481
482 /* SCB CPUID Register Definitions */
483 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
484 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
485
486 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
487 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
488
489 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
490 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
491
492 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
493 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
494
495 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
496 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
497
498 /* SCB Interrupt Control State Register Definitions */
499 #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
500 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
501
502 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
503 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
504
505 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
506 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
507
508 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
509 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
510
511 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
512 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
513
514 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
515 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
516
517 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
518 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
519
520 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
521 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
522
523 #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
524 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
525
526 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
527 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
528
529 /* SCB Vector Table Offset Register Definitions */
530 #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
531 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
532
533 /* SCB Application Interrupt and Reset Control Register Definitions */
534 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
535 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
536
537 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
538 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
539
540 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
541 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
542
543 #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
544 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
545
546 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
547 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
548
549 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
550 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
551
552 #define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
553 #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
554
555 /* SCB System Control Register Definitions */
556 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
557 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
558
559 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
560 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
561
562 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
563 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
564
565 /* SCB Configuration Control Register Definitions */
566 #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
567 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
568
569 #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
570 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
571
572 #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
573 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
574
575 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
576 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
577
578 #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
579 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
580
581 #define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
582 #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
583
584 /* SCB System Handler Control and State Register Definitions */
585 #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
586 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
587
588 #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
589 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
590
591 #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
592 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
593
594 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
595 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
596
597 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
598 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
599
600 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
601 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
602
603 #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
604 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
605
606 #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
607 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
608
609 #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
610 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
611
612 #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
613 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
614
615 #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
616 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
617
618 #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
619 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
620
621 #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
622 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
623
624 #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
625 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
626
627 /* SCB Configurable Fault Status Register Definitions */
628 #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
629 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
630
631 #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
632 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
633
634 #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
635 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
636
637 /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
638 #define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
639 #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
640
641 #define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
642 #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
643
644 #define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
645 #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
646
647 #define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
648 #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
649
650 #define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
651 #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
652
653 #define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
654 #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
655
656 /* BusFault Status Register (part of SCB Configurable Fault Status Register) */
657 #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
658 #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
659
660 #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
661 #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
662
663 #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
664 #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
665
666 #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
667 #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
668
669 #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
670 #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
671
672 #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
673 #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
674
675 #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
676 #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
677
678 /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
679 #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
680 #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
681
682 #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
683 #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
684
685 #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
686 #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
687
688 #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
689 #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
690
691 #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
692 #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
693
694 #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
695 #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
696
697 /* SCB Hard Fault Status Register Definitions */
698 #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
699 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
700
701 #define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
702 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
703
704 #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
705 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
706
707 /* SCB Debug Fault Status Register Definitions */
708 #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
709 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
710
711 #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
712 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
713
714 #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
715 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
716
717 #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
718 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
719
720 #define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
721 #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
722
723 /*@} end of group CMSIS_SCB */
724
725
726 /**
727 \ingroup CMSIS_core_register
728 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
729 \brief Type definitions for the System Control and ID Register not in the SCB
730 @{
731 */
732
733 /**
734 \brief Structure type to access the System Control and ID Register not in the SCB.
735 */
736 typedef struct
737 {
738 uint32_t RESERVED0[1U];
739 __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
740 __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
741 } SCnSCB_Type;
742
743 /* Interrupt Controller Type Register Definitions */
744 #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
745 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
746
747 /* Auxiliary Control Register Definitions */
748 #define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */
749 #define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */
750
751 #define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */
752 #define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */
753
754 #define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */
755 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
756
757 #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */
758 #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
759
760 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
761 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
762
763 /*@} end of group CMSIS_SCnotSCB */
764
765
766 /**
767 \ingroup CMSIS_core_register
768 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
769 \brief Type definitions for the System Timer Registers.
770 @{
771 */
772
773 /**
774 \brief Structure type to access the System Timer (SysTick).
775 */
776 typedef struct
777 {
778 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
779 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
780 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
781 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
782 } SysTick_Type;
783
784 /* SysTick Control / Status Register Definitions */
785 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
786 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
787
788 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
789 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
790
791 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
792 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
793
794 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
795 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
796
797 /* SysTick Reload Register Definitions */
798 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
799 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
800
801 /* SysTick Current Register Definitions */
802 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
803 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
804
805 /* SysTick Calibration Register Definitions */
806 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
807 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
808
809 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
810 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
811
812 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
813 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
814
815 /*@} end of group CMSIS_SysTick */
816
817
818 /**
819 \ingroup CMSIS_core_register
820 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
821 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
822 @{
823 */
824
825 /**
826 \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
827 */
828 typedef struct
829 {
830 __OM union
831 {
832 __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
833 __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
834 __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
835 } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
836 uint32_t RESERVED0[864U];
837 __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
838 uint32_t RESERVED1[15U];
839 __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
840 uint32_t RESERVED2[15U];
841 __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
842 uint32_t RESERVED3[32U];
843 uint32_t RESERVED4[43U];
844 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
845 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
846 uint32_t RESERVED5[6U];
847 __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
848 __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
849 __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
850 __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
851 __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
852 __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
853 __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
854 __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
855 __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
856 __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
857 __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
858 __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
859 } ITM_Type;
860
861 /* ITM Trace Privilege Register Definitions */
862 #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
863 #define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
864
865 /* ITM Trace Control Register Definitions */
866 #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
867 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
868
869 #define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */
870 #define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */
871
872 #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
873 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
874
875 #define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPrescale Position */
876 #define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPrescale Mask */
877
878 #define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
879 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
880
881 #define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
882 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
883
884 #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
885 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
886
887 #define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
888 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
889
890 #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
891 #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
892
893 /* ITM Lock Status Register Definitions */
894 #define ITM_LSR_BYTEACC_Pos 2U /*!< ITM LSR: ByteAcc Position */
895 #define ITM_LSR_BYTEACC_Msk (1UL << ITM_LSR_BYTEACC_Pos) /*!< ITM LSR: ByteAcc Mask */
896
897 #define ITM_LSR_ACCESS_Pos 1U /*!< ITM LSR: Access Position */
898 #define ITM_LSR_ACCESS_Msk (1UL << ITM_LSR_ACCESS_Pos) /*!< ITM LSR: Access Mask */
899
900 #define ITM_LSR_PRESENT_Pos 0U /*!< ITM LSR: Present Position */
901 #define ITM_LSR_PRESENT_Msk (1UL /*<< ITM_LSR_PRESENT_Pos*/) /*!< ITM LSR: Present Mask */
902
903 /*@}*/ /* end of group CMSIS_ITM */
904
905
906 /**
907 \ingroup CMSIS_core_register
908 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
909 \brief Type definitions for the Data Watchpoint and Trace (DWT)
910 @{
911 */
912
913 /**
914 \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
915 */
916 typedef struct
917 {
918 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
919 __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
920 __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
921 __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
922 __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
923 __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
924 __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
925 __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
926 __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
927 __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
928 __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
929 uint32_t RESERVED0[1U];
930 __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
931 __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
932 __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
933 uint32_t RESERVED1[1U];
934 __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
935 __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
936 __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
937 uint32_t RESERVED2[1U];
938 __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
939 __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
940 __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
941 } DWT_Type;
942
943 /* DWT Control Register Definitions */
944 #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
945 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
946
947 #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
948 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
949
950 #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
951 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
952
953 #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
954 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
955
956 #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
957 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
958
959 #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
960 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
961
962 #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
963 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
964
965 #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
966 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
967
968 #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
969 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
970
971 #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
972 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
973
974 #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
975 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
976
977 #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
978 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
979
980 #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
981 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
982
983 #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
984 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
985
986 #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
987 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
988
989 #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
990 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
991
992 #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
993 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
994
995 #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
996 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
997
998 /* DWT CPI Count Register Definitions */
999 #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
1000 #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
1001
1002 /* DWT Exception Overhead Count Register Definitions */
1003 #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
1004 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
1005
1006 /* DWT Sleep Count Register Definitions */
1007 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
1008 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
1009
1010 /* DWT LSU Count Register Definitions */
1011 #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
1012 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
1013
1014 /* DWT Folded-instruction Count Register Definitions */
1015 #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
1016 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
1017
1018 /* DWT Comparator Mask Register Definitions */
1019 #define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
1020 #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
1021
1022 /* DWT Comparator Function Register Definitions */
1023 #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
1024 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
1025
1026 #define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
1027 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
1028
1029 #define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
1030 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
1031
1032 #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
1033 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
1034
1035 #define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
1036 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
1037
1038 #define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
1039 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
1040
1041 #define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
1042 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
1043
1044 #define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
1045 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
1046
1047 #define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
1048 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
1049
1050 /*@}*/ /* end of group CMSIS_DWT */
1051
1052
1053 /**
1054 \ingroup CMSIS_core_register
1055 \defgroup CMSIS_TPI Trace Port Interface (TPI)
1056 \brief Type definitions for the Trace Port Interface (TPI)
1057 @{
1058 */
1059
1060 /**
1061 \brief Structure type to access the Trace Port Interface Register (TPI).
1062 */
1063 typedef struct
1064 {
1065 __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
1066 __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
1067 uint32_t RESERVED0[2U];
1068 __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
1069 uint32_t RESERVED1[55U];
1070 __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
1071 uint32_t RESERVED2[131U];
1072 __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
1073 __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
1074 __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
1075 uint32_t RESERVED3[759U];
1076 __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
1077 __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
1078 __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
1079 uint32_t RESERVED4[1U];
1080 __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
1081 __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
1082 __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
1083 uint32_t RESERVED5[39U];
1084 __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
1085 __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
1086 uint32_t RESERVED7[8U];
1087 __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
1088 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
1089 } TPI_Type;
1090
1091 /* TPI Asynchronous Clock Prescaler Register Definitions */
1092 #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
1093 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
1094
1095 /* TPI Selected Pin Protocol Register Definitions */
1096 #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
1097 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
1098
1099 /* TPI Formatter and Flush Status Register Definitions */
1100 #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
1101 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
1102
1103 #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
1104 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
1105
1106 #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
1107 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
1108
1109 #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
1110 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
1111
1112 /* TPI Formatter and Flush Control Register Definitions */
1113 #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
1114 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
1115
1116 #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
1117 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
1118
1119 /* TPI TRIGGER Register Definitions */
1120 #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
1121 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
1122
1123 /* TPI Integration ETM Data Register Definitions (FIFO0) */
1124 #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
1125 #define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
1126
1127 #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
1128 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
1129
1130 #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
1131 #define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
1132
1133 #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
1134 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
1135
1136 #define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
1137 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
1138
1139 #define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
1140 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
1141
1142 #define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
1143 #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
1144
1145 /* TPI ITATBCTR2 Register Definitions */
1146 #define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */
1147 #define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */
1148
1149 #define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */
1150 #define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */
1151
1152 /* TPI Integration ITM Data Register Definitions (FIFO1) */
1153 #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
1154 #define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
1155
1156 #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
1157 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
1158
1159 #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
1160 #define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
1161
1162 #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
1163 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
1164
1165 #define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
1166 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
1167
1168 #define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
1169 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
1170
1171 #define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
1172 #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
1173
1174 /* TPI ITATBCTR0 Register Definitions */
1175 #define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */
1176 #define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */
1177
1178 #define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */
1179 #define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */
1180
1181 /* TPI Integration Mode Control Register Definitions */
1182 #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
1183 #define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
1184
1185 /* TPI DEVID Register Definitions */
1186 #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
1187 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
1188
1189 #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
1190 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
1191
1192 #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
1193 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
1194
1195 #define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
1196 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
1197
1198 #define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
1199 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
1200
1201 #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
1202 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
1203
1204 /* TPI DEVTYPE Register Definitions */
1205 #define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
1206 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
1207
1208 #define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
1209 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
1210
1211 /*@}*/ /* end of group CMSIS_TPI */
1212
1213
1214 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1215 /**
1216 \ingroup CMSIS_core_register
1217 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
1218 \brief Type definitions for the Memory Protection Unit (MPU)
1219 @{
1220 */
1221
1222 /**
1223 \brief Structure type to access the Memory Protection Unit (MPU).
1224 */
1225 typedef struct
1226 {
1227 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
1228 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
1229 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
1230 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
1231 __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
1232 __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
1233 __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
1234 __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
1235 __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
1236 __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
1237 __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
1238 } MPU_Type;
1239
1240 #define MPU_TYPE_RALIASES 4U
1241
1242 /* MPU Type Register Definitions */
1243 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
1244 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
1245
1246 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
1247 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
1248
1249 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
1250 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
1251
1252 /* MPU Control Register Definitions */
1253 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
1254 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
1255
1256 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
1257 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
1258
1259 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
1260 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
1261
1262 /* MPU Region Number Register Definitions */
1263 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
1264 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
1265
1266 /* MPU Region Base Address Register Definitions */
1267 #define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
1268 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
1269
1270 #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
1271 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
1272
1273 #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
1274 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
1275
1276 /* MPU Region Attribute and Size Register Definitions */
1277 #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
1278 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
1279
1280 #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
1281 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
1282
1283 #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
1284 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
1285
1286 #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
1287 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
1288
1289 #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
1290 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
1291
1292 #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
1293 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
1294
1295 #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
1296 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
1297
1298 #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
1299 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
1300
1301 #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
1302 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
1303
1304 #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
1305 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
1306
1307 /*@} end of group CMSIS_MPU */
1308 #endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
1309
1310
1311 /**
1312 \ingroup CMSIS_core_register
1313 \defgroup CMSIS_FPU Floating Point Unit (FPU)
1314 \brief Type definitions for the Floating Point Unit (FPU)
1315 @{
1316 */
1317
1318 /**
1319 \brief Structure type to access the Floating Point Unit (FPU).
1320 */
1321 typedef struct
1322 {
1323 uint32_t RESERVED0[1U];
1324 __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
1325 __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
1326 __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
1327 __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
1328 __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
1329 __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */
1330 } FPU_Type;
1331
1332 /* Floating-Point Context Control Register Definitions */
1333 #define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
1334 #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
1335
1336 #define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
1337 #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
1338
1339 #define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
1340 #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
1341
1342 #define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
1343 #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
1344
1345 #define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
1346 #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
1347
1348 #define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
1349 #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
1350
1351 #define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
1352 #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
1353
1354 #define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
1355 #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
1356
1357 #define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
1358 #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
1359
1360 /* Floating-Point Context Address Register Definitions */
1361 #define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
1362 #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
1363
1364 /* Floating-Point Default Status Control Register Definitions */
1365 #define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
1366 #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
1367
1368 #define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
1369 #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
1370
1371 #define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
1372 #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
1373
1374 #define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
1375 #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
1376
1377 /* Media and FP Feature Register 0 Definitions */
1378 #define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
1379 #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
1380
1381 #define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
1382 #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
1383
1384 #define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
1385 #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
1386
1387 #define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
1388 #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
1389
1390 #define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
1391 #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
1392
1393 #define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
1394 #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
1395
1396 #define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
1397 #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
1398
1399 #define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
1400 #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
1401
1402 /* Media and FP Feature Register 1 Definitions */
1403 #define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
1404 #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
1405
1406 #define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
1407 #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
1408
1409 #define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
1410 #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
1411
1412 #define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
1413 #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
1414
1415 /* Media and FP Feature Register 2 Definitions */
1416
1417 #define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */
1418 #define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */
1419
1420 /*@} end of group CMSIS_FPU */
1421
1422
1423 /**
1424 \ingroup CMSIS_core_register
1425 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
1426 \brief Type definitions for the Core Debug Registers
1427 @{
1428 */
1429
1430 /**
1431 \brief Structure type to access the Core Debug Register (CoreDebug).
1432 */
1433 typedef struct
1434 {
1435 __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
1436 __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
1437 __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
1438 __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
1439 } CoreDebug_Type;
1440
1441 /* Debug Halting Control and Status Register Definitions */
1442 #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
1443 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
1444
1445 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
1446 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
1447
1448 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
1449 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
1450
1451 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
1452 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
1453
1454 #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
1455 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
1456
1457 #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
1458 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
1459
1460 #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
1461 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
1462
1463 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
1464 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
1465
1466 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
1467 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
1468
1469 #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
1470 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
1471
1472 #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
1473 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
1474
1475 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
1476 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
1477
1478 /* Debug Core Register Selector Register Definitions */
1479 #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
1480 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
1481
1482 #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
1483 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
1484
1485 /* Debug Exception and Monitor Control Register Definitions */
1486 #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
1487 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
1488
1489 #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
1490 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
1491
1492 #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
1493 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
1494
1495 #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
1496 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
1497
1498 #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
1499 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
1500
1501 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
1502 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
1503
1504 #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
1505 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
1506
1507 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
1508 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
1509
1510 #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
1511 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
1512
1513 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
1514 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
1515
1516 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
1517 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
1518
1519 #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
1520 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
1521
1522 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
1523 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
1524
1525 /*@} end of group CMSIS_CoreDebug */
1526
1527
1528 /**
1529 \ingroup CMSIS_core_register
1530 \defgroup CMSIS_core_bitfield Core register bit field macros
1531 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
1532 @{
1533 */
1534
1535 /**
1536 \brief Mask and shift a bit field value for use in a register bit range.
1537 \param[in] field Name of the register bit field.
1538 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
1539 \return Masked and shifted value.
1540 */
1541 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
1542
1543 /**
1544 \brief Mask and shift a register value to extract a bit filed value.
1545 \param[in] field Name of the register bit field.
1546 \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
1547 \return Masked and shifted bit field value.
1548 */
1549 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
1550
1551 /*@} end of group CMSIS_core_bitfield */
1552
1553
1554 /**
1555 \ingroup CMSIS_core_register
1556 \defgroup CMSIS_core_base Core Definitions
1557 \brief Definitions for base addresses, unions, and structures.
1558 @{
1559 */
1560
1561 /* Memory mapping of Core Hardware */
1562 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
1563 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
1564 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
1565 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
1566 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
1567 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
1568 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
1569 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
1570
1571 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
1572 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
1573 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
1574 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
1575 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
1576 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
1577 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
1578 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
1579
1580 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1581 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
1582 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
1583 #endif
1584
1585 #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
1586 #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
1587
1588 /*@} */
1589
1590
1591 /**
1592 \ingroup CMSIS_core_register
1593 \defgroup CMSIS_register_aliases Backwards Compatibility Aliases
1594 \brief Register alias definitions for backwards compatibility.
1595 @{
1596 */
1597
1598 /* Capitalize ITM_TCR Register Definitions */
1599
1600 /* ITM Trace Control Register Definitions */
1601 #define ITM_TCR_TraceBusID_Pos (ITM_TCR_TRACEBUSID_Pos) /*!< \deprecated ITM_TCR_TraceBusID_Pos */
1602 #define ITM_TCR_TraceBusID_Msk (ITM_TCR_TRACEBUSID_Msk) /*!< \deprecated ITM_TCR_TraceBusID_Msk */
1603
1604 #define ITM_TCR_TSPrescale_Pos (ITM_TCR_TSPRESCALE_Pos) /*!< \deprecated ITM_TCR_TSPrescale_Pos */
1605 #define ITM_TCR_TSPrescale_Msk (ITM_TCR_TSPRESCALE_Msk) /*!< \deprecated ITM_TCR_TSPrescale_Msk */
1606
1607 /* ITM Lock Status Register Definitions */
1608 #define ITM_LSR_ByteAcc_Pos (ITM_LSR_BYTEACC_Pos) /*!< \deprecated ITM_LSR_ByteAcc_Pos */
1609 #define ITM_LSR_ByteAcc_Msk (ITM_LSR_BYTEACC_Msk) /*!< \deprecated ITM_LSR_ByteAcc_Msk */
1610
1611 #define ITM_LSR_Access_Pos (ITM_LSR_ACCESS_Pos) /*!< \deprecated ITM_LSR_Access_Pos */
1612 #define ITM_LSR_Access_Msk (ITM_LSR_ACCESS_Msk) /*!< \deprecated ITM_LSR_Access_Msk */
1613
1614 #define ITM_LSR_Present_Pos (ITM_LSR_PRESENT_Pos) /*!< \deprecated ITM_LSR_Present_Pos */
1615 #define ITM_LSR_Present_Msk (ITM_LSR_PRESENT_Msk) /*!< \deprecated ITM_LSR_Present_Msk */
1616
1617 /*@} */
1618
1619
1620
1621 /*******************************************************************************
1622 * Hardware Abstraction Layer
1623 Core Function Interface contains:
1624 - Core NVIC Functions
1625 - Core SysTick Functions
1626 - Core Debug Functions
1627 - Core Register Access Functions
1628 ******************************************************************************/
1629 /**
1630 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
1631 */
1632
1633
1634
1635 /* ########################## NVIC functions #################################### */
1636 /**
1637 \ingroup CMSIS_Core_FunctionInterface
1638 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
1639 \brief Functions that manage interrupts and exceptions via the NVIC.
1640 @{
1641 */
1642
1643 #ifdef CMSIS_NVIC_VIRTUAL
1644 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
1645 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
1646 #endif
1647 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
1648 #else
1649 #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
1650 #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
1651 #define NVIC_EnableIRQ __NVIC_EnableIRQ
1652 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
1653 #define NVIC_DisableIRQ __NVIC_DisableIRQ
1654 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
1655 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
1656 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
1657 #define NVIC_GetActive __NVIC_GetActive
1658 #define NVIC_SetPriority __NVIC_SetPriority
1659 #define NVIC_GetPriority __NVIC_GetPriority
1660 #define NVIC_SystemReset __NVIC_SystemReset
1661 #endif /* CMSIS_NVIC_VIRTUAL */
1662
1663 #ifdef CMSIS_VECTAB_VIRTUAL
1664 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
1665 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
1666 #endif
1667 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
1668 #else
1669 #define NVIC_SetVector __NVIC_SetVector
1670 #define NVIC_GetVector __NVIC_GetVector
1671 #endif /* (CMSIS_VECTAB_VIRTUAL) */
1672
1673 #define NVIC_USER_IRQ_OFFSET 16
1674
1675
1676 /* The following EXC_RETURN values are saved the LR on exception entry */
1677 #define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
1678 #define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
1679 #define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
1680 #define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */
1681 #define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */
1682 #define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */
1683
1684
1685 /**
1686 \brief Set Priority Grouping
1687 \details Sets the priority grouping field using the required unlock sequence.
1688 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
1689 Only values from 0..7 are used.
1690 In case of a conflict between priority grouping and available
1691 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
1692 \param [in] PriorityGroup Priority grouping field.
1693 */
__NVIC_SetPriorityGrouping(uint32_t PriorityGroup)1694 __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
1695 {
1696 uint32_t reg_value;
1697 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
1698
1699 reg_value = SCB->AIRCR; /* read old register configuration */
1700 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
1701 reg_value = (reg_value |
1702 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
1703 (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
1704 SCB->AIRCR = reg_value;
1705 }
1706
1707
1708 /**
1709 \brief Get Priority Grouping
1710 \details Reads the priority grouping field from the NVIC Interrupt Controller.
1711 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
1712 */
__NVIC_GetPriorityGrouping(void)1713 __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
1714 {
1715 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
1716 }
1717
1718
1719 /**
1720 \brief Enable Interrupt
1721 \details Enables a device specific interrupt in the NVIC interrupt controller.
1722 \param [in] IRQn Device specific interrupt number.
1723 \note IRQn must not be negative.
1724 */
__NVIC_EnableIRQ(IRQn_Type IRQn)1725 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
1726 {
1727 if ((int32_t)(IRQn) >= 0)
1728 {
1729 __COMPILER_BARRIER();
1730 NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1731 __COMPILER_BARRIER();
1732 }
1733 }
1734
1735
1736 /**
1737 \brief Get Interrupt Enable status
1738 \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
1739 \param [in] IRQn Device specific interrupt number.
1740 \return 0 Interrupt is not enabled.
1741 \return 1 Interrupt is enabled.
1742 \note IRQn must not be negative.
1743 */
__NVIC_GetEnableIRQ(IRQn_Type IRQn)1744 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
1745 {
1746 if ((int32_t)(IRQn) >= 0)
1747 {
1748 return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1749 }
1750 else
1751 {
1752 return(0U);
1753 }
1754 }
1755
1756
1757 /**
1758 \brief Disable Interrupt
1759 \details Disables a device specific interrupt in the NVIC interrupt controller.
1760 \param [in] IRQn Device specific interrupt number.
1761 \note IRQn must not be negative.
1762 */
__NVIC_DisableIRQ(IRQn_Type IRQn)1763 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
1764 {
1765 if ((int32_t)(IRQn) >= 0)
1766 {
1767 NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1768 __DSB();
1769 __ISB();
1770 }
1771 }
1772
1773
1774 /**
1775 \brief Get Pending Interrupt
1776 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
1777 \param [in] IRQn Device specific interrupt number.
1778 \return 0 Interrupt status is not pending.
1779 \return 1 Interrupt status is pending.
1780 \note IRQn must not be negative.
1781 */
__NVIC_GetPendingIRQ(IRQn_Type IRQn)1782 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
1783 {
1784 if ((int32_t)(IRQn) >= 0)
1785 {
1786 return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1787 }
1788 else
1789 {
1790 return(0U);
1791 }
1792 }
1793
1794
1795 /**
1796 \brief Set Pending Interrupt
1797 \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
1798 \param [in] IRQn Device specific interrupt number.
1799 \note IRQn must not be negative.
1800 */
__NVIC_SetPendingIRQ(IRQn_Type IRQn)1801 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
1802 {
1803 if ((int32_t)(IRQn) >= 0)
1804 {
1805 NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1806 }
1807 }
1808
1809
1810 /**
1811 \brief Clear Pending Interrupt
1812 \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
1813 \param [in] IRQn Device specific interrupt number.
1814 \note IRQn must not be negative.
1815 */
__NVIC_ClearPendingIRQ(IRQn_Type IRQn)1816 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
1817 {
1818 if ((int32_t)(IRQn) >= 0)
1819 {
1820 NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1821 }
1822 }
1823
1824
1825 /**
1826 \brief Get Active Interrupt
1827 \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
1828 \param [in] IRQn Device specific interrupt number.
1829 \return 0 Interrupt status is not active.
1830 \return 1 Interrupt status is active.
1831 \note IRQn must not be negative.
1832 */
__NVIC_GetActive(IRQn_Type IRQn)1833 __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
1834 {
1835 if ((int32_t)(IRQn) >= 0)
1836 {
1837 return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1838 }
1839 else
1840 {
1841 return(0U);
1842 }
1843 }
1844
1845
1846 /**
1847 \brief Set Interrupt Priority
1848 \details Sets the priority of a device specific interrupt or a processor exception.
1849 The interrupt number can be positive to specify a device specific interrupt,
1850 or negative to specify a processor exception.
1851 \param [in] IRQn Interrupt number.
1852 \param [in] priority Priority to set.
1853 \note The priority cannot be set for every processor exception.
1854 */
__NVIC_SetPriority(IRQn_Type IRQn,uint32_t priority)1855 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
1856 {
1857 if ((int32_t)(IRQn) >= 0)
1858 {
1859 NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
1860 }
1861 else
1862 {
1863 SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
1864 }
1865 }
1866
1867
1868 /**
1869 \brief Get Interrupt Priority
1870 \details Reads the priority of a device specific interrupt or a processor exception.
1871 The interrupt number can be positive to specify a device specific interrupt,
1872 or negative to specify a processor exception.
1873 \param [in] IRQn Interrupt number.
1874 \return Interrupt Priority.
1875 Value is aligned automatically to the implemented priority bits of the microcontroller.
1876 */
__NVIC_GetPriority(IRQn_Type IRQn)1877 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
1878 {
1879
1880 if ((int32_t)(IRQn) >= 0)
1881 {
1882 return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
1883 }
1884 else
1885 {
1886 return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
1887 }
1888 }
1889
1890
1891 /**
1892 \brief Encode Priority
1893 \details Encodes the priority for an interrupt with the given priority group,
1894 preemptive priority value, and subpriority value.
1895 In case of a conflict between priority grouping and available
1896 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
1897 \param [in] PriorityGroup Used priority group.
1898 \param [in] PreemptPriority Preemptive priority value (starting from 0).
1899 \param [in] SubPriority Subpriority value (starting from 0).
1900 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
1901 */
NVIC_EncodePriority(uint32_t PriorityGroup,uint32_t PreemptPriority,uint32_t SubPriority)1902 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
1903 {
1904 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
1905 uint32_t PreemptPriorityBits;
1906 uint32_t SubPriorityBits;
1907
1908 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
1909 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
1910
1911 return (
1912 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
1913 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
1914 );
1915 }
1916
1917
1918 /**
1919 \brief Decode Priority
1920 \details Decodes an interrupt priority value with a given priority group to
1921 preemptive priority value and subpriority value.
1922 In case of a conflict between priority grouping and available
1923 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
1924 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
1925 \param [in] PriorityGroup Used priority group.
1926 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
1927 \param [out] pSubPriority Subpriority value (starting from 0).
1928 */
NVIC_DecodePriority(uint32_t Priority,uint32_t PriorityGroup,uint32_t * const pPreemptPriority,uint32_t * const pSubPriority)1929 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
1930 {
1931 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
1932 uint32_t PreemptPriorityBits;
1933 uint32_t SubPriorityBits;
1934
1935 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
1936 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
1937
1938 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
1939 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
1940 }
1941
1942
1943 /**
1944 \brief Set Interrupt Vector
1945 \details Sets an interrupt vector in SRAM based interrupt vector table.
1946 The interrupt number can be positive to specify a device specific interrupt,
1947 or negative to specify a processor exception.
1948 VTOR must been relocated to SRAM before.
1949 \param [in] IRQn Interrupt number
1950 \param [in] vector Address of interrupt handler function
1951 */
__NVIC_SetVector(IRQn_Type IRQn,uint32_t vector)1952 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
1953 {
1954 uint32_t *vectors = (uint32_t *)SCB->VTOR;
1955 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
1956 /* ARM Application Note 321 states that the M4 does not require the architectural barrier */
1957 }
1958
1959
1960 /**
1961 \brief Get Interrupt Vector
1962 \details Reads an interrupt vector from interrupt vector table.
1963 The interrupt number can be positive to specify a device specific interrupt,
1964 or negative to specify a processor exception.
1965 \param [in] IRQn Interrupt number.
1966 \return Address of interrupt handler function
1967 */
__NVIC_GetVector(IRQn_Type IRQn)1968 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
1969 {
1970 uint32_t *vectors = (uint32_t *)SCB->VTOR;
1971 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
1972 }
1973
1974
1975 /**
1976 \brief System Reset
1977 \details Initiates a system reset request to reset the MCU.
1978 */
__NVIC_SystemReset(void)1979 __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
1980 {
1981 __DSB(); /* Ensure all outstanding memory accesses included
1982 buffered write are completed before reset */
1983 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
1984 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
1985 SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
1986 __DSB(); /* Ensure completion of memory access */
1987
1988 for(;;) /* wait until reset */
1989 {
1990 __NOP();
1991 }
1992 }
1993
1994 /*@} end of CMSIS_Core_NVICFunctions */
1995
1996
1997 /* ########################## MPU functions #################################### */
1998
1999 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
2000
2001 #include "mpu_armv7.h"
2002
2003 #endif
2004
2005
2006 /* ########################## FPU functions #################################### */
2007 /**
2008 \ingroup CMSIS_Core_FunctionInterface
2009 \defgroup CMSIS_Core_FpuFunctions FPU Functions
2010 \brief Function that provides FPU type.
2011 @{
2012 */
2013
2014 /**
2015 \brief get FPU type
2016 \details returns the FPU type
2017 \returns
2018 - \b 0: No FPU
2019 - \b 1: Single precision FPU
2020 - \b 2: Double + Single precision FPU
2021 */
SCB_GetFPUType(void)2022 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
2023 {
2024 uint32_t mvfr0;
2025
2026 mvfr0 = FPU->MVFR0;
2027 if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
2028 {
2029 return 1U; /* Single precision FPU */
2030 }
2031 else
2032 {
2033 return 0U; /* No FPU */
2034 }
2035 }
2036
2037
2038 /*@} end of CMSIS_Core_FpuFunctions */
2039
2040
2041
2042 /* ################################## SysTick function ############################################ */
2043 /**
2044 \ingroup CMSIS_Core_FunctionInterface
2045 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
2046 \brief Functions that configure the System.
2047 @{
2048 */
2049
2050 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
2051
2052 /**
2053 \brief System Tick Configuration
2054 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
2055 Counter is in free running mode to generate periodic interrupts.
2056 \param [in] ticks Number of ticks between two interrupts.
2057 \return 0 Function succeeded.
2058 \return 1 Function failed.
2059 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
2060 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
2061 must contain a vendor-specific implementation of this function.
2062 */
SysTick_Config(uint32_t ticks)2063 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
2064 {
2065 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
2066 {
2067 return (1UL); /* Reload value impossible */
2068 }
2069
2070 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
2071 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
2072 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
2073 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
2074 SysTick_CTRL_TICKINT_Msk |
2075 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
2076 return (0UL); /* Function successful */
2077 }
2078
2079 #endif
2080
2081 /*@} end of CMSIS_Core_SysTickFunctions */
2082
2083
2084
2085 /* ##################################### Debug In/Output function ########################################### */
2086 /**
2087 \ingroup CMSIS_Core_FunctionInterface
2088 \defgroup CMSIS_core_DebugFunctions ITM Functions
2089 \brief Functions that access the ITM debug interface.
2090 @{
2091 */
2092
2093 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
2094 #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
2095
2096
2097 /**
2098 \brief ITM Send Character
2099 \details Transmits a character via the ITM channel 0, and
2100 \li Just returns when no debugger is connected that has booked the output.
2101 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
2102 \param [in] ch Character to transmit.
2103 \returns Character to transmit.
2104 */
ITM_SendChar(uint32_t ch)2105 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
2106 {
2107 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
2108 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
2109 {
2110 while (ITM->PORT[0U].u32 == 0UL)
2111 {
2112 __NOP();
2113 }
2114 ITM->PORT[0U].u8 = (uint8_t)ch;
2115 }
2116 return (ch);
2117 }
2118
2119
2120 /**
2121 \brief ITM Receive Character
2122 \details Inputs a character via the external variable \ref ITM_RxBuffer.
2123 \return Received character.
2124 \return -1 No character pending.
2125 */
ITM_ReceiveChar(void)2126 __STATIC_INLINE int32_t ITM_ReceiveChar (void)
2127 {
2128 int32_t ch = -1; /* no character available */
2129
2130 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
2131 {
2132 ch = ITM_RxBuffer;
2133 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
2134 }
2135
2136 return (ch);
2137 }
2138
2139
2140 /**
2141 \brief ITM Check Character
2142 \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
2143 \return 0 No character available.
2144 \return 1 Character available.
2145 */
ITM_CheckChar(void)2146 __STATIC_INLINE int32_t ITM_CheckChar (void)
2147 {
2148
2149 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
2150 {
2151 return (0); /* no character available */
2152 }
2153 else
2154 {
2155 return (1); /* character available */
2156 }
2157 }
2158
2159 /*@} end of CMSIS_core_DebugFunctions */
2160
2161
2162
2163
2164 #ifdef __cplusplus
2165 }
2166 #endif
2167
2168 #endif /* __CORE_CM4_H_DEPENDANT */
2169
2170 #endif /* __CMSIS_GENERIC */
2171