1 /**************************************************************************//**
2 * @file core_sc000.h
3 * @brief CMSIS SC000 Core Peripheral Access Layer Header File
4 * @version V5.1.0
5 * @date 04. April 2023
6 ******************************************************************************/
7 /*
8 * Copyright (c) 2009-2023 Arm Limited. All rights reserved.
9 *
10 * SPDX-License-Identifier: Apache-2.0
11 *
12 * Licensed under the Apache License, Version 2.0 (the License); you may
13 * not use this file except in compliance with the License.
14 * You may obtain a copy of the License at
15 *
16 * www.apache.org/licenses/LICENSE-2.0
17 *
18 * Unless required by applicable law or agreed to in writing, software
19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 * See the License for the specific language governing permissions and
22 * limitations under the License.
23 */
24
25 #if defined ( __ICCARM__ )
26 #pragma system_include /* treat file as system include file for MISRA check */
27 #elif defined (__clang__)
28 #pragma clang system_header /* treat file as system include file */
29 #endif
30
31 #ifndef __CORE_SC000_H_GENERIC
32 #define __CORE_SC000_H_GENERIC
33
34 #include <stdint.h>
35
36 #ifdef __cplusplus
37 extern "C" {
38 #endif
39
40 /**
41 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
42 CMSIS violates the following MISRA-C:2004 rules:
43
44 \li Required Rule 8.5, object/function definition in header file.<br>
45 Function definitions in header files are used to allow 'inlining'.
46
47 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
48 Unions are used for effective representation of core registers.
49
50 \li Advisory Rule 19.7, Function-like macro defined.<br>
51 Function-like macros are used to allow more efficient code.
52 */
53
54
55 /*******************************************************************************
56 * CMSIS definitions
57 ******************************************************************************/
58 /**
59 \ingroup SC000
60 @{
61 */
62
63 #include "cmsis_version.h"
64
65 /* CMSIS SC000 definitions */
66 #define __SC000_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
67 #define __SC000_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
68 #define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \
69 __SC000_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
70
71 #define __CORTEX_SC (000U) /*!< Cortex secure core */
72
73 /** __FPU_USED indicates whether an FPU is used or not.
74 This core does not support an FPU at all
75 */
76 #define __FPU_USED 0U
77
78 #if defined ( __CC_ARM )
79 #if defined __TARGET_FPU_VFP
80 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
81 #endif
82
83 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
84 #if defined __ARM_FP
85 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
86 #endif
87
88 #elif defined (__ti__)
89 #if defined (__ARM_FP)
90 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
91 #endif
92
93 #elif defined ( __GNUC__ )
94 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
95 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
96 #endif
97
98 #elif defined ( __ICCARM__ )
99 #if defined __ARMVFP__
100 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
101 #endif
102
103 #elif defined ( __TI_ARM__ )
104 #if defined __TI_VFP_SUPPORT__
105 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
106 #endif
107
108 #elif defined ( __TASKING__ )
109 #if defined __FPU_VFP__
110 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
111 #endif
112
113 #elif defined ( __CSMC__ )
114 #if ( __CSMC__ & 0x400U)
115 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
116 #endif
117
118 #endif
119
120 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
121
122
123 #ifdef __cplusplus
124 }
125 #endif
126
127 #endif /* __CORE_SC000_H_GENERIC */
128
129 #ifndef __CMSIS_GENERIC
130
131 #ifndef __CORE_SC000_H_DEPENDANT
132 #define __CORE_SC000_H_DEPENDANT
133
134 #ifdef __cplusplus
135 extern "C" {
136 #endif
137
138 /* check device defines and use defaults */
139 #if defined __CHECK_DEVICE_DEFINES
140 #ifndef __SC000_REV
141 #define __SC000_REV 0x0000U
142 #warning "__SC000_REV not defined in device header file; using default!"
143 #endif
144
145 #ifndef __MPU_PRESENT
146 #define __MPU_PRESENT 0U
147 #warning "__MPU_PRESENT not defined in device header file; using default!"
148 #endif
149
150 #ifndef __VTOR_PRESENT
151 #define __VTOR_PRESENT 0U
152 #warning "__VTOR_PRESENT not defined in device header file; using default!"
153 #endif
154
155 #ifndef __NVIC_PRIO_BITS
156 #define __NVIC_PRIO_BITS 2U
157 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
158 #endif
159
160 #ifndef __Vendor_SysTickConfig
161 #define __Vendor_SysTickConfig 0U
162 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
163 #endif
164 #endif
165
166 /* IO definitions (access restrictions to peripheral registers) */
167 /**
168 \defgroup CMSIS_glob_defs CMSIS Global Defines
169
170 <strong>IO Type Qualifiers</strong> are used
171 \li to specify the access to peripheral variables.
172 \li for automatic generation of peripheral register debug information.
173 */
174 #ifdef __cplusplus
175 #define __I volatile /*!< Defines 'read only' permissions */
176 #else
177 #define __I volatile const /*!< Defines 'read only' permissions */
178 #endif
179 #define __O volatile /*!< Defines 'write only' permissions */
180 #define __IO volatile /*!< Defines 'read / write' permissions */
181
182 /* following defines should be used for structure members */
183 #define __IM volatile const /*! Defines 'read only' structure member permissions */
184 #define __OM volatile /*! Defines 'write only' structure member permissions */
185 #define __IOM volatile /*! Defines 'read / write' structure member permissions */
186
187 /*@} end of group SC000 */
188
189
190
191 /*******************************************************************************
192 * Register Abstraction
193 Core Register contain:
194 - Core Register
195 - Core NVIC Register
196 - Core SCB Register
197 - Core SysTick Register
198 - Core MPU Register
199 ******************************************************************************/
200 /**
201 \defgroup CMSIS_core_register Defines and Type Definitions
202 \brief Type definitions and defines for Cortex-M processor based devices.
203 */
204
205 /**
206 \ingroup CMSIS_core_register
207 \defgroup CMSIS_CORE Status and Control Registers
208 \brief Core Register type definitions.
209 @{
210 */
211
212 /**
213 \brief Union type to access the Application Program Status Register (APSR).
214 */
215 typedef union
216 {
217 struct
218 {
219 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
220 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
221 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
222 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
223 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
224 } b; /*!< Structure used for bit access */
225 uint32_t w; /*!< Type used for word access */
226 } APSR_Type;
227
228 /* APSR Register Definitions */
229 #define APSR_N_Pos 31U /*!< APSR: N Position */
230 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
231
232 #define APSR_Z_Pos 30U /*!< APSR: Z Position */
233 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
234
235 #define APSR_C_Pos 29U /*!< APSR: C Position */
236 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
237
238 #define APSR_V_Pos 28U /*!< APSR: V Position */
239 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
240
241
242 /**
243 \brief Union type to access the Interrupt Program Status Register (IPSR).
244 */
245 typedef union
246 {
247 struct
248 {
249 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
250 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
251 } b; /*!< Structure used for bit access */
252 uint32_t w; /*!< Type used for word access */
253 } IPSR_Type;
254
255 /* IPSR Register Definitions */
256 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
257 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
258
259
260 /**
261 \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
262 */
263 typedef union
264 {
265 struct
266 {
267 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
268 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
269 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
270 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
271 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
272 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
273 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
274 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
275 } b; /*!< Structure used for bit access */
276 uint32_t w; /*!< Type used for word access */
277 } xPSR_Type;
278
279 /* xPSR Register Definitions */
280 #define xPSR_N_Pos 31U /*!< xPSR: N Position */
281 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
282
283 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
284 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
285
286 #define xPSR_C_Pos 29U /*!< xPSR: C Position */
287 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
288
289 #define xPSR_V_Pos 28U /*!< xPSR: V Position */
290 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
291
292 #define xPSR_T_Pos 24U /*!< xPSR: T Position */
293 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
294
295 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
296 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
297
298
299 /**
300 \brief Union type to access the Control Registers (CONTROL).
301 */
302 typedef union
303 {
304 struct
305 {
306 uint32_t _reserved0:1; /*!< bit: 0 Reserved */
307 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
308 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
309 } b; /*!< Structure used for bit access */
310 uint32_t w; /*!< Type used for word access */
311 } CONTROL_Type;
312
313 /* CONTROL Register Definitions */
314 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
315 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
316
317 /*@} end of group CMSIS_CORE */
318
319
320 /**
321 \ingroup CMSIS_core_register
322 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
323 \brief Type definitions for the NVIC Registers
324 @{
325 */
326
327 /**
328 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
329 */
330 typedef struct
331 {
332 __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
333 uint32_t RESERVED0[31U];
334 __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
335 uint32_t RSERVED1[31U];
336 __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
337 uint32_t RESERVED2[31U];
338 __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
339 uint32_t RESERVED3[31U];
340 uint32_t RESERVED4[64U];
341 __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
342 } NVIC_Type;
343
344 /*@} end of group CMSIS_NVIC */
345
346
347 /**
348 \ingroup CMSIS_core_register
349 \defgroup CMSIS_SCB System Control Block (SCB)
350 \brief Type definitions for the System Control Block Registers
351 @{
352 */
353
354 /**
355 \brief Structure type to access the System Control Block (SCB).
356 */
357 typedef struct
358 {
359 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
360 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
361 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
362 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
363 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
364 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
365 uint32_t RESERVED0[1U];
366 __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
367 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
368 uint32_t RESERVED1[154U];
369 __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */
370 } SCB_Type;
371
372 /* SCB CPUID Register Definitions */
373 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
374 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
375
376 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
377 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
378
379 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
380 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
381
382 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
383 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
384
385 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
386 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
387
388 /* SCB Interrupt Control State Register Definitions */
389 #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
390 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
391
392 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
393 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
394
395 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
396 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
397
398 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
399 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
400
401 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
402 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
403
404 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
405 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
406
407 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
408 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
409
410 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
411 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
412
413 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
414 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
415
416 /* SCB Interrupt Control State Register Definitions */
417 #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
418 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
419
420 /* SCB Application Interrupt and Reset Control Register Definitions */
421 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
422 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
423
424 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
425 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
426
427 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
428 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
429
430 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
431 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
432
433 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
434 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
435
436 /* SCB System Control Register Definitions */
437 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
438 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
439
440 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
441 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
442
443 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
444 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
445
446 /* SCB Configuration Control Register Definitions */
447 #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
448 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
449
450 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
451 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
452
453 /* SCB System Handler Control and State Register Definitions */
454 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
455 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
456
457 /*@} end of group CMSIS_SCB */
458
459
460 /**
461 \ingroup CMSIS_core_register
462 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
463 \brief Type definitions for the System Control and ID Register not in the SCB
464 @{
465 */
466
467 /**
468 \brief Structure type to access the System Control and ID Register not in the SCB.
469 */
470 typedef struct
471 {
472 uint32_t RESERVED0[2U];
473 __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
474 } SCnSCB_Type;
475
476 /* Auxiliary Control Register Definitions */
477 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
478 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
479
480 /*@} end of group CMSIS_SCnotSCB */
481
482
483 /**
484 \ingroup CMSIS_core_register
485 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
486 \brief Type definitions for the System Timer Registers.
487 @{
488 */
489
490 /**
491 \brief Structure type to access the System Timer (SysTick).
492 */
493 typedef struct
494 {
495 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
496 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
497 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
498 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
499 } SysTick_Type;
500
501 /* SysTick Control / Status Register Definitions */
502 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
503 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
504
505 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
506 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
507
508 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
509 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
510
511 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
512 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
513
514 /* SysTick Reload Register Definitions */
515 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
516 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
517
518 /* SysTick Current Register Definitions */
519 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
520 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
521
522 /* SysTick Calibration Register Definitions */
523 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
524 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
525
526 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
527 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
528
529 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
530 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
531
532 /*@} end of group CMSIS_SysTick */
533
534 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
535 /**
536 \ingroup CMSIS_core_register
537 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
538 \brief Type definitions for the Memory Protection Unit (MPU)
539 @{
540 */
541
542 /**
543 \brief Structure type to access the Memory Protection Unit (MPU).
544 */
545 typedef struct
546 {
547 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
548 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
549 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
550 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
551 __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
552 } MPU_Type;
553
554 /* MPU Type Register Definitions */
555 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
556 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
557
558 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
559 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
560
561 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
562 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
563
564 /* MPU Control Register Definitions */
565 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
566 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
567
568 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
569 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
570
571 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
572 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
573
574 /* MPU Region Number Register Definitions */
575 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
576 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
577
578 /* MPU Region Base Address Register Definitions */
579 #define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */
580 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
581
582 #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
583 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
584
585 #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
586 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
587
588 /* MPU Region Attribute and Size Register Definitions */
589 #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
590 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
591
592 #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
593 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
594
595 #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
596 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
597
598 #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
599 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
600
601 #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
602 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
603
604 #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
605 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
606
607 #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
608 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
609
610 #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
611 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
612
613 #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
614 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
615
616 #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
617 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
618
619 /*@} end of group CMSIS_MPU */
620 #endif
621
622
623 /**
624 \ingroup CMSIS_core_register
625 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
626 \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
627 Therefore they are not covered by the SC000 header file.
628 @{
629 */
630 /*@} end of group CMSIS_CoreDebug */
631
632
633 /**
634 \ingroup CMSIS_core_register
635 \defgroup CMSIS_core_bitfield Core register bit field macros
636 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
637 @{
638 */
639
640 /**
641 \brief Mask and shift a bit field value for use in a register bit range.
642 \param[in] field Name of the register bit field.
643 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
644 \return Masked and shifted value.
645 */
646 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
647
648 /**
649 \brief Mask and shift a register value to extract a bit filed value.
650 \param[in] field Name of the register bit field.
651 \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
652 \return Masked and shifted bit field value.
653 */
654 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
655
656 /*@} end of group CMSIS_core_bitfield */
657
658
659 /**
660 \ingroup CMSIS_core_register
661 \defgroup CMSIS_core_base Core Definitions
662 \brief Definitions for base addresses, unions, and structures.
663 @{
664 */
665
666 /* Memory mapping of Core Hardware */
667 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
668 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
669 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
670 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
671
672 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
673 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
674 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
675 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
676
677 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
678 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
679 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
680 #endif
681
682 /*@} */
683
684
685
686 /*******************************************************************************
687 * Hardware Abstraction Layer
688 Core Function Interface contains:
689 - Core NVIC Functions
690 - Core SysTick Functions
691 - Core Register Access Functions
692 ******************************************************************************/
693 /**
694 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
695 */
696
697
698
699 /* ########################## NVIC functions #################################### */
700 /**
701 \ingroup CMSIS_Core_FunctionInterface
702 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
703 \brief Functions that manage interrupts and exceptions via the NVIC.
704 @{
705 */
706
707 #ifdef CMSIS_NVIC_VIRTUAL
708 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
709 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
710 #endif
711 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
712 #else
713 /*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */
714 /*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */
715 #define NVIC_EnableIRQ __NVIC_EnableIRQ
716 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
717 #define NVIC_DisableIRQ __NVIC_DisableIRQ
718 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
719 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
720 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
721 /*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */
722 #define NVIC_SetPriority __NVIC_SetPriority
723 #define NVIC_GetPriority __NVIC_GetPriority
724 #define NVIC_SystemReset __NVIC_SystemReset
725 #endif /* CMSIS_NVIC_VIRTUAL */
726
727 #ifdef CMSIS_VECTAB_VIRTUAL
728 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
729 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
730 #endif
731 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
732 #else
733 #define NVIC_SetVector __NVIC_SetVector
734 #define NVIC_GetVector __NVIC_GetVector
735 #endif /* (CMSIS_VECTAB_VIRTUAL) */
736
737 #define NVIC_USER_IRQ_OFFSET 16
738
739
740 /* The following EXC_RETURN values are saved the LR on exception entry */
741 #define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
742 #define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
743 #define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
744
745
746 /* Interrupt Priorities are WORD accessible only under Armv6-M */
747 /* The following MACROS handle generation of the register offset and byte masks */
748 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
749 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
750 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
751
752
753 /**
754 \brief Enable Interrupt
755 \details Enables a device specific interrupt in the NVIC interrupt controller.
756 \param [in] IRQn Device specific interrupt number.
757 \note IRQn must not be negative.
758 */
__NVIC_EnableIRQ(IRQn_Type IRQn)759 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
760 {
761 if ((int32_t)(IRQn) >= 0)
762 {
763 __COMPILER_BARRIER();
764 NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
765 __COMPILER_BARRIER();
766 }
767 }
768
769
770 /**
771 \brief Get Interrupt Enable status
772 \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
773 \param [in] IRQn Device specific interrupt number.
774 \return 0 Interrupt is not enabled.
775 \return 1 Interrupt is enabled.
776 \note IRQn must not be negative.
777 */
__NVIC_GetEnableIRQ(IRQn_Type IRQn)778 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
779 {
780 if ((int32_t)(IRQn) >= 0)
781 {
782 return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
783 }
784 else
785 {
786 return(0U);
787 }
788 }
789
790
791 /**
792 \brief Disable Interrupt
793 \details Disables a device specific interrupt in the NVIC interrupt controller.
794 \param [in] IRQn Device specific interrupt number.
795 \note IRQn must not be negative.
796 */
__NVIC_DisableIRQ(IRQn_Type IRQn)797 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
798 {
799 if ((int32_t)(IRQn) >= 0)
800 {
801 NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
802 __DSB();
803 __ISB();
804 }
805 }
806
807
808 /**
809 \brief Get Pending Interrupt
810 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
811 \param [in] IRQn Device specific interrupt number.
812 \return 0 Interrupt status is not pending.
813 \return 1 Interrupt status is pending.
814 \note IRQn must not be negative.
815 */
__NVIC_GetPendingIRQ(IRQn_Type IRQn)816 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
817 {
818 if ((int32_t)(IRQn) >= 0)
819 {
820 return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
821 }
822 else
823 {
824 return(0U);
825 }
826 }
827
828
829 /**
830 \brief Set Pending Interrupt
831 \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
832 \param [in] IRQn Device specific interrupt number.
833 \note IRQn must not be negative.
834 */
__NVIC_SetPendingIRQ(IRQn_Type IRQn)835 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
836 {
837 if ((int32_t)(IRQn) >= 0)
838 {
839 NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
840 }
841 }
842
843
844 /**
845 \brief Clear Pending Interrupt
846 \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
847 \param [in] IRQn Device specific interrupt number.
848 \note IRQn must not be negative.
849 */
__NVIC_ClearPendingIRQ(IRQn_Type IRQn)850 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
851 {
852 if ((int32_t)(IRQn) >= 0)
853 {
854 NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
855 }
856 }
857
858
859 /**
860 \brief Set Interrupt Priority
861 \details Sets the priority of a device specific interrupt or a processor exception.
862 The interrupt number can be positive to specify a device specific interrupt,
863 or negative to specify a processor exception.
864 \param [in] IRQn Interrupt number.
865 \param [in] priority Priority to set.
866 \note The priority cannot be set for every processor exception.
867 */
__NVIC_SetPriority(IRQn_Type IRQn,uint32_t priority)868 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
869 {
870 if ((int32_t)(IRQn) >= 0)
871 {
872 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
873 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
874 }
875 else
876 {
877 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
878 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
879 }
880 }
881
882
883 /**
884 \brief Get Interrupt Priority
885 \details Reads the priority of a device specific interrupt or a processor exception.
886 The interrupt number can be positive to specify a device specific interrupt,
887 or negative to specify a processor exception.
888 \param [in] IRQn Interrupt number.
889 \return Interrupt Priority.
890 Value is aligned automatically to the implemented priority bits of the microcontroller.
891 */
__NVIC_GetPriority(IRQn_Type IRQn)892 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
893 {
894
895 if ((int32_t)(IRQn) >= 0)
896 {
897 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
898 }
899 else
900 {
901 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
902 }
903 }
904
905
906 /**
907 \brief Set Interrupt Vector
908 \details Sets an interrupt vector in SRAM based interrupt vector table.
909 The interrupt number can be positive to specify a device specific interrupt,
910 or negative to specify a processor exception.
911 VTOR must been relocated to SRAM before.
912 \param [in] IRQn Interrupt number
913 \param [in] vector Address of interrupt handler function
914 */
__NVIC_SetVector(IRQn_Type IRQn,uint32_t vector)915 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
916 {
917 uint32_t *vectors = (uint32_t *)SCB->VTOR;
918 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
919 /* ARM Application Note 321 states that the M0 and M0+ do not require the architectural barrier - assume SC000 is the same */
920 }
921
922
923 /**
924 \brief Get Interrupt Vector
925 \details Reads an interrupt vector from interrupt vector table.
926 The interrupt number can be positive to specify a device specific interrupt,
927 or negative to specify a processor exception.
928 \param [in] IRQn Interrupt number.
929 \return Address of interrupt handler function
930 */
__NVIC_GetVector(IRQn_Type IRQn)931 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
932 {
933 uint32_t *vectors = (uint32_t *)SCB->VTOR;
934 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
935 }
936
937
938 /**
939 \brief System Reset
940 \details Initiates a system reset request to reset the MCU.
941 */
__NVIC_SystemReset(void)942 __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
943 {
944 __DSB(); /* Ensure all outstanding memory accesses included
945 buffered write are completed before reset */
946 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
947 SCB_AIRCR_SYSRESETREQ_Msk);
948 __DSB(); /* Ensure completion of memory access */
949
950 for(;;) /* wait until reset */
951 {
952 __NOP();
953 }
954 }
955
956 /*@} end of CMSIS_Core_NVICFunctions */
957
958
959 /* ########################## FPU functions #################################### */
960 /**
961 \ingroup CMSIS_Core_FunctionInterface
962 \defgroup CMSIS_Core_FpuFunctions FPU Functions
963 \brief Function that provides FPU type.
964 @{
965 */
966
967 /**
968 \brief get FPU type
969 \details returns the FPU type
970 \returns
971 - \b 0: No FPU
972 - \b 1: Single precision FPU
973 - \b 2: Double + Single precision FPU
974 */
SCB_GetFPUType(void)975 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
976 {
977 return 0U; /* No FPU */
978 }
979
980
981 /*@} end of CMSIS_Core_FpuFunctions */
982
983
984
985 /* ################################## SysTick function ############################################ */
986 /**
987 \ingroup CMSIS_Core_FunctionInterface
988 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
989 \brief Functions that configure the System.
990 @{
991 */
992
993 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
994
995 /**
996 \brief System Tick Configuration
997 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
998 Counter is in free running mode to generate periodic interrupts.
999 \param [in] ticks Number of ticks between two interrupts.
1000 \return 0 Function succeeded.
1001 \return 1 Function failed.
1002 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
1003 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
1004 must contain a vendor-specific implementation of this function.
1005 */
SysTick_Config(uint32_t ticks)1006 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
1007 {
1008 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
1009 {
1010 return (1UL); /* Reload value impossible */
1011 }
1012
1013 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
1014 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
1015 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
1016 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
1017 SysTick_CTRL_TICKINT_Msk |
1018 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
1019 return (0UL); /* Function successful */
1020 }
1021
1022 #endif
1023
1024 /*@} end of CMSIS_Core_SysTickFunctions */
1025
1026
1027
1028
1029 #ifdef __cplusplus
1030 }
1031 #endif
1032
1033 #endif /* __CORE_SC000_H_DEPENDANT */
1034
1035 #endif /* __CMSIS_GENERIC */
1036