1 /**************************************************************************//** 2 * @file system_ARMCM55.c 3 * @brief CMSIS Device System Source File for 4 * ARMCM55 Device 5 * @version V1.1.0 6 * @date 28. March 2022 7 ******************************************************************************/ 8 /* 9 * Copyright (c) 2009-2022 Arm Limited. All rights reserved. 10 * 11 * SPDX-License-Identifier: Apache-2.0 12 * 13 * Licensed under the Apache License, Version 2.0 (the License); you may 14 * not use this file except in compliance with the License. 15 * You may obtain a copy of the License at 16 * 17 * www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 21 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 */ 25 26 #if defined (ARMCM55) 27 #include "ARMCM55.h" 28 #else 29 #error device not specified! 30 #endif 31 32 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 33 #include "partition_ARMCM55.h" 34 #endif 35 36 /*---------------------------------------------------------------------------- 37 Define clocks 38 *----------------------------------------------------------------------------*/ 39 #define XTAL ( 5000000UL) /* Oscillator frequency */ 40 41 #define SYSTEM_CLOCK (5U * XTAL) 42 43 44 /*---------------------------------------------------------------------------- 45 Exception / Interrupt Vector table 46 *----------------------------------------------------------------------------*/ 47 extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; 48 49 50 /*---------------------------------------------------------------------------- 51 System Core Clock Variable 52 *----------------------------------------------------------------------------*/ 53 uint32_t SystemCoreClock = SYSTEM_CLOCK; 54 55 56 /*---------------------------------------------------------------------------- 57 System Core Clock update function 58 *----------------------------------------------------------------------------*/ SystemCoreClockUpdate(void)59void SystemCoreClockUpdate (void) 60 { 61 SystemCoreClock = SYSTEM_CLOCK; 62 } 63 64 /*---------------------------------------------------------------------------- 65 System initialization function 66 *----------------------------------------------------------------------------*/ SystemInit(void)67void SystemInit (void) 68 { 69 70 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) 71 SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]); 72 #endif 73 74 #if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \ 75 (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U)) 76 SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ 77 (3U << 11U*2U) ); /* enable CP11 Full Access */ 78 79 /* Set low-power state for PDEPU */ 80 /* 0b00 | ON, PDEPU is not in low-power state */ 81 /* 0b01 | ON, but the clock is off */ 82 /* 0b10 | RET(ention) */ 83 /* 0b11 | OFF */ 84 85 /* Clear ELPSTATE, value is 0b11 on Cold reset */ 86 PWRMODCTL->CPDLPSTATE &= ~(PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk); 87 88 /* Favor best FP/MVE performance by default, avoid EPU switch-ON delays */ 89 /* PDEPU ON, Clock OFF */ 90 PWRMODCTL->CPDLPSTATE |= 0x1 << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos; 91 #endif 92 93 #ifdef UNALIGNED_SUPPORT_DISABLE 94 SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; 95 #endif 96 97 /* Enable Loop and branch info cache */ 98 SCB->CCR |= SCB_CCR_LOB_Msk; 99 __DSB(); 100 __ISB(); 101 102 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 103 TZ_SAU_Setup(); 104 #endif 105 106 SystemCoreClock = SYSTEM_CLOCK; 107 } 108