%c Invalid Selection ************************************************** * PL_RAM test application * 1 - Fill and Read Addresses via the peripheral 2 - Write + Read one address via the peripheral Select a demo to run: ****************************** * Peripheral Self Test ****************************** User logic memory test... - local memory address is 0x%08x - write pattern to local BRAM and read back - write/read memory failed on address 0x%08x - write/read memory passed * Simple Self Test ((((( AAAAAA BBBBBB H t } } a   b , s < H F , i 1 o 1 ( d 8 H 2 | t t 0 0 8 8 H H P X d d , , x x  ~ } $ $} ( , 0 4 8 < @ D H L P ~ 8} T ~ \} X \ ` } d p t x | t (} ,} 0 4 8 < @ D P X P \ ` h l 0000000000000000 } ? $@ Y@ @ @ @ j @ .A cA A e A _ B vH7B mB @ 0 B B 4& k C 7y AC W4vC Ngm C = ` X C@ x DP KD M D J - D yCx D <3 # I9= D 2 [%Co d( 7y AC n F ? O8M2 0 Hw Z< s O u 00000000000000000123456789ABCDEF xuartps.c C (z U V HX 0z U U U { z { z St13bad_exception std::exception std::bad_exception N10__cxxabiv119__foreign_exceptionE { pz { U V U St9exception z U @V HX N10__cxxabiv115__forced_unwindE { 8z 0z @{ xV V j j d c X $W V { L{ { N10__cxxabiv120__si_class_type_infoE pure virtual method called deleted virtual method called { Ld ld j j d c d e 8d { { | N10__cxxabiv117__class_type_infoE { | St9type_info | j j j j `k j terminate called recursively terminate called after throwing an instance of ' ' terminate called without an active exception what(): _GLOBAL_ (anonymous namespace) string literal std auto li cl dt pt qu [abi: :: {default arg# %ld }:: JArray [] vtable for VTT for construction vtable for -in- typeinfo for typeinfo name for typeinfo fn for non-virtual thunk to covariant return thunk to java Class for guard variable for TLS init function for TLS wrapper function for reference temporary # hidden alias for non-transaction clone for _Sat _Accum _Fract , operator operator ad gs ix : new ul ll ull false true java resource decltype ( ... this {parm# global constructors keyed to global destructors keyed to {lambda( )# {unnamed type# [clone >( restrict volatile const && complex imaginary ::* __vector( std::allocator allocator std::basic_string basic_string std::string std::basic_string<char, std::char_traits<char>, std::allocator<char> > std::istream std::basic_istream<char, std::char_traits<char> > basic_istream std::ostream std::basic_ostream<char, std::char_traits<char> > basic_ostream std::iostream std::basic_iostream<char, std::char_traits<char> > basic_iostream aN &= aS = aa & an at alignof az cc const_cast () cm , co ~ dV /= da delete[] dc dynamic_cast de * dl delete ds .* . dv / eO ^= eo ^ eq == ge >= gt lS <<= <= operator"" ls << lt < mI -= mL *= mi - ml mm -- na new[] ne != nt ! nw new oR |= oo || | pL += pl + pm ->* pp ++ ps -> ? rM %= rS >>= rc reinterpret_cast rm % rs >> sc static_cast sizeof sz tr throw tw throw signed char bool boolean char byte double long double float __float128 unsigned char int unsigned int unsigned long unsigned long __int128 unsigned __int128 short unsigned short void wchar_t long long unsigned long long decimal32 decimal64 decimal128 half char16_t char32_t decltype(nullptr) INF inf NAN nan 0123456789abcdef (null) 0 Infinity NaN POSIX
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mfgpr(rn) ({unsigned int rval; __asm__ __volatile__( "mov %0,r" stringify(rn) "\n" : "=r" (rval) ); rval; }) XREG_FPSCR_QC (1 << 27) XPAR_PS7_UART_1_INTR XPS_UART1_INT_ID XPAR_PS7_SCUTIMER_0_INTR XPS_SCU_TMR_INT_ID XREG_CP15_CACHE_SIZE_ID "p15, 1, %0, c0, c0, 0" __UACCUM_FBIT__ 16 __APCS_32__ 1 __LFRACT_EPSILON__ 0x1P-31LR __FLOAT_WORD_ORDER__ __ORDER_LITTLE_ENDIAN__ __UINT_LEAST32_MAX__ 4294967295UL XPAR_XTTCPS_5_INTR XPS_TTC1_2_INT_ID __DBL_EPSILON__ double(2.2204460492503131e-16L) XPAR_PS7_GPIO_0_BASEADDR 0xE000A000 mfcpsr() ({unsigned int rval; __asm__ __volatile__( "mrs %0, cpsr\n" : "=r" (rval) ); rval; }) FALSE 0 XPAR_PS7_UART_0_INTR XPS_UART0_INT_ID USER_RO_THREAD_PID "p15, 0, %0, c13, c0, 3" __USACCUM_MIN__ 0.0UHK XPS_PMU0_INT_ID 37 _REENT_L64A_BUF(ptr) ((ptr)->_new._reent._l64a_buf) XPAR_PS7_QSPI_0_HIGHADDR 0xE000DFFF XST_BUFFER_TOO_SMALL 12L XPS_FPGA8_INT_ID 84 XPS_FPGA1_INT_ID 62 __UACCUM_IBIT__ 16 XUARTPS_TXWM_MASK 0x0000003F XREG_GPR10 r10 _LONG_LONG_TYPE long long XREG_FPSID_REV_MASK (0xF << FPSID_REV_BIT) XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV1 50 _REENT_CHECK_RAND48(ptr) XPS_DMA0_INT_ID 46 UINT_LEAST8_MAX 255 __FLT_MAX_10_EXP__ 38 XPAR_PS7_TTC_1_TTC_CLK_CLKSRC 0 XST_USB_ALREADY_CONFIGURED 1410 XUARTPS_MODEMCR_RTS 0x00000002 XREG_FPSCR_AHP (1 << 26) XREG_CP15_CONTROL_AFE_BIT 0x20000000 XPAR_XSLCR_0_DEVICE_ID 0 _VOID void INT_LEAST16_MAX 32767 XREG_CP5 5 XREG_CP15_DATA_SYNC_BARRIER "p15, 0, %0, c7, c10, 4" __have_longlong64 1 uartCfg XREG_CP15_CONTROL_TE_BIT 0x40000000 XUARTPS_IXR_RXFULL 0x00000004 XPAR_DDR_MEM_HIGHADDR 0x3FFFFFFF XUARTPS_IXR_DMS 0x00000200 __GNUCLIKE_BUILTIN_CONSTANT_P 1 XPS_SYS_CTRL_BASEADDR 0xF8000000 _EXFUN(name,proto) name proto XST_TMRCTR_TIMER_FAILED 1226 __printflike(fmtarg,firstvararg) __attribute__((__format__ (__printf__, fmtarg, firstvararg))) XPS_USB1_BASEADDR 0xE0003000 XREG_CP15_PERF_MONITOR_CTRL "p15, 0, %0, c9, c12, 0" XUARTPS_MR_PARITY_ODD 0x00000008 XREG_CP15_NS_ACCESS_CONTROL "p15, 0, %0, c1, c1, 2" XPS_DMA7_INT_ID 75 XREG_CP15_CLEAN_INVAL_DC_LINE_SW "p15, 0, %0, c7, c14, 2" __ULLFRACT_IBIT__ 0 XREG_GPR6 r6 __SA_FBIT__ 15 __DEC128_MIN_EXP__ (-6142) USER_RW_THREAD_PID "p15, 0, %0, c13, c0, 2" __UDA_FBIT__ 32 XIL_ASSERT_OCCURRED 1 XPS_DMA2_INT_ID 48 Xil_ExceptionEnable() Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ) XPAR_PS7_SD_0_HIGHADDR 0xE0100FFF XST_FR_TX_BUSY 1401 XREG_CP15_MEMORY_FEATURE_2 "p15, 0, %0, c0, c1, 6" __UINT64_TYPE__ long long unsigned int __DBL_MAX_10_EXP__ 308 __const const XPAR_PS7_USB_0_HIGHADDR 0xE0002FFF XPAR_SCUGIC_0_DIST_BASEADDR 0xF8F01000 XST_IS_STOPPED 24L __WCHAR_TYPE__ unsigned int __GNUCLIKE___TYPEOF 1 isascii(__c) ((unsigned)(__c)<=0177) __UDA_IBIT__ 32 XUARTPS_MODEMSR_DSR 0x00000020 __ELF__ 1 XREG_CP15_DOMAIN_ACCESS_CTRL "p15, 0, %0, c3, c0, 0" __SIZEOF_LONG__ 4 INT_FAST16_MIN (-__STDINT_EXP(INT_MAX)-1) XST_DEVICE_IS_STARTED 5L XPAR_PS7_GLOBALTIMER_0_S_AXI_BASEADDR 0xF8F00200 14XUartPs_Config XPAR_XUSBPS_0_HIGHADDR 0xE0002FFF XUARTPS_IXR_TOVR 0x00001000 XPAR_XTTCPS_1_INTR XPS_TTC0_1_INT_ID XPAR_XDMAPS_NUM_INSTANCES 2 XPAR_PS7_I2C_1_INTR XPS_I2C1_INT_ID XUartPs_ReadReg(BaseAddress,RegOffset) Xil_In32((BaseAddress) + (RegOffset)) __WCHAR_T__ XREG_CP15_INVAL_DTLB_ASID "p15, 0, %0, c8, c6, 2" XST_DEVICE_BLOCK_NOT_FOUND 3L __need___va_list XPS_QSPI_INT_ID 51 __UINT_LEAST64_TYPE__ long long unsigned int _Alignas(x) __aligned(x) XPS_FIQ_INT_ID 28 __P(protos) protos __INTPTR_TYPE__ int XPAR_XQSPIPS_0_INTR XPS_QSPI_INT_ID __DQ_FBIT__ 63 __DBL_HAS_INFINITY__ 1 ___int_least32_t_defined 1 XST_IIC_SELFTEST_FAILED 1076 __USFRACT_MAX__ 0XFFP-8UHR XPAR_CPU_ID 0 __FLT_HAS_INFINITY__ 1 XREG_CP15_NOP2 "p15, 0, %0, c7, c13, 1" __INT_LEAST16_MAX__ 32767 __INT_MAX__ 2147483647 clz(arg) ({unsigned char rval; __asm__ __volatile__( "clz %0,%1" : "=r" (rval) : "r" (arg) ); rval; }) __DEC64_MIN_EXP__ (-382) XPAR_XTTCPS_0_DEVICE_ID XPAR_PS7_TTC_0_DEVICE_ID XPAR_XIICPS_1_INTR XPS_I2C1_INT_ID tostring(s) #s XUARTPS_IXR_TNFUL 0x00000800 XPAR_XWDTPS_0_INTR XPS_WDT_INT_ID XREG_GPR4 r4 XREG_CP15_VA_TO_PA_OTHER_2 "p15, 0, %0, c7, c8, 6" XUARTPS_OPER_MODE_LOCAL_LOOP 0x02 XPAR_PS7_RAM_1_S_AXI_BASEADDR 0xFFFC0000 __predict_true(exp) __builtin_expect((exp), 1) XPAR_XQSPIPS_0_BASEADDR 0xE000D000 XIL_EXCEPTION_ID_DATA_ABORT_INT 4 XST_NOT_ENABLED 29L XPAR_PS7_I2C_0_INTR XPS_I2C0_INT_ID XUARTPS_BAUDGEN_DISABLE 0x00000000 XUARTPS_SR_RXOVR 0x00000001 XPS_TTC0_1_INT_ID 43 __aligned(x) __attribute__((__aligned__(x))) __lock_acquire(lock) (_CAST_VOID 0) XST_SPI_COMMAND_ERROR 1162 XUARTPS_MR_CHMODE_R_LOOP 0x00000300 XPAR_PS7_DDR_0_S_AXI_BASEADDR 0x00100000 _T_PTRDIFF_ XPS_AFI1_BASEADDR 0xF8009000 XREG_MVFR0_DP_MASK (0xF << XREG_MVFR0_DP_BIT) __unbounded XST_OPBARB_INVALID_PRIORITY 1176 __USFRACT_MIN__ 0.0UHR _WANT_REGISTER_FINI 1 XPAR_PS7_DMA_NS_DEVICE_ID 0 __GNUCLIKE_BUILTIN_VAALIST 1 XUARTPS_MR_STOPMODE_SHIFT 6 XPAR_PS7_AFI_1_S_AXI_BASEADDR 0xF8009000 _MB_LEN_MAX 1 XUARTPS_SR_RACTIVE 0x00000400 XPAR_XCANPS_0_INTR XPS_CAN0_INT_ID XIL_EXCEPTION_ID_FIQ_INT 6 XPAR_XTTCPS_2_BASEADDR 0xF8001008 _VA_LIST_DEFINED __DEC128_MANT_DIG__ 34 XREG_CP15_AUX_DATA_FAULT_STATUS "p15, 0, %0, c5, c1, 0" XPAR_XDMAPS_0_DONE_INTR_0 XPS_DMA0_INT_ID __wchar_t__ __ARM_NEON_FP 6 XREG_CPSR_FIQ_ENABLE 0x40 XREG_CP15_CONTROL_NMFI_BIT 0x08000000 XPAR_XTTCPS_0_CLOCK_HZ XPAR_XTTCPS_0_TTC_CLK_FREQ_HZ XREG_CP15_CONTROL_M_BIT 0x00000001 _REENT_WCSRTOMBS_STATE(ptr) ((ptr)->_new._reent._wcsrtombs_state) strncmpi strncasecmp XUARTPS_MR_STOPMODE_MASK 0x000000A0 __fastcall __attribute__((__fastcall__)) XPS_FPGA6_INT_ID 67 XPAR_PS7_SD_0_BASEADDR 0xE0100000 XPAR_XDMAPS_0_DEVICE_ID XPAR_PS7_DMA_NS_DEVICE_ID XPS_DMAC0_SEC_BASEADDR 0xF8003000 _NOINLINE __attribute__ ((__noinline__)) _XPARAMETERS_PS_H_ DeviceId __LLACCUM_MIN__ (-0X1P31LLK-0X1P31LLK) XUARTPS_EVENT_RECV_ERROR 4 __GCC_ATOMIC_CHAR_LOCK_FREE 2 __UINT_FAST16_TYPE__ unsigned int XREG_CP15_CONTROL_TRE_BIT 0x10000000 XPAR_PS7_AFI_0_S_AXI_HIGHADDR 0xF8008FFF XREG_MVFR0_SP_BIT (4) XST_IIC_DTR_READBACK_ERROR 1084 XPAR_XSPIPS_0_INTR XPS_SPI0_INT_ID XPAR_PS7_RAM_0_S_AXI_HIGHADDR 0x0003FFFF XREG_GPR2 r2 XPAR_PS7_AFI_3_S_AXI_BASEADDR 0xF800B000 __SIZEOF_INT__ 4 __ARMEL__ 1 XPAR_PS7_CAN_1_INTR XPS_CAN1_INT_ID XPAR_PS7_RAM_0_S_AXI_BASEADDR 0x00000000 __Static_assert(x,y) ___Static_assert(x, y) __SIG_ATOMIC_TYPE__ int XUartPs_Handler __GNUCLIKE_CTOR_SECTION_HANDLING 1 XPAR_PS7_ETHERNET_0_ENET_SLCR_1000MBPS_DIV0 8 XPAR_PS7_XADC_0_HIGHADDR 0xF8007120 XREG_CP15_INVAL_TLB_MVA_ASID_IS "p15, 0, %0, c8, c3, 3" XPAR_PS7_TTC_0_BASEADDR 0XF8001000 XPAR_PS7_DEV_CFG_0_DEVICE_ID 0 XREG_CP15_AUXILARY_ID "p15, 1, %0, c0, c0, 7" __UINT_LEAST64_MAX__ 18446744073709551615ULL XPAR_PS7_QSPI_LINEAR_0_S_AXI_HIGHADDR 0xFCFFFFFF __UINT16_C(c) c __PRAGMA_REDEFINE_EXTNAME 1 XREG_CP15_DATA_FAULT_ADDRESS "p15, 0, %0, c6, c0, 0" target_address XREG_FPSCR c1 _DEFUN_VOID(name) name(_NOARGS) XUARTPS_SR_DMS 0x00000200 INST_SYNC isb() XPAR_PS7_ETHERNET_0_ENET_CLK_FREQ_HZ 125000000 XST_SPI_MODE_FAULT 1151 __sym_compat(sym,impl,verid) __asm__(".symver " #impl ", " #sym "@" #verid) XREG_FPSID_VARIANT_BIT (4) XREG_CP15_VEC_BASE_ADDR "p15, 0, %0, c12, c0, 0" ___int_wchar_t_h __SYS_LOCK_H__ XREG_CP6 6 XREG_CP15_INVAL_DTLB_MVA "p15, 0, %0, c8, c6, 1" _REENT_CHECK_ASCTIME_BUF(ptr) __QQ_FBIT__ 7 Xil_Ntohs(Data) Xil_EndianSwap16(Data) __DEC128_EPSILON__ 1E-33DL XPAR_PS7_CORTEXA9_0_CPU_CLK_FREQ_HZ 666666687 XPS_SCU_PERIPH_BASE 0xF8F00000 INTPTR_MAX PTRDIFF_MAX XREG_CP15_VA_TO_PA_OTHER_0 "p15, 0, %0, c7, c8, 4" __va_list__ 7XUartPs __BIGGEST_ALIGNMENT__ 8 __UINT8_TYPE__ unsigned char UINT_FAST16_MAX (__STDINT_EXP(INT_MAX)*2U+1U) __UINT_FAST16_MAX__ 4294967295U XPAR_PS7_DMA_S_HIGHADDR 0xF8003FFF _REENT_MBLEN_STATE(ptr) ((ptr)->_new._reent._mblen_state) XST_DMA_SG_COUNT_EXCEEDED 521L XREG_CP15_INVAL_TLB_ASID_IS "p15, 0, %0, c8, c3, 2" __ULLACCUM_MAX__ 0XFFFFFFFFFFFFFFFFP-32ULLK INT_FAST32_MAX __STDINT_EXP(INT_MAX) Index XST_SUCCESS 0L __LOCK_INIT_RECURSIVE(class,lock) static int lock = 0; XUARTPS_IXR_RXEMPTY 0x00000002 XREG_GPR0 r0 XPAR_SCUGIC_0_DEVICE_ID 0 XPS_AFI2_BASEADDR 0xF800A000 XST_INTC_FAIL_SELFTEST 1201 XPAR_PS7_SCUGIC_0_DEVICE_ID 0 __FLT_DENORM_MIN__ 1.4012984643248171e-45F XPAR_PS7_GPIO_0_INTR XPS_GPIO_INT_ID __SACCUM_IBIT__ 8 _ANSIDECL_H_ __UINT16_TYPE__ short unsigned int XPAR_PS7_GPV_0_S_AXI_BASEADDR 0xF8900000 XPS_IOU_S_SWITCH_BASEADDR 0xE0000000 __UINT_LEAST8_MAX__ 255 __EXP ldr(adr) ({unsigned long rval; __asm__ __volatile__( "ldr %0,[%1]" : "=r" (rval) : "r" (adr) ); rval; }) _T_SIZE_ XPAR_XDMAPS_0_HIGHADDR 0xF8004FFF __ISO_C_VISIBLE 2011 XREG_CP15_CACHE_LEVEL_ID "p15, 1, %0, c0, c0, 1" __INTPTR_MAX__ 2147483647 XUARTPS_MR_OFFSET 0x04 INT_LEAST32_MAX 2147483647L XPS_SPI0_BASEADDR 0xE0006000 _ATEXIT_SIZE 32 XUARTPS_MR_STOPMODE_1_5_BIT 0x00000040 XST_SPI_NOT_MASTER 1157 XST_EMAC_COLLISION_ERROR 1007L XPAR_PS7_L2CACHEC_0_S_AXI_HIGHADDR 0xF8F02FFF XUARTPS_FLOWDEL_MASK XUARTPS_RXWM_MASK __INT8_C(c) c XPAR_SCUGIC_0_CPU_BASEADDR 0xF8F00100 __ARM_EABI__ 1 __inline inline __printf0like(fmtarg,firstvararg) XPS_FPGA_AXI_S0_BASEADDR 0x40000000 XUARTPS_IXR_TOUT 0x00000100 XPAR_PL_RAM_0_S_AXI_HIGHADDR 0x5FFFFFFF XREG_CP15_MEMORY_FEATURE_1 "p15, 0, %0, c0, c1, 5" __IEEE_LITTLE_ENDIAN __FLT_MAX_EXP__ 128 __DBL_MIN__ double(2.2250738585072014e-308L) __ATOMIC_SEQ_CST 5 stricmp strcasecmp _GCC_SIZE_T XPS_CAN0_INT_ID 60 _X 0100 _REENT_CHECK_SIGNAL_BUF(ptr) _L 02 XUARTPS_MR_PARITY_NONE 0x00000020 __DBL_MAX__ double(1.7976931348623157e+308L) XST_MEMTEST_FAILED 401L XPS_FPGA13_INT_ID 89 __CC_SUPPORTS_WARNING 1 XIL_EXCEPTION_ID_SWI_INT 2 Xil_AssertVoidAlways() { Xil_Assert(__FILE__, __LINE__); Xil_AssertStatus = XIL_ASSERT_OCCURRED; return; } __UINT_FAST8_TYPE__ unsigned int XIL_EXCEPTION_ID_INT XIL_EXCEPTION_ID_IRQ_INT XREG_FPSID_IMPLEMENTER_BIT (24) XREG_CP15_COUNT_ENABLE_CLR "p15, 0, %0, c9, c12, 2" __UTA_FBIT__ 64 __DBL_DIG__ 15 XREG_MVFR0_RMODE_BIT (28) __EXP(x) __ ##x ##__ __DECIMAL_DIG__ 17 XUARTPS_MR_PARITY_SHIFT 3 _NEWLIB_VERSION "2.0.0" __long_double_t long double XPAR_PS7_UART_1_HAS_MODEM 0 XPAR_PS7_USB_0_INTR XPS_USB0_INT_ID XPS_CAN1_BASEADDR 0xE0009000 __has_feature(x) 0 XPAR_XDCFG_NUM_INSTANCES 1 _REENT_EMERGENCY_SIZE 25 __UTA_IBIT__ 64 __RAND_MAX 0x7fffffff dmb() __asm__ __volatile__ ("dmb" : : : "memory") XPAR_PS7_PL310_0_S_AXI_BASEADDR 0xF8F02000 XREG_FPSCR_LENGTH_MASK (7 << FPSCR_LENGTH_BIT) XPS_WDT_BASEADDR 0xF8005000 XUARTPS_IXR_OVER 0x00000020 XST_FLASH_ERROR 1128L _CONST const XPAR_PS7_ETHERNET_0_ENET_SLCR_10MBPS_DIV1 50 __LFRACT_IBIT__ 0 ldrb(adr) ({unsigned char rval; __asm__ __volatile__( "ldrb %0,[%1]" : "=r" (rval) : "r" (adr) ); rval; }) __USER_LABEL_PREFIX__ __attribute_malloc__ _SIZE_T_DECLARED XST_FIFO_ERROR 7L XPAR_PS7_DMA_NS_BASEADDR 0xF8004000 XUARTPS_IXR_MASK 0x00001FFF XST_PLBARB_FAIL_SELFTEST 1276L XPAR_PS7_L2CACHEC_0_S_AXI_BASEADDR 0xF8F02000 _HAVE_STDC __QQ_IBIT__ 0 UINT16_MAX 65535 XPAR_PS7_XADC_0_BASEADDR 0xF8007100 __ARM_FEATURE_SIMD32 1 XPS_TTC0_0_INT_ID 42 XREG_CP15_INVAL_UTLB_ASID "p15, 0, %0, c8, c7, 2" XREG_CR9 cr9 __GNUC_PATCHLEVEL__ 1 __GCC_HAVE_SYNC_COMPARE_AND_SWAP_8 1 XPS_GEM1_BASEADDR 0xE000C000 XIL_EXCEPTION_IRQ XREG_CPSR_IRQ_ENABLE XUARTPS_MR_CHMODE_NORM 0x00000000 XREG_FPSID_ARCH_MASK (0xF << FPSID_ARCH_BIT) strcmpi strcasecmp __nonnull(x) __attribute__((__nonnull__(x))) XUARTPS_RXWM_OFFSET 0x20 __LDBL_MAX__ 1.7976931348623157e+308L XUARTPS_CR_TXRST 0x00000002 XPS_USB1_INT_ID 76 XST_PFIFO_LACK_OF_DATA 501L __LLACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LLK __LLFRACT_MIN__ (-0.5LLR-0.5LLR) XPAR_PS7_ETHERNET_0_ENET_SLCR_1000MBPS_DIV1 1 __LDBL_MIN_EXP__ (-1021) __DBL_MIN_10_EXP__ (-307) XST_IIC_TBA_REG_RESET_ERROR 1082 __UFRACT_MIN__ 0.0UR SLEEP_H _GCC_PTRDIFF_T XPS_SCU_TMR_INT_ID 29 __cplusplus 199711L __FLT_MIN_10_EXP__ (-37) __UINT32_MAX__ 4294967295UL XST_PFIFO_BAD_REG_VALUE 503L isb() __asm__ __volatile__ ("isb" : : : "memory") XREG_MVFR1 c6 XREG_CP15_CONTROL_HA_BIT 0x00020000 Xil_Ntohl(Data) Xil_EndianSwap32(Data) __UDQ_IBIT__ 0 XUARTPS_CR_TORST 0x00000040 __DBL_MANT_DIG__ 53 __SACCUM_MIN__ (-0X1P7HK-0X1P7HK) XREG_MVFR0_EXEC_TRAP_MASK (0xF << XREG_MVFR0_EXEC_TRAP_BIT) XPAR_PS7_PL310_0_S_AXI_HIGHADDR 0xF8F02FFF __FBSDID(s) struct __hack XPS_FPGA5_INT_ID 66 __ULLACCUM_MIN__ 0.0ULLK __INT_WCHAR_T_H Xil_In16LE(Addr) Xil_In16(Addr) XST_IIC_ADR_READBACK_ERROR 1086 XREG_CP7 7 __DEC32_EPSILON__ 1E-6DF XUARTPS_MODEMCR_OFFSET 0x24 XREG_MVFR0_DIVIDE_MASK (0xF << XREG_MVFR0_DIVIDE_BIT) _WCHAR_T_DEFINED __INT_FAST8_MAX__ 2147483647 XPAR_XUARTPS_0_DEVICE_ID XPAR_PS7_UART_1_DEVICE_ID __size_t XUartPs_EnableUart(InstancePtr) Xil_Out32(((InstancePtr)->Config.BaseAddress + XUARTPS_CR_OFFSET), ((Xil_In32((InstancePtr)->Config.BaseAddress + XUARTPS_CR_OFFSET) & ~XUARTPS_CR_EN_DIS_MASK) | (XUARTPS_CR_RX_EN | XUARTPS_CR_TX_EN))) XREG_CP15_INVAL_BRANCH_ARRAY_IS "p15, 0, %0, c7, c1, 6" XPAR_DDR_MEM_BASEADDR 0x00000000 UINT8_C(x) x Xil_AssertNonvoid(Expression) { if (Expression) { Xil_AssertStatus = XIL_ASSERT_NONE; } else { Xil_Assert(__FILE__, __LINE__); Xil_AssertStatus = XIL_ASSERT_OCCURRED; return 0; } } XREG_CP15_INVAL_IC_POU_IS "p15, 0, %0, c7, c1, 0" XREG_FPSID_SOFTWARE (1<<23) XPAR_PS7_DDRC_0_S_AXI_BASEADDR 0xF8006000 __GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1 __UINT32_TYPE__ long unsigned int XST_INVALID_PARAM 15L __FLT_EPSILON__ 1.1920928955078125e-7F __GNUCLIKE___OFFSETOF 1 __USA_IBIT__ 16 XST_DMA_BD_ERROR 527L __UINT8_C(c) c XST_DMA_SG_IS_STARTED 514L __CC_SUPPORTS_INLINE 1 XPAR_PS7_QSPI_0_QSPI_MODE 0 XST_DMA_SG_NOTHING_TO_COMMIT 519L TRUE 1 XREG_CP15_INVAL_IC_LINE_MVA_POU "p15, 0, %0, c7, c5, 1" XST_PLB2OPB_FAIL_SELFTEST 1301L __ULFRACT_MAX__ 0XFFFFFFFFP-32ULR XPS_WDT_INT_ID 41 XST_DMA_SG_IS_STOPPED 515L __flexarr [0] __GNUG__ 4 _REENT_RAND48_ADD(ptr) ((ptr)->_new._reent._r48._add) XPAR_XDCFG_0_BASEADDR 0xF8007000 __ULLFRACT_MIN__ 0.0ULLR XPS_IRQ_INT_ID 31 XREG_FPSID c0 XST_UART_START_ERROR 1052L XUARTPS_TXWM_OFFSET 0x44 _RAND48_SEED_0 (0x330e) XREG_CP15_CLEAN_DC_LINE_MVA_POC "p15, 0, %0, c7, c10, 1" __LONG_LONG_MAX__ 9223372036854775807LL _SYS_REENT_H_ _VOLATILE volatile cpsidi() __asm__ __volatile__("cpsid i\n") __ORDER_LITTLE_ENDIAN__ 1234 _REENT_SIGNGAM(ptr) ((ptr)->_new._reent._gamma_signgam) XPAR_PS7_PMU_0_PMU1_S_AXI_HIGHADDR 0xF8893FFF XPAR_PS7_OCMC_0_S_AXI_BASEADDR 0xF800C000 __strong_reference(sym,aliassym) extern __typeof (sym) aliassym __attribute__ ((__alias__ (#sym))) XST_SPI_TRANSMIT_UNDERRUN 1153 XPS_DMA3_INT_ID 49 __FLT_DIG__ 6 __INT_LEAST64_MAX__ 9223372036854775807LL XREG_CP15_AUX_CONTROL "p15, 0, %0, c1, c0, 1" XUARTPS_MAX_RATE 921600 __DBL_MAX_EXP__ 1024 XREG_CP15_INVAL_TLB_IS "p15, 0, %0, c8, c3, 0" XPAR_XUSBPS_NUM_INSTANCES 1 unsigned signed XREG_CP15_SYS_CONTROL "p15, 0, %0, c1, c0, 0" XUARTPS_IDR_OFFSET 0x0C SIG_ATOMIC_MAX __STDINT_EXP(INT_MAX) XST_EMAC_PARSE_ERROR 1006L _REENT_STRTOK_LAST(ptr) ((ptr)->_new._reent._strtok_last) __EXCEPTIONS 1 __GNUCLIKE___SECTION 1 XUINT64_LSW(x) ((x).Lower) __SIZEOF_SIZE_T__ 4 XREG_CP15_CP_ACCESS_CONTROL "p15, 0, %0, c1, c0, 2" __DEC128_MAX__ 9.999999999999999999999999999999999E6144DL XREG_CP15_CACHE_TYPE "p15, 0, %0, c0, c0, 1" __INT_FAST16_TYPE__ int XUartPs_WriteReg(BaseAddress,RegOffset,RegisterValue) Xil_Out32((BaseAddress) + (RegOffset), (RegisterValue)) __LLFRACT_MAX__ 0X7FFFFFFFFFFFFFFFP-63LLR XPAR_PS7_SCUTIMER_0_HIGHADDR 0xF8F0061F XREG_CP15_CONTROL_Z_BIT 0x00000800 XUartPs_IsReceiveData(BaseAddress) !((Xil_In32((BaseAddress) + XUARTPS_SR_OFFSET) & XUARTPS_SR_RXEMPTY) == XUARTPS_SR_RXEMPTY) INT_FAST16_MAX __STDINT_EXP(INT_MAX) HAVE_INITFINI_ARRAY 1 XUARTPS_MR_CHARLEN_MASK 0x00000006 XREG_CP15_MAIN_TLB_VA "p15, 5, %0, c15, c5, 2" XREG_GPR14 r14 __format_arg(fmtarg) __attribute__((__format_arg__ (fmtarg))) XUARTPS_RXWM_RESET_VAL 0x00000020 XPS_DMA4_INT_ID 72 __WINT_MAX__ 4294967295U XPAR_XPARPORTPS_CTRL_BASEADDR XPS_PARPORT_CRTL_BASEADDR XPAR_XEMACPS_1_INTR XPS_GEM1_INT_ID __UACCUM_EPSILON__ 0x1P-16UK XST_NAND_OPT_NOT_SUPPORTED 1445L XREG_FPEXC_EX (1 << 31) __SFRACT_FBIT__ 7 __LLACCUM_EPSILON__ 0x1P-31LLK XST_NOT_SGDMA 16L PTRDIFF_MIN (-PTRDIFF_MAX - 1) XUARTPS_SR_TTRIG 0x00002000 __DBL_DECIMAL_DIG__ 17 __SIZEOF_LONG_LONG__ 8 XREG_FPSID_IMPLEMENTER_MASK (0xFF << FPSID_IMPLEMENTER_BIT) __INT_LEAST64_TYPE__ long long int XPAR_XTTCPS_2_INTR XPS_TTC0_2_INT_ID WCHAR_MAX __WCHAR_MAX__ XPAR_PS7_AFI_2_S_AXI_BASEADDR 0xF800A000 XREG_CP15_INVAL_DC_LINE_SW "p15, 0, %0, c7, c6, 2" XREG_CP15_CLEAN_DC_LINE_MVA_POU "p15, 0, %0, c7, c11, 1" __SIG_ATOMIC_MAX__ 2147483647 __ARM_ARCH_PROFILE 65 XST_NAND_PART_NOT_SUPPORTED 1444L _WCHAR_T_DEFINED_ XUARTPS_RXTOUT_MASK 0x000000FF __CS_SOURCERYGXX_MIN__ 11 __bounded __WINT_TYPE__ unsigned int XREG_CP15_EVENT_TYPE_SEL "p15, 0, %0, c9, c13, 1" XUARTPS_SR_PARITY 0x00000080 __SIZE_MAX__ 4294967295U _ATEXIT_DYNAMIC_ALLOC 1 XPAR_PS7_PMU_0_PMU1_S_AXI_BASEADDR 0xF8893000 XREG_FPSCR_N_BIT (1 << 31) XUartPs_IsTransmitFull(BaseAddress) ((Xil_In32((BaseAddress) + XUARTPS_SR_OFFSET) & XUARTPS_SR_TXFULL) == XUARTPS_SR_TXFULL) __FLT_MANT_DIG__ 24 XST_SPI_TRANSFER_DONE 1152 XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV0 8 __ULACCUM_FBIT__ 32 XST_SEND_ERROR 28L __va_copy(d,s) __builtin_va_copy(d,s) XUARTPS_ISR_OFFSET 0x14 __GNUC_VA_LIST_COMPATIBILITY 1 NULL __null __ARM_FP 14 XREG_FPSCR_C_BIT (1 << 29) XUARTPS_HW_H XPAR_SCUTIMER_INTR XPS_SCU_TMR_INT_ID XPAR_XQSPIPS_0_LINEAR_BASEADDR XPS_QSPI_LINEAR_BASEADDR ___int16_t_defined 1 XREG_CP15_CACHE_SIZE_SEL "p15, 2, %0, c0, c0, 0" __GNUCLIKE_MATH_BUILTIN_RELOPS XUARTPS_MIN_RATE 110 XREG_CP15_INST_FAULT_ADDRESS "p15, 0, %0, c6, c0, 2" XREG_CP15_PERF_MONITOR_COUNT "p15, 0, %0, c9, c13, 2" INT_LEAST64_MIN (-9223372036854775807LL-1LL) __ARM_NEON 1 XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC "p15, 0, %0, c7, c14, 1" __XSI_VISIBLE 700 XPS_TOP_BUS_CFG_BASEADDR 0xF8900000 XPS_CORE_PARITY0_INT_ID 32 __DEC32_MIN__ 1E-95DF __UQQ_FBIT__ 8 __FLT_MIN_EXP__ (-125) XUARTPS_MEDEMSR_RIX XUARTPS_MODEMSR_TERI __UINT_FAST64_MAX__ 18446744073709551615ULL XUARTPS_MR_PARITY_SPACE 0x00000010 __BYTE_ORDER__ __ORDER_LITTLE_ENDIAN__ _EXFUN_NOTHROW(name,proto) name proto _NOTHROW __UINT64_C(c) c ## ULL __FRACT_IBIT__ 0 XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ 666666687 __FLT_RADIX__ 2 __USA_FBIT__ 16 _ANSI_STDARG_H_ XST_IPIF_IP_STATUS_ERROR 536L _BEGIN_STD_C extern "C" { XPS_SPI0_INT_ID 58 XREG_CP8 8 __LDBL_EPSILON__ 2.2204460492503131e-16L XPS_PARPORT0_BASEADDR 0xE2000000 XPAR_XDMAPS_0_FAULT_INTR XPS_DMA0_ABORT_INT_ID __SQ_FBIT__ 31 INT64_MIN (-9223372036854775807LL-1LL) IsReady XREG_FPSCR_RMODE_MASK (3 << FPSCR_RMODE_BIT) __ACCUM_EPSILON__ 0x1P-15K _VA_LIST_ ModemPinsConnected __DEC128_MAX_EXP__ 6145 __LACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LK XPAR_PS7_USB_0_BASEADDR 0xE0002000 XPAR_PS7_XADC_0_INTR XPS_SYSMON_INT_ID XREG_GPR3 r3 XPAR_XQSPIPS_0_QSPI_MODE 0 __FLT_EVAL_METHOD__ 0 XPAR_XSDPS_0_BASEADDR 0xE0100000 __VERSION__ "4.8.1" XREG_CP15_INST_FEATURE_1 "p15, 0, %0, c0, c2, 1" __DEC32_SUBNORMAL_MIN__ 0.000001E-95DF __INT64_MAX__ 9223372036854775807LL _Z12test_addressm XREG_GPR11 r11 XST_NAND_ERROR 1443L __FRACT_EPSILON__ 0x1P-15R XREG_CORTEXA9_H __lock_release(lock) (_CAST_VOID 0) XPS_DMAC0_NON_SEC_BASEADDR 0xF8004000 XPAR_XTTCPS_0_INTR XPS_TTC0_0_INT_ID XPS_FPGA3_INT_ID 64 XPAR_PS7_SCUC_0_S_AXI_BASEADDR 0xF8F00000 XUARTPS_IXR_FRAMING 0x00000040 XREG_CPSR_N_BIT 0x80000000 XREG_CP15_INVAL_UTLB_MVA_ASID "p15, 0, %0, c8, c7, 3" XPAR_PL_RAM_0_DEVICE_ID 0 XPAR_XSCUTIMER_0_DEVICE_ID XPAR_PS7_SCUTIMER_0_DEVICE_ID XPAR_XUARTPS_0_HIGHADDR 0xE0001FFF __UDQ_FBIT__ 64 XUARTPS_IER_OFFSET 0x08 __int_fast8_t_defined 1 XPS_TTC0_BASEADDR 0xF8001000 XPAR_SCUWDT_0_HIGHADDR 0xF8F006FF __SFRACT_IBIT__ 0 __weak_reference(sym,alias) __asm__(".weak " #alias); __asm__(".equ " #alias ", " #sym) XPS_DMA6_INT_ID 74 XUARTPS_EVENT_SENT_DATA 3 ___int64_t_defined 1 __need_NULL __GNUCLIKE_BUILTIN_NEXT_ARG 1 _toupper(__c) ((unsigned char)(__c) - 'a' + 'A') XREG_CPSR_IRQ_MODE 0x12 XST_FLASH_ADDRESS_ERROR 1135L XPS_FPGA9_INT_ID 85 XPS_USB0_BASEADDR 0xE0002000 __GCC_ATOMIC_CHAR32_T_LOCK_FREE 2 va_arg(v,l) __builtin_va_arg(v,l) __INT16_TYPE__ short int XST_OPB2PLB_FAIL_SELFTEST 1326L _C 040 __int_fast16_t_defined 1 _REENT_RAND48_SEED(ptr) ((ptr)->_new._reent._r48._seed) XREG_CP15_INTR_ENABLE_SET "p15, 0, %0, c9, c14, 1" __FRACT_MIN__ (-0.5R-0.5R) __ULFRACT_FBIT__ 32 __GNUCLIKE_BUILTIN_MEMCPY 1 ___int_size_t_h __sym_default(sym,impl,verid) __asm__(".symver " #impl ", " #sym "@@" #verid) _Static_assert(x,y) __Static_assert(x, __COUNTER__) XST_EMAC_MEMORY_SIZE_ERROR 1001L XUARTPS_IXR_RXOVR 0x00000001 __GCC_ATOMIC_LONG_LOCK_FREE 2 XST_NAND_READY 1442L __int_fast32_t_defined 1 PTRDIFF_MAX __PTRDIFF_MAX__ __GXX_TYPEINFO_EQUALITY_INLINE 0 XPAR_XEMACPS_NUM_INSTANCES 1 __UHQ_FBIT__ 16 __WINT_MIN__ 0U XPS_SDIO1_INT_ID 79 __GNUC_MINOR__ 8 __lock_init(lock) (_CAST_VOID 0) userInput XUARTPS_MODEMSR_TERI 0x00000004 XREG_CP15_VA_TO_PA_CURRENT_2 "p15, 0, %0, c7, c8, 2" __compiler_membar() __asm __volatile(" " : : : "memory") print_main_menu XUARTPS_OPTION_RESET_RX 0x0008 XREG_CP15_CONTEXT_ID "p15, 0, %0, c13, c0, 1" XREG_FPSID_REV_BIT (0) XST_DMA_SG_LIST_EMPTY 513L XREG_CPSR_SYSTEM_MODE 0x1F XST_FLASH_TOO_MANY_REGIONS 1133L XUARTPS_MODEMSR_DDCD 0x00000008 XUARTPS_H __WCHAR_MIN__ 0U _REENT_MBSRTOWCS_STATE(ptr) ((ptr)->_new._reent._mbsrtowcs_state) XPAR_XDMAPS_1_DEVICE_ID XPAR_PS7_DMA_S_DEVICE_ID XUARTPS_CR_TX_DIS 0x00000020 _REENT_CHECK_MP(ptr) XPAR_XDCFG_0_INTR XPS_DVC_INT_ID __INT_LEAST32_MAX__ 2147483647L __CC_SUPPORTS___INLINE 1 _GCC_WCHAR_T XUARTPS_FORMAT_1_STOP_BIT 0 __LOCK_INIT(class,lock) static int lock = 0; XREG_CP15_TLB_LOCKDWN "p15, 0, %0, c10, c0, 0" XREG_FPSCR_IDC (1 << 7) XPAR_PS7_TTC_1_DEVICE_ID 1 XPAR_XQSPIPS_0_CLOCK_HZ XPAR_XQSPIPS_0_QSPI_CLK_FREQ_HZ XREG_MVFR0_SHORT_VEC_BIT (24) __LLFRACT_EPSILON__ 0x1P-63LLR XUARTPS_SR_RXFULL 0x00000004 XPAR_PS7_SCUWDT_0_BASEADDR 0xF8F00620 __FRACT_FBIT__ 15 mtgpr(rn,v) __asm__ __volatile__( "mov r" stringify(rn) ", %0 \n" : : "r" (v) ) __dead2 __attribute__((__noreturn__)) XREG_MVFR0_SHORT_VEC_MASK (0xF << XREG_MVFR0_SHORT_VEC_BIT) __need_size_t va_start(v,l) __builtin_va_start(v,l) __ULACCUM_MAX__ 0XFFFFFFFFFFFFFFFFP-32ULK XREG_CP14 14 dsb() __asm__ __volatile__ ("dsb" : : : "memory") __volatile volatile __CHAR_UNSIGNED__ 1 XUARTPS_OPTION_RESET_TX 0x0010 _BSD_WCHAR_T_ XUARTPS_EVENT_MODEM 5 XUARTPS_MR_CHARLEN_7_BIT 0x00000004 __GCC_HAVE_DWARF2_CFI_ASM 1 XREG_CPSR_THUMB_MODE 0x20 XREG_CP15_USER_ENABLE "p15, 0, %0, c9, c14, 0" XREG_FPSCR_OFC (1 << 2) __UINTMAX_MAX__ 18446744073709551615ULL XREG_CP15_VIRTUALIZATION_INTR "p15, 0, %0, c12, c1, 1" __need_size_t XST_ATMC_ERROR_COUNT_MAX 1101L XPAR_XCANPS_1_INTR XPS_CAN1_INT_ID __ULLFRACT_MAX__ 0XFFFFFFFFFFFFFFFFP-64ULLR XPS_AFI0_BASEADDR 0xF8008000 XST_OPBARB_NOT_SUSPENDED 1177 XST_UART_BAUD_ERROR 1055L __DQ_IBIT__ 0 XST_UART_INIT_ERROR 1051L __HA_FBIT__ 7 __UACCUM_MIN__ 0.0UK XREG_CP15_CONTROL_RR_BIT 0x00004000 toascii(__c) ((__c)&0177) __DEC128_MIN__ 1E-6143DL __GNUCLIKE_ASM 3 XST_IIC_BUS_BUSY 1077 __lock_close(lock) (_CAST_VOID 0) __UFRACT_EPSILON__ 0x1P-16UR __DEC64_MANT_DIG__ 16 XPAR_XGPIOPS_0_DEVICE_ID XPAR_PS7_GPIO_0_DEVICE_ID __FLT_HAS_QUIET_NAN__ 1 XPAR_XTTCPS_4_INTR XPS_TTC1_1_INT_ID STDOUT_BASEADDRESS 0xE0001000 _GCC_WRAP_STDINT_H XPS_SPI1_BASEADDR 0xE0007000 __WCHAR_UNSIGNED__ 1 XPAR_SCUGIC_CPU_BASEADDR (XPS_SCU_PERIPH_BASE + 0x0100) XREG_CP15_PHYS_ADDR "p15, 0, %0, c7, c4, 0" __INT_FAST64_MAX__ 9223372036854775807LL XPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV1 5 XPAR_XIICPS_0_CLOCK_HZ XPAR_XIICPS_0_I2C_CLK_FREQ_HZ XPS_FPGA10_INT_ID 86 XPAR_GLOBAL_TMR_INTR XPS_GLOBAL_TMR_INT_ID XPAR_PS7_QSPI_0_DEVICE_ID 0 XST_UART_BAUD_RANGE 1056L XUARTPS_OPTION_ASSERT_RTS 0x0004 XPAR_SCUGIC_0_CPU_HIGHADDR 0xF8F001FF _REENT_MP_RESULT_K(ptr) ((ptr)->_result_k) XUINT64_MSW(x) ((x).Upper) XPAR_XTTCPS_2_CLOCK_HZ XPAR_XTTCPS_2_TTC_CLK_FREQ_HZ __LONG_MAX__ 2147483647L XPS_I2C0_BASEADDR 0xE0004000 __ORDER_PDP_ENDIAN__ 3412 XREG_CR10 cr10 XREG_CPSR_DATA_ABORT_MODE 0x17 strnicmp strncasecmp XPAR_XGPIOPS_0_INTR XPS_GPIO_INT_ID XPAR_XEMACPS_0_ENET_SLCR_1000Mbps_DIV1 1 XREG_FPSCR_STRIDE_BIT (20) XREG_CP9 9 __INT_FAST64_TYPE__ long long int _REENT_MBTOWC_STATE(ptr) ((ptr)->_new._reent._mbtowc_state) XREG_CP12 12 __noinline __attribute__ ((__noinline__)) RequestedBytes XST_SPI_SLAVE_ONLY 1158 XST_FLASH_BUSY 1126L __attribute_pure__ _HAVE_LONG_DOUBLE 1 __ARM_FEATURE_QBIT 1 __UINT32_C(c) c ## UL XPAR_PS7_TTC_0_DEVICE_ID 0 _REENT_WCTOMB_STATE(ptr) ((ptr)->_new._reent._wctomb_state) __ARM_FEATURE_UNALIGNED 1 __SACCUM_MAX__ 0X7FFFP-7HK __section(x) __attribute__((__section__(x))) GNU C++ 4.8.1 -march=armv7-a -mfloat-abi=softfp -mfpu=neon-fp16 -g3 -O0 -fmessage-length=0 INT_FAST64_MAX INT_LEAST64_MAX XREG_CP15_CONTROL_SW_BIT 0x00000400 XST_OPBARB_PARK_NOT_ENABLED 1178 XPS_L2CC_INT_ID 34 __ACCUM_IBIT__ 16 XREG_CP15_VA_TO_PA_OTHER_1 "p15, 0, %0, c7, c8, 5" XPAR_XEMACPS_0_WAKE_INTR XPS_GEM0_WAKE_INT_ID XREG_FPSID_PART_MASK (0xFF << FPSID_PART_BIT) XPAR_PS7_PMU_0_S_AXI_BASEADDR 0xF8891000 __GNUC_VA_LIST XIL_PRINTF_H XPS_UART1_INT_ID 82 XUARTPS_RXTOUT_DISABLE 0x00000000 XUARTPS_MR_CHMODE_L_LOOP 0x00000200 XUARTPS_BAUDDIV_MASK 0x000000FF _Z15print_main_menuv XREG_FPSCR_IOC (1 << 0) XUARTPS_SR_RXEMPTY 0x00000002 XREG_CR12 cr12 XPAR_PS7_TTC_2_DEVICE_ID 2 __need_wint_t XPAR_XEMACPS_0_ENET_CLK_FREQ_HZ 125000000 __ATOMIC_RELAXED 0 __LDBL_MIN__ 2.2250738585072014e-308L XPAR_SCUGIC_SINGLE_DEVICE_ID 0 __ULACCUM_IBIT__ 32 XPAR_XTTCPS_1_BASEADDR 0xF8001004 XPS_SDIO1_BASEADDR 0xE0101000 XUARTPS_FORMAT_MARK_PARITY 3 __THUMB_INTERWORK__ 1 XPS_AFI3_BASEADDR 0xF800B000 __has_builtin(x) 0 XUARTPS_SR_TACTIVE 0x00000800 __POSIX_VISIBLE 200809 __FRACT_MAX__ 0X7FFFP-15R _DEFUN(name,arglist,args) name(args) __returns_twice __attribute__((__returns_twice__)) XPS_NAND_BASEADDR 0xE1000000 XREG_CP15_V_FLAG_STATUS "p15, 0, %0, c9, c12, 3" _REENT_MP_RESULT(ptr) ((ptr)->_result) XST_NAND_CACHE_ERROR 1450L XPS_SDIO0_INT_ID 56 __LLFRACT_IBIT__ 0 XST_DMA_SG_BD_LOCKED 518L XST_IIC_TX_FIFO_REG_RESET_ERROR 1080 XIL_EXCEPTION_ALL (XREG_CPSR_FIQ_ENABLE | XREG_CPSR_IRQ_ENABLE) __UFRACT_IBIT__ 0 XST_INTC_CONNECT_ERROR 1202 XPAR_PS7_SLCR_0_S_AXI_BASEADDR 0xF8000000 XST_NO_DATA 13L XPAR_SCUWDT_INTR XPS_SCU_WDT_INT_ID XREG_CP10 10 _REENT_GETDATE_ERR_P(ptr) (&((ptr)->_new._reent._getdate_err)) __SFRACT_MAX__ 0X7FP-7HR XREG_CP15_MONITOR_VEC_BASE_ADDR "p15, 0, %0, c12, c0, 1" __ptrvalue XPS_PMU1_INT_ID 38 XPAR_PS7_TTC_1_TTC_CLK_FREQ_HZ 111111115 _NULL 0 XPS_FPGA2_INT_ID 63 XST_PFIFO_ERROR 504L XREG_CPSR_Z_BIT 0x40000000 __ARM_ARCH_ISA_ARM 1 _WCHAR_T_DECLARED XREG_MVFR0_RMODE_MASK (0xF << XREG_MVFR0_RMODE_BIT) __containerof(x,s,m) ({ const volatile __typeof__(((s *)0)->m) *__x = (x); __DEQUALIFY(s *, (const volatile char *)__x - __offsetof(s, m));}) _REENT_CHECK_EMERGENCY(ptr) _UNBUF_STREAM_OPT 1 XPS_DMA1_INT_ID 47 XPAR_XDMAPS_0_DONE_INTR_1 XPS_DMA1_INT_ID __GXX_ABI_VERSION 1002 XPAR_PS7_SD_0_DEVICE_ID 0 _REENT_INIT_PTR(var) { memset((var), 0, sizeof(*(var))); (var)->_stdin = &(var)->__sf[0]; (var)->_stdout = &(var)->__sf[1]; (var)->_stderr = &(var)->__sf[2]; (var)->_current_locale = "C"; (var)->_new._reent._rand_next = 1; (var)->_new._reent._r48._seed[0] = _RAND48_SEED_0; (var)->_new._reent._r48._seed[1] = _RAND48_SEED_1; (var)->_new._reent._r48._seed[2] = _RAND48_SEED_2; (var)->_new._reent._r48._mult[0] = _RAND48_MULT_0; (var)->_new._reent._r48._mult[1] = _RAND48_MULT_1; (var)->_new._reent._r48._mult[2] = _RAND48_MULT_2; (var)->_new._reent._r48._add = _RAND48_ADD; } XST_ERROR_COUNT_MAX 22L XST_DMA_TRANSFER_ERROR 511L XST_FR_TX_ERROR 1400 XIL_EXCEPTION_ID_UNDEFINED_INT 1 XST_IIC_CR_READBACK_ERROR 1083 __CC_SUPPORTS___FUNC__ 1 uart __UTQ_IBIT__ 0 XPS_GPIO_BASEADDR 0xE000A000 XPAR_XGPIOPS_0_HIGHADDR 0xE000AFFF XREG_FPSCR_ROUND_TOZERO (3 << 22) __SIZEOF_WINT_T__ 4 __SIG_ATOMIC_MIN__ (-__SIG_ATOMIC_MAX__ - 1) XST_FLASH_NOT_SUPPORTED 1132L XUARTPS_OPER_MODE_REMOTE_LOOP 0x03 XUARTPS_CR_RXRST 0x00000001 XPS_I2C1_INT_ID 80 __ARM_FEATURE_SAT 1 XUARTPS_DFT_BAUDRATE 115200 XUARTPS_SR_TOUT 0x00000100 XREG_CP15_INST_FEATURE_3 "p15, 0, %0, c0, c2, 3" XREG_CP15_MULTI_PROC_AFFINITY "p15, 0, %0, c0, c0, 5" XPAR_SCUGIC_ACK_BEFORE 0 __FLT_MAX__ 3.4028234663852886e+38F XPAR_PS7_ETHERNET_1_INTR XPS_GEM1_INT_ID __INT_LEAST8_TYPE__ signed char _T_WCHAR __DEVOLATILE(type,var) ((type)(uintptr_t)(volatile void *)(var)) XPAR_XDMAPS_0_DONE_INTR_4 XPS_DMA4_INT_ID PL_RAM_H mtcp(rn,v) __asm__ __volatile__( "mcr " rn "\n" : : "r" (v) ); XREG_GPR9 r9 XREG_MVFR0_DIVIDE_BIT (16) __SIZEOF_WCHAR_T__ 4 XUARTPS_MR_CHARLEN_8_BIT 0x00000000 XUARTPS_BAUDGEN_OFFSET 0x18 __USACCUM_MAX__ 0XFFFFP-8UHK XIL_ASSERT_H INT32_MIN (-2147483647L-1) _CTYPE_H_ XREG_FPSCR_Z_BIT (1 << 30) XUARTPS_IXR_PARITY 0x00000080 XPAR_XTTCPS_2_TTC_CLK_CLKSRC 0 __lock_try_acquire(lock) (_CAST_VOID 0) __ATOMIC_ACQUIRE 2 XPAR_XIICPS_0_INTR XPS_I2C0_INT_ID XREG_CP15_TLB_TYPE "p15, 0, %0, c0, c0, 3" XPAR_XEMACPS_0_DEVICE_ID XPAR_PS7_ETHERNET_0_DEVICE_ID __GNUCLIKE_BUILTIN_VARARGS 1 _Kmax (sizeof (size_t) << 3) __ASMNAME(cname) __XSTRING (__USER_LABEL_PREFIX__) cname _Thread_local __thread XPAR_XDCFG_0_HIGHADDR 0xF80070FF XPS_CAN0_BASEADDR 0xE0008000 __USACCUM_EPSILON__ 0x1P-8UHK ___int_least16_t_defined 1 XPAR_XUARTPS_1_CLOCK_HZ XPAR_XUARTPS_1_UART_CLK_FREQ_HZ __has_include(x) 0 XPAR_XSDPS_0_SDIO_CLK_FREQ_HZ 50000000 XPAR_XDMAPS_1_BASEADDR 0xF8003000 XUARTPS_IXR_TXFULL 0x00000010 __INTMAX_C(c) c ## LL __LACCUM_MIN__ (-0X1P31LK-0X1P31LK) XUARTPS_RXWM_MASK 0x0000003F __UINT_FAST64_TYPE__ long long unsigned int XREG_CPSR_SVC_MODE 0x13 _REENT_RAND_NEXT(ptr) ((ptr)->_new._reent._rand_next) XST_FLASH_ERASE_SUSPENDED 1129L XUARTPS_MR_CLKSEL 0x00000001 XPAR_PS7_DEV_CFG_0_HIGHADDR 0xF80070FF UINT_FAST64_MAX UINT_LEAST64_MAX XREG_CP15_READ_TLB_ENTRY "p15, 5, %0, c15, c4, 2" XREG_FPSID_ARCH_BIT (16) __used __attribute__((__used__)) XPAR_PS7_ETHERNET_1_WAKE_INTR XPS_GEM1_WAKE_INT_ID XST_RESET_ERROR 8L _RAND48_MULT_0 (0xe66d) XPAR_PS7_TTC_1_BASEADDR 0XF8001004 XPAR_XUARTPS_0_BASEADDR 0xE0001000 XREG_CP15_SW_INC "p15, 0, %0, c9, c12, 4" XREG_FPEXC_DEX (1 << 29) XPAR_PS7_SCUTIMER_0_BASEADDR 0xF8F00600 _REENT_EMERGENCY(ptr) ((ptr)->_emergency) XST_DMA_SG_NO_LIST 523L _U 01 XREG_CPSR_V_BIT 0x10000000 XST_IPIF_IP_ACK_ERROR 537L XST_USB_NO_DESC_AVAILABLE 1412 XPS_UART1_BASEADDR 0xE0001000 _REENT _impure_ptr XPS_OCMINTR_INT_ID 35 XREG_CP15_INTERRUPT_STATUS "p15, 0, %0, c12, c1, 0" XPAR_PS7_GPIO_0_DEVICE_ID 0 __SQ_IBIT__ 0 XUARTPS_MODEMCR_FCM 0x00000010 XUARTPS_FORMAT_ODD_PARITY 1 XREG_CP15_INVAL_ITLB_ASID "p15, 0, %0, c8, c5, 2" __need_NULL XPAR_PS7_ETHERNET_0_ENET_SLCR_100MBPS_DIV0 8 XUARTPS_MR_STOPMODE_2_BIT 0x00000080 XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ XST_FLASH_READY 1127L __always_inline __attribute__((__always_inline__)) XST_IPIF_REG_WIDTH_ERROR 531L XPAR_PS7_SPI_1_INTR XPS_SPI1_INT_ID XPS_QSPI_LINEAR_BASEADDR 0xFC000000 XREG_CP15_MEMORY_FEATURE_0 "p15, 0, %0, c0, c1, 4" XST_IPIF_DEVICE_ID_ERROR 540L XST_SPI_NO_SLAVE 1155 XREG_GPR7 r7 __packed __attribute__((__packed__)) XPAR_PS7_QSPI_0_INTR XPS_QSPI_INT_ID XPAR_XTTCPS_0_TTC_CLK_CLKSRC 0 __SFRACT_MIN__ (-0.5HR-0.5HR) Xil_Out16LE(Addr,Value) Xil_Out16(Addr, Value) __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1 __LACCUM_FBIT__ 31 XREG_CP15_INVAL_TLB_MVA_IS "p15, 0, %0, c8, c3, 1" XUARTPS_OPTION_RESET_TMOUT 0x0020 __ULACCUM_MIN__ 0.0ULK XPAR_XTTCPS_4_CLOCK_HZ XPAR_XTTCPS_4_TTC_CLK_FREQ_HZ INT_LEAST32_MIN (-2147483647L-1) XPAR_XDMAPS_0_DONE_INTR_3 XPS_DMA3_INT_ID XUARTPS_MR_PARITY_MASK 0x00000038 _SYS__TYPES_H _RAND48_SEED_2 (0x1234) XREG_CP15_CONTROL_EE_BIT 0x02000000 XST_SPI_RECEIVE_NOT_EMPTY 1161 __RCSID(s) struct __hack __INT32_C(c) c ## L _AND , XREG_FPEXC_EN (1 << 30) __USQ_IBIT__ 0 sizetype XPAR_XSDIOPS_0_INTR XPS_SDIO0_INT_ID __DEC64_EPSILON__ 1E-15DD XPAR_XEMACPS_0_INTR XPS_GEM0_INT_ID XREG_CP15_NORM_MEM_REMAP "p15, 0, %0, c10, c2, 1" __GNUCLIKE_BUILTIN_STDARG 1 __int_least8_t_defined 1 __DEC32_MAX_EXP__ 97 XPAR_XDMAPS_0_DONE_INTR_2 XPS_DMA2_INT_ID XST_IPIF_DEVICE_ACK_ERROR 534L XPS_FPGA_AXI_S1_BASEADDR 0x80000000 __SACCUM_EPSILON__ 0x1P-7HK XUARTPS_SR_OFFSET 0x2C XST_VDMA_MISMATCH_ERROR 1430 XPS_FPGA7_INT_ID 68 XREG_FPINST c9 XIL_TYPES_H XREG_CP0 0 InputClockHz XST_IIC_TBA_READBACK_ERROR 1087 __lock_acquire_recursive(lock) (_CAST_VOID 0) XST_DMA_SG_BD_NOT_COMMITTED 524L __lock_release_recursive(lock) (_CAST_VOID 0) XREG_CP15_INVAL_ITLB_MVA "p15, 0, %0, c8, c5, 1" __size_t__ __SYS_CONFIG_H__ _REENT_INIT(var) { 0, &(var).__sf[0], &(var).__sf[1], &(var).__sf[2], 0, "", 0, "C", 0, _NULL, _NULL, 0, _NULL, _NULL, 0, _NULL, { { 0, _NULL, "", {0, 0, 0, 0, 0, 0, 0, 0, 0}, 0, 1, { {_RAND48_SEED_0, _RAND48_SEED_1, _RAND48_SEED_2}, {_RAND48_MULT_0, _RAND48_MULT_1, _RAND48_MULT_2}, _RAND48_ADD }, {0, {0}}, {0, {0}}, {0, {0}}, "", "", 0, {0, {0}}, {0, {0}}, {0, {0}}, {0, {0}}, {0, {0}} } }, _REENT_INIT_ATEXIT _NULL, {_NULL, 0, _NULL} } XUARTPS_TXWM_RESET_VAL 0x00000020 __predict_false(exp) __builtin_expect((exp), 0) XPS_EFUSE_BASEADDR 0xF800D000 XPAR_PS7_SCUC_0_S_AXI_HIGHADDR 0xF8F000FC _PTR void * WINT_MAX __WINT_MAX__ _END_STD_C } __ULLACCUM_EPSILON__ 0x1P-32ULLK __CHAR_BIT__ 8 Xil_Htons(Data) Xil_EndianSwap16(Data) __INTMAX_TYPE__ long long int XPAR_GLOBAL_TMR_BASEADDR (XPS_SCU_PERIPH_BASE + 0x200) _POINTER_INT long XREG_GPR5 r5 XST_NAND_ADDRESS_ERROR 1447L XPAR_PS7_ETHERNET_0_BASEADDR 0xE000B000 XPAR_PS7_SCUTIMER_0_DEVICE_ID 0 XPAR_PS7_UART_1_UART_CLK_FREQ_HZ 50000000 __INT16_MAX__ 32767 XUARTPS_RXWM_DISABLE 0x00000000 _GLOBAL_ATEXIT (_GLOBAL_REENT->_atexit) UINT64_MAX 18446744073709551615ULL _BSD_SIZE_T_ UINT32_C(x) x ##UL XPAR_PS7_TTC_2_TTC_CLK_FREQ_HZ 111111115 XUARTPS_IXR_TXEMPTY 0x00000008 XST_IIC_NOT_SLAVE 1088 _STRING_H_ XPAR_SCUWDT_0_BASEADDR 0xF8F00620 UINT_LEAST64_MAX 18446744073709551615ULL XPS_DMA0_ABORT_INT_ID 45 __GXX_RTTI 1 __CC_SUPPORTS_VARADIC_XXX 1 __BEGIN_DECLS extern "C" { XST_FIFO_NO_ROOM 11L XPS_PERIPHERAL_BASEADDR 0xE0000000 XPAR_PS7_DEV_CFG_0_BASEADDR 0xF8007000 _BSD_SIZE_T_DEFINED_ XPAR_PS7_DMA_NS_HIGHADDR 0xF8004FFF __GCC_ATOMIC_POINTER_LOCK_FREE 2 XPS_TTC1_BASEADDR 0xF8002000 XPS_SCU_WDT_INT_ID 30 INT_LEAST8_MIN -128 _RAND48_MULT_1 (0xdeec) XREG_CR7 cr7 XREG_CP15_VA_TO_PA_CURRENT_1 "p15, 0, %0, c7, c8, 1" __DOTS , ... __hidden __attribute__((__visibility__("hidden"))) XPS_FPGA0_INT_ID 61 INTPTR_MIN PTRDIFF_MIN _REENT_RAND48_MULT(ptr) ((ptr)->_new._reent._r48._mult) XPAR_XGPIOPS_0_BASEADDR 0xE000A000 __DEC64_MAX_EXP__ 385 XREG_CP15_CONTROL_V_BIT 0x00002000 _REENT_MBRTOWC_STATE(ptr) ((ptr)->_new._reent._mbrtowc_state) XUARTPS_EVENT_RECV_TOUT 2 __ACCUM_FBIT__ 15 __LDBL_HAS_DENORM__ 1 _ANSI_STDDEF_H XPAR_XTTCPS_2_TTC_CLK_FREQ_HZ 111111115 XPS_PERIPH_APB_BASEADDR 0xF8000000 XREG_CP15_INST_SYNC_BARRIER "p15, 0, %0, c7, c5, 4" XUARTPS_MR_CHARLEN_6_BIT 0x00000006 __UINT_FAST8_MAX__ 4294967295U _RAND48_MULT_2 (0x0005) XREG_FPSID_PART_BIT (8) XST_NOT_INTERRUPT 20L __USES_INITFINI__ 1 __XUINT64__ __GCC_ATOMIC_INT_LOCK_FREE 2 __has_extension __has_feature __REGISTER_PREFIX__ XPAR_XEMACPS_1_WAKE_INTR XPS_GEM1_WAKE_INT_ID XPAR_GLOBAL_TMR_NUM_INSTANCES 1 mfcp(rn) ({unsigned int rval; __asm__ __volatile__( "mrc " rn "\n" : "=r" (rval) ); rval; }) XPAR_XIICPS_1_CLOCK_HZ XPAR_XIICPS_1_I2C_CLK_FREQ_HZ XREG_CP15_SECURE_CONFIG "p15, 0, %0, c1, c1, 0" XPAR_XTTCPS_NUM_INSTANCES 3 Xil_AssertNonvoidAlways() { Xil_Assert(__FILE__, __LINE__); Xil_AssertStatus = XIL_ASSERT_OCCURRED; return 0; } XST_SPI_TOO_MANY_SLAVES 1156 XREG_CP15_VA_TO_PA_CURRENT_0 "p15, 0, %0, c7, c8, 0" INT_FAST8_MIN (-__STDINT_EXP(INT_MAX)-1) XPAR_PS7_CORESIGHT_COMP_0_S_AXI_HIGHADDR 0xF88FFFFF XST_PFIFO_NO_ROOM 502L XUARTPS_BAUDDIV_RESET_VAL 0x0000000F __warn_references(sym,msg) __asm__(".section .gnu.warning." #sym); __asm__(".asciz \"" msg "\""); __asm__(".previous") _REENT_ASCTIME_BUF(ptr) ((ptr)->_new._reent._asctime_buf) Xil_In32LE(Addr) Xil_In32(Addr) XPS_GEM1_WAKE_INT_ID 78 XREG_CP15_VIRTUAL_CONTROL "p15, 0, %0, c1, c1, 3" __USQ_FBIT__ 32 XST_USB_BUF_TOO_BIG 1413 __INT_FAST8_TYPE__ int XPAR_XUARTPS_0_UART_CLK_FREQ_HZ 50000000 XREG_MVFR0_A_SIMD_MASK (0xF << MVFR0_A_SIMD_BIT) __ptr_t void * XST_USB_NO_BUF 1414 XST_NAND_TIMEOUT_ERROR 1446L XPAR_PS7_SCUWDT_0_INTR XPS_SCU_WDT_INT_ID __INT_FAST16_MAX__ 2147483647 unsigned __STDC_HOSTED__ 1 __UINTMAX_C(c) c ## ULL __DEC64_SUBNORMAL_MIN__ 0.000000000000001E-383DD __need_ptrdiff_t XPAR_PS7_DDRC_0_S_AXI_HIGHADDR 0xF8006FFF XST_DMA_SG_LIST_ERROR 526L XPAR_PS7_ETHERNET_0_ENET_SLCR_100MBPS_DIV1 5 XUARTPS_IMR_OFFSET 0x10 __UACCUM_MAX__ 0XFFFFFFFFP-16UK _WINT_T XPAR_PS7_DDR_0_S_AXI_HIGHADDR 0x1FFFFFFF __UHQ_IBIT__ 0 XST_LOOPBACK_ERROR 17L _PARAMS(paramlist) paramlist XST_IPIF_DEVICE_ENABLE_ERROR 535L _SIGNED signed XPAR_XUSBPS_0_DEVICE_ID XPAR_PS7_USB_0_DEVICE_ID _REENT_MP_P5S(ptr) ((ptr)->_p5s) XPS_TTC0_2_INT_ID 44 __DBL_HAS_DENORM__ 1 XREG_FPSCR_UFC (1 << 3) XPS_CORESIGHT_BASEADDR 0xF8800000 __GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1 _GLOBAL_REENT _global_impure_ptr XST_INVALID_VERSION 4L XREG_FPSCR_DZC (1 << 1) _N_LISTS 30 __PTRDIFF_TYPE__ int XST_IPIF_RESET_REGISTER_ERROR 532L __GCC_ATOMIC_CHAR16_T_LOCK_FREE 2 XPAR_SCUGIC_NUM_INSTANCES 1 __USACCUM_FBIT__ 8 XREG_GPR1 r1 XUARTPS_MODEMSR_CTS 0x00000010 __LACCUM_EPSILON__ 0x1P-31LK XPS_FPGA14_INT_ID 90 XPAR_PS7_SCUGIC_0_BASEADDR 0xF8F00100 XUartPs_SetModeControl(InstancePtr,RegisterValue) Xil_Out32(((InstancePtr)->Config.BaseAddress) + XUARTPS_CR_OFFSET, (RegisterValue)) XREG_CP15_MAIN_ID "p15, 0, %0, c0, c0, 0" UINT8_MAX 255 __EXPORT __PMT(args) args INTMAX_MIN (-INTMAX_MAX - 1) XPAR_PS7_OCMC_0_S_AXI_HIGHADDR 0xF800CFFF XPS_GLOBAL_TMR_INT_ID 27 XREG_CR4 cr4 XST_PFIFO_DEADLOCK 505L __UTQ_FBIT__ 128 __strftimelike(fmtarg,firstvararg) __attribute__((__format__ (__strftime__, fmtarg, firstvararg))) RemainingBytes XUARTPS_MR_STOPMODE_1_BIT 0x00000000 __PTRDIFF_T XREG_CP15_VA_TO_PA_OTHER_3 "p15, 0, %0, c7, c8, 7" XPAR_PL_RAM_0_S_AXI_BASEADDR 0x40000000 XPS_SMC_INT_ID 50 XST_WDTTB_TIMER_FAILED 1251L __INT8_MAX__ 127 XPAR_PS7_QSPI_0_BASEADDR 0xE000D000 XPAR_XQSPIPS_NUM_INSTANCES 1 __CS_SOURCERYGXX_MAJ__ 2013 XREG_FPSCR_RMODE_BIT (22) _N 04 __strfmonlike(fmtarg,firstvararg) __attribute__((__format__ (__strfmon__, fmtarg, firstvararg))) XREG_CP1 1 UINTMAX_C(x) x ##ULL XST_FLASH_CFI_QUERY_ERROR 1138L Xil_AssertVoid(Expression) { if (Expression) { Xil_AssertStatus = XIL_ASSERT_NONE; } else { Xil_Assert(__FILE__, __LINE__); Xil_AssertStatus = XIL_ASSERT_OCCURRED; return; } } XPAR_XQSPIPS_0_QSPI_CLK_FREQ_HZ 200000000 __SACCUM_FBIT__ 7 __HQ_FBIT__ 15 XREG_CP15_DEBUG_FEATURE_0 "p15, 0, %0, c0, c1, 2" __LLACCUM_IBIT__ 32 XREG_GPR12 r12 XREG_CP15_COUNT_ENABLE_SET "p15, 0, %0, c9, c12, 1" _CAST_VOID (void) XUARTPS_MR_PARITY_EVEN 0x00000000 __SIZE_T XST_NOT_POLLED 10L __lock_close_recursive(lock) (_CAST_VOID 0) __LDBL_DIG__ 15 __CHAR32_TYPE__ long unsigned int Xil_DisableNestedInterrupts() __asm__ __volatile__ ("ldmfd sp!, {lr}"); __asm__ __volatile__ ("msr cpsr_c, #0x92"); __asm__ __volatile__ ("ldmfd sp!, {lr}"); __asm__ __volatile__ ("msr spsr_cxsf, lr"); XREG_CR11 cr11 __Long long __pure2 __attribute__((__const__)) __GCC_ATOMIC_SHORT_LOCK_FREE 2 XUARTPS_MODEMSR_RI 0x00000040 XUARTPS_MEDEMSR_DCDX XUARTPS_MODEMSR_DDCD offsetof(TYPE,MEMBER) __builtin_offsetof (TYPE, MEMBER) __SIZEOF_POINTER__ 4 INT_FAST32_MIN (-__STDINT_EXP(INT_MAX)-1) XUARTPS_FORMAT_1_5_STOP_BIT 1 __pure __attribute__((__pure__)) __ARM_SIZEOF_WCHAR_T 32 XPAR_PS7_CAN_0_INTR XPS_CAN0_INT_ID __UINTMAX_TYPE__ long long unsigned int XPAR_XTTCPS_3_INTR XPS_TTC1_0_INT_ID XUartPs_GetChannelStatus(InstancePtr) Xil_In32(((InstancePtr)->Config.BaseAddress) + XUARTPS_SR_OFFSET) XST_SYSACE_NO_LOCK 1351L XPAR_AXI_EMC __CONCAT1(x,y) x ## y UINT64_C(x) x ##ULL XPS_L2CC_BASEADDR 0xF8F02000 XPS_QSPI_BASEADDR 0xE000D000 XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR 0xFC000000 XPAR_PS7_AFI_2_S_AXI_HIGHADDR 0xF800AFFF __GNUC_PREREQ(maj,min) ((__GNUC__ << 16) + __GNUC_MINOR__ >= ((maj) << 16) + (min)) Xil_Htonl(Data) Xil_EndianSwap32(Data) XUARTPS_MODEMSR_DCD 0x00000080 XUARTPS_MODEMSR_FCMS 0x00000100 __FINITE_MATH_ONLY__ 0 XPAR_XADCPS_0_HIGHADDR 0xF8007120 XIL_EXCEPTION_FIQ XREG_CPSR_FIQ_ENABLE _T_WCHAR_ XST_IIC_DRR_READBACK_ERROR 1085 _NOARGS void XREG_FPSCR_DEFAULT_NAN (1 << 25) XUARTPS_MODEMSR_DCTS 0x00000001 __LFRACT_MIN__ (-0.5LR-0.5LR) _B 0200 XIL_COMPONENT_IS_READY 0x11111111 XPAR_XUSBPS_0_BASEADDR 0xE0002000 __RCSID_SOURCE(s) struct __hack XPAR_PS7_DMA_S_DEVICE_ID 1 XPS_I2C1_BASEADDR 0xE0005000 __GCC_ATOMIC_LLONG_LOCK_FREE 2 XREG_CPSR_FIQ_MODE 0x11 __ULFRACT_EPSILON__ 0x1P-32ULR XUARTPS_BAUDDIV_OFFSET 0x34 _tolower(__c) ((unsigned char)(__c) - 'A' + 'a') XPS_GPIO_INT_ID 52 UINT_FAST32_MAX (__STDINT_EXP(INT_MAX)*2U+1U) XUARTPS_MR_CHMODE_SHIFT 8 XREG_CP15_MAIN_TLB_PA "p15, 5, %0, c15, c6, 2" XREG_FPSCR_FLUSHTOZERO (1 << 24) XPAR_PS7_WDT_0_INTR XPS_WDT_INT_ID XREG_CP15_INST_FEATURE_2 "p15, 0, %0, c0, c2, 2" __NEWLIB_H__ 1 baseaddr XIL_EXCEPTION_ID_FIRST 0 XUartPs_DisableUart(InstancePtr) Xil_Out32(((InstancePtr)->Config.BaseAddress + XUARTPS_CR_OFFSET), (((Xil_In32((InstancePtr)->Config.BaseAddress + XUARTPS_CR_OFFSET)) & ~XUARTPS_CR_EN_DIS_MASK) | (XUARTPS_CR_RX_DIS | XUARTPS_CR_TX_DIS))) XIL_ASSERT_NONE 0 XPAR_XSDPS_0_HIGHADDR 0xE0100FFF XREG_CP15_INVAL_DTLB_UNLOCKED "p15, 0, %0, c8, c6, 0" XREG_CP15_PRI_MEM_REMAP "p15, 0, %0, c10, c2, 0" XPS_TTC1_0_INT_ID 69 XUARTPS_MR_CHMODE_ECHO 0x00000100 __ULLACCUM_FBIT__ 32 XREG_CR1 cr1 _REENT_SIGNAL_BUF(ptr) ((ptr)->_new._reent._signal_buf) USER_PRIV_THREAD_PID "p15, 0, %0, c13, c0, 4" __LDBL_HAS_QUIET_NAN__ 1 __ARM_FEATURE_DSP 1 __rangeof(type,start,end) (__offsetof(type, end) - __offsetof(type, start)) XPAR_SCUTIMER_DEVICE_ID 0 XUARTPS_RXTOUT_OFFSET 0x1C __NO_INLINE__ 1 va_end(v) __builtin_va_end(v) _SYS_CDEFS_H_ XREG_CP15_CONTROL_I_BIT 0x00001000 XUARTPS_CR_RX_EN 0x00000004 __ULLACCUM_IBIT__ 32 __DECONST(type,var) ((type)(uintptr_t)(const void *)(var)) XPAR_XSCUTIMER_NUM_INSTANCES 1 __PTRDIFF_MAX__ 2147483647 XUARTPS_OPTION_SET_BREAK 0x0080 __LDBL_MANT_DIG__ 53 XPS_SYSMON_INT_ID 39 XST_NAND_BUSY 1441L __ULLFRACT_FBIT__ 64 XUARTPS_SR_TXFULL 0x00000010 _EXFNPTR(name,proto) (* name) proto XPS_FPGA15_INT_ID 91 XUARTPS_CR_STARTBRK 0x00000080 __INT32_MAX__ 2147483647L _SIZE_T_DEFINED XUARTPS_MR_PARITY_MARK 0x00000018 __CS_SOURCERYGXX_REV__ 46 XPAR_XUARTPS_NUM_INSTANCES 1 __UQQ_IBIT__ 0 XREG_CP15_INST_FAULT_STATUS "p15, 0, %0, c5, c0, 1" ___int8_t_defined 1 XPAR_XTTCPS_5_CLOCK_HZ XPAR_XTTCPS_5_TTC_CLK_FREQ_HZ _Noreturn __dead2 XPAR_PS7_TTC_2_BASEADDR 0XF8001008 __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1 __BSD_VISIBLE 1 XREG_CR6 cr6 XPS_DMA5_INT_ID 73 XPAR_PS7_INTC_DIST_0_S_AXI_HIGHADDR 0xF8F01FFF XPAR_PS7_ETHERNET_0_ENET_SLCR_10MBPS_DIV0 8 XUARTPS_MODEMSR_DDSR 0x00000002 XPAR_XUARTPS_1_INTR XPS_UART1_INT_ID XST_FLASH_BLOCKING_CALL_ERROR 1137L XST_HWICAP_WRITE_DONE 1421 XPAR_PS7_AFI_1_S_AXI_HIGHADDR 0xF8009FFF __ACCUM_MIN__ (-0X1P15K-0X1P15K) __USFRACT_EPSILON__ 0x1P-8UHR __SCHAR_MAX__ 127 XREG_CP15_VA_TO_PA_CURRENT_3 "p15, 0, %0, c7, c8, 3" XUARTPS_FORMAT_2_STOP_BIT 2 __ORDER_BIG_ENDIAN__ 4321 XPAR_XADCPS_NUM_INSTANCES 1 __UFRACT_MAX__ 0XFFFFP-16UR XPAR_PS7_TTC_2_TTC_CLK_CLKSRC 0 _Z15test_peripheralm _MACHINE__DEFAULT_TYPES_H __UINT_FAST32_TYPE__ unsigned int BaseAddress XREG_CP15_CLEAN_DC_LINE_SW "p15, 0, %0, c7, c10, 2" PL_RAM_mWriteMemory(Address,Data) Xil_Out32(Address, (u32)(Data)) XPS_FPGA12_INT_ID 88 XPS_USB0_INT_ID 53 XST_NO_FEATURE 19L XPAR_XUSBPS_1_INTR XPS_USB1_INT_ID XST_NAND_WRITE_PROTECTED 1451L XPAR_PS7_USB_0_DEVICE_ID 0 XREG_MVFR0 c7 Xil_EnableNestedInterrupts() __asm__ __volatile__ ("mrs lr, spsr"); __asm__ __volatile__ ("stmfd sp!, {lr}"); __asm__ __volatile__ ("msr cpsr_c, #0x1F"); __asm__ __volatile__ ("stmfd sp!, {lr}"); __need_wchar_t __FLT_DECIMAL_DIG__ 9 __INT32_TYPE__ long int _T_PTRDIFF XST_EMAC_MEMORY_ALLOC_ERROR 1002L XST_DEVICE_NOT_FOUND 2L __USACCUM_IBIT__ 8 XIL_EXCEPTION_ID_IRQ_INT 5 XREG_CP2 2 XREG_CP15_INVAL_DC_LINE_MVA_POC "p15, 0, %0, c7, c6, 1" XST_UART_CONFIG_ERROR 1053L _READ_WRITE_RETURN_TYPE int XPAR_PS7_ETHERNET_0_INTR XPS_GEM0_INT_ID XUARTPS_SR_TNFUL 0x00004000 XPAR_PS7_QSPI_0_QSPI_CLK_FREQ_HZ 200000000 _REENT_INIT_ATEXIT _NULL, _ATEXIT_INIT, XREG_FPSCR_ROUND_PLUSINF (1 << 22) XPAR_XSDIOPS_1_INTR XPS_SDIO1_INT_ID __UINTPTR_TYPE__ unsigned int XREG_FPSCR_V_BIT (1 << 28) XST_OPBARB_NOT_FIXED_PRIORITY 1179 XREG_CPSR_C_BIT 0x20000000 XPS_DDR_CTRL_BASEADDR 0xF8006000 __LFRACT_FBIT__ 31 XST_IIC_STAND_REG_RESET_ERROR 1079 _SYS_SIZE_T_H XREG_CP15_DATA_MEMORY_BARRIER "p15, 0, %0, c7, c10, 5" XPAR_XADCPS_0_BASEADDR 0xF8007100 __STDC__ 1 __int_least64_t_defined 1 XPAR_PS7_SD_0_SDIO_CLK_FREQ_HZ 50000000 _NOTHROW __attribute__ ((nothrow)) XPS_SDIO0_BASEADDR 0xE0100000 __END_DECLS } XPAR_XGPIOPS_NUM_INSTANCES 1 _EXPARM(name,proto) (* name) proto __UINT16_MAX__ 65535 mtcpsr(v) __asm__ __volatile__( "msr cpsr,%0\n" : : "r" (v) ) __ARM_SIZEOF_MINIMAL_ENUM 1 XPAR_PS7_TTC_0_TTC_CLK_CLKSRC 0 __INT64_C(c) c ## LL XPAR_PS7_DMA_S_BASEADDR 0xF8003000 XST_FR_BUF_LOCKED 1402 XREG_FPSCR_LENGTH_BIT (16) __STDINT_EXP(x) __ ##x ##__ XREG_MVFR0_SQRT_BIT (20) XREG_CP15_EVENT_CNTR_SEL "p15, 0, %0, c9, c12, 5" __DA_FBIT__ 31 XUARTPS_IXR_TTRIG 0x00000400 SIZE_MAX __SIZE_MAX__ XREG_CPSR_UNDEFINED_MODE 0x1B XPAR_PS7_SCUWDT_0_HIGHADDR 0xF8F006FF XUARTPS_CR_EN_DIS_MASK 0x0000003C __XSTRING(x) __STRING(x) __SCCSID(s) struct __hack __GCC_ATOMIC_BOOL_LOCK_FREE 2 __DEC64_MAX__ 9.999999999999999E384DD __ARM_ARCH_7A__ 1 __WCHAR_MAX__ 4294967295U INT_LEAST16_MIN -32768 XPAR_PS7_SCUGIC_0_DIST_BASEADDR 0xF8F01000 XST_FR_NO_BUF 1403 WINT_MIN __WINT_MIN__ XST_DMA_SG_NO_DATA 525L XST_UART __DA_IBIT__ 32 __TQ_FBIT__ 127 __VFP_FP__ 1 XREG_CP15_CONTROL_B_BIT 0x00000080 XREG_MVFR0_DP_BIT (8) XPAR_SCUWDT_0_DEVICE_ID XPAR_PS7_SCUWDT_0_DEVICE_ID XPAR_XADCPS_INT_ID XPS_SYSMON_INT_ID __INT_LEAST8_MAX__ 127 _REENT_CHECK_MISC(ptr) XUARTPS_BAUDGEN_RESET_VAL 0x0000028B _WANT_IO_LONG_LONG 1 XPS_GEM1_INT_ID 77 __ULFRACT_IBIT__ 0 XPAR_XDMAPS_0_BASEADDR 0xF8004000 cpsief() __asm__ __volatile__("cpsie f\n") XPAR_XTTCPS_3_CLOCK_HZ XPAR_XTTCPS_3_TTC_CLK_FREQ_HZ XPAR_PS7_SPI_0_INTR XPS_SPI0_INT_ID XPS_FPGA4_INT_ID 65 UINT_FAST8_MAX (__STDINT_EXP(INT_MAX)*2U+1U) XST_NO_CALLBACK 18L XPAR_PS7_ETHERNET_0_WAKE_INTR XPS_GEM0_WAKE_INT_ID __ARM_NEON__ 1 XREG_CP15_CONFIG_BASE_ADDR "p15, 4, %0, c15, c0, 0" __SIZEOF_DOUBLE__ 8 __LDBL_MAX_EXP__ 1024 XPAR_XTTCPS_1_DEVICE_ID XPAR_PS7_TTC_1_DEVICE_ID XPS_CAN1_INT_ID 83 XREG_CR0 cr0 XPAR_XTTCPS_1_TTC_CLK_FREQ_HZ 111111115 XUARTPS_CR_STOPBRK 0x00000100 XREG_FPSCR_IXC (1 << 4) _BSD_WCHAR_T_ XPAR_XTTCPS_1_TTC_CLK_CLKSRC 0 XREG_FPSCR_STRIDE_MASK (3 << FPSCR_STRIDE_BIT) XPS_SAM_RAM_BASEADDR 0xFFFC0000 _RAND48_ADD (0x000b) XPAR_XUARTPS_0_CLOCK_HZ XPAR_XUARTPS_0_UART_CLK_FREQ_HZ __scanflike(fmtarg,firstvararg) __attribute__((__format__ (__scanf__, fmtarg, firstvararg))) XUARTPS_OPTION_STOP_BREAK 0x0040 XREG_CP15_TTBR1 "p15, 0, %0, c2, c0, 1" XREG_CP15_SECURE_DEBUG_ENABLE "p15, 0, %0, c1, c1, 1" INT16_MAX 32767 __INT_FAST32_MAX__ 2147483647 __LLACCUM_FBIT__ 31 XIL_EXCEPTION_ID_PREFETCH_ABORT_INT 3 XPS_DEV_CFG_APB_BASEADDR 0xF8007000 _REENT_MP_FREELIST(ptr) ((ptr)->_freelist) __signed signed __DEPRECATED 1 strb(adr,val) __asm__ __volatile__( "strb %0,[%1]\n" : : "r" (val), "r" (adr) ) XUARTPS_MODEMCR_DTR 0x00000001 _SYS_FEATURES_H XPAR_XTTCPS_0_BASEADDR 0xF8001000 __arm__ 1 XREG_CP15_INVAL_BRANCH_ARRAY "p15, 0, %0, c7, c5, 6" XUartPs_GetModeControl(InstancePtr) Xil_In32(((InstancePtr)->Config.BaseAddress) + XUARTPS_CR_OFFSET) CallBackRef XPAR_PS7_GPV_0_S_AXI_HIGHADDR 0xF89FFFFF XNULL NULL UINT_LEAST16_MAX 65535 XPAR_PS7_XADC_0_DEVICE_ID 0 XPAR_PS7_PMU_0_S_AXI_HIGHADDR 0xF8891FFF XPS_SPI1_INT_ID 81 test_address __ATOMIC_ACQ_REL 4 DATA_SYNC dsb() XIL_EXCEPTION_ID_LAST 6 _FVWRITE_IN_STREAMIO 1 _SIZET_ __INT8_TYPE__ signed char __LDBL_DENORM_MIN__ 4.9406564584124654e-324L XUARTPS_FLOWDEL_OFFSET 0x38 XREG_FPSID_VARIANT_MASK (0xF << FPSID_VARIANT_BIT) XREG_FPSCR_ROUND_MINUSINF (2 << 22) XIL_COMPONENT_IS_STARTED 0x22222222 _STDDEF_H_ __RAND_MAX XPAR_XDCFG_0_DEVICE_ID XPAR_PS7_DEV_CFG_0_DEVICE_ID XREG_CP15_PROC_FEATURE_0 "p15, 0, %0, c0, c1, 0" __GNUC_PREREQ__(ma,mi) __GNUC_PREREQ(ma, mi) __ACCUM_MAX__ 0X7FFFFFFFP-15K __ARM_PCS 1 __INT_FAST32_TYPE__ int __lock_init_recursive(lock) (_CAST_VOID 0) XPAR_XUARTPS_0_HAS_MODEM 0 XREG_CP15_TCM_TYPE "p15, 0, %0, c0, c0, 2" XST_SPI_RECEIVE_OVERRUN 1154 XREG_GPR15 r15 __DEQUALIFY(type,var) ((type)(uintptr_t)(const volatile void *)(var)) XPAR_PS7_UART_1_BASEADDR 0xE0001000 XPAR_PS7_AFI_3_S_AXI_HIGHADDR 0xF800BFFF INT_FAST64_MIN INT_LEAST64_MIN XSTATUS_H XST_NAND_ALIGNMENT_ERROR 1448L XUartPs_IsTransmitEmpty(InstancePtr) ((Xil_In32(((InstancePtr)->Config.BaseAddress) + XUARTPS_SR_OFFSET) & XUARTPS_SR_TXEMPTY) == XUARTPS_SR_TXEMPTY) XPS_UART0_BASEADDR 0xE0000000 XUARTPS_SR_OVER 0x00000020 __ATTRIBUTE_IMPURE_PTR__ XPS_GEM0_WAKE_INT_ID 55 __int_fast64_t_defined 1 _S 010 XREG_CP15_CONTROL_C_BIT 0x00000004 XPAR_PS7_SLCR_0_S_AXI_HIGHADDR 0xF8000FFF XREG_CR15 cr15 XPAR_PS7_AFI_0_S_AXI_BASEADDR 0xF8008000 _REENT_SIGNAL_SIZE 24 XUARTPS_OPER_MODE_AUTO_ECHO 0x01 __GNUC_GNU_INLINE__ 1 XREG_CP15_MAIN_TLB_ATTR "p15, 5, %0, c15, c7, 2" XPS_PARPORT_CRTL_BASEADDR 0xE000E000 _BSD_PTRDIFF_T_ __WCHAR_T XREG_MVFR0_SQRT_MASK (0xF << XREG_MVFR0_SQRT_BIT) XPAR_PS7_SCUWDT_0_DEVICE_ID 0 XREG_CP15_INST_FEATURE_4 "p15, 0, %0, c0, c2, 4" XREG_CP15_MEMORY_FEATURE_3 "p15, 0, %0, c0, c1, 7" XREG_CP3 3 __LACCUM_IBIT__ 32 XIL_EXCEPTION_H XPS_GEM0_INT_ID 54 __ULLFRACT_EPSILON__ 0x1P-64ULLR XPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV0 8 __DEC64_MIN__ 1E-383DD XST_DMA_SG_LIST_FULL 517L __INT16_C(c) c __THROW XPAR_PL_RAM_NUM_INSTANCES 1 SIG_ATOMIC_MIN (-__STDINT_EXP(INT_MAX) - 1) XST_DEVICE_IS_STOPPED 6L WCHAR_MIN __WCHAR_MIN__ __attribute_format_strfmon__(a,b) XPAR_PS7_TTC_0_TTC_CLK_FREQ_HZ 111111115 __SIZEOF_SHORT__ 2 XPAR_XTTCPS_1_CLOCK_HZ XPAR_XTTCPS_1_TTC_CLK_FREQ_HZ XREG_CR14 cr14 UINTPTR_MAX __UINTPTR_MAX__ __have_long32 1 XREG_CP15_AUX_INST_FAULT_STATUS "p15, 0, %0, c5, c1, 1" XPAR_XSPIPS_1_INTR XPS_SPI1_INT_ID XUARTPS_FORMAT_6_BITS 3 XUARTPS_SR_FRAME 0x00000040 XPS_FPGA11_INT_ID 87 XREG_CP15_TTB_CONTROL "p15, 0, %0, c2, c0, 2" XPAR_XSCUTIMER_0_HIGHADDR 0xF8F0061F Xil_ExceptionDisableMask(Mask) mtcpsr(mfcpsr() | (Mask & XIL_EXCEPTION_ALL)) XUARTPS_FORMAT_SPACE_PARITY 2 __ULFRACT_MIN__ 0.0ULR _REENT_WCRTOMB_STATE(ptr) ((ptr)->_new._reent._wcrtomb_state) XPS_CORE_PARITY1_INT_ID 33 XPAR_PS7_UART_1_DEVICE_ID 0 __UINT64_MAX__ 18446744073709551615ULL _REENT_SMALL_CHECK_INIT(ptr) __need_wint_t XREG_CR13 cr13 XPAR_PS7_UART_1_HIGHADDR 0xE0001FFF XST_IPIF_DEVICE_STATUS_ERROR 533L XPAR_XEMACPS_0_ENET_SLCR_1000Mbps_DIV0 8 _T_SIZE XREG_MVFR0_SP_MASK (0xF << XREG_MVFR0_SP_BIT) INT32_MAX 2147483647L XPAR_PS7_GLOBALTIMER_0_S_AXI_HIGHADDR 0xF8F002FF XIL_EXCEPTION_ID_RESET 0 XPSEUDO_ASM_GCC_H INT64_C(x) x ##LL XPAR_SCUGIC_DIST_BASEADDR (XPS_SCU_PERIPH_BASE + 0x1000) __SFRACT_EPSILON__ 0x1P-7HR __ATOMIC_CONSUME 1 __unused __attribute__((__unused__)) __FLT_MIN__ 1.1754943508222875e-38F __INT_LEAST16_TYPE__ short int XST_EMAC_OUT_OF_BUFFERS 1005L __INTMAX_MAX__ 9223372036854775807LL XREG_CP15 15 __USFRACT_FBIT__ 8 cpsiei() __asm__ __volatile__("cpsie i\n") XPAR_XSCUGIC_NUM_INSTANCES 1 XST_UART_TEST_FAIL 1054L XUARTPS_FORMAT_7_BITS 2 __GCC_ATOMIC_WCHAR_T_LOCK_FREE 2 __LLFRACT_FBIT__ 63 __SIZEOF_PTRDIFF_T__ 4 __restrict _REENT_TM(ptr) (&(ptr)->_new._reent._localtime_buf) XST_IPIF_IP_ENABLE_ERROR 538L Xil_ExceptionDisable() Xil_ExceptionDisableMask(XIL_EXCEPTION_IRQ) /home/mwerner/Projekte/MEMSEC/HW/HW.sdk/test/Debug INT16_MIN -32768 XPAR_XDMAPS_1_HIGHADDR 0xF8003FFF _ATTRIBUTE(attrs) __attribute__ (attrs) XPAR_PS7_SCUGIC_0_HIGHADDR 0xF8F001FF _VA_LIST_T_H XPAR_XSLCR_0_BASEADDR XPS_SYS_CTRL_BASEADDR XST_DMA_ERROR 9L XST_IPIF_DEVICE_PENDING_ERROR 539L XUARTPS_MEDEMSR_CTSX XUARTPS_MODEMSR_DCTS __UINT_LEAST16_MAX__ 65535 XPAR_XQSPIPS_0_HIGHADDR 0xE000DFFF __DBL_MIN_EXP__ (-1021) __exported __attribute__((__visibility__("default"))) XStatus XST_IIC_GENERAL_CALL_ADDRESS 1078 XREG_CP15_WRITE_TLB_ENTRY "p15, 5, %0, c15, c4, 4" XST_DEVICE_BUSY 21L _REENT_MBRLEN_STATE(ptr) ((ptr)->_new._reent._mbrlen_state) XPAR_XQSPIPS_0_DEVICE_ID XPAR_PS7_QSPI_0_DEVICE_ID XREG_CR3 cr3 XREG_CR8 cr8 UINT_LEAST32_MAX 4294967295UL __CC_SUPPORTS___INLINE__ 1 XREG_CP15_CONTROL_A_BIT 0x00000002 __CC_SUPPORTS_DYNAMIC_ARRAY_INIT 1 XPAR_PS7_ETHERNET_0_DEVICE_ID 0 XST_IS_STARTED 23L XST_FLASH_ALIGNMENT_ERROR 1136L __LDBL_MAX_10_EXP__ 308 Mem32Value INT_LEAST64_MAX 9223372036854775807LL __IMPORT ___int32_t_defined 1 XPAR_XEMACPS_0_HIGHADDR 0xE000BFFF XUARTPS_FORMAT_8_BITS 0 __INT64_TYPE__ long long int INT_FAST8_MAX __STDINT_EXP(INT_MAX) XUARTPS_OPTION_SET_FCM 0x0001 __DBL_DENORM_MIN__ double(4.9406564584124654e-324L) __TA_FBIT__ 63 __DEC32_MAX__ 9.999999E96DF XPAR_PS7_INTC_DIST_0_S_AXI_BASEADDR 0xF8F01000 XST_SPI_SLAVE_MODE_FAULT 1159 __malloc_like __attribute__((__malloc__)) ___int_ptrdiff_t_h __lock_try_acquire_recursive(lock) (_CAST_VOID 0) INT8_MIN -128 __UINT_LEAST32_TYPE__ long unsigned int __SHRT_MAX__ 32767 _NOINLINE_STATIC _NOINLINE static XPAR_SCUWDT_DEVICE_ID 0 _LONG_DOUBLE long double XREG_CP13 13 XREG_CPSR_MODE_BITS 0x1F STDIN_BASEADDRESS 0xE0001000 __HA_IBIT__ 8 __TA_IBIT__ 64 _ATEXIT_INIT {_NULL, 0, {_NULL}, {{_NULL}, {_NULL}, 0, 0}} XPAR_XTTCPS_0_TTC_CLK_FREQ_HZ 111111115 _P 020 XPAR_PS7_IOP_BUS_CONFIG_0_S_AXI_HIGHADDR 0xE0200FFF __ATOMIC_RELEASE 3 __HQ_IBIT__ 0 XUARTPS_CR_RX_DIS 0x00000008 XREG_CPSR_IRQ_ENABLE 0x80 __SA_IBIT__ 16 XUARTPS_MODEMSR_OFFSET 0x28 XUARTPS_BAUDGEN_MASK 0x0000FFFF __COPYRIGHT(s) struct __hack _WIDE_ORIENT 1 XUARTPS_CR_OFFSET 0x00 __UHA_FBIT__ 8 XST_EMAC_MII_BUSY 1004L XREG_CP15_PROC_FEATURE_1 "p15, 0, %0, c0, c1, 1" XST_RECV_ERROR 27L XREG_CP15_INVAL_UTLB_UNLOCKED "p15, 0, %0, c8, c7, 0" XPS_TTC1_1_INT_ID 70 __DEC128_SUBNORMAL_MIN__ 0.000000000000000000000000000000001E-6143DL __ARM_FEATURE_CLZ 1 XST_IPIF_ERROR 541L XREG_CP15_INVAL_IC_POU "p15, 0, %0, c7, c5, 0" __UINT8_MAX__ 255 __ARM_FEATURE_LDREX 15 XREG_FPEXC c8 XUARTPS_EVENT_RECV_DATA 1 XREG_CP15_INTR_ENABLE_CLR "p15, 0, %0, c9, c14, 2" XPS_IOU_BUS_CFG_BASEADDR 0xE0200000 XPAR_XDMAPS_0_DONE_INTR_7 XPS_DMA7_INT_ID XREG_CP15_DATA_FAULT_STATUS "p15, 0, %0, c5, c0, 0" XPAR_PS7_USB_1_INTR XPS_USB1_INT_ID __DEC32_MIN_EXP__ (-94) __ULACCUM_EPSILON__ 0x1P-32ULK test_peripheral _REENT_CHECK_TM(ptr) INT8_MAX 127 XPS_DVC_INT_ID 40 SYNCHRONIZE_IO dmb() __ARM_ARCH 7 XIL_CACHE_H str(adr,val) __asm__ __volatile__( "str %0,[%1]\n" : : "r" (val), "r" (adr) ) __CONCAT(x,y) __CONCAT1(x,y) XUARTPS_OPER_MODE_NORMAL 0x00 __DBL_HAS_QUIET_NAN__ 1 __LDBL_MIN_10_EXP__ (-307) stringify(s) tostring(s) __DEC32_MANT_DIG__ 7 XREG_CP15_POWER_CTRL "p15, 0, %0, c15, c0, 0" XREG_CP4 4 __UINTPTR_MAX__ 4294967295U __USFRACT_IBIT__ 0 XST_REGISTER_ERROR 14L XREG_CPSR cpsr _REENT_ASCTIME_SIZE 26 __DEC_EVAL_METHOD__ 2 XPAR_PS7_ETHERNET_0_HIGHADDR 0xE000BFFF __LDBL_HAS_INFINITY__ 1 XREG_CP11 11 XUARTPS_FORMAT_NO_PARITY 4 _FSEEK_OPTIMIZATION 1 __GXX_WEAK__ 1 XPAR_XSDPS_NUM_INSTANCES 1 XPAR_XUARTPS_0_INTR XPS_UART0_INT_ID XST_DMA_RESET_REGISTER_ERROR 512L XPS_UART0_INT_ID 59 XST_USB_BUF_ALIGN_ERROR 1411 XUARTPS_MEDEMSR_DSRX XUARTPS_MODEMSR_DDSR XREG_CR5 cr5 __UINT_FAST32_MAX__ 4294967295U __SIZEOF_LONG_DOUBLE__ 8 XUARTPS_OPTION_ASSERT_DTR 0x0002 XUARTPS_SR_TXEMPTY 0x00000008 13XUartPsBuffer Xil_Out32LE(Addr,Value) Xil_Out32(Addr, Value) XPAR_XSCUTIMER_0_BASEADDR 0xF8F00600 XPS_ECC_INT_ID 36 __FLT_HAS_DENORM__ 1 __GNUCLIKE_MATH_BUILTIN_CONSTANTS INT32_C(x) x ##L XPS_TTC1_2_INT_ID 71 XPS_PARPORT1_BASEADDR 0xE4000000 XPS_GEM0_BASEADDR 0xE000B000 XPAR_XEMACPS_0_BASEADDR 0xE000B000 XPAR_PS7_GPIO_0_HIGHADDR 0xE000AFFF ___Static_assert(x,y) typedef char __assert_ ## y[(x) ? 1 : -1] XUARTPS_FORMAT_EVEN_PARITY 0 UINT16_C(x) x __TQ_IBIT__ 0 XPAR_XTTCPS_2_DEVICE_ID XPAR_PS7_TTC_2_DEVICE_ID XPAR_PS7_CORESIGHT_COMP_0_S_AXI_BASEADDR 0xF8800000 XREG_GPR13 r13 __SIZEOF_FLOAT__ 4 main XPAR_GLOBAL_TMR_DEVICE_ID 0 __SIZE_T__ __SIZE_TYPE__ unsigned int XST_FAILURE 1L cpsidf() __asm__ __volatile__("cpsid f\n") XST_FLASH_TIMEOUT_ERROR 1134L _Alignof(x) __alignof(x) __offsetof(type,field) offsetof(type, field) XST_IIC_RX_FIFO_REG_RESET_ERROR 1081 __UINT_LEAST8_TYPE__ unsigned char _RAND48_SEED_1 (0xabcd) XST_NAND_PARAM_PAGE_ERROR 1449L XREG_CP15_INVAL_UTLB_MVA "p15, 0, %0, c8, c7, 1" XPAR_XDMAPS_0_DONE_INTR_6 XPS_DMA6_INT_ID __STRING(x) #x XPAR_PS7_IOP_BUS_CONFIG_0_S_AXI_BASEADDR 0xE0200000 _ELIDABLE_INLINE extern __inline__ _ATTRIBUTE ((__always_inline__)) XPAR_XADCPS_0_DEVICE_ID XPAR_PS7_XADC_0_DEVICE_ID __CHAR16_TYPE__ short unsigned int XPAR_XSLCR_NUM_INSTANCES 1 __UFRACT_FBIT__ 16 INT64_MAX 9223372036854775807LL XUARTPS_MR_CHARLEN_SHIFT 1 XREG_CP15_NOP "p15, 0, %0, c7, c0, 4" XST_EMAC_MII_READ_ERROR 1003L XST_SPI_SLAVE_MODE 1160 XREG_CP15_INST_FEATURE_0 "p15, 0, %0, c0, c2, 0" XREG_CPSR_USER_MODE 0x10 XPAR_XSCUWDT_NUM_INSTANCES 1 INT_LEAST8_MAX 127 XREG_CP15_INVAL_ITLB_UNLOCKED "p15, 0, %0, c8, c5, 0" XREG_FPINST2 c10 XST_PCI_INVALID_ADDRESS 1361L XREG_MVFR0_EXEC_TRAP_BIT (12) NextBytePtr XUARTPS_SR_FLOWDEL 0x00001000 XST_FLASH_WRITE_SUSPENDED 1130L XPS_OCM_BASEADDR 0xF800C000 _MACHINE__TYPES_H XPAR_XSDPS_0_DEVICE_ID XPAR_PS7_SD_0_DEVICE_ID XUARTPS_MR_CHMODE_MASK 0x00000300 UINT32_MAX 4294967295UL Xil_ExceptionEnableMask(Mask) mtcpsr(mfcpsr() & ~ (Mask & XIL_EXCEPTION_ALL)) PL_RAM_mReadMemory(Address) Xil_In32(Address) INTMAX_MAX __INTMAX_MAX__ XPS_I2C0_INT_ID 57 XST_FLASH_PART_NOT_SUPPORTED 1131L __UINT_LEAST16_TYPE__ short unsigned int XREG_CP15_PERF_CYCLE_COUNTER "p15, 0, %0, c9, c13, 0" _LDBL_EQ_DBL 1 XPAR_XUSBPS_0_INTR XPS_USB0_INT_ID __GNUC__ 4 ../src/main.cc XST_DMA_SG_LIST_EXISTS 522L XST_DATA_LOST 26L XREG_MVFR0_A_SIMD_BIT (0) XREG_FPSCR_ROUND_NEAREST (0 << 22) _STDARG_H XREG_CP15_TTBR0 "p15, 0, %0, c2, c0, 0" UINTMAX_MAX __UINTMAX_MAX__ __INT_LEAST32_TYPE__ long int XUARTPS_CR_TX_EN 0x00000010 __ARM_ARCH_ISA_THUMB 2 XPAR_PS7_RAM_1_S_AXI_HIGHADDR 0xFFFFFFFF __UHA_IBIT__ 8 XUARTPS_FIFO_OFFSET 0x30 XREG_GPR8 r8 XIL_IO_H XUARTPS_MR_CCLK 0x00000400 __LFRACT_MAX__ 0X7FFFFFFFP-31LR XPAR_XDMAPS_0_DONE_INTR_5 XPS_DMA5_INT_ID XREG_CR2 cr2 INTMAX_C(x) x ##LL /home/mwerner/Projekte/MEMSEC/HW/HW.sdk/bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src SWInterrupt FIQInterrupt Data DataAbortInterrupt GNU C 4.8.1 -march=armv7-a -mfloat-abi=soft -mfpu=neon -g -O2 XExc_VectorTable XExc_VectorTableEntry Xil_ExceptionHandler vectors.c IRQInterrupt PrefetchAbortInterrupt DieLoop exception_id Xil_ExceptionRegisterHandler Xil_ExceptionRemoveHandler index Xil_ExceptionInit xil_exception.c Xil_ExceptionNullHandler LoWord Xil_In16BE HiWord Xil_Out16BE Xil_EndianSwap16 Xil_EndianSwap32 Xil_Out32BE Xil_Out16 xil_io.c Xil_Out32 temp Xil_In16 Xil_In32BE Xil_In32 OutAddress Xil_Out8 Xil_In8 digits xil_printf outnum outbuf long_flag outs num1 strlen num2 __ctype_ptr__ ctrl1 left_flag do_padding l_flag charptr params_t __ap getnum ctrl try_next argp params_s dot_flag xil_printf.c linep pad_character outbyte __gnuc_va_list negative Xtime xtime_l.c XTime_GetTime high XTime_SetTime XTime BytesSent XUartPs_SendBuffer XUartPs_SetBaudRate ReceivedCount xuartps.c CsrRegister BRGR_Value XUartPs_StubHandler Event BufferPtr BaudError /home/mwerner/Projekte/MEMSEC/HW/HW.sdk/bsp/ps7_cortexa9_0/libsrc/uartps_v2_1/src XUartPs_Send PercentError GNU C 4.8.1 -march=armv7-a -mfloat-abi=softfp -mfpu=neon-fp16 -g -O2 EffectiveAddr InputClk XUartPs_CfgInitialize ModeReg InstancePtr XUartPs_ReceiveBuffer Best_BRGR CalcBaudRate Xil_AssertStatus ModeRegister IterBAUDDIV ImrRegister NumBytes SentCount Xil_Assert ByteCount Best_BAUDDIV Best_Error XUartPs_Recv xuartps_sinit.c XUartPs_LookupConfig XUartPs_ConfigTable CfgPtr outbyte.c XUartPs_SendByte Xil_AssertCallback XNullHandler Line Xil_AssertSetCallback File Xil_AssertCallbackRoutine Xil_AssertWait xil_assert.c NullParameter xuartps_g.c xuartps_hw.c XUartPs_RecvByte XUartPs_ResetHw status _exit.c _exit _getpid getpid.c kill.c _kill incr _sbrk.c prev_heap _sbrk _heap_start caddr_t _heap_end _write nbytes write.c close.c _close st_mtime nlink_t st_atime __uid_t st_nlink st_size ino_t st_ino st_spare1 st_spare2 st_spare3 st_spare4 __dev_t st_blocks st_mode _off_t st_rdev st_ctime time_t st_uid __gid_t fstat.c _fstat st_dev st_gid st_blksize mode_t isatty.c _isatty _lseek __errno whence lseek.c _read read.c inbyte __sdidinit _flags2 _mblen_state _l64a_buf __wch _lbfsize __value __sbuf _result_k _offset __sf _signal_buf _wcsrtombs_state _localtime_buf __count __tm_mday _glue _mbsrtowcs_state _r48 _stdout _atexit _emergency _cvtlen _nbuf _LOCK_RECURSIVE_T _niobs __FILE _getdate_err __tm_min _sig_func _nmalloc _freelist _data _fns _mbstate __tm_wday _fnargs errno.c _lock _mult __tm_isdst _atexit0 _fntypes _fpos_t _flock_t __tm_sec __tm_hour _nextf _stderr __wchb _h_errno __sglue _on_exit_args _mbrtowc_state _cvtbuf _cookie _base _file _gamma_signgam _unused_rand _wds __tm _unused _mbtowc_state _mbrlen_state _current_category _is_cxa __cleanup _mbstate_t _Bigint _maxwds __tm_year _strtok_last _seed _rand48 __tm_yday _iobs __ULong _seek _result __tm_mon _add _inc _ind _wctomb_state _dso_handle _p5s _sign _rand_next _stdin _current_locale _reent _wcrtomb_state _flags _ubuf _asctime_buf __sFILE _new inbyte.c
GCC: (Sourcery CodeBench Lite 2013.11-46) 4.8.1
.symtab .strtab .shstrtab .text .init .fini .rodata .ARM.extab.text.__cxa_pure_virtual .ARM.extab.text.__cxa_deleted_virtual .ARM.extab.text._ZL21base_of_encoded_valuehP15_Unwind_Context .ARM.extab.text.__gxx_personality_v0 .ARM.extab.text.__cxa_begin_catch .ARM.extab.text._ZN10__cxxabiv111__terminateEPFvvE .ARM.extab.text._ZN10__cxxabiv112__unexpectedEPFvvE .ARM.extab.text._ZSt10unexpectedv .ARM.extab.text.__cxa_call_unexpected .ARM.extab.text._ZN9__gnu_cxx27__verbose_terminate_handlerEv .data .eh_frame .mmu_tbl .ARM.exidx .init_array .fini_array .ARM.attributes .bss .heap .stack .debug_info .debug_abbrev .debug_aranges .debug_macro .debug_line .debug_str .comment .debug_frame .debug_loc .debug_ranges
asm_vectors.o $a Undefined SVCHandler PrefetchAbortHandler DataAbortHandler FIQHandler FIQLoop $d boot.o PSS_L2CC_BASE_ADDR PSS_SLCR_BASE_ADDR RESERVED LRemap L2CCWay L2CCSync L2CCCrtl L2CCAuxCrtl L2CCTAGLatReg L2CCDataLatReg L2CCIntClear L2CCIntRaw SLCRlockReg SLCRUnlockReg SLCRL2cRamReg CRValMmuCac CRValHiVectorAddr L2CCAuxControl L2CCControl L2CCTAGLatency L2CCDataLatency SLCRlockKey SLCRUnlockKey SLCRL2cRamConfig FPEXC_EN OKToRun EndlessLoop0 invalidate_dcache Sync finished loop1 skip loop2 loop3 /optl/Xilinx2014.2/SDK/2014.2/gnu/arm/lin/bin/../lib/gcc/arm-xilinx-eabi/4.8.1/crti.o crtstuff.c __EH_FRAME_BEGIN__ __JCR_LIST__ deregister_tm_clones register_tm_clones __do_global_dtors_aux completed.8780 __do_global_dtors_aux_fini_array_entry frame_dummy object.8785 __frame_dummy_init_array_entry main.cc translation_table.o SECT vectors.c xil-crt0.S xil_exception.c Xil_ExceptionNullHandler xil_io.c xil_printf.c padding.part.0 xtime_l.c xuartps.c XUartPs_StubHandler xuartps_sinit.c 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