1gpu_id: 201 2cmd: deqp-gles2/185: fence=1250 3############################################################ 4cmdstream: 124 dwords 5t0 write RB_BC_CONTROL (0f01) 6 RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 } 70122d000: 0000: 00000f01 1c004046 8t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 9 PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 } 100122d008: 0000: c0012d00 00040293 00000020 11t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 12 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 } 130122d014: 0000: c0012d00 00040316 00000002 14t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 15 VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 } 160122d020: 0000: c0012d00 00040317 00000002 17t0 write CP_PERFMON_CNTL (0444) 18 CP_PERFMON_CNTL: 0 190122d02c: 0000: 00000444 00000000 20t0 write RBBM_PM_OVERRIDE1 (039c) 21 RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE } 22 RBBM_PM_OVERRIDE2: 0xfff 230122d034: 0000: 0001039c ffffffff 00000fff 24t0 write TP0_CHICKEN (0e1e) 25 TP0_CHICKEN: 0x2 260122d040: 0000: 00000e1e 00000002 27t3 opcode: CP_INVALIDATE_STATE (3b) (2 dwords) 280122d048: 0000: c0003b00 00007fff 29t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 30 SQ_VS_CONST: { BASE = 32 | SIZE = 256 } 310122d050: 0000: c0012d00 00040307 00100020 32t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 33 SQ_PS_CONST: { BASE = 288 | SIZE = 224 } 340122d05c: 0000: c0012d00 00040308 000e0120 35t3 opcode: CP_SET_CONSTANT (2d) (4 dwords) 36 VGT_MAX_VTX_INDX: 0xffffffff 37 VGT_MIN_VTX_INDX: 0 380122d068: 0000: c0022d00 00040100 ffffffff 00000000 39t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 40 VGT_INDX_OFFSET: 0 410122d078: 0000: c0012d00 00040102 00000000 42t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 43 SQ_CONTEXT_MISC: { SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 } 440122d084: 0000: c0012d00 00040181 00000004 45t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 46 SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 } 470122d090: 0000: c0012d00 00040182 ffffffff 48t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 49 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 } 500122d09c: 0000: c0012d00 00040301 00000000 51t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 52 PA_SC_LINE_CNTL: { BRES_CNTL = 0 } 530122d0a8: 0000: c0012d00 00040300 00000000 54t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 55 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 } 560122d0b4: 0000: c0012d00 00040080 00000000 57t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 58 RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH } 590122d0c0: 0000: c0012d00 00040208 00000004 60t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 61 RB_SAMPLE_POS: 0x88888888 620122d0cc: 0000: c0012d00 0004020a 88888888 63t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 64 RB_COLOR_DEST_MASK: 0xffffffff 650122d0d8: 0000: c0012d00 00040326 ffffffff 66t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 67 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 680122d0e4: 0000: c0012d00 0004031b 0003c000 69t3 opcode: CP_SET_CONSTANT (2d) (4 dwords) 70 SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 } 71 SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 } 720122d0f0: 0000: c0022d00 00040183 00000000 00000000 73t3 opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords) 740122d100: 0000: c0004b00 00000000 75t3 opcode: CP_WAIT_REG_EQ (52) (5 dwords) 760122d108: 0000: c0035200 000005d0 00000000 5f601000 00000001 77t0 write SQ_INST_STORE_MANAGMENT (0d02) 78 SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 } 790122d11c: 0000: 00000d02 00000180 80t3 opcode: CP_INVALIDATE_STATE (3b) (2 dwords) 810122d124: 0000: c0003b00 00000300 82t3 opcode: CP_SET_SHADER_BASES (4a) (2 dwords) 830122d12c: 0000: c0004a00 80000180 84t3 opcode: CP_SET_CONSTANT (2d) (14 dwords) 850122d13c: 0.000000 0.000000 0.000000 0.000000 20000.000000 1.000000 0.500000 0.000000 860122d15c: 2.000000 0.750000 0.375000 0.250000 870122d134: 0000: c00c2d00 00000000 00000000 00000000 00000000 00000000 469c4000 3f800000 880122d154: 0020: 3f000000 00000000 40000000 3f400000 3ec00000 3e800000 89t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 90 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 910122d16c: 0000: c0012d00 00040104 0000000f 92t3 opcode: CP_SET_CONSTANT (2d) (6 dwords) 93 RB_BLEND_RED: 0 94 RB_BLEND_GREEN: 0 95 RB_BLEND_BLUE: 0 96 RB_BLEND_ALPHA: 0xff 970122d178: 0000: c0042d00 00040105 00000000 00000000 00000000 000000ff 98t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 99 PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT } 1000122d190: 0000: c0012d00 00040206 0000043f 101t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 102 RB_SURFACE_INFO: { SURFACE_PITCH = 64 | MSAA_SAMPLES = 0 } 1030122d19c: 0000: c0012d00 00040000 00000040 104t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 105 RB_COLOR_INFO: { FORMAT = COLORX_16_16_16_16_FLOAT | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 0 | BASE = 0x110d000 } 1060122d1a8: 0000: c0012d00 00040001 0110d009 107t3 opcode: CP_SET_CONSTANT (2d) (4 dwords) 108 PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 } 109 PA_SC_SCREEN_SCISSOR_BR: { X = 64 | Y = 128 } 1100122d1b4: 0000: c0022d00 0004000e 80000000 00800040 111t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 112 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 } 1130122d1c4: 0000: c0012d00 00040080 00000000 114t0 write CP_SCRATCH_REG6 (057e) 115 CP_SCRATCH_REG6: 9 116 :0,0,9,0 1170122d1d0: 0000: 0000057e 00000009 118t3 opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords) 119 ibaddr:0122e000 120 ibsize:000000b6 121t3 opcode: CP_SET_CONSTANT (2d) (6 dwords) 122 set shader const 0078 1230122e000: 0000: c0042d00 00010078 0112d003 00100000 0112d003 00100000 124t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 125 PA_SC_AA_MASK: 0xffff 1260122e018: 0000: c0012d00 00040312 0000ffff 127t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 128 RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP } 1290122e024: 0000: c0012d00 00040200 00000000 130t3 opcode: CP_SET_CONSTANT (2d) (5 dwords) 131 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 132 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 133 RB_ALPHA_REF: 0 1340122e030: 0000: c0032d00 0004010c 00000000 00000000 00000000 135t3 opcode: CP_SET_CONSTANT (2d) (4 dwords) 136 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL } 137 PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST } 1380122e044: 0000: c0022d00 00040204 00000000 00090244 139t3 opcode: CP_SET_CONSTANT (2d) (6 dwords) 140 PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 } 141 PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 } 142 PA_SU_LINE_CNTL: { WIDTH = 0.000000 } 143 PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER } 1440122e054: 0000: c0042d00 00040280 00000000 00000000 00000000 00000000 145t3 opcode: CP_SET_CONSTANT (2d) (7 dwords) 146 PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH } 147 PA_CL_GB_VERT_CLIP_ADJ: 1.000000 148 PA_CL_GB_VERT_DISC_ADJ: 1.000000 149 PA_CL_GB_HORZ_CLIP_ADJ: 1.000000 150 PA_CL_GB_HORZ_DISC_ADJ: 1.000000 1510122e06c: 0000: c0052d00 00040302 00000001 3f800000 3f800000 3f800000 3f800000 152t3 opcode: CP_SET_CONSTANT (2d) (4 dwords) 153 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 154 PA_SC_WINDOW_SCISSOR_BR: { X = 64 | Y = 128 } 1550122e088: 0000: c0022d00 00040081 00000000 00800040 156t3 opcode: CP_SET_CONSTANT (2d) (8 dwords) 157 PA_CL_VPORT_XSCALE: 32.000000 158 PA_CL_VPORT_XOFFSET: 32.000000 159 PA_CL_VPORT_YSCALE: 64.000000 160 PA_CL_VPORT_YOFFSET: 64.000000 161 PA_CL_VPORT_ZSCALE: 0.000000 162 PA_CL_VPORT_ZOFFSET: 0.000000 1630122e098: 0000: c0062d00 0004010f 42000000 42000000 42800000 42800000 00000000 00000000 164t3 opcode: CP_SET_CONSTANT (2d) (10 dwords) 1650122e0c0: 32.000000 64.000000 0.000000 0.000000 32.000000 64.000000 0.000000 0.000000 1660122e0b8: 0000: c0082d00 00000184 42000000 42800000 00000000 00000000 42000000 42800000 167* 168t3 opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords) 169 vertex shader, start=0000, size=0015 170 2003 0007 1000 EXEC ADDR(0x3) CNT(0x2) 171 03: 19481000 00262688 00000020 (S)FETCH: VERTEX R1.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) CONST(20, 0) 172 04: 13480000 40262688 00001020 FETCH: VERTEX R0.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) OFFSET(16) CONST(20, 1) 173 0000 0000 c200 ALLOC POSITION SIZE(0x0) 174 1005 0002 1000 EXEC ADDR(0x5) CNT(0x1) 175 05: 000f803e 00000000 c2010100 (S)ALU: MAXv export62 = R1, R1 ; gl_Position 176 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0) 177 1006 0000 2000 EXEC_END ADDR(0x6) CNT(0x1) 178 06: 000f8000 00000000 c2000000 ALU: MAXv export0 = R0, R0 179 0000 0000 0000 NOP 1800122e0e0: 0000: c0162b00 00000000 00000015 00072003 00001000 c2000000 00021005 00001000 1810122e100: 0020: c4000000 00001006 00002000 00000000 19481000 00262688 00000020 13480000 1820122e120: 0040: 40262688 00001020 000f803e 00000000 c2010100 000f8000 00000000 c2000000 183t3 opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords) 184 fragment shader, start=0000, size=000c 185 1002 0003 1000 EXEC ADDR(0x2) CNT(0x1) 186 02: 90000001 1ffff688 00000002 (S)FETCH: SAMPLE R0.xyzw = R0.xyz CONST(0) LOCATION(CENTER) 187 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0) 188 1003 0002 2000 EXEC_END ADDR(0x3) CNT(0x1) 189 03: 000f8000 00000000 c2000000 (S)ALU: MAXv export0 = R0, R0 ; gl_FragColor 190 0000 0000 0000 NOP 1910122e140: 0000: c00d2b00 00000001 0000000c 00031002 00001000 c4000000 00021003 00002000 1920122e160: 0020: 00000000 90000001 1ffff688 00000002 000f8000 00000000 c2000000 193t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 194 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 } 1950122e17c: 0000: c0012d00 00040181 00000106 196t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 197 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 } 1980122e188: 0000: c0012d00 00040180 10030002 199t3 opcode: CP_SET_CONSTANT (2d) (6 dwords) 2000122e19c: 0.000000 0.000000 0.000000 0.000000 2010122e194: 0000: c0042d00 00000080 00000000 00000000 00000000 00000000 202t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 203 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 } 2040122e1ac: 0000: c0012d00 00040202 00000c20 205t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 206 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO } 2070122e1b8: 0000: c0012d00 00040201 00000000 208t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 209 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 2100122e1c4: 0000: c0012d00 00040104 0000000f 211t3 opcode: CP_SET_CONSTANT (2d) (6 dwords) 212 RB_BLEND_RED: 0 213 RB_BLEND_GREEN: 0 214 RB_BLEND_BLUE: 0 215 RB_BLEND_ALPHA: 0 2160122e1d0: 0000: c0042d00 00040105 00000000 00000000 00000000 00000000 217t3 opcode: CP_SET_CONSTANT (2d) (8 dwords) 218 set texture const 0000 219 clamp x/y/z: clamp-last-texel/clamp-last-texel/clamp-last-texel 220 filter min/mag: point/point 221 swizzle: xyzw 222 addr=0111d000 (flags=820), size=64x128, pitch=64, format=FMT_1_REVERSE 223 mipaddr=00000000 (flags=200) 2240122e1e8: 0000: c0062d00 00010000 00824800 0111d820 000fe03f 00000d11 00000000 00000200 225t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 226 VGT_INDX_OFFSET: 0 2270122e208: 0000: c0012d00 00040102 00000000 228t0 write TC_CNTL_STATUS (0e00) 229 TC_CNTL_STATUS: { L2_INVALIDATE } 2300122e214: 0000: 00000e00 00000001 231t3 opcode: CP_WAIT_REG_EQ (52) (5 dwords) 2320122e21c: 0000: c0035200 000005d0 00000000 00001000 00000001 233t3 opcode: CP_DRAW_INDX_BIN (34) (7 dwords) 2340122e230: 0000: c0053400 00000000 0003c004 00000000 00000003 01009040 00000006 235t0 write CP_SCRATCH_REG7 (057f) 236 CP_SCRATCH_REG7: 5 237 :0,0,9,5 2380122e24c: 0000: 0000057f 00000005 239t3 opcode: CP_NOP (10) (2 dwords) 2400122e254: 0000: c0001000 00000000 241t3 opcode: CP_DRAW_INDX (22) (3 dwords) 242 { VIZ_QUERY = 0 } 243 { PRIM_TYPE = DI_PT_TRIFAN | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | NUM_INSTANCES = 0 | 0x40000 } 244 draw: 0 245 prim_type: DI_PT_TRIFAN (5) 246 source_select: DI_SRC_SEL_AUTO_INDEX (2) 247 num_indices: 1407 248 draw[0] register values 249!+ ffffffff RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE } 250!+ 00000fff RBBM_PM_OVERRIDE2: 0xfff 251 + 00000000 CP_PERFMON_CNTL: 0 252!+ 00000009 CP_SCRATCH_REG6: 9 253 :0,0,9,5 254!+ 00000005 CP_SCRATCH_REG7: 5 255 :0,0,9,5 256!+ 00000180 SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 } 257!+ 00000001 TC_CNTL_STATUS: { L2_INVALIDATE } 258!+ 00000002 TP0_CHICKEN: 0x2 259!+ 1c004046 RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 } 260!+ 00000040 RB_SURFACE_INFO: { SURFACE_PITCH = 64 | MSAA_SAMPLES = 0 } 261!+ 0110d009 RB_COLOR_INFO: { FORMAT = COLORX_16_16_16_16_FLOAT | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 0 | BASE = 0x110d000 } 262!+ 80000000 PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 } 263!+ 00800040 PA_SC_SCREEN_SCISSOR_BR: { X = 64 | Y = 128 } 264 + 00000000 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 } 265 + 00000000 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 266!+ 00800040 PA_SC_WINDOW_SCISSOR_BR: { X = 64 | Y = 128 } 267!+ ffffffff VGT_MAX_VTX_INDX: 0xffffffff 268 + 00000000 VGT_MIN_VTX_INDX: 0 269 + 00000000 VGT_INDX_OFFSET: 0 270!+ 0000000f RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 271 + 00000000 RB_BLEND_RED: 0 272 + 00000000 RB_BLEND_GREEN: 0 273 + 00000000 RB_BLEND_BLUE: 0 274 + 00000000 RB_BLEND_ALPHA: 0 275 + 00000000 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 276 + 00000000 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 277 + 00000000 RB_ALPHA_REF: 0 278!+ 42000000 PA_CL_VPORT_XSCALE: 32.000000 279!+ 42000000 PA_CL_VPORT_XOFFSET: 32.000000 280!+ 42800000 PA_CL_VPORT_YSCALE: 64.000000 281!+ 42800000 PA_CL_VPORT_YOFFSET: 64.000000 282 + 00000000 PA_CL_VPORT_ZSCALE: 0.000000 283 + 00000000 PA_CL_VPORT_ZOFFSET: 0.000000 284!+ 10030002 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 } 285!+ 00000106 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 } 286!+ ffffffff SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 } 287 + 00000000 SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 } 288 + 00000000 SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 } 289 + 00000000 RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP } 290 + 00000000 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO } 291!+ 00000c20 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 } 292 + 00000000 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL } 293!+ 00090244 PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST } 294!+ 0000043f PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT } 295!+ 00000004 RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH } 296!+ 88888888 RB_SAMPLE_POS: 0x88888888 297 + 00000000 PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 } 298 + 00000000 PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 } 299 + 00000000 PA_SU_LINE_CNTL: { WIDTH = 0.000000 } 300 + 00000000 PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER } 301!+ 00000020 PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 } 302 + 00000000 PA_SC_LINE_CNTL: { BRES_CNTL = 0 } 303 + 00000000 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 } 304!+ 00000001 PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH } 305!+ 3f800000 PA_CL_GB_VERT_CLIP_ADJ: 1.000000 306!+ 3f800000 PA_CL_GB_VERT_DISC_ADJ: 1.000000 307!+ 3f800000 PA_CL_GB_HORZ_CLIP_ADJ: 1.000000 308!+ 3f800000 PA_CL_GB_HORZ_DISC_ADJ: 1.000000 309!+ 00100020 SQ_VS_CONST: { BASE = 32 | SIZE = 256 } 310!+ 000e0120 SQ_PS_CONST: { BASE = 288 | SIZE = 224 } 311!+ 0000ffff PA_SC_AA_MASK: 0xffff 312!+ 00000002 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 } 313!+ 00000002 VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 } 314!+ 0003c000 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 315!+ ffffffff RB_COLOR_DEST_MASK: 0xffffffff 3160122e25c: 0000: c0012200 00000000 00040085 317t0 write CP_SCRATCH_REG7 (057f) 318NEEDS WFI: CP_SCRATCH_REG7 (57f) 319 CP_SCRATCH_REG7: 6 320 :0,0,9,6 3210122e268: 0000: 0000057f 00000006 322t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 3230122e270: 0000: c0002600 00000000 324t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 325 { EVENT = CACHE_FLUSH } 326 event CACHE_FLUSH 3270122e278: 0000: c0004600 00000006 328t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 329 { EVENT = CACHE_FLUSH } 330 event CACHE_FLUSH 3310122e280: 0000: c0004600 00000006 332t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 333 { EVENT = CACHE_FLUSH } 334 event CACHE_FLUSH 3350122e288: 0000: c0004600 00000006 336t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 337 { EVENT = CACHE_FLUSH } 338 event CACHE_FLUSH 3390122e290: 0000: c0004600 00000006 340t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 341 { EVENT = CACHE_FLUSH } 342 event CACHE_FLUSH 3430122e298: 0000: c0004600 00000006 344t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 345 { EVENT = CACHE_FLUSH } 346 event CACHE_FLUSH 3470122e2a0: 0000: c0004600 00000006 348t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 349 { EVENT = CACHE_FLUSH } 350 event CACHE_FLUSH 3510122e2a8: 0000: c0004600 00000006 352t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 353 { EVENT = CACHE_FLUSH } 354 event CACHE_FLUSH 3550122e2b0: 0000: c0004600 00000006 356t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 357 { EVENT = CACHE_FLUSH } 358 event CACHE_FLUSH 3590122e2b8: 0000: c0004600 00000006 360t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 361 { EVENT = CACHE_FLUSH } 362 event CACHE_FLUSH 3630122e2c0: 0000: c0004600 00000006 364t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 365 { EVENT = CACHE_FLUSH } 366 event CACHE_FLUSH 3670122e2c8: 0000: c0004600 00000006 368t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 369 { EVENT = CACHE_FLUSH } 370 event CACHE_FLUSH 3710122e2d0: 0000: c0004600 00000006 3720122d1d8: 0000: c0013700 0122e000 000000b6 373t2 nop 374############################################################ 375vertices: 0 376cmd: deqp-gles2/185: fence=1251 377############################################################ 378cmdstream: 124 dwords 379t0 write RB_BC_CONTROL (0f01) 380 RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 } 3810122f000: 0000: 00000f01 1c004046 382t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 383 PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 } 3840122f008: 0000: c0012d00 00040293 00000020 385t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 386 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 } 3870122f014: 0000: c0012d00 00040316 00000002 388t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 389 VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 } 3900122f020: 0000: c0012d00 00040317 00000002 391t0 write CP_PERFMON_CNTL (0444) 392 CP_PERFMON_CNTL: 0 3930122f02c: 0000: 00000444 00000000 394t0 write RBBM_PM_OVERRIDE1 (039c) 395 RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE } 396 RBBM_PM_OVERRIDE2: 0xfff 3970122f034: 0000: 0001039c ffffffff 00000fff 398t0 write TP0_CHICKEN (0e1e) 399 TP0_CHICKEN: 0x2 4000122f040: 0000: 00000e1e 00000002 401t3 opcode: CP_INVALIDATE_STATE (3b) (2 dwords) 4020122f048: 0000: c0003b00 00007fff 403t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 404 SQ_VS_CONST: { BASE = 32 | SIZE = 256 } 4050122f050: 0000: c0012d00 00040307 00100020 406t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 407 SQ_PS_CONST: { BASE = 288 | SIZE = 224 } 4080122f05c: 0000: c0012d00 00040308 000e0120 409t3 opcode: CP_SET_CONSTANT (2d) (4 dwords) 410 VGT_MAX_VTX_INDX: 0xffffffff 411 VGT_MIN_VTX_INDX: 0 4120122f068: 0000: c0022d00 00040100 ffffffff 00000000 413t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 414 VGT_INDX_OFFSET: 0 4150122f078: 0000: c0012d00 00040102 00000000 416t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 417 SQ_CONTEXT_MISC: { SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 } 4180122f084: 0000: c0012d00 00040181 00000004 419t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 420 SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 } 4210122f090: 0000: c0012d00 00040182 ffffffff 422t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 423 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 } 4240122f09c: 0000: c0012d00 00040301 00000000 425t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 426 PA_SC_LINE_CNTL: { BRES_CNTL = 0 } 4270122f0a8: 0000: c0012d00 00040300 00000000 428t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 429 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 } 4300122f0b4: 0000: c0012d00 00040080 00000000 431t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 432 RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH } 4330122f0c0: 0000: c0012d00 00040208 00000004 434t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 435 RB_SAMPLE_POS: 0x88888888 4360122f0cc: 0000: c0012d00 0004020a 88888888 437t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 438 RB_COLOR_DEST_MASK: 0xffffffff 4390122f0d8: 0000: c0012d00 00040326 ffffffff 440t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 441 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 4420122f0e4: 0000: c0012d00 0004031b 0003c000 443t3 opcode: CP_SET_CONSTANT (2d) (4 dwords) 444 SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 } 445 SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 } 4460122f0f0: 0000: c0022d00 00040183 00000000 00000000 447t3 opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords) 4480122f100: 0000: c0004b00 00000000 449t3 opcode: CP_WAIT_REG_EQ (52) (5 dwords) 4500122f108: 0000: c0035200 000005d0 00000000 5f601000 00000001 451t0 write SQ_INST_STORE_MANAGMENT (0d02) 452 SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 } 4530122f11c: 0000: 00000d02 00000180 454t3 opcode: CP_INVALIDATE_STATE (3b) (2 dwords) 4550122f124: 0000: c0003b00 00000300 456t3 opcode: CP_SET_SHADER_BASES (4a) (2 dwords) 4570122f12c: 0000: c0004a00 80000180 458t3 opcode: CP_SET_CONSTANT (2d) (14 dwords) 4590122f13c: 0.000000 0.000000 0.000000 0.000000 20000.000000 1.000000 0.500000 0.000000 4600122f15c: 2.000000 0.750000 0.375000 0.250000 4610122f134: 0000: c00c2d00 00000000 00000000 00000000 00000000 00000000 469c4000 3f800000 4620122f154: 0020: 3f000000 00000000 40000000 3f400000 3ec00000 3e800000 463t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 464 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 4650122f16c: 0000: c0012d00 00040104 0000000f 466t3 opcode: CP_SET_CONSTANT (2d) (6 dwords) 467 RB_BLEND_RED: 0 468 RB_BLEND_GREEN: 0 469 RB_BLEND_BLUE: 0 470 RB_BLEND_ALPHA: 0xff 4710122f178: 0000: c0042d00 00040105 00000000 00000000 00000000 000000ff 472t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 473 PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT } 4740122f190: 0000: c0012d00 00040206 0000043f 475t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 476 RB_SURFACE_INFO: { SURFACE_PITCH = 32 | MSAA_SAMPLES = 0 } 4770122f19c: 0000: c0012d00 00040000 00000020 478t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 479 RB_COLOR_INFO: { FORMAT = COLORX_16_16_16_16_FLOAT | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 0 | BASE = 0x1240000 } 4800122f1a8: 0000: c0012d00 00040001 01240009 481t3 opcode: CP_SET_CONSTANT (2d) (4 dwords) 482 PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 } 483 PA_SC_SCREEN_SCISSOR_BR: { X = 32 | Y = 64 } 4840122f1b4: 0000: c0022d00 0004000e 80000000 00400020 485t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 486 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 } 4870122f1c4: 0000: c0012d00 00040080 00000000 488t0 write CP_SCRATCH_REG6 (057e) 489 CP_SCRATCH_REG6: 15 490 :0,0,15,6 4910122f1d0: 0000: 0000057e 0000000f 492t3 opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords) 493 ibaddr:0122e000 494 ibsize:000000b6 495t3 opcode: CP_SET_CONSTANT (2d) (6 dwords) 496 set shader const 0078 4970122e000: 0000: c0042d00 00010078 0112d083 00100000 0112d083 00100000 498t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 499 PA_SC_AA_MASK: 0xffff 5000122e018: 0000: c0012d00 00040312 0000ffff 501t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 502 RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP } 5030122e024: 0000: c0012d00 00040200 00000000 504t3 opcode: CP_SET_CONSTANT (2d) (5 dwords) 505 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 506 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 507 RB_ALPHA_REF: 0 5080122e030: 0000: c0032d00 0004010c 00000000 00000000 00000000 509t3 opcode: CP_SET_CONSTANT (2d) (4 dwords) 510 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL } 511 PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST } 5120122e044: 0000: c0022d00 00040204 00000000 00090244 513t3 opcode: CP_SET_CONSTANT (2d) (6 dwords) 514 PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 } 515 PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 } 516 PA_SU_LINE_CNTL: { WIDTH = 0.000000 } 517 PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER } 5180122e054: 0000: c0042d00 00040280 00000000 00000000 00000000 00000000 519t3 opcode: CP_SET_CONSTANT (2d) (7 dwords) 520 PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH } 521 PA_CL_GB_VERT_CLIP_ADJ: 1.000000 522 PA_CL_GB_VERT_DISC_ADJ: 1.000000 523 PA_CL_GB_HORZ_CLIP_ADJ: 1.000000 524 PA_CL_GB_HORZ_DISC_ADJ: 1.000000 5250122e06c: 0000: c0052d00 00040302 00000001 3f800000 3f800000 3f800000 3f800000 526t3 opcode: CP_SET_CONSTANT (2d) (4 dwords) 527 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 528 PA_SC_WINDOW_SCISSOR_BR: { X = 32 | Y = 64 } 5290122e088: 0000: c0022d00 00040081 00000000 00400020 530t3 opcode: CP_SET_CONSTANT (2d) (8 dwords) 531 PA_CL_VPORT_XSCALE: 16.000000 532 PA_CL_VPORT_XOFFSET: 16.000000 533 PA_CL_VPORT_YSCALE: 32.000000 534 PA_CL_VPORT_YOFFSET: 32.000000 535 PA_CL_VPORT_ZSCALE: 0.000000 536 PA_CL_VPORT_ZOFFSET: 0.000000 5370122e098: 0000: c0062d00 0004010f 41800000 41800000 42000000 42000000 00000000 00000000 538t3 opcode: CP_SET_CONSTANT (2d) (10 dwords) 5390122e0c0: 16.000000 32.000000 0.000000 0.000000 16.000000 32.000000 0.000000 0.000000 5400122e0b8: 0000: c0082d00 00000184 41800000 42000000 00000000 00000000 41800000 42000000 541* 542t3 opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords) 543 vertex shader, start=0000, size=0015 544 2003 0007 1000 EXEC ADDR(0x3) CNT(0x2) 545 03: 19481000 00262688 00000020 (S)FETCH: VERTEX R1.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) CONST(20, 0) 546 04: 13480000 40262688 00001020 FETCH: VERTEX R0.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) OFFSET(16) CONST(20, 1) 547 0000 0000 c200 ALLOC POSITION SIZE(0x0) 548 1005 0002 1000 EXEC ADDR(0x5) CNT(0x1) 549 05: 000f803e 00000000 c2010100 (S)ALU: MAXv export62 = R1, R1 ; gl_Position 550 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0) 551 1006 0000 2000 EXEC_END ADDR(0x6) CNT(0x1) 552 06: 000f8000 00000000 c2000000 ALU: MAXv export0 = R0, R0 553 0000 0000 0000 NOP 5540122e0e0: 0000: c0162b00 00000000 00000015 00072003 00001000 c2000000 00021005 00001000 5550122e100: 0020: c4000000 00001006 00002000 00000000 19481000 00262688 00000020 13480000 5560122e120: 0040: 40262688 00001020 000f803e 00000000 c2010100 000f8000 00000000 c2000000 557t3 opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords) 558 fragment shader, start=0000, size=000c 559 1002 0003 1000 EXEC ADDR(0x2) CNT(0x1) 560 02: 90000001 1ffff688 00000002 (S)FETCH: SAMPLE R0.xyzw = R0.xyz CONST(0) LOCATION(CENTER) 561 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0) 562 1003 0002 2000 EXEC_END ADDR(0x3) CNT(0x1) 563 03: 000f8000 00000000 c2000000 (S)ALU: MAXv export0 = R0, R0 ; gl_FragColor 564 0000 0000 0000 NOP 5650122e140: 0000: c00d2b00 00000001 0000000c 00031002 00001000 c4000000 00021003 00002000 5660122e160: 0020: 00000000 90000001 1ffff688 00000002 000f8000 00000000 c2000000 567t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 568 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 } 5690122e17c: 0000: c0012d00 00040181 00000106 570t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 571 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 } 5720122e188: 0000: c0012d00 00040180 10030002 573t3 opcode: CP_SET_CONSTANT (2d) (6 dwords) 5740122e19c: 0.000000 0.000000 0.000000 0.000000 5750122e194: 0000: c0042d00 00000080 00000000 00000000 00000000 00000000 576t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 577 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 } 5780122e1ac: 0000: c0012d00 00040202 00000c20 579t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 580 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO } 5810122e1b8: 0000: c0012d00 00040201 00000000 582t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 583 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 5840122e1c4: 0000: c0012d00 00040104 0000000f 585t3 opcode: CP_SET_CONSTANT (2d) (6 dwords) 586 RB_BLEND_RED: 0 587 RB_BLEND_GREEN: 0 588 RB_BLEND_BLUE: 0 589 RB_BLEND_ALPHA: 0 5900122e1d0: 0000: c0042d00 00040105 00000000 00000000 00000000 00000000 591t3 opcode: CP_SET_CONSTANT (2d) (8 dwords) 592 set texture const 0000 593 clamp x/y/z: clamp-last-texel/clamp-last-texel/clamp-last-texel 594 filter min/mag: point/point 595 swizzle: xyzw 596 addr=01250000 (flags=820), size=32x64, pitch=32, format=FMT_1_REVERSE 597 mipaddr=00000000 (flags=200) 5980122e1e8: 0000: c0062d00 00010000 00424800 01250820 0007e01f 00000d11 00000000 00000200 599t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 600 VGT_INDX_OFFSET: 0 6010122e208: 0000: c0012d00 00040102 00000000 602t0 write TC_CNTL_STATUS (0e00) 603 TC_CNTL_STATUS: { L2_INVALIDATE } 6040122e214: 0000: 00000e00 00000001 605t3 opcode: CP_WAIT_REG_EQ (52) (5 dwords) 6060122e21c: 0000: c0035200 000005d0 00000000 00001000 00000001 607t3 opcode: CP_DRAW_INDX_BIN (34) (7 dwords) 6080122e230: 0000: c0053400 00000000 0003c004 00000000 00000003 01009040 00000006 609t0 write CP_SCRATCH_REG7 (057f) 610 CP_SCRATCH_REG7: 11 611 :0,0,15,11 6120122e24c: 0000: 0000057f 0000000b 613t3 opcode: CP_NOP (10) (2 dwords) 6140122e254: 0000: c0001000 00000000 615t3 opcode: CP_DRAW_INDX (22) (3 dwords) 616 { VIZ_QUERY = 0 } 617 { PRIM_TYPE = DI_PT_TRIFAN | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | NUM_INSTANCES = 0 | 0x40000 } 618 draw: 0 619 prim_type: DI_PT_TRIFAN (5) 620 source_select: DI_SRC_SEL_AUTO_INDEX (2) 621 num_indices: 1407 622 draw[1] register values 623 + ffffffff RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE } 624 + 00000fff RBBM_PM_OVERRIDE2: 0xfff 625 + 00000000 CP_PERFMON_CNTL: 0 626!+ 0000000f CP_SCRATCH_REG6: 15 627 :0,0,15,11 628!+ 0000000b CP_SCRATCH_REG7: 11 629 :0,0,15,11 630 + 00000180 SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 } 631 + 00000001 TC_CNTL_STATUS: { L2_INVALIDATE } 632 + 00000002 TP0_CHICKEN: 0x2 633 + 1c004046 RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 } 634!+ 00000020 RB_SURFACE_INFO: { SURFACE_PITCH = 32 | MSAA_SAMPLES = 0 } 635!+ 01240009 RB_COLOR_INFO: { FORMAT = COLORX_16_16_16_16_FLOAT | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 0 | BASE = 0x1240000 } 636 + 80000000 PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 } 637!+ 00400020 PA_SC_SCREEN_SCISSOR_BR: { X = 32 | Y = 64 } 638 + 00000000 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 } 639 + 00000000 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 640!+ 00400020 PA_SC_WINDOW_SCISSOR_BR: { X = 32 | Y = 64 } 641 + ffffffff VGT_MAX_VTX_INDX: 0xffffffff 642 + 00000000 VGT_MIN_VTX_INDX: 0 643 + 00000000 VGT_INDX_OFFSET: 0 644 + 0000000f RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 645 + 00000000 RB_BLEND_RED: 0 646 + 00000000 RB_BLEND_GREEN: 0 647 + 00000000 RB_BLEND_BLUE: 0 648 + 00000000 RB_BLEND_ALPHA: 0 649 + 00000000 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 650 + 00000000 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 651 + 00000000 RB_ALPHA_REF: 0 652!+ 41800000 PA_CL_VPORT_XSCALE: 16.000000 653!+ 41800000 PA_CL_VPORT_XOFFSET: 16.000000 654!+ 42000000 PA_CL_VPORT_YSCALE: 32.000000 655!+ 42000000 PA_CL_VPORT_YOFFSET: 32.000000 656 + 00000000 PA_CL_VPORT_ZSCALE: 0.000000 657 + 00000000 PA_CL_VPORT_ZOFFSET: 0.000000 658 + 10030002 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 } 659 + 00000106 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 } 660 + ffffffff SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 } 661 + 00000000 SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 } 662 + 00000000 SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 } 663 + 00000000 RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP } 664 + 00000000 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO } 665 + 00000c20 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 } 666 + 00000000 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL } 667 + 00090244 PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST } 668 + 0000043f PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT } 669 + 00000004 RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH } 670 + 88888888 RB_SAMPLE_POS: 0x88888888 671 + 00000000 PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 } 672 + 00000000 PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 } 673 + 00000000 PA_SU_LINE_CNTL: { WIDTH = 0.000000 } 674 + 00000000 PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER } 675 + 00000020 PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 } 676 + 00000000 PA_SC_LINE_CNTL: { BRES_CNTL = 0 } 677 + 00000000 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 } 678 + 00000001 PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH } 679 + 3f800000 PA_CL_GB_VERT_CLIP_ADJ: 1.000000 680 + 3f800000 PA_CL_GB_VERT_DISC_ADJ: 1.000000 681 + 3f800000 PA_CL_GB_HORZ_CLIP_ADJ: 1.000000 682 + 3f800000 PA_CL_GB_HORZ_DISC_ADJ: 1.000000 683 + 00100020 SQ_VS_CONST: { BASE = 32 | SIZE = 256 } 684 + 000e0120 SQ_PS_CONST: { BASE = 288 | SIZE = 224 } 685 + 0000ffff PA_SC_AA_MASK: 0xffff 686 + 00000002 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 } 687 + 00000002 VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 } 688 + 0003c000 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 689 + ffffffff RB_COLOR_DEST_MASK: 0xffffffff 6900122e25c: 0000: c0012200 00000000 00040085 691t0 write CP_SCRATCH_REG7 (057f) 692NEEDS WFI: CP_SCRATCH_REG7 (57f) 693 CP_SCRATCH_REG7: 12 694 :0,0,15,12 6950122e268: 0000: 0000057f 0000000c 696t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 6970122e270: 0000: c0002600 00000000 698t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 699 { EVENT = CACHE_FLUSH } 700 event CACHE_FLUSH 7010122e278: 0000: c0004600 00000006 702t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 703 { EVENT = CACHE_FLUSH } 704 event CACHE_FLUSH 7050122e280: 0000: c0004600 00000006 706t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 707 { EVENT = CACHE_FLUSH } 708 event CACHE_FLUSH 7090122e288: 0000: c0004600 00000006 710t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 711 { EVENT = CACHE_FLUSH } 712 event CACHE_FLUSH 7130122e290: 0000: c0004600 00000006 714t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 715 { EVENT = CACHE_FLUSH } 716 event CACHE_FLUSH 7170122e298: 0000: c0004600 00000006 718t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 719 { EVENT = CACHE_FLUSH } 720 event CACHE_FLUSH 7210122e2a0: 0000: c0004600 00000006 722t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 723 { EVENT = CACHE_FLUSH } 724 event CACHE_FLUSH 7250122e2a8: 0000: c0004600 00000006 726t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 727 { EVENT = CACHE_FLUSH } 728 event CACHE_FLUSH 7290122e2b0: 0000: c0004600 00000006 730t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 731 { EVENT = CACHE_FLUSH } 732 event CACHE_FLUSH 7330122e2b8: 0000: c0004600 00000006 734t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 735 { EVENT = CACHE_FLUSH } 736 event CACHE_FLUSH 7370122e2c0: 0000: c0004600 00000006 738t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 739 { EVENT = CACHE_FLUSH } 740 event CACHE_FLUSH 7410122e2c8: 0000: c0004600 00000006 742t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 743 { EVENT = CACHE_FLUSH } 744 event CACHE_FLUSH 7450122e2d0: 0000: c0004600 00000006 7460122f1d8: 0000: c0013700 0122e000 000000b6 747t2 nop 748############################################################ 749vertices: 0 750cmd: deqp-gles2/185: fence=1252 751############################################################ 752cmdstream: 124 dwords 753t0 write RB_BC_CONTROL (0f01) 754 RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 } 7550122d000: 0000: 00000f01 1c004046 756t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 757 PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 } 7580122d008: 0000: c0012d00 00040293 00000020 759t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 760 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 } 7610122d014: 0000: c0012d00 00040316 00000002 762t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 763 VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 } 7640122d020: 0000: c0012d00 00040317 00000002 765t0 write CP_PERFMON_CNTL (0444) 766 CP_PERFMON_CNTL: 0 7670122d02c: 0000: 00000444 00000000 768t0 write RBBM_PM_OVERRIDE1 (039c) 769 RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE } 770 RBBM_PM_OVERRIDE2: 0xfff 7710122d034: 0000: 0001039c ffffffff 00000fff 772t0 write TP0_CHICKEN (0e1e) 773 TP0_CHICKEN: 0x2 7740122d040: 0000: 00000e1e 00000002 775t3 opcode: CP_INVALIDATE_STATE (3b) (2 dwords) 7760122d048: 0000: c0003b00 00007fff 777t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 778 SQ_VS_CONST: { BASE = 32 | SIZE = 256 } 7790122d050: 0000: c0012d00 00040307 00100020 780t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 781 SQ_PS_CONST: { BASE = 288 | SIZE = 224 } 7820122d05c: 0000: c0012d00 00040308 000e0120 783t3 opcode: CP_SET_CONSTANT (2d) (4 dwords) 784 VGT_MAX_VTX_INDX: 0xffffffff 785 VGT_MIN_VTX_INDX: 0 7860122d068: 0000: c0022d00 00040100 ffffffff 00000000 787t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 788 VGT_INDX_OFFSET: 0 7890122d078: 0000: c0012d00 00040102 00000000 790t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 791 SQ_CONTEXT_MISC: { SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 } 7920122d084: 0000: c0012d00 00040181 00000004 793t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 794 SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 } 7950122d090: 0000: c0012d00 00040182 ffffffff 796t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 797 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 } 7980122d09c: 0000: c0012d00 00040301 00000000 799t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 800 PA_SC_LINE_CNTL: { BRES_CNTL = 0 } 8010122d0a8: 0000: c0012d00 00040300 00000000 802t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 803 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 } 8040122d0b4: 0000: c0012d00 00040080 00000000 805t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 806 RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH } 8070122d0c0: 0000: c0012d00 00040208 00000004 808t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 809 RB_SAMPLE_POS: 0x88888888 8100122d0cc: 0000: c0012d00 0004020a 88888888 811t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 812 RB_COLOR_DEST_MASK: 0xffffffff 8130122d0d8: 0000: c0012d00 00040326 ffffffff 814t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 815 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 8160122d0e4: 0000: c0012d00 0004031b 0003c000 817t3 opcode: CP_SET_CONSTANT (2d) (4 dwords) 818 SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 } 819 SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 } 8200122d0f0: 0000: c0022d00 00040183 00000000 00000000 821t3 opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords) 8220122d100: 0000: c0004b00 00000000 823t3 opcode: CP_WAIT_REG_EQ (52) (5 dwords) 8240122d108: 0000: c0035200 000005d0 00000000 5f601000 00000001 825t0 write SQ_INST_STORE_MANAGMENT (0d02) 826 SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 } 8270122d11c: 0000: 00000d02 00000180 828t3 opcode: CP_INVALIDATE_STATE (3b) (2 dwords) 8290122d124: 0000: c0003b00 00000300 830t3 opcode: CP_SET_SHADER_BASES (4a) (2 dwords) 8310122d12c: 0000: c0004a00 80000180 832t3 opcode: CP_SET_CONSTANT (2d) (14 dwords) 8330122d13c: 0.000000 0.000000 0.000000 0.000000 20000.000000 1.000000 0.500000 0.000000 8340122d15c: 2.000000 0.750000 0.375000 0.250000 8350122d134: 0000: c00c2d00 00000000 00000000 00000000 00000000 00000000 469c4000 3f800000 8360122d154: 0020: 3f000000 00000000 40000000 3f400000 3ec00000 3e800000 837t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 838 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 8390122d16c: 0000: c0012d00 00040104 0000000f 840t3 opcode: CP_SET_CONSTANT (2d) (6 dwords) 841 RB_BLEND_RED: 0 842 RB_BLEND_GREEN: 0 843 RB_BLEND_BLUE: 0 844 RB_BLEND_ALPHA: 0xff 8450122d178: 0000: c0042d00 00040105 00000000 00000000 00000000 000000ff 846t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 847 PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT } 8480122d190: 0000: c0012d00 00040206 0000043f 849t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 850 RB_SURFACE_INFO: { SURFACE_PITCH = 32 | MSAA_SAMPLES = 0 } 8510122d19c: 0000: c0012d00 00040000 00000020 852t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 853 RB_COLOR_INFO: { FORMAT = COLORX_16_16_16_16_FLOAT | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 0 | BASE = 0x1244000 } 8540122d1a8: 0000: c0012d00 00040001 01244009 855t3 opcode: CP_SET_CONSTANT (2d) (4 dwords) 856 PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 } 857 PA_SC_SCREEN_SCISSOR_BR: { X = 16 | Y = 32 } 8580122d1b4: 0000: c0022d00 0004000e 80000000 00200010 859t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 860 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 } 8610122d1c4: 0000: c0012d00 00040080 00000000 862t0 write CP_SCRATCH_REG6 (057e) 863 CP_SCRATCH_REG6: 21 864 :0,0,21,12 8650122d1d0: 0000: 0000057e 00000015 866t3 opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords) 867 ibaddr:0122e000 868 ibsize:000000b6 869t3 opcode: CP_SET_CONSTANT (2d) (6 dwords) 870 set shader const 0078 8710122e000: 0000: c0042d00 00010078 0112d103 00100000 0112d103 00100000 872t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 873 PA_SC_AA_MASK: 0xffff 8740122e018: 0000: c0012d00 00040312 0000ffff 875t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 876 RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP } 8770122e024: 0000: c0012d00 00040200 00000000 878t3 opcode: CP_SET_CONSTANT (2d) (5 dwords) 879 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 880 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 881 RB_ALPHA_REF: 0 8820122e030: 0000: c0032d00 0004010c 00000000 00000000 00000000 883t3 opcode: CP_SET_CONSTANT (2d) (4 dwords) 884 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL } 885 PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST } 8860122e044: 0000: c0022d00 00040204 00000000 00090244 887t3 opcode: CP_SET_CONSTANT (2d) (6 dwords) 888 PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 } 889 PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 } 890 PA_SU_LINE_CNTL: { WIDTH = 0.000000 } 891 PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER } 8920122e054: 0000: c0042d00 00040280 00000000 00000000 00000000 00000000 893t3 opcode: CP_SET_CONSTANT (2d) (7 dwords) 894 PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH } 895 PA_CL_GB_VERT_CLIP_ADJ: 1.000000 896 PA_CL_GB_VERT_DISC_ADJ: 1.000000 897 PA_CL_GB_HORZ_CLIP_ADJ: 1.000000 898 PA_CL_GB_HORZ_DISC_ADJ: 1.000000 8990122e06c: 0000: c0052d00 00040302 00000001 3f800000 3f800000 3f800000 3f800000 900t3 opcode: CP_SET_CONSTANT (2d) (4 dwords) 901 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 902 PA_SC_WINDOW_SCISSOR_BR: { X = 16 | Y = 32 } 9030122e088: 0000: c0022d00 00040081 00000000 00200010 904t3 opcode: CP_SET_CONSTANT (2d) (8 dwords) 905 PA_CL_VPORT_XSCALE: 8.000000 906 PA_CL_VPORT_XOFFSET: 8.000000 907 PA_CL_VPORT_YSCALE: 16.000000 908 PA_CL_VPORT_YOFFSET: 16.000000 909 PA_CL_VPORT_ZSCALE: 0.000000 910 PA_CL_VPORT_ZOFFSET: 0.000000 9110122e098: 0000: c0062d00 0004010f 41000000 41000000 41800000 41800000 00000000 00000000 912t3 opcode: CP_SET_CONSTANT (2d) (10 dwords) 9130122e0c0: 8.000000 16.000000 0.000000 0.000000 8.000000 16.000000 0.000000 0.000000 9140122e0b8: 0000: c0082d00 00000184 41000000 41800000 00000000 00000000 41000000 41800000 915* 916t3 opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords) 917 vertex shader, start=0000, size=0015 918 2003 0007 1000 EXEC ADDR(0x3) CNT(0x2) 919 03: 19481000 00262688 00000020 (S)FETCH: VERTEX R1.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) CONST(20, 0) 920 04: 13480000 40262688 00001020 FETCH: VERTEX R0.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) OFFSET(16) CONST(20, 1) 921 0000 0000 c200 ALLOC POSITION SIZE(0x0) 922 1005 0002 1000 EXEC ADDR(0x5) CNT(0x1) 923 05: 000f803e 00000000 c2010100 (S)ALU: MAXv export62 = R1, R1 ; gl_Position 924 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0) 925 1006 0000 2000 EXEC_END ADDR(0x6) CNT(0x1) 926 06: 000f8000 00000000 c2000000 ALU: MAXv export0 = R0, R0 927 0000 0000 0000 NOP 9280122e0e0: 0000: c0162b00 00000000 00000015 00072003 00001000 c2000000 00021005 00001000 9290122e100: 0020: c4000000 00001006 00002000 00000000 19481000 00262688 00000020 13480000 9300122e120: 0040: 40262688 00001020 000f803e 00000000 c2010100 000f8000 00000000 c2000000 931t3 opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords) 932 fragment shader, start=0000, size=000c 933 1002 0003 1000 EXEC ADDR(0x2) CNT(0x1) 934 02: 90000001 1ffff688 00000002 (S)FETCH: SAMPLE R0.xyzw = R0.xyz CONST(0) LOCATION(CENTER) 935 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0) 936 1003 0002 2000 EXEC_END ADDR(0x3) CNT(0x1) 937 03: 000f8000 00000000 c2000000 (S)ALU: MAXv export0 = R0, R0 ; gl_FragColor 938 0000 0000 0000 NOP 9390122e140: 0000: c00d2b00 00000001 0000000c 00031002 00001000 c4000000 00021003 00002000 9400122e160: 0020: 00000000 90000001 1ffff688 00000002 000f8000 00000000 c2000000 941t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 942 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 } 9430122e17c: 0000: c0012d00 00040181 00000106 944t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 945 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 } 9460122e188: 0000: c0012d00 00040180 10030002 947t3 opcode: CP_SET_CONSTANT (2d) (6 dwords) 9480122e19c: 0.000000 0.000000 0.000000 0.000000 9490122e194: 0000: c0042d00 00000080 00000000 00000000 00000000 00000000 950t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 951 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 } 9520122e1ac: 0000: c0012d00 00040202 00000c20 953t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 954 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO } 9550122e1b8: 0000: c0012d00 00040201 00000000 956t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 957 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 9580122e1c4: 0000: c0012d00 00040104 0000000f 959t3 opcode: CP_SET_CONSTANT (2d) (6 dwords) 960 RB_BLEND_RED: 0 961 RB_BLEND_GREEN: 0 962 RB_BLEND_BLUE: 0 963 RB_BLEND_ALPHA: 0 9640122e1d0: 0000: c0042d00 00040105 00000000 00000000 00000000 00000000 965t3 opcode: CP_SET_CONSTANT (2d) (8 dwords) 966 set texture const 0000 967 clamp x/y/z: clamp-last-texel/clamp-last-texel/clamp-last-texel 968 filter min/mag: point/point 969 swizzle: xyzw 970 addr=01254000 (flags=820), size=16x32, pitch=32, format=FMT_1_REVERSE 971 mipaddr=00000000 (flags=200) 9720122e1e8: 0000: c0062d00 00010000 00424800 01254820 0003e00f 00000d11 00000000 00000200 973t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 974 VGT_INDX_OFFSET: 0 9750122e208: 0000: c0012d00 00040102 00000000 976t0 write TC_CNTL_STATUS (0e00) 977 TC_CNTL_STATUS: { L2_INVALIDATE } 9780122e214: 0000: 00000e00 00000001 979t3 opcode: CP_WAIT_REG_EQ (52) (5 dwords) 9800122e21c: 0000: c0035200 000005d0 00000000 00001000 00000001 981t3 opcode: CP_DRAW_INDX_BIN (34) (7 dwords) 9820122e230: 0000: c0053400 00000000 0003c004 00000000 00000003 01009040 00000006 983t0 write CP_SCRATCH_REG7 (057f) 984 CP_SCRATCH_REG7: 17 985 :0,0,21,17 9860122e24c: 0000: 0000057f 00000011 987t3 opcode: CP_NOP (10) (2 dwords) 9880122e254: 0000: c0001000 00000000 989t3 opcode: CP_DRAW_INDX (22) (3 dwords) 990 { VIZ_QUERY = 0 } 991 { PRIM_TYPE = DI_PT_TRIFAN | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | NUM_INSTANCES = 0 | 0x40000 } 992 draw: 0 993 prim_type: DI_PT_TRIFAN (5) 994 source_select: DI_SRC_SEL_AUTO_INDEX (2) 995 num_indices: 1407 996 draw[2] register values 997 + ffffffff RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE } 998 + 00000fff RBBM_PM_OVERRIDE2: 0xfff 999 + 00000000 CP_PERFMON_CNTL: 0 1000!+ 00000015 CP_SCRATCH_REG6: 21 1001 :0,0,21,17 1002!+ 00000011 CP_SCRATCH_REG7: 17 1003 :0,0,21,17 1004 + 00000180 SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 } 1005 + 00000001 TC_CNTL_STATUS: { L2_INVALIDATE } 1006 + 00000002 TP0_CHICKEN: 0x2 1007 + 1c004046 RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 } 1008 + 00000020 RB_SURFACE_INFO: { SURFACE_PITCH = 32 | MSAA_SAMPLES = 0 } 1009!+ 01244009 RB_COLOR_INFO: { FORMAT = COLORX_16_16_16_16_FLOAT | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 0 | BASE = 0x1244000 } 1010 + 80000000 PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 } 1011!+ 00200010 PA_SC_SCREEN_SCISSOR_BR: { X = 16 | Y = 32 } 1012 + 00000000 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 } 1013 + 00000000 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 1014!+ 00200010 PA_SC_WINDOW_SCISSOR_BR: { X = 16 | Y = 32 } 1015 + ffffffff VGT_MAX_VTX_INDX: 0xffffffff 1016 + 00000000 VGT_MIN_VTX_INDX: 0 1017 + 00000000 VGT_INDX_OFFSET: 0 1018 + 0000000f RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 1019 + 00000000 RB_BLEND_RED: 0 1020 + 00000000 RB_BLEND_GREEN: 0 1021 + 00000000 RB_BLEND_BLUE: 0 1022 + 00000000 RB_BLEND_ALPHA: 0 1023 + 00000000 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 1024 + 00000000 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 1025 + 00000000 RB_ALPHA_REF: 0 1026!+ 41000000 PA_CL_VPORT_XSCALE: 8.000000 1027!+ 41000000 PA_CL_VPORT_XOFFSET: 8.000000 1028!+ 41800000 PA_CL_VPORT_YSCALE: 16.000000 1029!+ 41800000 PA_CL_VPORT_YOFFSET: 16.000000 1030 + 00000000 PA_CL_VPORT_ZSCALE: 0.000000 1031 + 00000000 PA_CL_VPORT_ZOFFSET: 0.000000 1032 + 10030002 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 } 1033 + 00000106 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 } 1034 + ffffffff SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 } 1035 + 00000000 SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 } 1036 + 00000000 SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 } 1037 + 00000000 RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP } 1038 + 00000000 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO } 1039 + 00000c20 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 } 1040 + 00000000 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL } 1041 + 00090244 PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST } 1042 + 0000043f PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT } 1043 + 00000004 RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH } 1044 + 88888888 RB_SAMPLE_POS: 0x88888888 1045 + 00000000 PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 } 1046 + 00000000 PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 } 1047 + 00000000 PA_SU_LINE_CNTL: { WIDTH = 0.000000 } 1048 + 00000000 PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER } 1049 + 00000020 PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 } 1050 + 00000000 PA_SC_LINE_CNTL: { BRES_CNTL = 0 } 1051 + 00000000 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 } 1052 + 00000001 PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH } 1053 + 3f800000 PA_CL_GB_VERT_CLIP_ADJ: 1.000000 1054 + 3f800000 PA_CL_GB_VERT_DISC_ADJ: 1.000000 1055 + 3f800000 PA_CL_GB_HORZ_CLIP_ADJ: 1.000000 1056 + 3f800000 PA_CL_GB_HORZ_DISC_ADJ: 1.000000 1057 + 00100020 SQ_VS_CONST: { BASE = 32 | SIZE = 256 } 1058 + 000e0120 SQ_PS_CONST: { BASE = 288 | SIZE = 224 } 1059 + 0000ffff PA_SC_AA_MASK: 0xffff 1060 + 00000002 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 } 1061 + 00000002 VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 } 1062 + 0003c000 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 1063 + ffffffff RB_COLOR_DEST_MASK: 0xffffffff 10640122e25c: 0000: c0012200 00000000 00040085 1065t0 write CP_SCRATCH_REG7 (057f) 1066NEEDS WFI: CP_SCRATCH_REG7 (57f) 1067 CP_SCRATCH_REG7: 18 1068 :0,0,21,18 10690122e268: 0000: 0000057f 00000012 1070t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 10710122e270: 0000: c0002600 00000000 1072t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 1073 { EVENT = CACHE_FLUSH } 1074 event CACHE_FLUSH 10750122e278: 0000: c0004600 00000006 1076t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 1077 { EVENT = CACHE_FLUSH } 1078 event CACHE_FLUSH 10790122e280: 0000: c0004600 00000006 1080t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 1081 { EVENT = CACHE_FLUSH } 1082 event CACHE_FLUSH 10830122e288: 0000: c0004600 00000006 1084t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 1085 { EVENT = CACHE_FLUSH } 1086 event CACHE_FLUSH 10870122e290: 0000: c0004600 00000006 1088t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 1089 { EVENT = CACHE_FLUSH } 1090 event CACHE_FLUSH 10910122e298: 0000: c0004600 00000006 1092t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 1093 { EVENT = CACHE_FLUSH } 1094 event CACHE_FLUSH 10950122e2a0: 0000: c0004600 00000006 1096t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 1097 { EVENT = CACHE_FLUSH } 1098 event CACHE_FLUSH 10990122e2a8: 0000: c0004600 00000006 1100t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 1101 { EVENT = CACHE_FLUSH } 1102 event CACHE_FLUSH 11030122e2b0: 0000: c0004600 00000006 1104t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 1105 { EVENT = CACHE_FLUSH } 1106 event CACHE_FLUSH 11070122e2b8: 0000: c0004600 00000006 1108t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 1109 { EVENT = CACHE_FLUSH } 1110 event CACHE_FLUSH 11110122e2c0: 0000: c0004600 00000006 1112t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 1113 { EVENT = CACHE_FLUSH } 1114 event CACHE_FLUSH 11150122e2c8: 0000: c0004600 00000006 1116t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 1117 { EVENT = CACHE_FLUSH } 1118 event CACHE_FLUSH 11190122e2d0: 0000: c0004600 00000006 11200122d1d8: 0000: c0013700 0122e000 000000b6 1121t2 nop 1122############################################################ 1123vertices: 0 1124cmd: deqp-gles2/185: fence=1253 1125############################################################ 1126cmdstream: 124 dwords 1127t0 write RB_BC_CONTROL (0f01) 1128 RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 } 11290122f000: 0000: 00000f01 1c004046 1130t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1131 PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 } 11320122f008: 0000: c0012d00 00040293 00000020 1133t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1134 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 } 11350122f014: 0000: c0012d00 00040316 00000002 1136t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1137 VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 } 11380122f020: 0000: c0012d00 00040317 00000002 1139t0 write CP_PERFMON_CNTL (0444) 1140 CP_PERFMON_CNTL: 0 11410122f02c: 0000: 00000444 00000000 1142t0 write RBBM_PM_OVERRIDE1 (039c) 1143 RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE } 1144 RBBM_PM_OVERRIDE2: 0xfff 11450122f034: 0000: 0001039c ffffffff 00000fff 1146t0 write TP0_CHICKEN (0e1e) 1147 TP0_CHICKEN: 0x2 11480122f040: 0000: 00000e1e 00000002 1149t3 opcode: CP_INVALIDATE_STATE (3b) (2 dwords) 11500122f048: 0000: c0003b00 00007fff 1151t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1152 SQ_VS_CONST: { BASE = 32 | SIZE = 256 } 11530122f050: 0000: c0012d00 00040307 00100020 1154t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1155 SQ_PS_CONST: { BASE = 288 | SIZE = 224 } 11560122f05c: 0000: c0012d00 00040308 000e0120 1157t3 opcode: CP_SET_CONSTANT (2d) (4 dwords) 1158 VGT_MAX_VTX_INDX: 0xffffffff 1159 VGT_MIN_VTX_INDX: 0 11600122f068: 0000: c0022d00 00040100 ffffffff 00000000 1161t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1162 VGT_INDX_OFFSET: 0 11630122f078: 0000: c0012d00 00040102 00000000 1164t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1165 SQ_CONTEXT_MISC: { SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 } 11660122f084: 0000: c0012d00 00040181 00000004 1167t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1168 SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 } 11690122f090: 0000: c0012d00 00040182 ffffffff 1170t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1171 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 } 11720122f09c: 0000: c0012d00 00040301 00000000 1173t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1174 PA_SC_LINE_CNTL: { BRES_CNTL = 0 } 11750122f0a8: 0000: c0012d00 00040300 00000000 1176t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1177 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 } 11780122f0b4: 0000: c0012d00 00040080 00000000 1179t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1180 RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH } 11810122f0c0: 0000: c0012d00 00040208 00000004 1182t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1183 RB_SAMPLE_POS: 0x88888888 11840122f0cc: 0000: c0012d00 0004020a 88888888 1185t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1186 RB_COLOR_DEST_MASK: 0xffffffff 11870122f0d8: 0000: c0012d00 00040326 ffffffff 1188t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1189 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 11900122f0e4: 0000: c0012d00 0004031b 0003c000 1191t3 opcode: CP_SET_CONSTANT (2d) (4 dwords) 1192 SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 } 1193 SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 } 11940122f0f0: 0000: c0022d00 00040183 00000000 00000000 1195t3 opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords) 11960122f100: 0000: c0004b00 00000000 1197t3 opcode: CP_WAIT_REG_EQ (52) (5 dwords) 11980122f108: 0000: c0035200 000005d0 00000000 5f601000 00000001 1199t0 write SQ_INST_STORE_MANAGMENT (0d02) 1200 SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 } 12010122f11c: 0000: 00000d02 00000180 1202t3 opcode: CP_INVALIDATE_STATE (3b) (2 dwords) 12030122f124: 0000: c0003b00 00000300 1204t3 opcode: CP_SET_SHADER_BASES (4a) (2 dwords) 12050122f12c: 0000: c0004a00 80000180 1206t3 opcode: CP_SET_CONSTANT (2d) (14 dwords) 12070122f13c: 0.000000 0.000000 0.000000 0.000000 20000.000000 1.000000 0.500000 0.000000 12080122f15c: 2.000000 0.750000 0.375000 0.250000 12090122f134: 0000: c00c2d00 00000000 00000000 00000000 00000000 00000000 469c4000 3f800000 12100122f154: 0020: 3f000000 00000000 40000000 3f400000 3ec00000 3e800000 1211t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1212 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 12130122f16c: 0000: c0012d00 00040104 0000000f 1214t3 opcode: CP_SET_CONSTANT (2d) (6 dwords) 1215 RB_BLEND_RED: 0 1216 RB_BLEND_GREEN: 0 1217 RB_BLEND_BLUE: 0 1218 RB_BLEND_ALPHA: 0xff 12190122f178: 0000: c0042d00 00040105 00000000 00000000 00000000 000000ff 1220t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1221 PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT } 12220122f190: 0000: c0012d00 00040206 0000043f 1223t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1224 RB_SURFACE_INFO: { SURFACE_PITCH = 32 | MSAA_SAMPLES = 0 } 12250122f19c: 0000: c0012d00 00040000 00000020 1226t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1227 RB_COLOR_INFO: { FORMAT = COLORX_16_16_16_16_FLOAT | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 0 | BASE = 0x1246000 } 12280122f1a8: 0000: c0012d00 00040001 01246009 1229t3 opcode: CP_SET_CONSTANT (2d) (4 dwords) 1230 PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 } 1231 PA_SC_SCREEN_SCISSOR_BR: { X = 8 | Y = 16 } 12320122f1b4: 0000: c0022d00 0004000e 80000000 00100008 1233t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1234 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 } 12350122f1c4: 0000: c0012d00 00040080 00000000 1236t0 write CP_SCRATCH_REG6 (057e) 1237 CP_SCRATCH_REG6: 27 1238 :0,0,27,18 12390122f1d0: 0000: 0000057e 0000001b 1240t3 opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords) 1241 ibaddr:0122e000 1242 ibsize:000000b6 1243t3 opcode: CP_SET_CONSTANT (2d) (6 dwords) 1244 set shader const 0078 12450122e000: 0000: c0042d00 00010078 0112d183 00100000 0112d183 00100000 1246t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1247 PA_SC_AA_MASK: 0xffff 12480122e018: 0000: c0012d00 00040312 0000ffff 1249t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1250 RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP } 12510122e024: 0000: c0012d00 00040200 00000000 1252t3 opcode: CP_SET_CONSTANT (2d) (5 dwords) 1253 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 1254 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 1255 RB_ALPHA_REF: 0 12560122e030: 0000: c0032d00 0004010c 00000000 00000000 00000000 1257t3 opcode: CP_SET_CONSTANT (2d) (4 dwords) 1258 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL } 1259 PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST } 12600122e044: 0000: c0022d00 00040204 00000000 00090244 1261t3 opcode: CP_SET_CONSTANT (2d) (6 dwords) 1262 PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 } 1263 PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 } 1264 PA_SU_LINE_CNTL: { WIDTH = 0.000000 } 1265 PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER } 12660122e054: 0000: c0042d00 00040280 00000000 00000000 00000000 00000000 1267t3 opcode: CP_SET_CONSTANT (2d) (7 dwords) 1268 PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH } 1269 PA_CL_GB_VERT_CLIP_ADJ: 1.000000 1270 PA_CL_GB_VERT_DISC_ADJ: 1.000000 1271 PA_CL_GB_HORZ_CLIP_ADJ: 1.000000 1272 PA_CL_GB_HORZ_DISC_ADJ: 1.000000 12730122e06c: 0000: c0052d00 00040302 00000001 3f800000 3f800000 3f800000 3f800000 1274t3 opcode: CP_SET_CONSTANT (2d) (4 dwords) 1275 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 1276 PA_SC_WINDOW_SCISSOR_BR: { X = 8 | Y = 16 } 12770122e088: 0000: c0022d00 00040081 00000000 00100008 1278t3 opcode: CP_SET_CONSTANT (2d) (8 dwords) 1279 PA_CL_VPORT_XSCALE: 4.000000 1280 PA_CL_VPORT_XOFFSET: 4.000000 1281 PA_CL_VPORT_YSCALE: 8.000000 1282 PA_CL_VPORT_YOFFSET: 8.000000 1283 PA_CL_VPORT_ZSCALE: 0.000000 1284 PA_CL_VPORT_ZOFFSET: 0.000000 12850122e098: 0000: c0062d00 0004010f 40800000 40800000 41000000 41000000 00000000 00000000 1286t3 opcode: CP_SET_CONSTANT (2d) (10 dwords) 12870122e0c0: 4.000000 8.000000 0.000000 0.000000 4.000000 8.000000 0.000000 0.000000 12880122e0b8: 0000: c0082d00 00000184 40800000 41000000 00000000 00000000 40800000 41000000 1289* 1290t3 opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords) 1291 vertex shader, start=0000, size=0015 1292 2003 0007 1000 EXEC ADDR(0x3) CNT(0x2) 1293 03: 19481000 00262688 00000020 (S)FETCH: VERTEX R1.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) CONST(20, 0) 1294 04: 13480000 40262688 00001020 FETCH: VERTEX R0.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) OFFSET(16) CONST(20, 1) 1295 0000 0000 c200 ALLOC POSITION SIZE(0x0) 1296 1005 0002 1000 EXEC ADDR(0x5) CNT(0x1) 1297 05: 000f803e 00000000 c2010100 (S)ALU: MAXv export62 = R1, R1 ; gl_Position 1298 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0) 1299 1006 0000 2000 EXEC_END ADDR(0x6) CNT(0x1) 1300 06: 000f8000 00000000 c2000000 ALU: MAXv export0 = R0, R0 1301 0000 0000 0000 NOP 13020122e0e0: 0000: c0162b00 00000000 00000015 00072003 00001000 c2000000 00021005 00001000 13030122e100: 0020: c4000000 00001006 00002000 00000000 19481000 00262688 00000020 13480000 13040122e120: 0040: 40262688 00001020 000f803e 00000000 c2010100 000f8000 00000000 c2000000 1305t3 opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords) 1306 fragment shader, start=0000, size=000c 1307 1002 0003 1000 EXEC ADDR(0x2) CNT(0x1) 1308 02: 90000001 1ffff688 00000002 (S)FETCH: SAMPLE R0.xyzw = R0.xyz CONST(0) LOCATION(CENTER) 1309 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0) 1310 1003 0002 2000 EXEC_END ADDR(0x3) CNT(0x1) 1311 03: 000f8000 00000000 c2000000 (S)ALU: MAXv export0 = R0, R0 ; gl_FragColor 1312 0000 0000 0000 NOP 13130122e140: 0000: c00d2b00 00000001 0000000c 00031002 00001000 c4000000 00021003 00002000 13140122e160: 0020: 00000000 90000001 1ffff688 00000002 000f8000 00000000 c2000000 1315t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1316 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 } 13170122e17c: 0000: c0012d00 00040181 00000106 1318t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1319 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 } 13200122e188: 0000: c0012d00 00040180 10030002 1321t3 opcode: CP_SET_CONSTANT (2d) (6 dwords) 13220122e19c: 0.000000 0.000000 0.000000 0.000000 13230122e194: 0000: c0042d00 00000080 00000000 00000000 00000000 00000000 1324t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1325 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 } 13260122e1ac: 0000: c0012d00 00040202 00000c20 1327t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1328 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO } 13290122e1b8: 0000: c0012d00 00040201 00000000 1330t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1331 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 13320122e1c4: 0000: c0012d00 00040104 0000000f 1333t3 opcode: CP_SET_CONSTANT (2d) (6 dwords) 1334 RB_BLEND_RED: 0 1335 RB_BLEND_GREEN: 0 1336 RB_BLEND_BLUE: 0 1337 RB_BLEND_ALPHA: 0 13380122e1d0: 0000: c0042d00 00040105 00000000 00000000 00000000 00000000 1339t3 opcode: CP_SET_CONSTANT (2d) (8 dwords) 1340 set texture const 0000 1341 clamp x/y/z: clamp-last-texel/clamp-last-texel/clamp-last-texel 1342 filter min/mag: point/point 1343 swizzle: xyzw 1344 addr=01254000 (flags=820), size=8x16, pitch=32, format=FMT_1_REVERSE 1345 mipaddr=00000000 (flags=200) 13460122e1e8: 0000: c0062d00 00010000 00424800 01254820 0001e007 00000d11 00000000 00000200 1347t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1348 VGT_INDX_OFFSET: 0 13490122e208: 0000: c0012d00 00040102 00000000 1350t0 write TC_CNTL_STATUS (0e00) 1351 TC_CNTL_STATUS: { L2_INVALIDATE } 13520122e214: 0000: 00000e00 00000001 1353t3 opcode: CP_WAIT_REG_EQ (52) (5 dwords) 13540122e21c: 0000: c0035200 000005d0 00000000 00001000 00000001 1355t3 opcode: CP_DRAW_INDX_BIN (34) (7 dwords) 13560122e230: 0000: c0053400 00000000 0003c004 00000000 00000003 01009040 00000006 1357t0 write CP_SCRATCH_REG7 (057f) 1358 CP_SCRATCH_REG7: 23 1359 :0,0,27,23 13600122e24c: 0000: 0000057f 00000017 1361t3 opcode: CP_NOP (10) (2 dwords) 13620122e254: 0000: c0001000 00000000 1363t3 opcode: CP_DRAW_INDX (22) (3 dwords) 1364 { VIZ_QUERY = 0 } 1365 { PRIM_TYPE = DI_PT_TRIFAN | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | NUM_INSTANCES = 0 | 0x40000 } 1366 draw: 0 1367 prim_type: DI_PT_TRIFAN (5) 1368 source_select: DI_SRC_SEL_AUTO_INDEX (2) 1369 num_indices: 1407 1370 draw[3] register values 1371 + ffffffff RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE } 1372 + 00000fff RBBM_PM_OVERRIDE2: 0xfff 1373 + 00000000 CP_PERFMON_CNTL: 0 1374!+ 0000001b CP_SCRATCH_REG6: 27 1375 :0,0,27,23 1376!+ 00000017 CP_SCRATCH_REG7: 23 1377 :0,0,27,23 1378 + 00000180 SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 } 1379 + 00000001 TC_CNTL_STATUS: { L2_INVALIDATE } 1380 + 00000002 TP0_CHICKEN: 0x2 1381 + 1c004046 RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 } 1382 + 00000020 RB_SURFACE_INFO: { SURFACE_PITCH = 32 | MSAA_SAMPLES = 0 } 1383!+ 01246009 RB_COLOR_INFO: { FORMAT = COLORX_16_16_16_16_FLOAT | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 0 | BASE = 0x1246000 } 1384 + 80000000 PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 } 1385!+ 00100008 PA_SC_SCREEN_SCISSOR_BR: { X = 8 | Y = 16 } 1386 + 00000000 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 } 1387 + 00000000 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 1388!+ 00100008 PA_SC_WINDOW_SCISSOR_BR: { X = 8 | Y = 16 } 1389 + ffffffff VGT_MAX_VTX_INDX: 0xffffffff 1390 + 00000000 VGT_MIN_VTX_INDX: 0 1391 + 00000000 VGT_INDX_OFFSET: 0 1392 + 0000000f RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 1393 + 00000000 RB_BLEND_RED: 0 1394 + 00000000 RB_BLEND_GREEN: 0 1395 + 00000000 RB_BLEND_BLUE: 0 1396 + 00000000 RB_BLEND_ALPHA: 0 1397 + 00000000 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 1398 + 00000000 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 1399 + 00000000 RB_ALPHA_REF: 0 1400!+ 40800000 PA_CL_VPORT_XSCALE: 4.000000 1401!+ 40800000 PA_CL_VPORT_XOFFSET: 4.000000 1402!+ 41000000 PA_CL_VPORT_YSCALE: 8.000000 1403!+ 41000000 PA_CL_VPORT_YOFFSET: 8.000000 1404 + 00000000 PA_CL_VPORT_ZSCALE: 0.000000 1405 + 00000000 PA_CL_VPORT_ZOFFSET: 0.000000 1406 + 10030002 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 } 1407 + 00000106 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 } 1408 + ffffffff SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 } 1409 + 00000000 SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 } 1410 + 00000000 SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 } 1411 + 00000000 RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP } 1412 + 00000000 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO } 1413 + 00000c20 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 } 1414 + 00000000 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL } 1415 + 00090244 PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST } 1416 + 0000043f PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT } 1417 + 00000004 RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH } 1418 + 88888888 RB_SAMPLE_POS: 0x88888888 1419 + 00000000 PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 } 1420 + 00000000 PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 } 1421 + 00000000 PA_SU_LINE_CNTL: { WIDTH = 0.000000 } 1422 + 00000000 PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER } 1423 + 00000020 PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 } 1424 + 00000000 PA_SC_LINE_CNTL: { BRES_CNTL = 0 } 1425 + 00000000 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 } 1426 + 00000001 PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH } 1427 + 3f800000 PA_CL_GB_VERT_CLIP_ADJ: 1.000000 1428 + 3f800000 PA_CL_GB_VERT_DISC_ADJ: 1.000000 1429 + 3f800000 PA_CL_GB_HORZ_CLIP_ADJ: 1.000000 1430 + 3f800000 PA_CL_GB_HORZ_DISC_ADJ: 1.000000 1431 + 00100020 SQ_VS_CONST: { BASE = 32 | SIZE = 256 } 1432 + 000e0120 SQ_PS_CONST: { BASE = 288 | SIZE = 224 } 1433 + 0000ffff PA_SC_AA_MASK: 0xffff 1434 + 00000002 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 } 1435 + 00000002 VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 } 1436 + 0003c000 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 1437 + ffffffff RB_COLOR_DEST_MASK: 0xffffffff 14380122e25c: 0000: c0012200 00000000 00040085 1439t0 write CP_SCRATCH_REG7 (057f) 1440NEEDS WFI: CP_SCRATCH_REG7 (57f) 1441 CP_SCRATCH_REG7: 24 1442 :0,0,27,24 14430122e268: 0000: 0000057f 00000018 1444t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 14450122e270: 0000: c0002600 00000000 1446t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 1447 { EVENT = CACHE_FLUSH } 1448 event CACHE_FLUSH 14490122e278: 0000: c0004600 00000006 1450t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 1451 { EVENT = CACHE_FLUSH } 1452 event CACHE_FLUSH 14530122e280: 0000: c0004600 00000006 1454t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 1455 { EVENT = CACHE_FLUSH } 1456 event CACHE_FLUSH 14570122e288: 0000: c0004600 00000006 1458t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 1459 { EVENT = CACHE_FLUSH } 1460 event CACHE_FLUSH 14610122e290: 0000: c0004600 00000006 1462t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 1463 { EVENT = CACHE_FLUSH } 1464 event CACHE_FLUSH 14650122e298: 0000: c0004600 00000006 1466t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 1467 { EVENT = CACHE_FLUSH } 1468 event CACHE_FLUSH 14690122e2a0: 0000: c0004600 00000006 1470t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 1471 { EVENT = CACHE_FLUSH } 1472 event CACHE_FLUSH 14730122e2a8: 0000: c0004600 00000006 1474t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 1475 { EVENT = CACHE_FLUSH } 1476 event CACHE_FLUSH 14770122e2b0: 0000: c0004600 00000006 1478t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 1479 { EVENT = CACHE_FLUSH } 1480 event CACHE_FLUSH 14810122e2b8: 0000: c0004600 00000006 1482t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 1483 { EVENT = CACHE_FLUSH } 1484 event CACHE_FLUSH 14850122e2c0: 0000: c0004600 00000006 1486t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 1487 { EVENT = CACHE_FLUSH } 1488 event CACHE_FLUSH 14890122e2c8: 0000: c0004600 00000006 1490t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 1491 { EVENT = CACHE_FLUSH } 1492 event CACHE_FLUSH 14930122e2d0: 0000: c0004600 00000006 14940122f1d8: 0000: c0013700 0122e000 000000b6 1495t2 nop 1496############################################################ 1497vertices: 0 1498cmd: deqp-gles2/185: fence=1254 1499############################################################ 1500cmdstream: 124 dwords 1501t0 write RB_BC_CONTROL (0f01) 1502 RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 } 15030122d000: 0000: 00000f01 1c004046 1504t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1505 PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 } 15060122d008: 0000: c0012d00 00040293 00000020 1507t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1508 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 } 15090122d014: 0000: c0012d00 00040316 00000002 1510t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1511 VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 } 15120122d020: 0000: c0012d00 00040317 00000002 1513t0 write CP_PERFMON_CNTL (0444) 1514 CP_PERFMON_CNTL: 0 15150122d02c: 0000: 00000444 00000000 1516t0 write RBBM_PM_OVERRIDE1 (039c) 1517 RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE } 1518 RBBM_PM_OVERRIDE2: 0xfff 15190122d034: 0000: 0001039c ffffffff 00000fff 1520t0 write TP0_CHICKEN (0e1e) 1521 TP0_CHICKEN: 0x2 15220122d040: 0000: 00000e1e 00000002 1523t3 opcode: CP_INVALIDATE_STATE (3b) (2 dwords) 15240122d048: 0000: c0003b00 00007fff 1525t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1526 SQ_VS_CONST: { BASE = 32 | SIZE = 256 } 15270122d050: 0000: c0012d00 00040307 00100020 1528t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1529 SQ_PS_CONST: { BASE = 288 | SIZE = 224 } 15300122d05c: 0000: c0012d00 00040308 000e0120 1531t3 opcode: CP_SET_CONSTANT (2d) (4 dwords) 1532 VGT_MAX_VTX_INDX: 0xffffffff 1533 VGT_MIN_VTX_INDX: 0 15340122d068: 0000: c0022d00 00040100 ffffffff 00000000 1535t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1536 VGT_INDX_OFFSET: 0 15370122d078: 0000: c0012d00 00040102 00000000 1538t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1539 SQ_CONTEXT_MISC: { SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 } 15400122d084: 0000: c0012d00 00040181 00000004 1541t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1542 SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 } 15430122d090: 0000: c0012d00 00040182 ffffffff 1544t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1545 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 } 15460122d09c: 0000: c0012d00 00040301 00000000 1547t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1548 PA_SC_LINE_CNTL: { BRES_CNTL = 0 } 15490122d0a8: 0000: c0012d00 00040300 00000000 1550t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1551 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 } 15520122d0b4: 0000: c0012d00 00040080 00000000 1553t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1554 RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH } 15550122d0c0: 0000: c0012d00 00040208 00000004 1556t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1557 RB_SAMPLE_POS: 0x88888888 15580122d0cc: 0000: c0012d00 0004020a 88888888 1559t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1560 RB_COLOR_DEST_MASK: 0xffffffff 15610122d0d8: 0000: c0012d00 00040326 ffffffff 1562t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1563 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 15640122d0e4: 0000: c0012d00 0004031b 0003c000 1565t3 opcode: CP_SET_CONSTANT (2d) (4 dwords) 1566 SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 } 1567 SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 } 15680122d0f0: 0000: c0022d00 00040183 00000000 00000000 1569t3 opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords) 15700122d100: 0000: c0004b00 00000000 1571t3 opcode: CP_WAIT_REG_EQ (52) (5 dwords) 15720122d108: 0000: c0035200 000005d0 00000000 5f601000 00000001 1573t0 write SQ_INST_STORE_MANAGMENT (0d02) 1574 SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 } 15750122d11c: 0000: 00000d02 00000180 1576t3 opcode: CP_INVALIDATE_STATE (3b) (2 dwords) 15770122d124: 0000: c0003b00 00000300 1578t3 opcode: CP_SET_SHADER_BASES (4a) (2 dwords) 15790122d12c: 0000: c0004a00 80000180 1580t3 opcode: CP_SET_CONSTANT (2d) (14 dwords) 15810122d13c: 0.000000 0.000000 0.000000 0.000000 20000.000000 1.000000 0.500000 0.000000 15820122d15c: 2.000000 0.750000 0.375000 0.250000 15830122d134: 0000: c00c2d00 00000000 00000000 00000000 00000000 00000000 469c4000 3f800000 15840122d154: 0020: 3f000000 00000000 40000000 3f400000 3ec00000 3e800000 1585t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1586 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 15870122d16c: 0000: c0012d00 00040104 0000000f 1588t3 opcode: CP_SET_CONSTANT (2d) (6 dwords) 1589 RB_BLEND_RED: 0 1590 RB_BLEND_GREEN: 0 1591 RB_BLEND_BLUE: 0 1592 RB_BLEND_ALPHA: 0xff 15930122d178: 0000: c0042d00 00040105 00000000 00000000 00000000 000000ff 1594t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1595 PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT } 15960122d190: 0000: c0012d00 00040206 0000043f 1597t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1598 RB_SURFACE_INFO: { SURFACE_PITCH = 32 | MSAA_SAMPLES = 0 } 15990122d19c: 0000: c0012d00 00040000 00000020 1600t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1601 RB_COLOR_INFO: { FORMAT = COLORX_16_16_16_16_FLOAT | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 0 | BASE = 0x1248000 } 16020122d1a8: 0000: c0012d00 00040001 01248009 1603t3 opcode: CP_SET_CONSTANT (2d) (4 dwords) 1604 PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 } 1605 PA_SC_SCREEN_SCISSOR_BR: { X = 4 | Y = 8 } 16060122d1b4: 0000: c0022d00 0004000e 80000000 00080004 1607t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1608 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 } 16090122d1c4: 0000: c0012d00 00040080 00000000 1610t0 write CP_SCRATCH_REG6 (057e) 1611 CP_SCRATCH_REG6: 33 1612 :0,0,33,24 16130122d1d0: 0000: 0000057e 00000021 1614t3 opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords) 1615 ibaddr:0122e000 1616 ibsize:000000b6 1617t3 opcode: CP_SET_CONSTANT (2d) (6 dwords) 1618 set shader const 0078 16190122e000: 0000: c0042d00 00010078 0112d203 00100000 0112d203 00100000 1620t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1621 PA_SC_AA_MASK: 0xffff 16220122e018: 0000: c0012d00 00040312 0000ffff 1623t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1624 RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP } 16250122e024: 0000: c0012d00 00040200 00000000 1626t3 opcode: CP_SET_CONSTANT (2d) (5 dwords) 1627 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 1628 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 1629 RB_ALPHA_REF: 0 16300122e030: 0000: c0032d00 0004010c 00000000 00000000 00000000 1631t3 opcode: CP_SET_CONSTANT (2d) (4 dwords) 1632 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL } 1633 PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST } 16340122e044: 0000: c0022d00 00040204 00000000 00090244 1635t3 opcode: CP_SET_CONSTANT (2d) (6 dwords) 1636 PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 } 1637 PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 } 1638 PA_SU_LINE_CNTL: { WIDTH = 0.000000 } 1639 PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER } 16400122e054: 0000: c0042d00 00040280 00000000 00000000 00000000 00000000 1641t3 opcode: CP_SET_CONSTANT (2d) (7 dwords) 1642 PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH } 1643 PA_CL_GB_VERT_CLIP_ADJ: 1.000000 1644 PA_CL_GB_VERT_DISC_ADJ: 1.000000 1645 PA_CL_GB_HORZ_CLIP_ADJ: 1.000000 1646 PA_CL_GB_HORZ_DISC_ADJ: 1.000000 16470122e06c: 0000: c0052d00 00040302 00000001 3f800000 3f800000 3f800000 3f800000 1648t3 opcode: CP_SET_CONSTANT (2d) (4 dwords) 1649 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 1650 PA_SC_WINDOW_SCISSOR_BR: { X = 4 | Y = 8 } 16510122e088: 0000: c0022d00 00040081 00000000 00080004 1652t3 opcode: CP_SET_CONSTANT (2d) (8 dwords) 1653 PA_CL_VPORT_XSCALE: 2.000000 1654 PA_CL_VPORT_XOFFSET: 2.000000 1655 PA_CL_VPORT_YSCALE: 4.000000 1656 PA_CL_VPORT_YOFFSET: 4.000000 1657 PA_CL_VPORT_ZSCALE: 0.000000 1658 PA_CL_VPORT_ZOFFSET: 0.000000 16590122e098: 0000: c0062d00 0004010f 40000000 40000000 40800000 40800000 00000000 00000000 1660t3 opcode: CP_SET_CONSTANT (2d) (10 dwords) 16610122e0c0: 2.000000 4.000000 0.000000 0.000000 2.000000 4.000000 0.000000 0.000000 16620122e0b8: 0000: c0082d00 00000184 40000000 40800000 00000000 00000000 40000000 40800000 1663* 1664t3 opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords) 1665 vertex shader, start=0000, size=0015 1666 2003 0007 1000 EXEC ADDR(0x3) CNT(0x2) 1667 03: 19481000 00262688 00000020 (S)FETCH: VERTEX R1.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) CONST(20, 0) 1668 04: 13480000 40262688 00001020 FETCH: VERTEX R0.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) OFFSET(16) CONST(20, 1) 1669 0000 0000 c200 ALLOC POSITION SIZE(0x0) 1670 1005 0002 1000 EXEC ADDR(0x5) CNT(0x1) 1671 05: 000f803e 00000000 c2010100 (S)ALU: MAXv export62 = R1, R1 ; gl_Position 1672 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0) 1673 1006 0000 2000 EXEC_END ADDR(0x6) CNT(0x1) 1674 06: 000f8000 00000000 c2000000 ALU: MAXv export0 = R0, R0 1675 0000 0000 0000 NOP 16760122e0e0: 0000: c0162b00 00000000 00000015 00072003 00001000 c2000000 00021005 00001000 16770122e100: 0020: c4000000 00001006 00002000 00000000 19481000 00262688 00000020 13480000 16780122e120: 0040: 40262688 00001020 000f803e 00000000 c2010100 000f8000 00000000 c2000000 1679t3 opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords) 1680 fragment shader, start=0000, size=000c 1681 1002 0003 1000 EXEC ADDR(0x2) CNT(0x1) 1682 02: 90000001 1ffff688 00000002 (S)FETCH: SAMPLE R0.xyzw = R0.xyz CONST(0) LOCATION(CENTER) 1683 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0) 1684 1003 0002 2000 EXEC_END ADDR(0x3) CNT(0x1) 1685 03: 000f8000 00000000 c2000000 (S)ALU: MAXv export0 = R0, R0 ; gl_FragColor 1686 0000 0000 0000 NOP 16870122e140: 0000: c00d2b00 00000001 0000000c 00031002 00001000 c4000000 00021003 00002000 16880122e160: 0020: 00000000 90000001 1ffff688 00000002 000f8000 00000000 c2000000 1689t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1690 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 } 16910122e17c: 0000: c0012d00 00040181 00000106 1692t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1693 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 } 16940122e188: 0000: c0012d00 00040180 10030002 1695t3 opcode: CP_SET_CONSTANT (2d) (6 dwords) 16960122e19c: 0.000000 0.000000 0.000000 0.000000 16970122e194: 0000: c0042d00 00000080 00000000 00000000 00000000 00000000 1698t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1699 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 } 17000122e1ac: 0000: c0012d00 00040202 00000c20 1701t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1702 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO } 17030122e1b8: 0000: c0012d00 00040201 00000000 1704t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1705 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 17060122e1c4: 0000: c0012d00 00040104 0000000f 1707t3 opcode: CP_SET_CONSTANT (2d) (6 dwords) 1708 RB_BLEND_RED: 0 1709 RB_BLEND_GREEN: 0 1710 RB_BLEND_BLUE: 0 1711 RB_BLEND_ALPHA: 0 17120122e1d0: 0000: c0042d00 00040105 00000000 00000000 00000000 00000000 1713t3 opcode: CP_SET_CONSTANT (2d) (8 dwords) 1714 set texture const 0000 1715 clamp x/y/z: clamp-last-texel/clamp-last-texel/clamp-last-texel 1716 filter min/mag: point/point 1717 swizzle: xyzw 1718 addr=01254000 (flags=820), size=4x8, pitch=32, format=FMT_1_REVERSE 1719 mipaddr=00000000 (flags=200) 17200122e1e8: 0000: c0062d00 00010000 00424800 01254820 0000e003 00000d11 00000000 00000200 1721t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1722 VGT_INDX_OFFSET: 0 17230122e208: 0000: c0012d00 00040102 00000000 1724t0 write TC_CNTL_STATUS (0e00) 1725 TC_CNTL_STATUS: { L2_INVALIDATE } 17260122e214: 0000: 00000e00 00000001 1727t3 opcode: CP_WAIT_REG_EQ (52) (5 dwords) 17280122e21c: 0000: c0035200 000005d0 00000000 00001000 00000001 1729t3 opcode: CP_DRAW_INDX_BIN (34) (7 dwords) 17300122e230: 0000: c0053400 00000000 0003c004 00000000 00000003 01009040 00000006 1731t0 write CP_SCRATCH_REG7 (057f) 1732 CP_SCRATCH_REG7: 29 1733 :0,0,33,29 17340122e24c: 0000: 0000057f 0000001d 1735t3 opcode: CP_NOP (10) (2 dwords) 17360122e254: 0000: c0001000 00000000 1737t3 opcode: CP_DRAW_INDX (22) (3 dwords) 1738 { VIZ_QUERY = 0 } 1739 { PRIM_TYPE = DI_PT_TRIFAN | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | NUM_INSTANCES = 0 | 0x40000 } 1740 draw: 0 1741 prim_type: DI_PT_TRIFAN (5) 1742 source_select: DI_SRC_SEL_AUTO_INDEX (2) 1743 num_indices: 1407 1744 draw[4] register values 1745 + ffffffff RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE } 1746 + 00000fff RBBM_PM_OVERRIDE2: 0xfff 1747 + 00000000 CP_PERFMON_CNTL: 0 1748!+ 00000021 CP_SCRATCH_REG6: 33 1749 :0,0,33,29 1750!+ 0000001d CP_SCRATCH_REG7: 29 1751 :0,0,33,29 1752 + 00000180 SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 } 1753 + 00000001 TC_CNTL_STATUS: { L2_INVALIDATE } 1754 + 00000002 TP0_CHICKEN: 0x2 1755 + 1c004046 RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 } 1756 + 00000020 RB_SURFACE_INFO: { SURFACE_PITCH = 32 | MSAA_SAMPLES = 0 } 1757!+ 01248009 RB_COLOR_INFO: { FORMAT = COLORX_16_16_16_16_FLOAT | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 0 | BASE = 0x1248000 } 1758 + 80000000 PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 } 1759!+ 00080004 PA_SC_SCREEN_SCISSOR_BR: { X = 4 | Y = 8 } 1760 + 00000000 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 } 1761 + 00000000 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 1762!+ 00080004 PA_SC_WINDOW_SCISSOR_BR: { X = 4 | Y = 8 } 1763 + ffffffff VGT_MAX_VTX_INDX: 0xffffffff 1764 + 00000000 VGT_MIN_VTX_INDX: 0 1765 + 00000000 VGT_INDX_OFFSET: 0 1766 + 0000000f RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 1767 + 00000000 RB_BLEND_RED: 0 1768 + 00000000 RB_BLEND_GREEN: 0 1769 + 00000000 RB_BLEND_BLUE: 0 1770 + 00000000 RB_BLEND_ALPHA: 0 1771 + 00000000 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 1772 + 00000000 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 1773 + 00000000 RB_ALPHA_REF: 0 1774!+ 40000000 PA_CL_VPORT_XSCALE: 2.000000 1775!+ 40000000 PA_CL_VPORT_XOFFSET: 2.000000 1776!+ 40800000 PA_CL_VPORT_YSCALE: 4.000000 1777!+ 40800000 PA_CL_VPORT_YOFFSET: 4.000000 1778 + 00000000 PA_CL_VPORT_ZSCALE: 0.000000 1779 + 00000000 PA_CL_VPORT_ZOFFSET: 0.000000 1780 + 10030002 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 } 1781 + 00000106 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 } 1782 + ffffffff SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 } 1783 + 00000000 SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 } 1784 + 00000000 SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 } 1785 + 00000000 RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP } 1786 + 00000000 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO } 1787 + 00000c20 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 } 1788 + 00000000 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL } 1789 + 00090244 PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST } 1790 + 0000043f PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT } 1791 + 00000004 RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH } 1792 + 88888888 RB_SAMPLE_POS: 0x88888888 1793 + 00000000 PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 } 1794 + 00000000 PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 } 1795 + 00000000 PA_SU_LINE_CNTL: { WIDTH = 0.000000 } 1796 + 00000000 PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER } 1797 + 00000020 PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 } 1798 + 00000000 PA_SC_LINE_CNTL: { BRES_CNTL = 0 } 1799 + 00000000 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 } 1800 + 00000001 PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH } 1801 + 3f800000 PA_CL_GB_VERT_CLIP_ADJ: 1.000000 1802 + 3f800000 PA_CL_GB_VERT_DISC_ADJ: 1.000000 1803 + 3f800000 PA_CL_GB_HORZ_CLIP_ADJ: 1.000000 1804 + 3f800000 PA_CL_GB_HORZ_DISC_ADJ: 1.000000 1805 + 00100020 SQ_VS_CONST: { BASE = 32 | SIZE = 256 } 1806 + 000e0120 SQ_PS_CONST: { BASE = 288 | SIZE = 224 } 1807 + 0000ffff PA_SC_AA_MASK: 0xffff 1808 + 00000002 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 } 1809 + 00000002 VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 } 1810 + 0003c000 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 1811 + ffffffff RB_COLOR_DEST_MASK: 0xffffffff 18120122e25c: 0000: c0012200 00000000 00040085 1813t0 write CP_SCRATCH_REG7 (057f) 1814NEEDS WFI: CP_SCRATCH_REG7 (57f) 1815 CP_SCRATCH_REG7: 30 1816 :0,0,33,30 18170122e268: 0000: 0000057f 0000001e 1818t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 18190122e270: 0000: c0002600 00000000 1820t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 1821 { EVENT = CACHE_FLUSH } 1822 event CACHE_FLUSH 18230122e278: 0000: c0004600 00000006 1824t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 1825 { EVENT = CACHE_FLUSH } 1826 event CACHE_FLUSH 18270122e280: 0000: c0004600 00000006 1828t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 1829 { EVENT = CACHE_FLUSH } 1830 event CACHE_FLUSH 18310122e288: 0000: c0004600 00000006 1832t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 1833 { EVENT = CACHE_FLUSH } 1834 event CACHE_FLUSH 18350122e290: 0000: c0004600 00000006 1836t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 1837 { EVENT = CACHE_FLUSH } 1838 event CACHE_FLUSH 18390122e298: 0000: c0004600 00000006 1840t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 1841 { EVENT = CACHE_FLUSH } 1842 event CACHE_FLUSH 18430122e2a0: 0000: c0004600 00000006 1844t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 1845 { EVENT = CACHE_FLUSH } 1846 event CACHE_FLUSH 18470122e2a8: 0000: c0004600 00000006 1848t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 1849 { EVENT = CACHE_FLUSH } 1850 event CACHE_FLUSH 18510122e2b0: 0000: c0004600 00000006 1852t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 1853 { EVENT = CACHE_FLUSH } 1854 event CACHE_FLUSH 18550122e2b8: 0000: c0004600 00000006 1856t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 1857 { EVENT = CACHE_FLUSH } 1858 event CACHE_FLUSH 18590122e2c0: 0000: c0004600 00000006 1860t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 1861 { EVENT = CACHE_FLUSH } 1862 event CACHE_FLUSH 18630122e2c8: 0000: c0004600 00000006 1864t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 1865 { EVENT = CACHE_FLUSH } 1866 event CACHE_FLUSH 18670122e2d0: 0000: c0004600 00000006 18680122d1d8: 0000: c0013700 0122e000 000000b6 1869t2 nop 1870############################################################ 1871vertices: 0 1872cmd: deqp-gles2/185: fence=1255 1873############################################################ 1874cmdstream: 124 dwords 1875t0 write RB_BC_CONTROL (0f01) 1876 RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 } 18770122f000: 0000: 00000f01 1c004046 1878t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1879 PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 } 18800122f008: 0000: c0012d00 00040293 00000020 1881t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1882 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 } 18830122f014: 0000: c0012d00 00040316 00000002 1884t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1885 VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 } 18860122f020: 0000: c0012d00 00040317 00000002 1887t0 write CP_PERFMON_CNTL (0444) 1888 CP_PERFMON_CNTL: 0 18890122f02c: 0000: 00000444 00000000 1890t0 write RBBM_PM_OVERRIDE1 (039c) 1891 RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE } 1892 RBBM_PM_OVERRIDE2: 0xfff 18930122f034: 0000: 0001039c ffffffff 00000fff 1894t0 write TP0_CHICKEN (0e1e) 1895 TP0_CHICKEN: 0x2 18960122f040: 0000: 00000e1e 00000002 1897t3 opcode: CP_INVALIDATE_STATE (3b) (2 dwords) 18980122f048: 0000: c0003b00 00007fff 1899t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1900 SQ_VS_CONST: { BASE = 32 | SIZE = 256 } 19010122f050: 0000: c0012d00 00040307 00100020 1902t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1903 SQ_PS_CONST: { BASE = 288 | SIZE = 224 } 19040122f05c: 0000: c0012d00 00040308 000e0120 1905t3 opcode: CP_SET_CONSTANT (2d) (4 dwords) 1906 VGT_MAX_VTX_INDX: 0xffffffff 1907 VGT_MIN_VTX_INDX: 0 19080122f068: 0000: c0022d00 00040100 ffffffff 00000000 1909t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1910 VGT_INDX_OFFSET: 0 19110122f078: 0000: c0012d00 00040102 00000000 1912t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1913 SQ_CONTEXT_MISC: { SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 } 19140122f084: 0000: c0012d00 00040181 00000004 1915t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1916 SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 } 19170122f090: 0000: c0012d00 00040182 ffffffff 1918t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1919 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 } 19200122f09c: 0000: c0012d00 00040301 00000000 1921t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1922 PA_SC_LINE_CNTL: { BRES_CNTL = 0 } 19230122f0a8: 0000: c0012d00 00040300 00000000 1924t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1925 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 } 19260122f0b4: 0000: c0012d00 00040080 00000000 1927t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1928 RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH } 19290122f0c0: 0000: c0012d00 00040208 00000004 1930t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1931 RB_SAMPLE_POS: 0x88888888 19320122f0cc: 0000: c0012d00 0004020a 88888888 1933t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1934 RB_COLOR_DEST_MASK: 0xffffffff 19350122f0d8: 0000: c0012d00 00040326 ffffffff 1936t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1937 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 19380122f0e4: 0000: c0012d00 0004031b 0003c000 1939t3 opcode: CP_SET_CONSTANT (2d) (4 dwords) 1940 SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 } 1941 SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 } 19420122f0f0: 0000: c0022d00 00040183 00000000 00000000 1943t3 opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords) 19440122f100: 0000: c0004b00 00000000 1945t3 opcode: CP_WAIT_REG_EQ (52) (5 dwords) 19460122f108: 0000: c0035200 000005d0 00000000 5f601000 00000001 1947t0 write SQ_INST_STORE_MANAGMENT (0d02) 1948 SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 } 19490122f11c: 0000: 00000d02 00000180 1950t3 opcode: CP_INVALIDATE_STATE (3b) (2 dwords) 19510122f124: 0000: c0003b00 00000300 1952t3 opcode: CP_SET_SHADER_BASES (4a) (2 dwords) 19530122f12c: 0000: c0004a00 80000180 1954t3 opcode: CP_SET_CONSTANT (2d) (14 dwords) 19550122f13c: 0.000000 0.000000 0.000000 0.000000 20000.000000 1.000000 0.500000 0.000000 19560122f15c: 2.000000 0.750000 0.375000 0.250000 19570122f134: 0000: c00c2d00 00000000 00000000 00000000 00000000 00000000 469c4000 3f800000 19580122f154: 0020: 3f000000 00000000 40000000 3f400000 3ec00000 3e800000 1959t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1960 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 19610122f16c: 0000: c0012d00 00040104 0000000f 1962t3 opcode: CP_SET_CONSTANT (2d) (6 dwords) 1963 RB_BLEND_RED: 0 1964 RB_BLEND_GREEN: 0 1965 RB_BLEND_BLUE: 0 1966 RB_BLEND_ALPHA: 0xff 19670122f178: 0000: c0042d00 00040105 00000000 00000000 00000000 000000ff 1968t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1969 PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT } 19700122f190: 0000: c0012d00 00040206 0000043f 1971t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1972 RB_SURFACE_INFO: { SURFACE_PITCH = 32 | MSAA_SAMPLES = 0 } 19730122f19c: 0000: c0012d00 00040000 00000020 1974t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1975 RB_COLOR_INFO: { FORMAT = COLORX_16_16_16_16_FLOAT | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 0 | BASE = 0x124a000 } 19760122f1a8: 0000: c0012d00 00040001 0124a009 1977t3 opcode: CP_SET_CONSTANT (2d) (4 dwords) 1978 PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 } 1979 PA_SC_SCREEN_SCISSOR_BR: { X = 2 | Y = 4 } 19800122f1b4: 0000: c0022d00 0004000e 80000000 00040002 1981t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1982 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 } 19830122f1c4: 0000: c0012d00 00040080 00000000 1984t0 write CP_SCRATCH_REG6 (057e) 1985 CP_SCRATCH_REG6: 39 1986 :0,0,39,30 19870122f1d0: 0000: 0000057e 00000027 1988t3 opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords) 1989 ibaddr:0122e000 1990 ibsize:000000b6 1991t3 opcode: CP_SET_CONSTANT (2d) (6 dwords) 1992 set shader const 0078 19930122e000: 0000: c0042d00 00010078 0112d283 00100000 0112d283 00100000 1994t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1995 PA_SC_AA_MASK: 0xffff 19960122e018: 0000: c0012d00 00040312 0000ffff 1997t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 1998 RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP } 19990122e024: 0000: c0012d00 00040200 00000000 2000t3 opcode: CP_SET_CONSTANT (2d) (5 dwords) 2001 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 2002 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 2003 RB_ALPHA_REF: 0 20040122e030: 0000: c0032d00 0004010c 00000000 00000000 00000000 2005t3 opcode: CP_SET_CONSTANT (2d) (4 dwords) 2006 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL } 2007 PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST } 20080122e044: 0000: c0022d00 00040204 00000000 00090244 2009t3 opcode: CP_SET_CONSTANT (2d) (6 dwords) 2010 PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 } 2011 PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 } 2012 PA_SU_LINE_CNTL: { WIDTH = 0.000000 } 2013 PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER } 20140122e054: 0000: c0042d00 00040280 00000000 00000000 00000000 00000000 2015t3 opcode: CP_SET_CONSTANT (2d) (7 dwords) 2016 PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH } 2017 PA_CL_GB_VERT_CLIP_ADJ: 1.000000 2018 PA_CL_GB_VERT_DISC_ADJ: 1.000000 2019 PA_CL_GB_HORZ_CLIP_ADJ: 1.000000 2020 PA_CL_GB_HORZ_DISC_ADJ: 1.000000 20210122e06c: 0000: c0052d00 00040302 00000001 3f800000 3f800000 3f800000 3f800000 2022t3 opcode: CP_SET_CONSTANT (2d) (4 dwords) 2023 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 2024 PA_SC_WINDOW_SCISSOR_BR: { X = 2 | Y = 4 } 20250122e088: 0000: c0022d00 00040081 00000000 00040002 2026t3 opcode: CP_SET_CONSTANT (2d) (8 dwords) 2027 PA_CL_VPORT_XSCALE: 1.000000 2028 PA_CL_VPORT_XOFFSET: 1.000000 2029 PA_CL_VPORT_YSCALE: 2.000000 2030 PA_CL_VPORT_YOFFSET: 2.000000 2031 PA_CL_VPORT_ZSCALE: 0.000000 2032 PA_CL_VPORT_ZOFFSET: 0.000000 20330122e098: 0000: c0062d00 0004010f 3f800000 3f800000 40000000 40000000 00000000 00000000 2034t3 opcode: CP_SET_CONSTANT (2d) (10 dwords) 20350122e0c0: 1.000000 2.000000 0.000000 0.000000 1.000000 2.000000 0.000000 0.000000 20360122e0b8: 0000: c0082d00 00000184 3f800000 40000000 00000000 00000000 3f800000 40000000 2037* 2038t3 opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords) 2039 vertex shader, start=0000, size=0015 2040 2003 0007 1000 EXEC ADDR(0x3) CNT(0x2) 2041 03: 19481000 00262688 00000020 (S)FETCH: VERTEX R1.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) CONST(20, 0) 2042 04: 13480000 40262688 00001020 FETCH: VERTEX R0.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) OFFSET(16) CONST(20, 1) 2043 0000 0000 c200 ALLOC POSITION SIZE(0x0) 2044 1005 0002 1000 EXEC ADDR(0x5) CNT(0x1) 2045 05: 000f803e 00000000 c2010100 (S)ALU: MAXv export62 = R1, R1 ; gl_Position 2046 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0) 2047 1006 0000 2000 EXEC_END ADDR(0x6) CNT(0x1) 2048 06: 000f8000 00000000 c2000000 ALU: MAXv export0 = R0, R0 2049 0000 0000 0000 NOP 20500122e0e0: 0000: c0162b00 00000000 00000015 00072003 00001000 c2000000 00021005 00001000 20510122e100: 0020: c4000000 00001006 00002000 00000000 19481000 00262688 00000020 13480000 20520122e120: 0040: 40262688 00001020 000f803e 00000000 c2010100 000f8000 00000000 c2000000 2053t3 opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords) 2054 fragment shader, start=0000, size=000c 2055 1002 0003 1000 EXEC ADDR(0x2) CNT(0x1) 2056 02: 90000001 1ffff688 00000002 (S)FETCH: SAMPLE R0.xyzw = R0.xyz CONST(0) LOCATION(CENTER) 2057 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0) 2058 1003 0002 2000 EXEC_END ADDR(0x3) CNT(0x1) 2059 03: 000f8000 00000000 c2000000 (S)ALU: MAXv export0 = R0, R0 ; gl_FragColor 2060 0000 0000 0000 NOP 20610122e140: 0000: c00d2b00 00000001 0000000c 00031002 00001000 c4000000 00021003 00002000 20620122e160: 0020: 00000000 90000001 1ffff688 00000002 000f8000 00000000 c2000000 2063t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2064 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 } 20650122e17c: 0000: c0012d00 00040181 00000106 2066t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2067 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 } 20680122e188: 0000: c0012d00 00040180 10030002 2069t3 opcode: CP_SET_CONSTANT (2d) (6 dwords) 20700122e19c: 0.000000 0.000000 0.000000 0.000000 20710122e194: 0000: c0042d00 00000080 00000000 00000000 00000000 00000000 2072t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2073 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 } 20740122e1ac: 0000: c0012d00 00040202 00000c20 2075t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2076 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO } 20770122e1b8: 0000: c0012d00 00040201 00000000 2078t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2079 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 20800122e1c4: 0000: c0012d00 00040104 0000000f 2081t3 opcode: CP_SET_CONSTANT (2d) (6 dwords) 2082 RB_BLEND_RED: 0 2083 RB_BLEND_GREEN: 0 2084 RB_BLEND_BLUE: 0 2085 RB_BLEND_ALPHA: 0 20860122e1d0: 0000: c0042d00 00040105 00000000 00000000 00000000 00000000 2087t3 opcode: CP_SET_CONSTANT (2d) (8 dwords) 2088 set texture const 0000 2089 clamp x/y/z: clamp-last-texel/clamp-last-texel/clamp-last-texel 2090 filter min/mag: point/point 2091 swizzle: xyzw 2092 addr=01254000 (flags=820), size=2x4, pitch=32, format=FMT_1_REVERSE 2093 mipaddr=00000000 (flags=200) 20940122e1e8: 0000: c0062d00 00010000 00424800 01254820 00006001 00000d11 00000000 00000200 2095t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2096 VGT_INDX_OFFSET: 0 20970122e208: 0000: c0012d00 00040102 00000000 2098t0 write TC_CNTL_STATUS (0e00) 2099 TC_CNTL_STATUS: { L2_INVALIDATE } 21000122e214: 0000: 00000e00 00000001 2101t3 opcode: CP_WAIT_REG_EQ (52) (5 dwords) 21020122e21c: 0000: c0035200 000005d0 00000000 00001000 00000001 2103t3 opcode: CP_DRAW_INDX_BIN (34) (7 dwords) 21040122e230: 0000: c0053400 00000000 0003c004 00000000 00000003 01009040 00000006 2105t0 write CP_SCRATCH_REG7 (057f) 2106 CP_SCRATCH_REG7: 35 2107 :0,0,39,35 21080122e24c: 0000: 0000057f 00000023 2109t3 opcode: CP_NOP (10) (2 dwords) 21100122e254: 0000: c0001000 00000000 2111t3 opcode: CP_DRAW_INDX (22) (3 dwords) 2112 { VIZ_QUERY = 0 } 2113 { PRIM_TYPE = DI_PT_TRIFAN | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | NUM_INSTANCES = 0 | 0x40000 } 2114 draw: 0 2115 prim_type: DI_PT_TRIFAN (5) 2116 source_select: DI_SRC_SEL_AUTO_INDEX (2) 2117 num_indices: 1407 2118 draw[5] register values 2119 + ffffffff RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE } 2120 + 00000fff RBBM_PM_OVERRIDE2: 0xfff 2121 + 00000000 CP_PERFMON_CNTL: 0 2122!+ 00000027 CP_SCRATCH_REG6: 39 2123 :0,0,39,35 2124!+ 00000023 CP_SCRATCH_REG7: 35 2125 :0,0,39,35 2126 + 00000180 SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 } 2127 + 00000001 TC_CNTL_STATUS: { L2_INVALIDATE } 2128 + 00000002 TP0_CHICKEN: 0x2 2129 + 1c004046 RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 } 2130 + 00000020 RB_SURFACE_INFO: { SURFACE_PITCH = 32 | MSAA_SAMPLES = 0 } 2131!+ 0124a009 RB_COLOR_INFO: { FORMAT = COLORX_16_16_16_16_FLOAT | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 0 | BASE = 0x124a000 } 2132 + 80000000 PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 } 2133!+ 00040002 PA_SC_SCREEN_SCISSOR_BR: { X = 2 | Y = 4 } 2134 + 00000000 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 } 2135 + 00000000 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 2136!+ 00040002 PA_SC_WINDOW_SCISSOR_BR: { X = 2 | Y = 4 } 2137 + ffffffff VGT_MAX_VTX_INDX: 0xffffffff 2138 + 00000000 VGT_MIN_VTX_INDX: 0 2139 + 00000000 VGT_INDX_OFFSET: 0 2140 + 0000000f RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 2141 + 00000000 RB_BLEND_RED: 0 2142 + 00000000 RB_BLEND_GREEN: 0 2143 + 00000000 RB_BLEND_BLUE: 0 2144 + 00000000 RB_BLEND_ALPHA: 0 2145 + 00000000 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 2146 + 00000000 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 2147 + 00000000 RB_ALPHA_REF: 0 2148!+ 3f800000 PA_CL_VPORT_XSCALE: 1.000000 2149!+ 3f800000 PA_CL_VPORT_XOFFSET: 1.000000 2150!+ 40000000 PA_CL_VPORT_YSCALE: 2.000000 2151!+ 40000000 PA_CL_VPORT_YOFFSET: 2.000000 2152 + 00000000 PA_CL_VPORT_ZSCALE: 0.000000 2153 + 00000000 PA_CL_VPORT_ZOFFSET: 0.000000 2154 + 10030002 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 } 2155 + 00000106 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 } 2156 + ffffffff SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 } 2157 + 00000000 SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 } 2158 + 00000000 SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 } 2159 + 00000000 RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP } 2160 + 00000000 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO } 2161 + 00000c20 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 } 2162 + 00000000 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL } 2163 + 00090244 PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST } 2164 + 0000043f PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT } 2165 + 00000004 RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH } 2166 + 88888888 RB_SAMPLE_POS: 0x88888888 2167 + 00000000 PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 } 2168 + 00000000 PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 } 2169 + 00000000 PA_SU_LINE_CNTL: { WIDTH = 0.000000 } 2170 + 00000000 PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER } 2171 + 00000020 PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 } 2172 + 00000000 PA_SC_LINE_CNTL: { BRES_CNTL = 0 } 2173 + 00000000 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 } 2174 + 00000001 PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH } 2175 + 3f800000 PA_CL_GB_VERT_CLIP_ADJ: 1.000000 2176 + 3f800000 PA_CL_GB_VERT_DISC_ADJ: 1.000000 2177 + 3f800000 PA_CL_GB_HORZ_CLIP_ADJ: 1.000000 2178 + 3f800000 PA_CL_GB_HORZ_DISC_ADJ: 1.000000 2179 + 00100020 SQ_VS_CONST: { BASE = 32 | SIZE = 256 } 2180 + 000e0120 SQ_PS_CONST: { BASE = 288 | SIZE = 224 } 2181 + 0000ffff PA_SC_AA_MASK: 0xffff 2182 + 00000002 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 } 2183 + 00000002 VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 } 2184 + 0003c000 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 2185 + ffffffff RB_COLOR_DEST_MASK: 0xffffffff 21860122e25c: 0000: c0012200 00000000 00040085 2187t0 write CP_SCRATCH_REG7 (057f) 2188NEEDS WFI: CP_SCRATCH_REG7 (57f) 2189 CP_SCRATCH_REG7: 36 2190 :0,0,39,36 21910122e268: 0000: 0000057f 00000024 2192t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 21930122e270: 0000: c0002600 00000000 2194t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 2195 { EVENT = CACHE_FLUSH } 2196 event CACHE_FLUSH 21970122e278: 0000: c0004600 00000006 2198t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 2199 { EVENT = CACHE_FLUSH } 2200 event CACHE_FLUSH 22010122e280: 0000: c0004600 00000006 2202t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 2203 { EVENT = CACHE_FLUSH } 2204 event CACHE_FLUSH 22050122e288: 0000: c0004600 00000006 2206t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 2207 { EVENT = CACHE_FLUSH } 2208 event CACHE_FLUSH 22090122e290: 0000: c0004600 00000006 2210t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 2211 { EVENT = CACHE_FLUSH } 2212 event CACHE_FLUSH 22130122e298: 0000: c0004600 00000006 2214t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 2215 { EVENT = CACHE_FLUSH } 2216 event CACHE_FLUSH 22170122e2a0: 0000: c0004600 00000006 2218t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 2219 { EVENT = CACHE_FLUSH } 2220 event CACHE_FLUSH 22210122e2a8: 0000: c0004600 00000006 2222t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 2223 { EVENT = CACHE_FLUSH } 2224 event CACHE_FLUSH 22250122e2b0: 0000: c0004600 00000006 2226t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 2227 { EVENT = CACHE_FLUSH } 2228 event CACHE_FLUSH 22290122e2b8: 0000: c0004600 00000006 2230t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 2231 { EVENT = CACHE_FLUSH } 2232 event CACHE_FLUSH 22330122e2c0: 0000: c0004600 00000006 2234t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 2235 { EVENT = CACHE_FLUSH } 2236 event CACHE_FLUSH 22370122e2c8: 0000: c0004600 00000006 2238t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 2239 { EVENT = CACHE_FLUSH } 2240 event CACHE_FLUSH 22410122e2d0: 0000: c0004600 00000006 22420122f1d8: 0000: c0013700 0122e000 000000b6 2243t2 nop 2244############################################################ 2245vertices: 0 2246cmd: deqp-gles2/185: fence=1256 2247############################################################ 2248cmdstream: 124 dwords 2249t0 write RB_BC_CONTROL (0f01) 2250 RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 } 22510122d000: 0000: 00000f01 1c004046 2252t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2253 PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 } 22540122d008: 0000: c0012d00 00040293 00000020 2255t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2256 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 } 22570122d014: 0000: c0012d00 00040316 00000002 2258t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2259 VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 } 22600122d020: 0000: c0012d00 00040317 00000002 2261t0 write CP_PERFMON_CNTL (0444) 2262 CP_PERFMON_CNTL: 0 22630122d02c: 0000: 00000444 00000000 2264t0 write RBBM_PM_OVERRIDE1 (039c) 2265 RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE } 2266 RBBM_PM_OVERRIDE2: 0xfff 22670122d034: 0000: 0001039c ffffffff 00000fff 2268t0 write TP0_CHICKEN (0e1e) 2269 TP0_CHICKEN: 0x2 22700122d040: 0000: 00000e1e 00000002 2271t3 opcode: CP_INVALIDATE_STATE (3b) (2 dwords) 22720122d048: 0000: c0003b00 00007fff 2273t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2274 SQ_VS_CONST: { BASE = 32 | SIZE = 256 } 22750122d050: 0000: c0012d00 00040307 00100020 2276t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2277 SQ_PS_CONST: { BASE = 288 | SIZE = 224 } 22780122d05c: 0000: c0012d00 00040308 000e0120 2279t3 opcode: CP_SET_CONSTANT (2d) (4 dwords) 2280 VGT_MAX_VTX_INDX: 0xffffffff 2281 VGT_MIN_VTX_INDX: 0 22820122d068: 0000: c0022d00 00040100 ffffffff 00000000 2283t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2284 VGT_INDX_OFFSET: 0 22850122d078: 0000: c0012d00 00040102 00000000 2286t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2287 SQ_CONTEXT_MISC: { SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 } 22880122d084: 0000: c0012d00 00040181 00000004 2289t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2290 SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 } 22910122d090: 0000: c0012d00 00040182 ffffffff 2292t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2293 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 } 22940122d09c: 0000: c0012d00 00040301 00000000 2295t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2296 PA_SC_LINE_CNTL: { BRES_CNTL = 0 } 22970122d0a8: 0000: c0012d00 00040300 00000000 2298t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2299 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 } 23000122d0b4: 0000: c0012d00 00040080 00000000 2301t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2302 RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH } 23030122d0c0: 0000: c0012d00 00040208 00000004 2304t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2305 RB_SAMPLE_POS: 0x88888888 23060122d0cc: 0000: c0012d00 0004020a 88888888 2307t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2308 RB_COLOR_DEST_MASK: 0xffffffff 23090122d0d8: 0000: c0012d00 00040326 ffffffff 2310t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2311 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 23120122d0e4: 0000: c0012d00 0004031b 0003c000 2313t3 opcode: CP_SET_CONSTANT (2d) (4 dwords) 2314 SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 } 2315 SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 } 23160122d0f0: 0000: c0022d00 00040183 00000000 00000000 2317t3 opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords) 23180122d100: 0000: c0004b00 00000000 2319t3 opcode: CP_WAIT_REG_EQ (52) (5 dwords) 23200122d108: 0000: c0035200 000005d0 00000000 5f601000 00000001 2321t0 write SQ_INST_STORE_MANAGMENT (0d02) 2322 SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 } 23230122d11c: 0000: 00000d02 00000180 2324t3 opcode: CP_INVALIDATE_STATE (3b) (2 dwords) 23250122d124: 0000: c0003b00 00000300 2326t3 opcode: CP_SET_SHADER_BASES (4a) (2 dwords) 23270122d12c: 0000: c0004a00 80000180 2328t3 opcode: CP_SET_CONSTANT (2d) (14 dwords) 23290122d13c: 0.000000 0.000000 0.000000 0.000000 20000.000000 1.000000 0.500000 0.000000 23300122d15c: 2.000000 0.750000 0.375000 0.250000 23310122d134: 0000: c00c2d00 00000000 00000000 00000000 00000000 00000000 469c4000 3f800000 23320122d154: 0020: 3f000000 00000000 40000000 3f400000 3ec00000 3e800000 2333t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2334 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 23350122d16c: 0000: c0012d00 00040104 0000000f 2336t3 opcode: CP_SET_CONSTANT (2d) (6 dwords) 2337 RB_BLEND_RED: 0 2338 RB_BLEND_GREEN: 0 2339 RB_BLEND_BLUE: 0 2340 RB_BLEND_ALPHA: 0xff 23410122d178: 0000: c0042d00 00040105 00000000 00000000 00000000 000000ff 2342t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2343 PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT } 23440122d190: 0000: c0012d00 00040206 0000043f 2345t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2346 RB_SURFACE_INFO: { SURFACE_PITCH = 32 | MSAA_SAMPLES = 0 } 23470122d19c: 0000: c0012d00 00040000 00000020 2348t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2349 RB_COLOR_INFO: { FORMAT = COLORX_16_16_16_16_FLOAT | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 0 | BASE = 0x124c000 } 23500122d1a8: 0000: c0012d00 00040001 0124c009 2351t3 opcode: CP_SET_CONSTANT (2d) (4 dwords) 2352 PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 } 2353 PA_SC_SCREEN_SCISSOR_BR: { X = 1 | Y = 2 } 23540122d1b4: 0000: c0022d00 0004000e 80000000 00020001 2355t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2356 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 } 23570122d1c4: 0000: c0012d00 00040080 00000000 2358t0 write CP_SCRATCH_REG6 (057e) 2359 CP_SCRATCH_REG6: 45 2360 :0,0,45,36 23610122d1d0: 0000: 0000057e 0000002d 2362t3 opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords) 2363 ibaddr:0122e000 2364 ibsize:000000b6 2365t3 opcode: CP_SET_CONSTANT (2d) (6 dwords) 2366 set shader const 0078 23670122e000: 0000: c0042d00 00010078 0112d303 00100000 0112d303 00100000 2368t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2369 PA_SC_AA_MASK: 0xffff 23700122e018: 0000: c0012d00 00040312 0000ffff 2371t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2372 RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP } 23730122e024: 0000: c0012d00 00040200 00000000 2374t3 opcode: CP_SET_CONSTANT (2d) (5 dwords) 2375 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 2376 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 2377 RB_ALPHA_REF: 0 23780122e030: 0000: c0032d00 0004010c 00000000 00000000 00000000 2379t3 opcode: CP_SET_CONSTANT (2d) (4 dwords) 2380 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL } 2381 PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST } 23820122e044: 0000: c0022d00 00040204 00000000 00090244 2383t3 opcode: CP_SET_CONSTANT (2d) (6 dwords) 2384 PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 } 2385 PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 } 2386 PA_SU_LINE_CNTL: { WIDTH = 0.000000 } 2387 PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER } 23880122e054: 0000: c0042d00 00040280 00000000 00000000 00000000 00000000 2389t3 opcode: CP_SET_CONSTANT (2d) (7 dwords) 2390 PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH } 2391 PA_CL_GB_VERT_CLIP_ADJ: 1.000000 2392 PA_CL_GB_VERT_DISC_ADJ: 1.000000 2393 PA_CL_GB_HORZ_CLIP_ADJ: 1.000000 2394 PA_CL_GB_HORZ_DISC_ADJ: 1.000000 23950122e06c: 0000: c0052d00 00040302 00000001 3f800000 3f800000 3f800000 3f800000 2396t3 opcode: CP_SET_CONSTANT (2d) (4 dwords) 2397 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 2398 PA_SC_WINDOW_SCISSOR_BR: { X = 1 | Y = 2 } 23990122e088: 0000: c0022d00 00040081 00000000 00020001 2400t3 opcode: CP_SET_CONSTANT (2d) (8 dwords) 2401 PA_CL_VPORT_XSCALE: 0.500000 2402 PA_CL_VPORT_XOFFSET: 0.500000 2403 PA_CL_VPORT_YSCALE: 1.000000 2404 PA_CL_VPORT_YOFFSET: 1.000000 2405 PA_CL_VPORT_ZSCALE: 0.000000 2406 PA_CL_VPORT_ZOFFSET: 0.000000 24070122e098: 0000: c0062d00 0004010f 3f000000 3f000000 3f800000 3f800000 00000000 00000000 2408t3 opcode: CP_SET_CONSTANT (2d) (10 dwords) 24090122e0c0: 0.500000 1.000000 0.000000 0.000000 0.500000 1.000000 0.000000 0.000000 24100122e0b8: 0000: c0082d00 00000184 3f000000 3f800000 00000000 00000000 3f000000 3f800000 2411* 2412t3 opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords) 2413 vertex shader, start=0000, size=0015 2414 2003 0007 1000 EXEC ADDR(0x3) CNT(0x2) 2415 03: 19481000 00262688 00000020 (S)FETCH: VERTEX R1.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) CONST(20, 0) 2416 04: 13480000 40262688 00001020 FETCH: VERTEX R0.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) OFFSET(16) CONST(20, 1) 2417 0000 0000 c200 ALLOC POSITION SIZE(0x0) 2418 1005 0002 1000 EXEC ADDR(0x5) CNT(0x1) 2419 05: 000f803e 00000000 c2010100 (S)ALU: MAXv export62 = R1, R1 ; gl_Position 2420 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0) 2421 1006 0000 2000 EXEC_END ADDR(0x6) CNT(0x1) 2422 06: 000f8000 00000000 c2000000 ALU: MAXv export0 = R0, R0 2423 0000 0000 0000 NOP 24240122e0e0: 0000: c0162b00 00000000 00000015 00072003 00001000 c2000000 00021005 00001000 24250122e100: 0020: c4000000 00001006 00002000 00000000 19481000 00262688 00000020 13480000 24260122e120: 0040: 40262688 00001020 000f803e 00000000 c2010100 000f8000 00000000 c2000000 2427t3 opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords) 2428 fragment shader, start=0000, size=000c 2429 1002 0003 1000 EXEC ADDR(0x2) CNT(0x1) 2430 02: 90000001 1ffff688 00000002 (S)FETCH: SAMPLE R0.xyzw = R0.xyz CONST(0) LOCATION(CENTER) 2431 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0) 2432 1003 0002 2000 EXEC_END ADDR(0x3) CNT(0x1) 2433 03: 000f8000 00000000 c2000000 (S)ALU: MAXv export0 = R0, R0 ; gl_FragColor 2434 0000 0000 0000 NOP 24350122e140: 0000: c00d2b00 00000001 0000000c 00031002 00001000 c4000000 00021003 00002000 24360122e160: 0020: 00000000 90000001 1ffff688 00000002 000f8000 00000000 c2000000 2437t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2438 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 } 24390122e17c: 0000: c0012d00 00040181 00000106 2440t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2441 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 } 24420122e188: 0000: c0012d00 00040180 10030002 2443t3 opcode: CP_SET_CONSTANT (2d) (6 dwords) 24440122e19c: 0.000000 0.000000 0.000000 0.000000 24450122e194: 0000: c0042d00 00000080 00000000 00000000 00000000 00000000 2446t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2447 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 } 24480122e1ac: 0000: c0012d00 00040202 00000c20 2449t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2450 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO } 24510122e1b8: 0000: c0012d00 00040201 00000000 2452t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2453 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 24540122e1c4: 0000: c0012d00 00040104 0000000f 2455t3 opcode: CP_SET_CONSTANT (2d) (6 dwords) 2456 RB_BLEND_RED: 0 2457 RB_BLEND_GREEN: 0 2458 RB_BLEND_BLUE: 0 2459 RB_BLEND_ALPHA: 0 24600122e1d0: 0000: c0042d00 00040105 00000000 00000000 00000000 00000000 2461t3 opcode: CP_SET_CONSTANT (2d) (8 dwords) 2462 set texture const 0000 2463 clamp x/y/z: clamp-last-texel/clamp-last-texel/clamp-last-texel 2464 filter min/mag: point/point 2465 swizzle: xyzw 2466 addr=01254000 (flags=820), size=1x2, pitch=32, format=FMT_1_REVERSE 2467 mipaddr=00000000 (flags=200) 24680122e1e8: 0000: c0062d00 00010000 00424800 01254820 00002000 00000d11 00000000 00000200 2469t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2470 VGT_INDX_OFFSET: 0 24710122e208: 0000: c0012d00 00040102 00000000 2472t0 write TC_CNTL_STATUS (0e00) 2473 TC_CNTL_STATUS: { L2_INVALIDATE } 24740122e214: 0000: 00000e00 00000001 2475t3 opcode: CP_WAIT_REG_EQ (52) (5 dwords) 24760122e21c: 0000: c0035200 000005d0 00000000 00001000 00000001 2477t3 opcode: CP_DRAW_INDX_BIN (34) (7 dwords) 24780122e230: 0000: c0053400 00000000 0003c004 00000000 00000003 01009040 00000006 2479t0 write CP_SCRATCH_REG7 (057f) 2480 CP_SCRATCH_REG7: 41 2481 :0,0,45,41 24820122e24c: 0000: 0000057f 00000029 2483t3 opcode: CP_NOP (10) (2 dwords) 24840122e254: 0000: c0001000 00000000 2485t3 opcode: CP_DRAW_INDX (22) (3 dwords) 2486 { VIZ_QUERY = 0 } 2487 { PRIM_TYPE = DI_PT_TRIFAN | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | NUM_INSTANCES = 0 | 0x40000 } 2488 draw: 0 2489 prim_type: DI_PT_TRIFAN (5) 2490 source_select: DI_SRC_SEL_AUTO_INDEX (2) 2491 num_indices: 1407 2492 draw[6] register values 2493 + ffffffff RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE } 2494 + 00000fff RBBM_PM_OVERRIDE2: 0xfff 2495 + 00000000 CP_PERFMON_CNTL: 0 2496!+ 0000002d CP_SCRATCH_REG6: 45 2497 :0,0,45,41 2498!+ 00000029 CP_SCRATCH_REG7: 41 2499 :0,0,45,41 2500 + 00000180 SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 } 2501 + 00000001 TC_CNTL_STATUS: { L2_INVALIDATE } 2502 + 00000002 TP0_CHICKEN: 0x2 2503 + 1c004046 RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 } 2504 + 00000020 RB_SURFACE_INFO: { SURFACE_PITCH = 32 | MSAA_SAMPLES = 0 } 2505!+ 0124c009 RB_COLOR_INFO: { FORMAT = COLORX_16_16_16_16_FLOAT | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 0 | BASE = 0x124c000 } 2506 + 80000000 PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 } 2507!+ 00020001 PA_SC_SCREEN_SCISSOR_BR: { X = 1 | Y = 2 } 2508 + 00000000 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 } 2509 + 00000000 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 2510!+ 00020001 PA_SC_WINDOW_SCISSOR_BR: { X = 1 | Y = 2 } 2511 + ffffffff VGT_MAX_VTX_INDX: 0xffffffff 2512 + 00000000 VGT_MIN_VTX_INDX: 0 2513 + 00000000 VGT_INDX_OFFSET: 0 2514 + 0000000f RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 2515 + 00000000 RB_BLEND_RED: 0 2516 + 00000000 RB_BLEND_GREEN: 0 2517 + 00000000 RB_BLEND_BLUE: 0 2518 + 00000000 RB_BLEND_ALPHA: 0 2519 + 00000000 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 2520 + 00000000 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 2521 + 00000000 RB_ALPHA_REF: 0 2522!+ 3f000000 PA_CL_VPORT_XSCALE: 0.500000 2523!+ 3f000000 PA_CL_VPORT_XOFFSET: 0.500000 2524!+ 3f800000 PA_CL_VPORT_YSCALE: 1.000000 2525!+ 3f800000 PA_CL_VPORT_YOFFSET: 1.000000 2526 + 00000000 PA_CL_VPORT_ZSCALE: 0.000000 2527 + 00000000 PA_CL_VPORT_ZOFFSET: 0.000000 2528 + 10030002 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 } 2529 + 00000106 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 } 2530 + ffffffff SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 } 2531 + 00000000 SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 } 2532 + 00000000 SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 } 2533 + 00000000 RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP } 2534 + 00000000 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO } 2535 + 00000c20 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 } 2536 + 00000000 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL } 2537 + 00090244 PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST } 2538 + 0000043f PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT } 2539 + 00000004 RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH } 2540 + 88888888 RB_SAMPLE_POS: 0x88888888 2541 + 00000000 PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 } 2542 + 00000000 PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 } 2543 + 00000000 PA_SU_LINE_CNTL: { WIDTH = 0.000000 } 2544 + 00000000 PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER } 2545 + 00000020 PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 } 2546 + 00000000 PA_SC_LINE_CNTL: { BRES_CNTL = 0 } 2547 + 00000000 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 } 2548 + 00000001 PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH } 2549 + 3f800000 PA_CL_GB_VERT_CLIP_ADJ: 1.000000 2550 + 3f800000 PA_CL_GB_VERT_DISC_ADJ: 1.000000 2551 + 3f800000 PA_CL_GB_HORZ_CLIP_ADJ: 1.000000 2552 + 3f800000 PA_CL_GB_HORZ_DISC_ADJ: 1.000000 2553 + 00100020 SQ_VS_CONST: { BASE = 32 | SIZE = 256 } 2554 + 000e0120 SQ_PS_CONST: { BASE = 288 | SIZE = 224 } 2555 + 0000ffff PA_SC_AA_MASK: 0xffff 2556 + 00000002 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 } 2557 + 00000002 VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 } 2558 + 0003c000 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 2559 + ffffffff RB_COLOR_DEST_MASK: 0xffffffff 25600122e25c: 0000: c0012200 00000000 00040085 2561t0 write CP_SCRATCH_REG7 (057f) 2562NEEDS WFI: CP_SCRATCH_REG7 (57f) 2563 CP_SCRATCH_REG7: 42 2564 :0,0,45,42 25650122e268: 0000: 0000057f 0000002a 2566t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 25670122e270: 0000: c0002600 00000000 2568t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 2569 { EVENT = CACHE_FLUSH } 2570 event CACHE_FLUSH 25710122e278: 0000: c0004600 00000006 2572t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 2573 { EVENT = CACHE_FLUSH } 2574 event CACHE_FLUSH 25750122e280: 0000: c0004600 00000006 2576t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 2577 { EVENT = CACHE_FLUSH } 2578 event CACHE_FLUSH 25790122e288: 0000: c0004600 00000006 2580t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 2581 { EVENT = CACHE_FLUSH } 2582 event CACHE_FLUSH 25830122e290: 0000: c0004600 00000006 2584t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 2585 { EVENT = CACHE_FLUSH } 2586 event CACHE_FLUSH 25870122e298: 0000: c0004600 00000006 2588t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 2589 { EVENT = CACHE_FLUSH } 2590 event CACHE_FLUSH 25910122e2a0: 0000: c0004600 00000006 2592t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 2593 { EVENT = CACHE_FLUSH } 2594 event CACHE_FLUSH 25950122e2a8: 0000: c0004600 00000006 2596t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 2597 { EVENT = CACHE_FLUSH } 2598 event CACHE_FLUSH 25990122e2b0: 0000: c0004600 00000006 2600t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 2601 { EVENT = CACHE_FLUSH } 2602 event CACHE_FLUSH 26030122e2b8: 0000: c0004600 00000006 2604t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 2605 { EVENT = CACHE_FLUSH } 2606 event CACHE_FLUSH 26070122e2c0: 0000: c0004600 00000006 2608t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 2609 { EVENT = CACHE_FLUSH } 2610 event CACHE_FLUSH 26110122e2c8: 0000: c0004600 00000006 2612t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 2613 { EVENT = CACHE_FLUSH } 2614 event CACHE_FLUSH 26150122e2d0: 0000: c0004600 00000006 26160122d1d8: 0000: c0013700 0122e000 000000b6 2617t2 nop 2618############################################################ 2619vertices: 0 2620cmd: deqp-gles2/185: fence=1257 2621############################################################ 2622cmdstream: 124 dwords 2623t0 write RB_BC_CONTROL (0f01) 2624 RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 } 26250122f000: 0000: 00000f01 1c004046 2626t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2627 PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 } 26280122f008: 0000: c0012d00 00040293 00000020 2629t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2630 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 } 26310122f014: 0000: c0012d00 00040316 00000002 2632t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2633 VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 } 26340122f020: 0000: c0012d00 00040317 00000002 2635t0 write CP_PERFMON_CNTL (0444) 2636 CP_PERFMON_CNTL: 0 26370122f02c: 0000: 00000444 00000000 2638t0 write RBBM_PM_OVERRIDE1 (039c) 2639 RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE } 2640 RBBM_PM_OVERRIDE2: 0xfff 26410122f034: 0000: 0001039c ffffffff 00000fff 2642t0 write TP0_CHICKEN (0e1e) 2643 TP0_CHICKEN: 0x2 26440122f040: 0000: 00000e1e 00000002 2645t3 opcode: CP_INVALIDATE_STATE (3b) (2 dwords) 26460122f048: 0000: c0003b00 00007fff 2647t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2648 SQ_VS_CONST: { BASE = 32 | SIZE = 256 } 26490122f050: 0000: c0012d00 00040307 00100020 2650t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2651 SQ_PS_CONST: { BASE = 288 | SIZE = 224 } 26520122f05c: 0000: c0012d00 00040308 000e0120 2653t3 opcode: CP_SET_CONSTANT (2d) (4 dwords) 2654 VGT_MAX_VTX_INDX: 0xffffffff 2655 VGT_MIN_VTX_INDX: 0 26560122f068: 0000: c0022d00 00040100 ffffffff 00000000 2657t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2658 VGT_INDX_OFFSET: 0 26590122f078: 0000: c0012d00 00040102 00000000 2660t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2661 SQ_CONTEXT_MISC: { SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 } 26620122f084: 0000: c0012d00 00040181 00000004 2663t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2664 SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 } 26650122f090: 0000: c0012d00 00040182 ffffffff 2666t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2667 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 } 26680122f09c: 0000: c0012d00 00040301 00000000 2669t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2670 PA_SC_LINE_CNTL: { BRES_CNTL = 0 } 26710122f0a8: 0000: c0012d00 00040300 00000000 2672t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2673 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 } 26740122f0b4: 0000: c0012d00 00040080 00000000 2675t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2676 RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH } 26770122f0c0: 0000: c0012d00 00040208 00000004 2678t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2679 RB_SAMPLE_POS: 0x88888888 26800122f0cc: 0000: c0012d00 0004020a 88888888 2681t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2682 RB_COLOR_DEST_MASK: 0xffffffff 26830122f0d8: 0000: c0012d00 00040326 ffffffff 2684t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2685 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 26860122f0e4: 0000: c0012d00 0004031b 0003c000 2687t3 opcode: CP_SET_CONSTANT (2d) (4 dwords) 2688 SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 } 2689 SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 } 26900122f0f0: 0000: c0022d00 00040183 00000000 00000000 2691t3 opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords) 26920122f100: 0000: c0004b00 00000000 2693t3 opcode: CP_WAIT_REG_EQ (52) (5 dwords) 26940122f108: 0000: c0035200 000005d0 00000000 5f601000 00000001 2695t0 write SQ_INST_STORE_MANAGMENT (0d02) 2696 SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 } 26970122f11c: 0000: 00000d02 00000180 2698t3 opcode: CP_INVALIDATE_STATE (3b) (2 dwords) 26990122f124: 0000: c0003b00 00000300 2700t3 opcode: CP_SET_SHADER_BASES (4a) (2 dwords) 27010122f12c: 0000: c0004a00 80000180 2702t3 opcode: CP_SET_CONSTANT (2d) (14 dwords) 27030122f13c: 0.000000 0.000000 0.000000 0.000000 20000.000000 1.000000 0.500000 0.000000 27040122f15c: 2.000000 0.750000 0.375000 0.250000 27050122f134: 0000: c00c2d00 00000000 00000000 00000000 00000000 00000000 469c4000 3f800000 27060122f154: 0020: 3f000000 00000000 40000000 3f400000 3ec00000 3e800000 2707t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2708 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 27090122f16c: 0000: c0012d00 00040104 0000000f 2710t3 opcode: CP_SET_CONSTANT (2d) (6 dwords) 2711 RB_BLEND_RED: 0 2712 RB_BLEND_GREEN: 0 2713 RB_BLEND_BLUE: 0 2714 RB_BLEND_ALPHA: 0xff 27150122f178: 0000: c0042d00 00040105 00000000 00000000 00000000 000000ff 2716t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2717 PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT } 27180122f190: 0000: c0012d00 00040206 0000043f 2719t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2720 RB_SURFACE_INFO: { SURFACE_PITCH = 32 | MSAA_SAMPLES = 0 } 27210122f19c: 0000: c0012d00 00040000 00000020 2722t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2723 RB_COLOR_INFO: { FORMAT = COLORX_16_16_16_16_FLOAT | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 0 | BASE = 0x124e000 } 27240122f1a8: 0000: c0012d00 00040001 0124e009 2725t3 opcode: CP_SET_CONSTANT (2d) (4 dwords) 2726 PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 } 2727 PA_SC_SCREEN_SCISSOR_BR: { X = 1 | Y = 1 } 27280122f1b4: 0000: c0022d00 0004000e 80000000 00010001 2729t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2730 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 } 27310122f1c4: 0000: c0012d00 00040080 00000000 2732t0 write CP_SCRATCH_REG6 (057e) 2733 CP_SCRATCH_REG6: 51 2734 :0,0,51,42 27350122f1d0: 0000: 0000057e 00000033 2736t3 opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords) 2737 ibaddr:0122e000 2738 ibsize:000000b6 2739t3 opcode: CP_SET_CONSTANT (2d) (6 dwords) 2740 set shader const 0078 27410122e000: 0000: c0042d00 00010078 0112d383 00100000 0112d383 00100000 2742t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2743 PA_SC_AA_MASK: 0xffff 27440122e018: 0000: c0012d00 00040312 0000ffff 2745t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2746 RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP } 27470122e024: 0000: c0012d00 00040200 00000000 2748t3 opcode: CP_SET_CONSTANT (2d) (5 dwords) 2749 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 2750 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 2751 RB_ALPHA_REF: 0 27520122e030: 0000: c0032d00 0004010c 00000000 00000000 00000000 2753t3 opcode: CP_SET_CONSTANT (2d) (4 dwords) 2754 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL } 2755 PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST } 27560122e044: 0000: c0022d00 00040204 00000000 00090244 2757t3 opcode: CP_SET_CONSTANT (2d) (6 dwords) 2758 PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 } 2759 PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 } 2760 PA_SU_LINE_CNTL: { WIDTH = 0.000000 } 2761 PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER } 27620122e054: 0000: c0042d00 00040280 00000000 00000000 00000000 00000000 2763t3 opcode: CP_SET_CONSTANT (2d) (7 dwords) 2764 PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH } 2765 PA_CL_GB_VERT_CLIP_ADJ: 1.000000 2766 PA_CL_GB_VERT_DISC_ADJ: 1.000000 2767 PA_CL_GB_HORZ_CLIP_ADJ: 1.000000 2768 PA_CL_GB_HORZ_DISC_ADJ: 1.000000 27690122e06c: 0000: c0052d00 00040302 00000001 3f800000 3f800000 3f800000 3f800000 2770t3 opcode: CP_SET_CONSTANT (2d) (4 dwords) 2771 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 2772 PA_SC_WINDOW_SCISSOR_BR: { X = 1 | Y = 1 } 27730122e088: 0000: c0022d00 00040081 00000000 00010001 2774t3 opcode: CP_SET_CONSTANT (2d) (8 dwords) 2775 PA_CL_VPORT_XSCALE: 0.500000 2776 PA_CL_VPORT_XOFFSET: 0.500000 2777 PA_CL_VPORT_YSCALE: 0.500000 2778 PA_CL_VPORT_YOFFSET: 0.500000 2779 PA_CL_VPORT_ZSCALE: 0.000000 2780 PA_CL_VPORT_ZOFFSET: 0.000000 27810122e098: 0000: c0062d00 0004010f 3f000000 3f000000 3f000000 3f000000 00000000 00000000 2782t3 opcode: CP_SET_CONSTANT (2d) (10 dwords) 27830122e0c0: 0.500000 0.500000 0.000000 0.000000 0.500000 0.500000 0.000000 0.000000 27840122e0b8: 0000: c0082d00 00000184 3f000000 3f000000 00000000 00000000 3f000000 3f000000 2785* 2786t3 opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords) 2787 vertex shader, start=0000, size=0015 2788 2003 0007 1000 EXEC ADDR(0x3) CNT(0x2) 2789 03: 19481000 00262688 00000020 (S)FETCH: VERTEX R1.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) CONST(20, 0) 2790 04: 13480000 40262688 00001020 FETCH: VERTEX R0.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) OFFSET(16) CONST(20, 1) 2791 0000 0000 c200 ALLOC POSITION SIZE(0x0) 2792 1005 0002 1000 EXEC ADDR(0x5) CNT(0x1) 2793 05: 000f803e 00000000 c2010100 (S)ALU: MAXv export62 = R1, R1 ; gl_Position 2794 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0) 2795 1006 0000 2000 EXEC_END ADDR(0x6) CNT(0x1) 2796 06: 000f8000 00000000 c2000000 ALU: MAXv export0 = R0, R0 2797 0000 0000 0000 NOP 27980122e0e0: 0000: c0162b00 00000000 00000015 00072003 00001000 c2000000 00021005 00001000 27990122e100: 0020: c4000000 00001006 00002000 00000000 19481000 00262688 00000020 13480000 28000122e120: 0040: 40262688 00001020 000f803e 00000000 c2010100 000f8000 00000000 c2000000 2801t3 opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords) 2802 fragment shader, start=0000, size=000c 2803 1002 0003 1000 EXEC ADDR(0x2) CNT(0x1) 2804 02: 90000001 1ffff688 00000002 (S)FETCH: SAMPLE R0.xyzw = R0.xyz CONST(0) LOCATION(CENTER) 2805 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0) 2806 1003 0002 2000 EXEC_END ADDR(0x3) CNT(0x1) 2807 03: 000f8000 00000000 c2000000 (S)ALU: MAXv export0 = R0, R0 ; gl_FragColor 2808 0000 0000 0000 NOP 28090122e140: 0000: c00d2b00 00000001 0000000c 00031002 00001000 c4000000 00021003 00002000 28100122e160: 0020: 00000000 90000001 1ffff688 00000002 000f8000 00000000 c2000000 2811t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2812 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 } 28130122e17c: 0000: c0012d00 00040181 00000106 2814t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2815 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 } 28160122e188: 0000: c0012d00 00040180 10030002 2817t3 opcode: CP_SET_CONSTANT (2d) (6 dwords) 28180122e19c: 0.000000 0.000000 0.000000 0.000000 28190122e194: 0000: c0042d00 00000080 00000000 00000000 00000000 00000000 2820t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2821 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 } 28220122e1ac: 0000: c0012d00 00040202 00000c20 2823t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2824 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO } 28250122e1b8: 0000: c0012d00 00040201 00000000 2826t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2827 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 28280122e1c4: 0000: c0012d00 00040104 0000000f 2829t3 opcode: CP_SET_CONSTANT (2d) (6 dwords) 2830 RB_BLEND_RED: 0 2831 RB_BLEND_GREEN: 0 2832 RB_BLEND_BLUE: 0 2833 RB_BLEND_ALPHA: 0 28340122e1d0: 0000: c0042d00 00040105 00000000 00000000 00000000 00000000 2835t3 opcode: CP_SET_CONSTANT (2d) (8 dwords) 2836 set texture const 0000 2837 clamp x/y/z: clamp-last-texel/clamp-last-texel/clamp-last-texel 2838 filter min/mag: point/point 2839 swizzle: xyzw 2840 addr=01254000 (flags=820), size=1x1, pitch=32, format=FMT_1_REVERSE 2841 mipaddr=00000000 (flags=200) 28420122e1e8: 0000: c0062d00 00010000 00424800 01254820 00000000 00000d11 00000000 00000200 2843t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 2844 VGT_INDX_OFFSET: 0 28450122e208: 0000: c0012d00 00040102 00000000 2846t0 write TC_CNTL_STATUS (0e00) 2847 TC_CNTL_STATUS: { L2_INVALIDATE } 28480122e214: 0000: 00000e00 00000001 2849t3 opcode: CP_WAIT_REG_EQ (52) (5 dwords) 28500122e21c: 0000: c0035200 000005d0 00000000 00001000 00000001 2851t3 opcode: CP_DRAW_INDX_BIN (34) (7 dwords) 28520122e230: 0000: c0053400 00000000 0003c004 00000000 00000003 01009040 00000006 2853t0 write CP_SCRATCH_REG7 (057f) 2854 CP_SCRATCH_REG7: 47 2855 :0,0,51,47 28560122e24c: 0000: 0000057f 0000002f 2857t3 opcode: CP_NOP (10) (2 dwords) 28580122e254: 0000: c0001000 00000000 2859t3 opcode: CP_DRAW_INDX (22) (3 dwords) 2860 { VIZ_QUERY = 0 } 2861 { PRIM_TYPE = DI_PT_TRIFAN | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | NUM_INSTANCES = 0 | 0x40000 } 2862 draw: 0 2863 prim_type: DI_PT_TRIFAN (5) 2864 source_select: DI_SRC_SEL_AUTO_INDEX (2) 2865 num_indices: 1407 2866 draw[7] register values 2867 + ffffffff RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE } 2868 + 00000fff RBBM_PM_OVERRIDE2: 0xfff 2869 + 00000000 CP_PERFMON_CNTL: 0 2870!+ 00000033 CP_SCRATCH_REG6: 51 2871 :0,0,51,47 2872!+ 0000002f CP_SCRATCH_REG7: 47 2873 :0,0,51,47 2874 + 00000180 SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 } 2875 + 00000001 TC_CNTL_STATUS: { L2_INVALIDATE } 2876 + 00000002 TP0_CHICKEN: 0x2 2877 + 1c004046 RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 } 2878 + 00000020 RB_SURFACE_INFO: { SURFACE_PITCH = 32 | MSAA_SAMPLES = 0 } 2879!+ 0124e009 RB_COLOR_INFO: { FORMAT = COLORX_16_16_16_16_FLOAT | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 0 | BASE = 0x124e000 } 2880 + 80000000 PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 } 2881!+ 00010001 PA_SC_SCREEN_SCISSOR_BR: { X = 1 | Y = 1 } 2882 + 00000000 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 } 2883 + 00000000 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 2884!+ 00010001 PA_SC_WINDOW_SCISSOR_BR: { X = 1 | Y = 1 } 2885 + ffffffff VGT_MAX_VTX_INDX: 0xffffffff 2886 + 00000000 VGT_MIN_VTX_INDX: 0 2887 + 00000000 VGT_INDX_OFFSET: 0 2888 + 0000000f RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 2889 + 00000000 RB_BLEND_RED: 0 2890 + 00000000 RB_BLEND_GREEN: 0 2891 + 00000000 RB_BLEND_BLUE: 0 2892 + 00000000 RB_BLEND_ALPHA: 0 2893 + 00000000 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 2894 + 00000000 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 2895 + 00000000 RB_ALPHA_REF: 0 2896 + 3f000000 PA_CL_VPORT_XSCALE: 0.500000 2897 + 3f000000 PA_CL_VPORT_XOFFSET: 0.500000 2898!+ 3f000000 PA_CL_VPORT_YSCALE: 0.500000 2899!+ 3f000000 PA_CL_VPORT_YOFFSET: 0.500000 2900 + 00000000 PA_CL_VPORT_ZSCALE: 0.000000 2901 + 00000000 PA_CL_VPORT_ZOFFSET: 0.000000 2902 + 10030002 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 } 2903 + 00000106 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 } 2904 + ffffffff SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 } 2905 + 00000000 SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 } 2906 + 00000000 SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 } 2907 + 00000000 RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP } 2908 + 00000000 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO } 2909 + 00000c20 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 } 2910 + 00000000 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL } 2911 + 00090244 PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST } 2912 + 0000043f PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT } 2913 + 00000004 RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH } 2914 + 88888888 RB_SAMPLE_POS: 0x88888888 2915 + 00000000 PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 } 2916 + 00000000 PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 } 2917 + 00000000 PA_SU_LINE_CNTL: { WIDTH = 0.000000 } 2918 + 00000000 PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER } 2919 + 00000020 PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 } 2920 + 00000000 PA_SC_LINE_CNTL: { BRES_CNTL = 0 } 2921 + 00000000 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 } 2922 + 00000001 PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH } 2923 + 3f800000 PA_CL_GB_VERT_CLIP_ADJ: 1.000000 2924 + 3f800000 PA_CL_GB_VERT_DISC_ADJ: 1.000000 2925 + 3f800000 PA_CL_GB_HORZ_CLIP_ADJ: 1.000000 2926 + 3f800000 PA_CL_GB_HORZ_DISC_ADJ: 1.000000 2927 + 00100020 SQ_VS_CONST: { BASE = 32 | SIZE = 256 } 2928 + 000e0120 SQ_PS_CONST: { BASE = 288 | SIZE = 224 } 2929 + 0000ffff PA_SC_AA_MASK: 0xffff 2930 + 00000002 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 } 2931 + 00000002 VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 } 2932 + 0003c000 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 2933 + ffffffff RB_COLOR_DEST_MASK: 0xffffffff 29340122e25c: 0000: c0012200 00000000 00040085 2935t0 write CP_SCRATCH_REG7 (057f) 2936NEEDS WFI: CP_SCRATCH_REG7 (57f) 2937 CP_SCRATCH_REG7: 48 2938 :0,0,51,48 29390122e268: 0000: 0000057f 00000030 2940t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 29410122e270: 0000: c0002600 00000000 2942t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 2943 { EVENT = CACHE_FLUSH } 2944 event CACHE_FLUSH 29450122e278: 0000: c0004600 00000006 2946t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 2947 { EVENT = CACHE_FLUSH } 2948 event CACHE_FLUSH 29490122e280: 0000: c0004600 00000006 2950t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 2951 { EVENT = CACHE_FLUSH } 2952 event CACHE_FLUSH 29530122e288: 0000: c0004600 00000006 2954t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 2955 { EVENT = CACHE_FLUSH } 2956 event CACHE_FLUSH 29570122e290: 0000: c0004600 00000006 2958t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 2959 { EVENT = CACHE_FLUSH } 2960 event CACHE_FLUSH 29610122e298: 0000: c0004600 00000006 2962t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 2963 { EVENT = CACHE_FLUSH } 2964 event CACHE_FLUSH 29650122e2a0: 0000: c0004600 00000006 2966t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 2967 { EVENT = CACHE_FLUSH } 2968 event CACHE_FLUSH 29690122e2a8: 0000: c0004600 00000006 2970t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 2971 { EVENT = CACHE_FLUSH } 2972 event CACHE_FLUSH 29730122e2b0: 0000: c0004600 00000006 2974t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 2975 { EVENT = CACHE_FLUSH } 2976 event CACHE_FLUSH 29770122e2b8: 0000: c0004600 00000006 2978t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 2979 { EVENT = CACHE_FLUSH } 2980 event CACHE_FLUSH 29810122e2c0: 0000: c0004600 00000006 2982t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 2983 { EVENT = CACHE_FLUSH } 2984 event CACHE_FLUSH 29850122e2c8: 0000: c0004600 00000006 2986t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 2987 { EVENT = CACHE_FLUSH } 2988 event CACHE_FLUSH 29890122e2d0: 0000: c0004600 00000006 29900122f1d8: 0000: c0013700 0122e000 000000b6 2991t2 nop 2992############################################################ 2993vertices: 0 2994cmd: deqp-gles2/185: fence=1258 2995############################################################ 2996cmdstream: 124 dwords 2997t0 write RB_BC_CONTROL (0f01) 2998 RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 } 29990122d000: 0000: 00000f01 1c004046 3000t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3001 PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 } 30020122d008: 0000: c0012d00 00040293 00000020 3003t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3004 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 } 30050122d014: 0000: c0012d00 00040316 00000002 3006t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3007 VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 } 30080122d020: 0000: c0012d00 00040317 00000002 3009t0 write CP_PERFMON_CNTL (0444) 3010 CP_PERFMON_CNTL: 0 30110122d02c: 0000: 00000444 00000000 3012t0 write RBBM_PM_OVERRIDE1 (039c) 3013 RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE } 3014 RBBM_PM_OVERRIDE2: 0xfff 30150122d034: 0000: 0001039c ffffffff 00000fff 3016t0 write TP0_CHICKEN (0e1e) 3017 TP0_CHICKEN: 0x2 30180122d040: 0000: 00000e1e 00000002 3019t3 opcode: CP_INVALIDATE_STATE (3b) (2 dwords) 30200122d048: 0000: c0003b00 00007fff 3021t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3022 SQ_VS_CONST: { BASE = 32 | SIZE = 256 } 30230122d050: 0000: c0012d00 00040307 00100020 3024t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3025 SQ_PS_CONST: { BASE = 288 | SIZE = 224 } 30260122d05c: 0000: c0012d00 00040308 000e0120 3027t3 opcode: CP_SET_CONSTANT (2d) (4 dwords) 3028 VGT_MAX_VTX_INDX: 0xffffffff 3029 VGT_MIN_VTX_INDX: 0 30300122d068: 0000: c0022d00 00040100 ffffffff 00000000 3031t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3032 VGT_INDX_OFFSET: 0 30330122d078: 0000: c0012d00 00040102 00000000 3034t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3035 SQ_CONTEXT_MISC: { SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 } 30360122d084: 0000: c0012d00 00040181 00000004 3037t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3038 SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 } 30390122d090: 0000: c0012d00 00040182 ffffffff 3040t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3041 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 } 30420122d09c: 0000: c0012d00 00040301 00000000 3043t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3044 PA_SC_LINE_CNTL: { BRES_CNTL = 0 } 30450122d0a8: 0000: c0012d00 00040300 00000000 3046t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3047 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 } 30480122d0b4: 0000: c0012d00 00040080 00000000 3049t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3050 RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH } 30510122d0c0: 0000: c0012d00 00040208 00000004 3052t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3053 RB_SAMPLE_POS: 0x88888888 30540122d0cc: 0000: c0012d00 0004020a 88888888 3055t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3056 RB_COLOR_DEST_MASK: 0xffffffff 30570122d0d8: 0000: c0012d00 00040326 ffffffff 3058t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3059 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 30600122d0e4: 0000: c0012d00 0004031b 0003c000 3061t3 opcode: CP_SET_CONSTANT (2d) (4 dwords) 3062 SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 } 3063 SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 } 30640122d0f0: 0000: c0022d00 00040183 00000000 00000000 3065t3 opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords) 30660122d100: 0000: c0004b00 00000000 3067t3 opcode: CP_WAIT_REG_EQ (52) (5 dwords) 30680122d108: 0000: c0035200 000005d0 00000000 5f601000 00000001 3069t0 write SQ_INST_STORE_MANAGMENT (0d02) 3070 SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 } 30710122d11c: 0000: 00000d02 00000180 3072t3 opcode: CP_INVALIDATE_STATE (3b) (2 dwords) 30730122d124: 0000: c0003b00 00000300 3074t3 opcode: CP_SET_SHADER_BASES (4a) (2 dwords) 30750122d12c: 0000: c0004a00 80000180 3076t3 opcode: CP_SET_CONSTANT (2d) (14 dwords) 30770122d13c: 0.000000 0.000000 0.000000 0.000000 20000.000000 1.000000 0.500000 0.000000 30780122d15c: 2.000000 0.750000 0.375000 0.250000 30790122d134: 0000: c00c2d00 00000000 00000000 00000000 00000000 00000000 469c4000 3f800000 30800122d154: 0020: 3f000000 00000000 40000000 3f400000 3ec00000 3e800000 3081t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3082 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 30830122d16c: 0000: c0012d00 00040104 0000000f 3084t3 opcode: CP_SET_CONSTANT (2d) (6 dwords) 3085 RB_BLEND_RED: 0 3086 RB_BLEND_GREEN: 0 3087 RB_BLEND_BLUE: 0 3088 RB_BLEND_ALPHA: 0xff 30890122d178: 0000: c0042d00 00040105 00000000 00000000 00000000 000000ff 3090t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3091 PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT } 30920122d190: 0000: c0012d00 00040206 0000043f 3093t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3094 RB_SURFACE_INFO: { SURFACE_PITCH = 64 | MSAA_SAMPLES = 0 } 30950122d19c: 0000: c0012d00 00040000 00000040 3096t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3097 RB_COLOR_INFO: { FORMAT = COLORX_16_16_16_16_FLOAT | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 0 | BASE = 0x1230000 } 30980122d1a8: 0000: c0012d00 00040001 01230009 3099t3 opcode: CP_SET_CONSTANT (2d) (4 dwords) 3100 PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 } 3101 PA_SC_SCREEN_SCISSOR_BR: { X = 64 | Y = 128 } 31020122d1b4: 0000: c0022d00 0004000e 80000000 00800040 3103t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3104 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 } 31050122d1c4: 0000: c0012d00 00040080 00000000 3106t0 write CP_SCRATCH_REG6 (057e) 3107 CP_SCRATCH_REG6: 57 3108 :0,0,57,48 31090122d1d0: 0000: 0000057e 00000039 3110t3 opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords) 3111 ibaddr:0122e000 3112 ibsize:000000b6 3113t3 opcode: CP_SET_CONSTANT (2d) (6 dwords) 3114 set shader const 0078 31150122e000: 0000: c0042d00 00010078 0112d403 00100000 0112d403 00100000 3116t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3117 PA_SC_AA_MASK: 0xffff 31180122e018: 0000: c0012d00 00040312 0000ffff 3119t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3120 RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP } 31210122e024: 0000: c0012d00 00040200 00000000 3122t3 opcode: CP_SET_CONSTANT (2d) (5 dwords) 3123 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 3124 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 3125 RB_ALPHA_REF: 0 31260122e030: 0000: c0032d00 0004010c 00000000 00000000 00000000 3127t3 opcode: CP_SET_CONSTANT (2d) (4 dwords) 3128 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL } 3129 PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST } 31300122e044: 0000: c0022d00 00040204 00000000 00090244 3131t3 opcode: CP_SET_CONSTANT (2d) (6 dwords) 3132 PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 } 3133 PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 } 3134 PA_SU_LINE_CNTL: { WIDTH = 0.000000 } 3135 PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER } 31360122e054: 0000: c0042d00 00040280 00000000 00000000 00000000 00000000 3137t3 opcode: CP_SET_CONSTANT (2d) (7 dwords) 3138 PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH } 3139 PA_CL_GB_VERT_CLIP_ADJ: 1.000000 3140 PA_CL_GB_VERT_DISC_ADJ: 1.000000 3141 PA_CL_GB_HORZ_CLIP_ADJ: 1.000000 3142 PA_CL_GB_HORZ_DISC_ADJ: 1.000000 31430122e06c: 0000: c0052d00 00040302 00000001 3f800000 3f800000 3f800000 3f800000 3144t3 opcode: CP_SET_CONSTANT (2d) (4 dwords) 3145 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 3146 PA_SC_WINDOW_SCISSOR_BR: { X = 64 | Y = 128 } 31470122e088: 0000: c0022d00 00040081 00000000 00800040 3148t3 opcode: CP_SET_CONSTANT (2d) (8 dwords) 3149 PA_CL_VPORT_XSCALE: 32.000000 3150 PA_CL_VPORT_XOFFSET: 32.000000 3151 PA_CL_VPORT_YSCALE: 64.000000 3152 PA_CL_VPORT_YOFFSET: 64.000000 3153 PA_CL_VPORT_ZSCALE: 0.000000 3154 PA_CL_VPORT_ZOFFSET: 0.000000 31550122e098: 0000: c0062d00 0004010f 42000000 42000000 42800000 42800000 00000000 00000000 3156t3 opcode: CP_SET_CONSTANT (2d) (10 dwords) 31570122e0c0: 32.000000 64.000000 0.000000 0.000000 32.000000 64.000000 0.000000 0.000000 31580122e0b8: 0000: c0082d00 00000184 42000000 42800000 00000000 00000000 42000000 42800000 3159* 3160t3 opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords) 3161 vertex shader, start=0000, size=0015 3162 2003 0007 1000 EXEC ADDR(0x3) CNT(0x2) 3163 03: 19481000 00262688 00000020 (S)FETCH: VERTEX R1.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) CONST(20, 0) 3164 04: 13480000 40262688 00001020 FETCH: VERTEX R0.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) OFFSET(16) CONST(20, 1) 3165 0000 0000 c200 ALLOC POSITION SIZE(0x0) 3166 1005 0002 1000 EXEC ADDR(0x5) CNT(0x1) 3167 05: 000f803e 00000000 c2010100 (S)ALU: MAXv export62 = R1, R1 ; gl_Position 3168 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0) 3169 1006 0000 2000 EXEC_END ADDR(0x6) CNT(0x1) 3170 06: 000f8000 00000000 c2000000 ALU: MAXv export0 = R0, R0 3171 0000 0000 0000 NOP 31720122e0e0: 0000: c0162b00 00000000 00000015 00072003 00001000 c2000000 00021005 00001000 31730122e100: 0020: c4000000 00001006 00002000 00000000 19481000 00262688 00000020 13480000 31740122e120: 0040: 40262688 00001020 000f803e 00000000 c2010100 000f8000 00000000 c2000000 3175t3 opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords) 3176 fragment shader, start=0000, size=000c 3177 1002 0003 1000 EXEC ADDR(0x2) CNT(0x1) 3178 02: 90000001 1ffff688 00000002 (S)FETCH: SAMPLE R0.xyzw = R0.xyz CONST(0) LOCATION(CENTER) 3179 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0) 3180 1003 0002 2000 EXEC_END ADDR(0x3) CNT(0x1) 3181 03: 000f8000 00000000 c2000000 (S)ALU: MAXv export0 = R0, R0 ; gl_FragColor 3182 0000 0000 0000 NOP 31830122e140: 0000: c00d2b00 00000001 0000000c 00031002 00001000 c4000000 00021003 00002000 31840122e160: 0020: 00000000 90000001 1ffff688 00000002 000f8000 00000000 c2000000 3185t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3186 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 } 31870122e17c: 0000: c0012d00 00040181 00000106 3188t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3189 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 } 31900122e188: 0000: c0012d00 00040180 10030002 3191t3 opcode: CP_SET_CONSTANT (2d) (6 dwords) 31920122e19c: 0.000000 0.000000 0.000000 0.000000 31930122e194: 0000: c0042d00 00000080 00000000 00000000 00000000 00000000 3194t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3195 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 } 31960122e1ac: 0000: c0012d00 00040202 00000c20 3197t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3198 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO } 31990122e1b8: 0000: c0012d00 00040201 00000000 3200t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3201 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 32020122e1c4: 0000: c0012d00 00040104 0000000f 3203t3 opcode: CP_SET_CONSTANT (2d) (6 dwords) 3204 RB_BLEND_RED: 0 3205 RB_BLEND_GREEN: 0 3206 RB_BLEND_BLUE: 0 3207 RB_BLEND_ALPHA: 0 32080122e1d0: 0000: c0042d00 00040105 00000000 00000000 00000000 00000000 3209t3 opcode: CP_SET_CONSTANT (2d) (8 dwords) 3210 set texture const 0000 3211 clamp x/y/z: clamp-last-texel/clamp-last-texel/clamp-last-texel 3212 filter min/mag: point/point 3213 swizzle: xyzw 3214 addr=0110d000 (flags=820), size=64x128, pitch=16448, format=FMT_1_REVERSE 3215 mipaddr=00000000 (flags=200) 32160122e1e8: 0000: c0062d00 00010000 80824800 0110d820 000fe03f 00000d11 00000000 00000200 3217t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3218 VGT_INDX_OFFSET: 0 32190122e208: 0000: c0012d00 00040102 00000000 3220t0 write TC_CNTL_STATUS (0e00) 3221 TC_CNTL_STATUS: { L2_INVALIDATE } 32220122e214: 0000: 00000e00 00000001 3223t3 opcode: CP_WAIT_REG_EQ (52) (5 dwords) 32240122e21c: 0000: c0035200 000005d0 00000000 00001000 00000001 3225t3 opcode: CP_DRAW_INDX_BIN (34) (7 dwords) 32260122e230: 0000: c0053400 00000000 0003c004 00000000 00000003 01009040 00000006 3227t0 write CP_SCRATCH_REG7 (057f) 3228 CP_SCRATCH_REG7: 53 3229 :0,0,57,53 32300122e24c: 0000: 0000057f 00000035 3231t3 opcode: CP_NOP (10) (2 dwords) 32320122e254: 0000: c0001000 00000000 3233t3 opcode: CP_DRAW_INDX (22) (3 dwords) 3234 { VIZ_QUERY = 0 } 3235 { PRIM_TYPE = DI_PT_TRIFAN | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | NUM_INSTANCES = 0 | 0x40000 } 3236 draw: 0 3237 prim_type: DI_PT_TRIFAN (5) 3238 source_select: DI_SRC_SEL_AUTO_INDEX (2) 3239 num_indices: 1407 3240 draw[8] register values 3241 + ffffffff RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE } 3242 + 00000fff RBBM_PM_OVERRIDE2: 0xfff 3243 + 00000000 CP_PERFMON_CNTL: 0 3244!+ 00000039 CP_SCRATCH_REG6: 57 3245 :0,0,57,53 3246!+ 00000035 CP_SCRATCH_REG7: 53 3247 :0,0,57,53 3248 + 00000180 SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 } 3249 + 00000001 TC_CNTL_STATUS: { L2_INVALIDATE } 3250 + 00000002 TP0_CHICKEN: 0x2 3251 + 1c004046 RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 } 3252!+ 00000040 RB_SURFACE_INFO: { SURFACE_PITCH = 64 | MSAA_SAMPLES = 0 } 3253!+ 01230009 RB_COLOR_INFO: { FORMAT = COLORX_16_16_16_16_FLOAT | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 0 | BASE = 0x1230000 } 3254 + 80000000 PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 } 3255!+ 00800040 PA_SC_SCREEN_SCISSOR_BR: { X = 64 | Y = 128 } 3256 + 00000000 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 } 3257 + 00000000 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 3258!+ 00800040 PA_SC_WINDOW_SCISSOR_BR: { X = 64 | Y = 128 } 3259 + ffffffff VGT_MAX_VTX_INDX: 0xffffffff 3260 + 00000000 VGT_MIN_VTX_INDX: 0 3261 + 00000000 VGT_INDX_OFFSET: 0 3262 + 0000000f RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 3263 + 00000000 RB_BLEND_RED: 0 3264 + 00000000 RB_BLEND_GREEN: 0 3265 + 00000000 RB_BLEND_BLUE: 0 3266 + 00000000 RB_BLEND_ALPHA: 0 3267 + 00000000 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 3268 + 00000000 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 3269 + 00000000 RB_ALPHA_REF: 0 3270!+ 42000000 PA_CL_VPORT_XSCALE: 32.000000 3271!+ 42000000 PA_CL_VPORT_XOFFSET: 32.000000 3272!+ 42800000 PA_CL_VPORT_YSCALE: 64.000000 3273!+ 42800000 PA_CL_VPORT_YOFFSET: 64.000000 3274 + 00000000 PA_CL_VPORT_ZSCALE: 0.000000 3275 + 00000000 PA_CL_VPORT_ZOFFSET: 0.000000 3276 + 10030002 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 } 3277 + 00000106 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 } 3278 + ffffffff SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 } 3279 + 00000000 SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 } 3280 + 00000000 SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 } 3281 + 00000000 RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP } 3282 + 00000000 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO } 3283 + 00000c20 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 } 3284 + 00000000 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL } 3285 + 00090244 PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST } 3286 + 0000043f PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT } 3287 + 00000004 RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH } 3288 + 88888888 RB_SAMPLE_POS: 0x88888888 3289 + 00000000 PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 } 3290 + 00000000 PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 } 3291 + 00000000 PA_SU_LINE_CNTL: { WIDTH = 0.000000 } 3292 + 00000000 PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER } 3293 + 00000020 PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 } 3294 + 00000000 PA_SC_LINE_CNTL: { BRES_CNTL = 0 } 3295 + 00000000 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 } 3296 + 00000001 PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH } 3297 + 3f800000 PA_CL_GB_VERT_CLIP_ADJ: 1.000000 3298 + 3f800000 PA_CL_GB_VERT_DISC_ADJ: 1.000000 3299 + 3f800000 PA_CL_GB_HORZ_CLIP_ADJ: 1.000000 3300 + 3f800000 PA_CL_GB_HORZ_DISC_ADJ: 1.000000 3301 + 00100020 SQ_VS_CONST: { BASE = 32 | SIZE = 256 } 3302 + 000e0120 SQ_PS_CONST: { BASE = 288 | SIZE = 224 } 3303 + 0000ffff PA_SC_AA_MASK: 0xffff 3304 + 00000002 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 } 3305 + 00000002 VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 } 3306 + 0003c000 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 3307 + ffffffff RB_COLOR_DEST_MASK: 0xffffffff 33080122e25c: 0000: c0012200 00000000 00040085 3309t0 write CP_SCRATCH_REG7 (057f) 3310NEEDS WFI: CP_SCRATCH_REG7 (57f) 3311 CP_SCRATCH_REG7: 54 3312 :0,0,57,54 33130122e268: 0000: 0000057f 00000036 3314t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 33150122e270: 0000: c0002600 00000000 3316t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 3317 { EVENT = CACHE_FLUSH } 3318 event CACHE_FLUSH 33190122e278: 0000: c0004600 00000006 3320t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 3321 { EVENT = CACHE_FLUSH } 3322 event CACHE_FLUSH 33230122e280: 0000: c0004600 00000006 3324t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 3325 { EVENT = CACHE_FLUSH } 3326 event CACHE_FLUSH 33270122e288: 0000: c0004600 00000006 3328t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 3329 { EVENT = CACHE_FLUSH } 3330 event CACHE_FLUSH 33310122e290: 0000: c0004600 00000006 3332t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 3333 { EVENT = CACHE_FLUSH } 3334 event CACHE_FLUSH 33350122e298: 0000: c0004600 00000006 3336t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 3337 { EVENT = CACHE_FLUSH } 3338 event CACHE_FLUSH 33390122e2a0: 0000: c0004600 00000006 3340t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 3341 { EVENT = CACHE_FLUSH } 3342 event CACHE_FLUSH 33430122e2a8: 0000: c0004600 00000006 3344t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 3345 { EVENT = CACHE_FLUSH } 3346 event CACHE_FLUSH 33470122e2b0: 0000: c0004600 00000006 3348t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 3349 { EVENT = CACHE_FLUSH } 3350 event CACHE_FLUSH 33510122e2b8: 0000: c0004600 00000006 3352t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 3353 { EVENT = CACHE_FLUSH } 3354 event CACHE_FLUSH 33550122e2c0: 0000: c0004600 00000006 3356t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 3357 { EVENT = CACHE_FLUSH } 3358 event CACHE_FLUSH 33590122e2c8: 0000: c0004600 00000006 3360t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 3361 { EVENT = CACHE_FLUSH } 3362 event CACHE_FLUSH 33630122e2d0: 0000: c0004600 00000006 33640122d1d8: 0000: c0013700 0122e000 000000b6 3365t2 nop 3366############################################################ 3367vertices: 0 3368cmd: deqp-gles2/185: fence=1259 3369############################################################ 3370cmdstream: 340 dwords 3371t0 write RB_BC_CONTROL (0f01) 3372 RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 } 33730110a000: 0000: 00000f01 1c004046 3374t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3375 PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 } 33760110a008: 0000: c0012d00 00040293 00000020 3377t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3378 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 } 33790110a014: 0000: c0012d00 00040316 00000002 3380t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3381 VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 } 33820110a020: 0000: c0012d00 00040317 00000002 3383t0 write CP_PERFMON_CNTL (0444) 3384 CP_PERFMON_CNTL: 0 33850110a02c: 0000: 00000444 00000000 3386t0 write RBBM_PM_OVERRIDE1 (039c) 3387 RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE } 3388 RBBM_PM_OVERRIDE2: 0xfff 33890110a034: 0000: 0001039c ffffffff 00000fff 3390t0 write TP0_CHICKEN (0e1e) 3391 TP0_CHICKEN: 0x2 33920110a040: 0000: 00000e1e 00000002 3393t3 opcode: CP_INVALIDATE_STATE (3b) (2 dwords) 33940110a048: 0000: c0003b00 00007fff 3395t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3396 SQ_VS_CONST: { BASE = 32 | SIZE = 256 } 33970110a050: 0000: c0012d00 00040307 00100020 3398t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3399 SQ_PS_CONST: { BASE = 288 | SIZE = 224 } 34000110a05c: 0000: c0012d00 00040308 000e0120 3401t3 opcode: CP_SET_CONSTANT (2d) (4 dwords) 3402 VGT_MAX_VTX_INDX: 0xffffffff 3403 VGT_MIN_VTX_INDX: 0 34040110a068: 0000: c0022d00 00040100 ffffffff 00000000 3405t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3406 VGT_INDX_OFFSET: 0 34070110a078: 0000: c0012d00 00040102 00000000 3408t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3409 SQ_CONTEXT_MISC: { SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 } 34100110a084: 0000: c0012d00 00040181 00000004 3411t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3412 SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 } 34130110a090: 0000: c0012d00 00040182 ffffffff 3414t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3415 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 } 34160110a09c: 0000: c0012d00 00040301 00000000 3417t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3418 PA_SC_LINE_CNTL: { BRES_CNTL = 0 } 34190110a0a8: 0000: c0012d00 00040300 00000000 3420t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3421 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 } 34220110a0b4: 0000: c0012d00 00040080 00000000 3423t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3424 RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH } 34250110a0c0: 0000: c0012d00 00040208 00000004 3426t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3427 RB_SAMPLE_POS: 0x88888888 34280110a0cc: 0000: c0012d00 0004020a 88888888 3429t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3430 RB_COLOR_DEST_MASK: 0xffffffff 34310110a0d8: 0000: c0012d00 00040326 ffffffff 3432t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3433 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 34340110a0e4: 0000: c0012d00 0004031b 0003c000 3435t3 opcode: CP_SET_CONSTANT (2d) (4 dwords) 3436 SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 } 3437 SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 } 34380110a0f0: 0000: c0022d00 00040183 00000000 00000000 3439t3 opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords) 34400110a100: 0000: c0004b00 00000000 3441t3 opcode: CP_WAIT_REG_EQ (52) (5 dwords) 34420110a108: 0000: c0035200 000005d0 00000000 5f601000 00000001 3443t0 write SQ_INST_STORE_MANAGMENT (0d02) 3444 SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 } 34450110a11c: 0000: 00000d02 00000180 3446t3 opcode: CP_INVALIDATE_STATE (3b) (2 dwords) 34470110a124: 0000: c0003b00 00000300 3448t3 opcode: CP_SET_SHADER_BASES (4a) (2 dwords) 34490110a12c: 0000: c0004a00 80000180 3450t3 opcode: CP_SET_CONSTANT (2d) (14 dwords) 34510110a13c: 0.000000 0.000000 0.000000 0.000000 20000.000000 1.000000 0.500000 0.000000 34520110a15c: 2.000000 0.750000 0.375000 0.250000 34530110a134: 0000: c00c2d00 00000000 00000000 00000000 00000000 00000000 469c4000 3f800000 34540110a154: 0020: 3f000000 00000000 40000000 3f400000 3ec00000 3e800000 3455t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3456 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 34570110a16c: 0000: c0012d00 00040104 0000000f 3458t3 opcode: CP_SET_CONSTANT (2d) (6 dwords) 3459 RB_BLEND_RED: 0 3460 RB_BLEND_GREEN: 0 3461 RB_BLEND_BLUE: 0 3462 RB_BLEND_ALPHA: 0xff 34630110a178: 0000: c0042d00 00040105 00000000 00000000 00000000 000000ff 3464t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3465 PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT } 34660110a190: 0000: c0012d00 00040206 0000043f 3467t3 opcode: CP_SET_CONSTANT (2d) (5 dwords) 3468 RB_SURFACE_INFO: { SURFACE_PITCH = 128 | MSAA_SAMPLES = 0 } 3469 RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 1 | BASE = 0 } 3470 RB_DEPTH_INFO: { DEPTH_FORMAT = DEPTHX_24_8 | DEPTH_BASE = 65536 } 34710110a19c: 0000: c0032d00 00040000 00000080 00000205 00010001 3472t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3473 VGT_CURRENT_BIN_ID_MIN: { COLUMN = 0 | ROW = 0 | GUARD_BAND_MASK = 0 } 34740110a1b0: 0000: c0012d00 00040207 00000000 3475t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3476 VGT_CURRENT_BIN_ID_MAX: { COLUMN = 0 | ROW = 0 | GUARD_BAND_MASK = 0 } 34770110a1bc: 0000: c0012d00 00040203 00000000 3478t3 opcode: CP_SET_CONSTANT (2d) (6 dwords) 34790110a1d0: 3.069580 0.000000 8441856.000000 8454144.000000 34800110a1c8: 0000: c0042d00 0000000c 40447400 00000000 4b00d000 4b010000 3481t3 opcode: CP_SET_CONSTANT (2d) (10 dwords) 34820110a1e8: 0.125490 0.125490 0.500000 0.000000 0.000980 0.000980 0.000000 0.000000 34830110a1e0: 0000: c0082d00 0000018c 3e008081 3e008081 3f000000 00000000 3a808081 3a808081 3484* 3485t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3486 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 0 } 34870110a208: 0000: c0012d00 00040316 00000000 3488t0 write CP_SCRATCH_REG6 (057e) 3489 CP_SCRATCH_REG6: 67 3490 :0,0,67,54 34910110a214: 0000: 0000057e 00000043 3492t3 opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords) 3493 ibaddr:0110c000 3494 ibsize:000000c5 3495t3 opcode: CP_SET_CONSTANT (2d) (6 dwords) 3496 set shader const 0078 34970110c000: 0000: c0042d00 00010078 0112d483 00100000 0112d4c3 00100000 3498t3 opcode: CP_IM_LOAD_IMMEDIATE (2b) (102 dwords) 3499 vertex shader, start=0000, size=0063 3500 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0) 3501 100b 0003 1000 EXEC ADDR(0xb) CNT(0x1) 3502 0b: 19480000 00262688 00000010 (S)FETCH: VERTEX R0.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(16) CONST(20, 0) 3503 400c 0002 1000 EXEC ADDR(0xc) CNT(0x4) 3504 0c: 00010001 00036c00 82000000 (S)ALU: MAXv R1.x___ = R0.wyzw, C0.xxxx 3505 0d: 4c110302 0000006c 60400201 ALU: ADDv R2.x___ = C0, R2 3506 RECIP_IEEE R3.x___ = R1.xxxx 3507 0e: 000f0004 00006c00 c1000300 ALU: MULv R4 = R0, R3.xxxx 3508 0f: 000f0005 00000000 4b420441 ALU: MULADDv R5 = C1, C2, R4 3509 0000 0000 c200 ALLOC POSITION SIZE(0x0) 3510 1010 0000 1000 EXEC ADDR(0x10) CNT(0x1) 3511 10: 000f803e 00000000 c2000000 ALU: MAXv export62 = R0, R0 ; gl_Position 3512 0000 0000 c600 ALLOC MEMORY SIZE(0x0) 3513 2011 0000 2000 EXEC_END ADDR(0x11) CNT(0x2) 3514 11: 000f8020 20136c00 4b010203 ALU: MULADDv export32 = C3, C1.wyww, R2.xxxx 3515 12: 000f8021 00000000 4b440543 ALU: MULADDv export33 = C3, C4, R5 3516 0000 0000 c600 ALLOC MEMORY SIZE(0x0) 3517 2013 0000 1000 EXEC ADDR(0x13) CNT(0x2) 3518 13: 000f8020 20136c00 4b010204 ALU: MULADDv export32 = C4, C1.wyww, R2.xxxx 3519 14: 000f8021 00000000 4b460545 ALU: MULADDv export33 = C5, C6, R5 3520 0000 0000 c600 ALLOC MEMORY SIZE(0x0) 3521 2015 0000 1000 EXEC ADDR(0x15) CNT(0x2) 3522 15: 000f8020 20136c00 4b010205 ALU: MULADDv export32 = C5, C1.wyww, R2.xxxx 3523 16: 000f8021 00000000 4b480547 ALU: MULADDv export33 = C7, C8, R5 3524 0000 0000 c600 ALLOC MEMORY SIZE(0x0) 3525 2017 0000 1000 EXEC ADDR(0x17) CNT(0x2) 3526 17: 000f8020 20136c00 4b010206 ALU: MULADDv export32 = C6, C1.wyww, R2.xxxx 3527 18: 000f8021 00000000 4b4a0549 ALU: MULADDv export33 = C9, C10, R5 3528 0000 0000 c600 ALLOC MEMORY SIZE(0x0) 3529 2019 0000 1000 EXEC ADDR(0x19) CNT(0x2) 3530 19: 000f8020 20136c00 4b010207 ALU: MULADDv export32 = C7, C1.wyww, R2.xxxx 3531 1a: 000f8021 00000000 4b4c054b ALU: MULADDv export33 = C11, C12, R5 3532 0000 0000 c600 ALLOC MEMORY SIZE(0x0) 3533 201b 0000 1000 EXEC ADDR(0x1b) CNT(0x2) 3534 1b: 000f8020 20136c00 4b010208 ALU: MULADDv export32 = C8, C1.wyww, R2.xxxx 3535 1c: 000f8021 00000000 4b4e054d ALU: MULADDv export33 = C13, C14, R5 3536 0000 0000 c600 ALLOC MEMORY SIZE(0x0) 3537 201d 0000 1000 EXEC ADDR(0x1d) CNT(0x2) 3538 1d: 000f8020 20136c00 4b010209 ALU: MULADDv export32 = C9, C1.wyww, R2.xxxx 3539 1e: 000f8021 00000000 4b50054f ALU: MULADDv export33 = C15, C16, R5 3540 0000 0000 c600 ALLOC MEMORY SIZE(0x0) 3541 201f 0000 2000 EXEC_END ADDR(0x1f) CNT(0x2) 3542 1f: 000f8020 20136c00 4b01020a ALU: MULADDv export32 = C10, C1.wyww, R2.xxxx 3543 20: 000f8021 00000000 4b520551 ALU: MULADDv export33 = C17, C18, R5 3544 0000 0000 0000 NOP 35450110c018: 0000: c0642b00 00000000 00000063 00000000 100bc400 10000003 0002400c 00001000 35460110c038: 0020: c2000000 00001010 00001000 c6000000 00002011 00002000 c6000000 00002013 35470110c058: 0040: 00001000 c6000000 00002015 00001000 c6000000 00002017 00001000 c6000000 35480110c078: 0060: 00002019 00001000 c6000000 0000201b 00001000 c6000000 0000201d 00001000 35490110c098: 0080: c6000000 0000201f 00002000 00000000 19480000 00262688 00000010 00010001 35500110c0b8: 00a0: 00036c00 82000000 4c110302 0000006c 60400201 000f0004 00006c00 c1000300 35510110c0d8: 00c0: 000f0005 00000000 4b420441 000f803e 00000000 c2000000 000f8020 20136c00 35520110c0f8: 00e0: 4b010203 000f8021 00000000 4b440543 000f8020 20136c00 4b010204 000f8021 35530110c118: 0100: 00000000 4b460545 000f8020 20136c00 4b010205 000f8021 00000000 4b480547 35540110c138: 0120: 000f8020 20136c00 4b010206 000f8021 00000000 4b4a0549 000f8020 20136c00 35550110c158: 0140: 4b010207 000f8021 00000000 4b4c054b 000f8020 20136c00 4b010208 000f8021 35560110c178: 0160: 00000000 4b4e054d 000f8020 20136c00 4b010209 000f8021 00000000 4b50054f 35570110c198: 0180: 000f8020 20136c00 4b01020a 000f8021 00000000 4b520551 3558t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3559 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 } 35600110c1b0: 0000: c0012d00 00040181 00000006 3561t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3562 SQ_PROGRAM_CNTL: { VS_REGS = 5 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 | GEN_INDEX_VTX } 35630110c1bc: 0000: c0012d00 00040180 90030005 3564t3 opcode: CP_SET_CONSTANT (2d) (6 dwords) 35650110c1d0: 0.000000 0.000000 0.000000 0.000000 35660110c1c8: 0000: c0042d00 00000080 00000000 00000000 00000000 00000000 3567t3 opcode: CP_SET_CONSTANT (2d) (10 dwords) 35680110c1e8: 128.000000 128.000000 0.500000 0.000000 128.000000 -128.000000 0.500000 0.000000 35690110c1e0: 0000: c0082d00 00000184 43000000 43000000 3f000000 00000000 43000000 c3000000 35700110c200: 0020: 3f000000 00000000 3571t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3572 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO } 35730110c208: 0000: c0012d00 00040201 00000000 3574t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3575 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 35760110c214: 0000: c0012d00 00040104 0000000f 3577t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3578 PA_SU_SC_MODE_CNTL: { POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_POINTS | BACK_PTYPE = PC_DRAW_POINTS | FACE_KILL_ENABLE } 35790110c220: 0000: c0012d00 00040205 40000000 3580t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3581 VGT_INDX_OFFSET: 0 35820110c22c: 0000: c0012d00 00040102 00000000 3583t0 write TC_CNTL_STATUS (0e00) 3584 TC_CNTL_STATUS: { L2_INVALIDATE } 35850110c238: 0000: 00000e00 00000001 3586t3 opcode: CP_WAIT_REG_EQ (52) (5 dwords) 35870110c240: 0000: c0035200 000005d0 00000000 00001000 00000001 3588t3 opcode: CP_DRAW_INDX_BIN (34) (7 dwords) 35890110c254: 0000: c0053400 00000000 0003c004 00000000 00000003 01009040 00000006 3590t3 opcode: CP_SET_CONSTANT (2d) (6 dwords) 35910110c278: 0.000000 0.000000 0.000000 0.000000 35920110c270: 0000: c0042d00 00000180 00000000 00000000 00000000 00000000 3593t0 write CP_SCRATCH_REG7 (057f) 3594 CP_SCRATCH_REG7: 61 3595 :0,0,67,61 35960110c288: 0000: 0000057f 0000003d 3597t3 opcode: CP_DRAW_INDX (22) (5 dwords) 3598 { VIZ_QUERY = 0 } 3599 { PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_DMA | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | NUM_INSTANCES = 0 | 0x60000 } 3600 { NUM_INDICES = 18011360 } 3601 { INDX_BASE = 0xc } 3602 draw: 0 3603 prim_type: DI_PT_TRILIST (4) 3604 source_select: DI_SRC_SEL_DMA (0) 3605 num_indices: 18011360 3606 draw[9] register values 3607 + ffffffff RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE } 3608 + 00000fff RBBM_PM_OVERRIDE2: 0xfff 3609 + 00000000 CP_PERFMON_CNTL: 0 3610!+ 00000043 CP_SCRATCH_REG6: 67 3611 :0,0,67,61 3612!+ 0000003d CP_SCRATCH_REG7: 61 3613 :0,0,67,61 3614 + 00000180 SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 } 3615 + 00000001 TC_CNTL_STATUS: { L2_INVALIDATE } 3616 + 00000002 TP0_CHICKEN: 0x2 3617 + 1c004046 RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 } 3618!+ 00000080 RB_SURFACE_INFO: { SURFACE_PITCH = 128 | MSAA_SAMPLES = 0 } 3619!+ 00000205 RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 1 | BASE = 0 } 3620!+ 00010001 RB_DEPTH_INFO: { DEPTH_FORMAT = DEPTHX_24_8 | DEPTH_BASE = 65536 } 3621 + 00000000 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 } 3622 + ffffffff VGT_MAX_VTX_INDX: 0xffffffff 3623 + 00000000 VGT_MIN_VTX_INDX: 0 3624 + 00000000 VGT_INDX_OFFSET: 0 3625 + 0000000f RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 3626 + 00000000 RB_BLEND_RED: 0 3627 + 00000000 RB_BLEND_GREEN: 0 3628 + 00000000 RB_BLEND_BLUE: 0 3629!+ 000000ff RB_BLEND_ALPHA: 0xff 3630!+ 90030005 SQ_PROGRAM_CNTL: { VS_REGS = 5 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 | GEN_INDEX_VTX } 3631!+ 00000006 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 } 3632 + ffffffff SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 } 3633 + 00000000 SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 } 3634 + 00000000 SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 } 3635 + 00000000 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO } 3636 + 00000000 VGT_CURRENT_BIN_ID_MAX: { COLUMN = 0 | ROW = 0 | GUARD_BAND_MASK = 0 } 3637!+ 40000000 PA_SU_SC_MODE_CNTL: { POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_POINTS | BACK_PTYPE = PC_DRAW_POINTS | FACE_KILL_ENABLE } 3638 + 0000043f PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT } 3639 + 00000000 VGT_CURRENT_BIN_ID_MIN: { COLUMN = 0 | ROW = 0 | GUARD_BAND_MASK = 0 } 3640 + 00000004 RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH } 3641 + 88888888 RB_SAMPLE_POS: 0x88888888 3642 + 00000020 PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 } 3643 + 00000000 PA_SC_LINE_CNTL: { BRES_CNTL = 0 } 3644 + 00000000 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 } 3645 + 00100020 SQ_VS_CONST: { BASE = 32 | SIZE = 256 } 3646 + 000e0120 SQ_PS_CONST: { BASE = 288 | SIZE = 224 } 3647!+ 00000000 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 0 } 3648 + 00000002 VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 } 3649 + 0003c000 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 3650 + ffffffff RB_COLOR_DEST_MASK: 0xffffffff 36510110c290: 0000: c0032200 00000000 00060004 0112d4e0 0000000c 3652t0 write CP_SCRATCH_REG7 (057f) 3653NEEDS WFI: CP_SCRATCH_REG7 (57f) 3654 CP_SCRATCH_REG7: 62 3655 :0,0,67,62 36560110c2a4: 0000: 0000057f 0000003e 3657t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 36580110c2ac: 0000: c0002600 00000000 3659t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 3660 { EVENT = CACHE_FLUSH } 3661 event CACHE_FLUSH 36620110c2b4: 0000: c0004600 00000006 3663t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 3664 { EVENT = CACHE_FLUSH } 3665 event CACHE_FLUSH 36660110c2bc: 0000: c0004600 00000006 3667t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 3668 { EVENT = CACHE_FLUSH } 3669 event CACHE_FLUSH 36700110c2c4: 0000: c0004600 00000006 3671t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 3672 { EVENT = CACHE_FLUSH } 3673 event CACHE_FLUSH 36740110c2cc: 0000: c0004600 00000006 3675t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 3676 { EVENT = CACHE_FLUSH } 3677 event CACHE_FLUSH 36780110c2d4: 0000: c0004600 00000006 3679t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 3680 { EVENT = CACHE_FLUSH } 3681 event CACHE_FLUSH 36820110c2dc: 0000: c0004600 00000006 3683t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 3684 { EVENT = CACHE_FLUSH } 3685 event CACHE_FLUSH 36860110c2e4: 0000: c0004600 00000006 3687t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 3688 { EVENT = CACHE_FLUSH } 3689 event CACHE_FLUSH 36900110c2ec: 0000: c0004600 00000006 3691t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 3692 { EVENT = CACHE_FLUSH } 3693 event CACHE_FLUSH 36940110c2f4: 0000: c0004600 00000006 3695t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 3696 { EVENT = CACHE_FLUSH } 3697 event CACHE_FLUSH 36980110c2fc: 0000: c0004600 00000006 3699t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 3700 { EVENT = CACHE_FLUSH } 3701 event CACHE_FLUSH 37020110c304: 0000: c0004600 00000006 3703t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 3704 { EVENT = CACHE_FLUSH } 3705 event CACHE_FLUSH 37060110c30c: 0000: c0004600 00000006 37070110a21c: 0000: c0013700 0110c000 000000c5 3708t2 nop 3709t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3710 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 } 37110110a234: 0000: c0012d00 00040316 00000002 3712t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3713 RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 1 | BASE = 0 } 37140110a240: 0000: c0012d00 00040001 00000205 3715t3 opcode: CP_SET_CONSTANT (2d) (4 dwords) 3716 PA_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } 3717 PA_SC_SCREEN_SCISSOR_BR: { X = 128 | Y = 128 } 37180110a24c: 0000: c0022d00 0004000e 00000000 00800080 3719t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3720 RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 1 | BASE = 0 } 37210110a25c: 0000: c0012d00 00040001 00000205 3722t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3723 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 } 37240110a268: 0000: c0012d00 00040080 00000000 3725t3 opcode: CP_MEM_WRITE (3d) (3 dwords) 3726 { ADDR_LO = 0x100903c } 3727 { ADDR_HI = 0x800080 } 3728 gpuaddr:0100903c 37290110a27c: 0.000000 37300110a274: 0000: c0013d00 0100903c 00800080 3731t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3732 RB_COPY_DEST_OFFSET: { X = 0 | Y = 0 } 37330110a280: 0000: c0012d00 0004031c 00000000 3734t3 opcode: CP_SET_CONSTANT (2d) (6 dwords) 37350110a294: 0.000000 0.000000 0.000000 0.000000 37360110a28c: 0000: c0042d00 00000580 00000000 00000000 00000000 00000000 3737t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3738 VGT_CURRENT_BIN_ID_MIN: { COLUMN = 1 | ROW = 1 | GUARD_BAND_MASK = 0 } 37390110a2a4: 0000: c0012d00 00040207 00000009 3740t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3741 VGT_CURRENT_BIN_ID_MAX: { COLUMN = 1 | ROW = 1 | GUARD_BAND_MASK = 0 } 37420110a2b0: 0000: c0012d00 00040203 00000009 3743t3 opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords) 37440110a2bc: 0000: c0004b00 0111d000 3745t0 write CP_SCRATCH_REG6 (057e) 3746 CP_SCRATCH_REG6: 69 3747 :0,0,69,62 37480110a2c4: 0000: 0000057e 00000045 3749t3 opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords) 3750 ibaddr:0110b000 3751 ibsize:00000198 3752t3 opcode: CP_SET_CONSTANT (2d) (4 dwords) 3753 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 3754 PA_SC_WINDOW_SCISSOR_BR: { X = 16383 | Y = 16383 } 37550110b000: 0000: c0022d00 00040081 00000000 3fff3fff 3756t3 opcode: CP_SET_CONSTANT (2d) (6 dwords) 3757 PA_CL_VPORT_XSCALE: 4096.000000 3758 PA_CL_VPORT_XOFFSET: 4096.000000 3759 PA_CL_VPORT_YSCALE: 4096.000000 3760 PA_CL_VPORT_YOFFSET: 4096.000000 37610110b010: 0000: c0042d00 0004010f 45800000 45800000 45800000 45800000 3762t3 opcode: CP_SET_CONSTANT (2d) (4 dwords) 3763 set shader const 009c 37640110b028: 0000: c0022d00 0001009c 01009003 00000024 3765t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3766 VGT_INDX_OFFSET: 0 37670110b038: 0000: c0012d00 00040102 00000000 3768t3 opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords) 3769 vertex shader, start=0000, size=000c 3770 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0) 3771 1002 0003 1000 EXEC ADDR(0x2) CNT(0x1) 3772 02: 19a80000 00392a88 0000000c (S)FETCH: VERTEX R0.xyz1 = R0.x FMT_32_32_32_FLOAT UNSIGNED STRIDE(12) CONST(26, 0) 3773 0000 0000 c200 ALLOC POSITION SIZE(0x0) 3774 1003 0002 2000 EXEC_END ADDR(0x3) CNT(0x1) 3775 03: 000f803e 00000000 c2000000 (S)ALU: MAXv export62 = R0, R0 ; gl_Position 37760110b044: 0000: c00d2b00 00000000 0000000c 00000000 1002c400 10000003 00000000 1003c200 37770110b064: 0020: 20000002 19a80000 00392a88 0000000c 000f803e 00000000 c2000000 3778t3 opcode: CP_IM_LOAD_IMMEDIATE (2b) (9 dwords) 3779 fragment shader, start=0000, size=0006 3780 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0) 3781 1001 0002 2000 EXEC_END ADDR(0x1) CNT(0x1) 3782 01: 000f8000 00000000 02000000 (S)ALU: MAXv export0 = C0, C0 ; gl_FragColor 37830110b080: 0000: c0072b00 00000001 00000006 00000000 1001c400 20000002 000f8000 00000000 37840110b0a0: 0020: 02000000 3785t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3786 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 } 37870110b0a4: 0000: c0012d00 00040181 00000006 3788t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3789 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 128 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 } 37900110b0b0: 0000: c0012d00 00040180 10038002 3791t0 write TC_CNTL_STATUS (0e00) 3792 TC_CNTL_STATUS: { L2_INVALIDATE } 37930110b0bc: 0000: 00000e00 00000001 3794t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3795 RB_DEPTHCONTROL: { STENCIL_ENABLE | Z_ENABLE | Z_WRITE_ENABLE | EARLY_Z_ENABLE | ZFUNC = FUNC_ALWAYS | STENCILFUNC = FUNC_ALWAYS | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_REPLACE | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP } 37960110b0c4: 0000: c0012d00 00040200 0000877f 3797t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3798 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_ALWAYS | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 } 37990110b0d0: 0000: c0012d00 00040202 00000c27 3800t3 opcode: CP_SET_CONSTANT (2d) (4 dwords) 3801 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL } 3802 PA_SU_SC_MODE_CNTL: { POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | MSAA_ENABLE | PROVOKING_VTX_LAST } 38030110b0dc: 0000: c0022d00 00040204 00000000 00088240 3804t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3805 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 3 | MAX_SAMPLE_DIST = 0 } 38060110b0ec: 0000: c0012d00 00040301 00000003 3807t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3808 PA_SC_AA_MASK: 0xffff 38090110b0f8: 0000: c0012d00 00040312 0000ffff 3810t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3811 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 38120110b104: 0000: c0012d00 00040104 0000000f 3813t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3814 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO } 38150110b110: 0000: c0012d00 00040201 00000000 3816t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3817 PA_SC_SCREEN_SCISSOR_BR: { X = 32 | Y = 64 } 38180110b11c: 0000: c0012d00 0004000f 00400020 3819t3 opcode: CP_SET_CONSTANT (2d) (5 dwords) 3820 RB_SURFACE_INFO: { SURFACE_PITCH = 32 | MSAA_SAMPLES = 2 } 3821 RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 0 | BASE = 0 } 3822 RB_DEPTH_INFO: { DEPTH_FORMAT = DEPTHX_24_8 | DEPTH_BASE = 32768 } 38230110b128: 0000: c0032d00 00040000 00008020 00000005 00008001 3824t3 opcode: CP_SET_CONSTANT (2d) (6 dwords) 38250110b144: 0.501961 0.250980 0.125490 1.000000 38260110b13c: 0000: c0042d00 00000480 3f008081 3e808081 3e008081 3f800000 3827t3 opcode: CP_SET_CONSTANT (2d) (4 dwords) 3828 PA_CL_VPORT_ZSCALE: 0.000000 3829 PA_CL_VPORT_ZOFFSET: 0.996586 38300110b154: 0000: c0022d00 00040113 00000000 3f7f2041 3831t3 opcode: CP_SET_CONSTANT (2d) (4 dwords) 3832 RB_STENCILREFMASK_BF: { STENCILREF = 0x80 | STENCILMASK = 0 | STENCILWRITEMASK = 0xff | 0xff000000 } 3833 RB_STENCILREFMASK: { STENCILREF = 0x80 | STENCILMASK = 0 | STENCILWRITEMASK = 0xff | 0xff000000 } 38340110b164: 0000: c0022d00 0004010c ffff0080 ffff0080 3835t0 write CP_SCRATCH_REG7 (057f) 3836 CP_SCRATCH_REG7: 1 3837 :0,0,69,1 38380110b174: 0000: 0000057f 00000001 3839t3 opcode: CP_DRAW_INDX (22) (3 dwords) 3840 { VIZ_QUERY = 0 } 3841 { PRIM_TYPE = DI_PT_RECTLIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | NUM_INSTANCES = 0 | 0x30000 } 3842 draw: 0 3843 prim_type: DI_PT_RECTLIST (8) 3844 source_select: DI_SRC_SEL_AUTO_INDEX (2) 3845 num_indices: 1407 3846 draw[10] register values 3847!+ 00000045 CP_SCRATCH_REG6: 69 3848 :0,0,69,1 3849!+ 00000001 CP_SCRATCH_REG7: 1 3850 :0,0,69,1 3851 + 00000001 TC_CNTL_STATUS: { L2_INVALIDATE } 3852!+ 00008020 RB_SURFACE_INFO: { SURFACE_PITCH = 32 | MSAA_SAMPLES = 2 } 3853!+ 00000005 RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 0 | BASE = 0 } 3854!+ 00008001 RB_DEPTH_INFO: { DEPTH_FORMAT = DEPTHX_24_8 | DEPTH_BASE = 32768 } 3855!+ 00000000 PA_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } 3856!+ 00400020 PA_SC_SCREEN_SCISSOR_BR: { X = 32 | Y = 64 } 3857 + 00000000 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 } 3858 + 00000000 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 3859!+ 3fff3fff PA_SC_WINDOW_SCISSOR_BR: { X = 16383 | Y = 16383 } 3860 + 00000000 VGT_INDX_OFFSET: 0 3861 + 0000000f RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 3862!+ ffff0080 RB_STENCILREFMASK_BF: { STENCILREF = 0x80 | STENCILMASK = 0 | STENCILWRITEMASK = 0xff | 0xff000000 } 3863!+ ffff0080 RB_STENCILREFMASK: { STENCILREF = 0x80 | STENCILMASK = 0 | STENCILWRITEMASK = 0xff | 0xff000000 } 3864!+ 45800000 PA_CL_VPORT_XSCALE: 4096.000000 3865!+ 45800000 PA_CL_VPORT_XOFFSET: 4096.000000 3866!+ 45800000 PA_CL_VPORT_YSCALE: 4096.000000 3867!+ 45800000 PA_CL_VPORT_YOFFSET: 4096.000000 3868 + 00000000 PA_CL_VPORT_ZSCALE: 0.000000 3869!+ 3f7f2041 PA_CL_VPORT_ZOFFSET: 0.996586 3870!+ 10038002 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 128 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 } 3871 + 00000006 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 } 3872!+ 0000877f RB_DEPTHCONTROL: { STENCIL_ENABLE | Z_ENABLE | Z_WRITE_ENABLE | EARLY_Z_ENABLE | ZFUNC = FUNC_ALWAYS | STENCILFUNC = FUNC_ALWAYS | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_REPLACE | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP } 3873 + 00000000 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO } 3874!+ 00000c27 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_ALWAYS | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 } 3875!+ 00000009 VGT_CURRENT_BIN_ID_MAX: { COLUMN = 1 | ROW = 1 | GUARD_BAND_MASK = 0 } 3876 + 00000000 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL } 3877!+ 00088240 PA_SU_SC_MODE_CNTL: { POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | MSAA_ENABLE | PROVOKING_VTX_LAST } 3878!+ 00000009 VGT_CURRENT_BIN_ID_MIN: { COLUMN = 1 | ROW = 1 | GUARD_BAND_MASK = 0 } 3879!+ 00000003 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 3 | MAX_SAMPLE_DIST = 0 } 3880 + 0000ffff PA_SC_AA_MASK: 0xffff 3881!+ 00000002 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 } 3882 + 00000000 RB_COPY_DEST_OFFSET: { X = 0 | Y = 0 } 38830110b17c: 0000: c0012200 00000000 00030088 3884t0 write CP_SCRATCH_REG7 (057f) 3885NEEDS WFI: CP_SCRATCH_REG7 (57f) 3886 CP_SCRATCH_REG7: 2 3887 :0,0,69,2 38880110b188: 0000: 0000057f 00000002 3889t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3890 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 } 38910110b190: 0000: c0012d00 00040301 00000000 3892t3 opcode: CP_LOAD_CONSTANT_CONTEXT (2e) (4 dwords) 38930110b19c: 0000: c0022e00 01009000 0004000f 00000001 3894t3 opcode: CP_SET_CONSTANT (2d) (5 dwords) 3895 RB_SURFACE_INFO: { SURFACE_PITCH = 128 | MSAA_SAMPLES = 0 } 3896 RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 1 | BASE = 0 } 3897 RB_DEPTH_INFO: { DEPTH_FORMAT = DEPTHX_24_8 | DEPTH_BASE = 65536 } 38980110b1ac: 0000: c0032d00 00040000 00000080 00000205 00010001 3899t3 opcode: CP_SET_CONSTANT (2d) (4 dwords) 3900 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 3901 PA_SC_WINDOW_SCISSOR_BR: { X = 16383 | Y = 16383 } 39020110b1c0: 0000: c0022d00 00040081 00000000 3fff3fff 3903t3 opcode: CP_SET_CONSTANT (2d) (6 dwords) 3904 PA_CL_VPORT_XSCALE: 4096.000000 3905 PA_CL_VPORT_XOFFSET: 4096.000000 3906 PA_CL_VPORT_YSCALE: 4096.000000 3907 PA_CL_VPORT_YOFFSET: 4096.000000 39080110b1d0: 0000: c0042d00 0004010f 45800000 45800000 45800000 45800000 3909t3 opcode: CP_SET_CONSTANT (2d) (4 dwords) 3910 set shader const 009c 39110110b1e8: 0000: c0022d00 0001009c 01009003 00000024 3912t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3913 VGT_INDX_OFFSET: 0 39140110b1f8: 0000: c0012d00 00040102 00000000 3915t3 opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords) 3916 vertex shader, start=0000, size=000c 3917 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0) 3918 1002 0003 1000 EXEC ADDR(0x2) CNT(0x1) 3919 02: 19a80000 00392a88 0000000c (S)FETCH: VERTEX R0.xyz1 = R0.x FMT_32_32_32_FLOAT UNSIGNED STRIDE(12) CONST(26, 0) 3920 0000 0000 c200 ALLOC POSITION SIZE(0x0) 3921 1003 0002 2000 EXEC_END ADDR(0x3) CNT(0x1) 3922 03: 000f803e 00000000 c2000000 (S)ALU: MAXv export62 = R0, R0 ; gl_Position 39230110b204: 0000: c00d2b00 00000000 0000000c 00000000 1002c400 10000003 00000000 1003c200 39240110b224: 0020: 20000002 19a80000 00392a88 0000000c 000f803e 00000000 c2000000 3925t3 opcode: CP_IM_LOAD_IMMEDIATE (2b) (9 dwords) 3926 fragment shader, start=0000, size=0006 3927 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0) 3928 1001 0002 2000 EXEC_END ADDR(0x1) CNT(0x1) 3929 01: 000f8000 00000000 02000000 (S)ALU: MAXv export0 = C0, C0 ; gl_FragColor 39300110b240: 0000: c0072b00 00000001 00000006 00000000 1001c400 20000002 000f8000 00000000 39310110b260: 0020: 02000000 3932t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3933 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 } 39340110b264: 0000: c0012d00 00040181 00000006 3935t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3936 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 128 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 } 39370110b270: 0000: c0012d00 00040180 10038002 3938t0 write TC_CNTL_STATUS (0e00) 3939NEEDS WFI: TC_CNTL_STATUS (e00) 3940 TC_CNTL_STATUS: { L2_INVALIDATE } 39410110b27c: 0000: 00000e00 00000001 3942t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3943 RB_DEPTHCONTROL: { STENCIL_ENABLE | Z_ENABLE | Z_WRITE_ENABLE | EARLY_Z_ENABLE | ZFUNC = FUNC_ALWAYS | STENCILFUNC = FUNC_ALWAYS | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_REPLACE | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP } 39440110b284: 0000: c0012d00 00040200 0000877f 3945t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3946 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_ALWAYS | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 } 39470110b290: 0000: c0012d00 00040202 00000c27 3948t3 opcode: CP_SET_CONSTANT (2d) (4 dwords) 3949 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL } 3950 PA_SU_SC_MODE_CNTL: { POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | MSAA_ENABLE | PROVOKING_VTX_LAST } 39510110b29c: 0000: c0022d00 00040204 00000000 00088240 3952t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3953 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 3 | MAX_SAMPLE_DIST = 0 } 39540110b2ac: 0000: c0012d00 00040301 00000003 3955t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3956 PA_SC_AA_MASK: 0xffff 39570110b2b8: 0000: c0012d00 00040312 0000ffff 3958t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3959 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 39600110b2c4: 0000: c0012d00 00040104 0000000f 3961t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3962 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO } 39630110b2d0: 0000: c0012d00 00040201 00000000 3964t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 3965 PA_SC_SCREEN_SCISSOR_BR: { X = 32 | Y = 128 } 39660110b2dc: 0000: c0012d00 0004000f 00800020 3967t3 opcode: CP_SET_CONSTANT (2d) (5 dwords) 3968 RB_SURFACE_INFO: { SURFACE_PITCH = 32 | MSAA_SAMPLES = 2 } 3969 RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 0 | BASE = 0 } 3970 RB_DEPTH_INFO: { DEPTH_FORMAT = DEPTHX_24_8 | DEPTH_BASE = 65536 } 39710110b2e8: 0000: c0032d00 00040000 00008020 00000005 00010001 3972t3 opcode: CP_SET_CONSTANT (2d) (6 dwords) 39730110b304: 0.501961 0.250980 0.125490 1.000000 39740110b2fc: 0000: c0042d00 00000480 3f008081 3e808081 3e008081 3f800000 3975t3 opcode: CP_SET_CONSTANT (2d) (4 dwords) 3976 PA_CL_VPORT_ZSCALE: 0.000000 3977 PA_CL_VPORT_ZOFFSET: 1.000000 39780110b314: 0000: c0022d00 00040113 00000000 3f800000 3979t3 opcode: CP_SET_CONSTANT (2d) (4 dwords) 3980 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0xff | 0xff000000 } 3981 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0xff | 0xff000000 } 39820110b324: 0000: c0022d00 0004010c ffff0000 ffff0000 3983t0 write CP_SCRATCH_REG7 (057f) 3984NEEDS WFI: CP_SCRATCH_REG7 (57f) 3985 CP_SCRATCH_REG7: 3 3986 :0,0,69,3 39870110b334: 0000: 0000057f 00000003 3988t3 opcode: CP_DRAW_INDX (22) (3 dwords) 3989 { VIZ_QUERY = 0 } 3990 { PRIM_TYPE = DI_PT_RECTLIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | NUM_INSTANCES = 0 | 0x30000 } 3991 draw: 1 3992 prim_type: DI_PT_RECTLIST (8) 3993 source_select: DI_SRC_SEL_AUTO_INDEX (2) 3994 num_indices: 1407 3995 draw[11] register values 3996!+ 00000003 CP_SCRATCH_REG7: 3 3997 :0,0,69,3 3998 + 00000001 TC_CNTL_STATUS: { L2_INVALIDATE } 3999 + 00008020 RB_SURFACE_INFO: { SURFACE_PITCH = 32 | MSAA_SAMPLES = 2 } 4000 + 00000005 RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 0 | BASE = 0 } 4001!+ 00010001 RB_DEPTH_INFO: { DEPTH_FORMAT = DEPTHX_24_8 | DEPTH_BASE = 65536 } 4002!+ 00800020 PA_SC_SCREEN_SCISSOR_BR: { X = 32 | Y = 128 } 4003 + 00000000 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 4004 + 3fff3fff PA_SC_WINDOW_SCISSOR_BR: { X = 16383 | Y = 16383 } 4005 + 00000000 VGT_INDX_OFFSET: 0 4006 + 0000000f RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 4007!+ ffff0000 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0xff | 0xff000000 } 4008!+ ffff0000 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0xff | 0xff000000 } 4009 + 45800000 PA_CL_VPORT_XSCALE: 4096.000000 4010 + 45800000 PA_CL_VPORT_XOFFSET: 4096.000000 4011 + 45800000 PA_CL_VPORT_YSCALE: 4096.000000 4012 + 45800000 PA_CL_VPORT_YOFFSET: 4096.000000 4013 + 00000000 PA_CL_VPORT_ZSCALE: 0.000000 4014!+ 3f800000 PA_CL_VPORT_ZOFFSET: 1.000000 4015 + 10038002 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 128 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 } 4016 + 00000006 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 } 4017 + 0000877f RB_DEPTHCONTROL: { STENCIL_ENABLE | Z_ENABLE | Z_WRITE_ENABLE | EARLY_Z_ENABLE | ZFUNC = FUNC_ALWAYS | STENCILFUNC = FUNC_ALWAYS | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_REPLACE | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP } 4018 + 00000000 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO } 4019 + 00000c27 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_ALWAYS | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 } 4020 + 00000000 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL } 4021 + 00088240 PA_SU_SC_MODE_CNTL: { POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | MSAA_ENABLE | PROVOKING_VTX_LAST } 4022 + 00000003 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 3 | MAX_SAMPLE_DIST = 0 } 4023 + 0000ffff PA_SC_AA_MASK: 0xffff 40240110b33c: 0000: c0012200 00000000 00030088 4025t0 write CP_SCRATCH_REG7 (057f) 4026NEEDS WFI: CP_SCRATCH_REG7 (57f) 4027 CP_SCRATCH_REG7: 4 4028 :0,0,69,4 40290110b348: 0000: 0000057f 00000004 4030t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4031 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 } 40320110b350: 0000: c0012d00 00040301 00000000 4033t3 opcode: CP_LOAD_CONSTANT_CONTEXT (2e) (4 dwords) 40340110b35c: 0000: c0022e00 01009000 0004000f 00000001 4035t3 opcode: CP_SET_CONSTANT (2d) (5 dwords) 4036 RB_SURFACE_INFO: { SURFACE_PITCH = 128 | MSAA_SAMPLES = 0 } 4037 RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 1 | BASE = 0 } 4038 RB_DEPTH_INFO: { DEPTH_FORMAT = DEPTHX_24_8 | DEPTH_BASE = 65536 } 40390110b36c: 0000: c0032d00 00040000 00000080 00000205 00010001 4040t3 opcode: CP_SET_CONSTANT (2d) (6 dwords) 4041 set shader const 0078 40420110b380: 0000: c0042d00 00010078 0112d483 00100000 0112d4c3 00100000 4043t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4044 PA_SC_AA_MASK: 0xffff 40450110b398: 0000: c0012d00 00040312 0000ffff 4046t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4047 RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP } 40480110b3a4: 0000: c0012d00 00040200 00000000 4049t3 opcode: CP_SET_CONSTANT (2d) (5 dwords) 4050 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 4051 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 4052 RB_ALPHA_REF: 0 40530110b3b0: 0000: c0032d00 0004010c 00000000 00000000 00000000 4054t3 opcode: CP_SET_CONSTANT (2d) (4 dwords) 4055 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL } 4056 PA_SU_SC_MODE_CNTL: { POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST } 40570110b3c4: 0000: c0022d00 00040204 00000000 00090240 4058t3 opcode: CP_SET_CONSTANT (2d) (6 dwords) 4059 PA_SU_POINT_SIZE: { HEIGHT = 0.500000 | WIDTH = 0.500000 } 4060 PA_SU_POINT_MINMAX: { MIN = 0.500000 | MAX = 0.500000 } 4061 PA_SU_LINE_CNTL: { WIDTH = 0.500000 } 4062 PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER } 40630110b3d4: 0000: c0042d00 00040280 00080008 00080008 00000008 00000000 4064t3 opcode: CP_SET_CONSTANT (2d) (7 dwords) 4065 PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH } 4066 PA_CL_GB_VERT_CLIP_ADJ: 1.000000 4067 PA_CL_GB_VERT_DISC_ADJ: 1.000000 4068 PA_CL_GB_HORZ_CLIP_ADJ: 1.000000 4069 PA_CL_GB_HORZ_DISC_ADJ: 1.000000 40700110b3ec: 0000: c0052d00 00040302 00000001 3f800000 3f800000 3f800000 3f800000 4071t3 opcode: CP_SET_CONSTANT (2d) (4 dwords) 4072 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 4073 PA_SC_WINDOW_SCISSOR_BR: { X = 256 | Y = 256 } 40740110b408: 0000: c0022d00 00040081 00000000 01000100 4075t3 opcode: CP_SET_CONSTANT (2d) (8 dwords) 4076 PA_CL_VPORT_XSCALE: 128.000000 4077 PA_CL_VPORT_XOFFSET: 128.000000 4078 PA_CL_VPORT_YSCALE: -128.000000 4079 PA_CL_VPORT_YOFFSET: 128.000000 4080 PA_CL_VPORT_ZSCALE: 0.500000 4081 PA_CL_VPORT_ZOFFSET: 0.500000 40820110b418: 0000: c0062d00 0004010f 43000000 43000000 c3000000 43000000 3f000000 3f000000 4083t3 opcode: CP_SET_CONSTANT (2d) (10 dwords) 40840110b440: 128.000000 128.000000 0.500000 0.000000 128.000000 -128.000000 0.500000 0.000000 40850110b438: 0000: c0082d00 00000184 43000000 43000000 3f000000 00000000 43000000 c3000000 40860110b458: 0020: 3f000000 00000000 4087t3 opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords) 4088 vertex shader, start=0000, size=0015 4089 2003 0007 1000 EXEC ADDR(0x3) CNT(0x2) 4090 03: 19481000 00262688 00000010 (S)FETCH: VERTEX R1.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(16) CONST(20, 0) 4091 04: 13480000 40252fc8 00000008 FETCH: VERTEX R0.xy__ = R0.x FMT_32_32_FLOAT UNSIGNED STRIDE(8) CONST(20, 1) 4092 0000 0000 c200 ALLOC POSITION SIZE(0x0) 4093 1005 0002 1000 EXEC ADDR(0x5) CNT(0x1) 4094 05: 000f803e 00000000 c2010100 (S)ALU: MAXv export62 = R1, R1 ; gl_Position 4095 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0) 4096 1006 0000 2000 EXEC_END ADDR(0x6) CNT(0x1) 4097 06: 00038000 00000000 c2000000 ALU: MAXv export0.xy__ = R0, R0 4098 0000 0000 0000 NOP 40990110b460: 0000: c0162b00 00000000 00000015 00072003 00001000 c2000000 00021005 00001000 41000110b480: 0020: c4000000 00001006 00002000 00000000 19481000 00262688 00000010 13480000 41010110b4a0: 0040: 40252fc8 00000008 000f803e 00000000 c2010100 00038000 00000000 c2000000 4102t3 opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords) 4103 fragment shader, start=0000, size=000c 4104 1002 0003 1000 EXEC ADDR(0x2) CNT(0x1) 4105 02: 90000001 1ffff688 00000002 (S)FETCH: SAMPLE R0.xyzw = R0.xyz CONST(0) LOCATION(CENTER) 4106 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0) 4107 1003 0002 2000 EXEC_END ADDR(0x3) CNT(0x1) 4108 03: 000f8000 00000000 c2000000 (S)ALU: MAXv export0 = R0, R0 ; gl_FragColor 4109 0000 0000 0000 NOP 41100110b4c0: 0000: c00d2b00 00000001 0000000c 00031002 00001000 c4000000 00021003 00002000 41110110b4e0: 0020: 00000000 90000001 1ffff688 00000002 000f8000 00000000 c2000000 4112t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4113 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 } 41140110b4fc: 0000: c0012d00 00040181 00000106 4115t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4116 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 } 41170110b508: 0000: c0012d00 00040180 10030002 4118t3 opcode: CP_SET_CONSTANT (2d) (6 dwords) 41190110b51c: 0.000000 0.000000 0.000000 0.000000 41200110b514: 0000: c0042d00 00000080 00000000 00000000 00000000 00000000 4121t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4122 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_ALWAYS | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 } 41230110b52c: 0000: c0012d00 00040202 00001c20 4124t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4125 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO } 41260110b538: 0000: c0012d00 00040201 00000000 4127t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4128 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 41290110b544: 0000: c0012d00 00040104 0000000f 4130t3 opcode: CP_SET_CONSTANT (2d) (6 dwords) 4131 RB_BLEND_RED: 0 4132 RB_BLEND_GREEN: 0 4133 RB_BLEND_BLUE: 0 4134 RB_BLEND_ALPHA: 0 41350110b550: 0000: c0042d00 00040105 00000000 00000000 00000000 00000000 4136t3 opcode: CP_SET_CONSTANT (2d) (8 dwords) 4137 set texture const 0000 4138 clamp x/y/z: clamp-last-texel/clamp-last-texel/wrap 4139 filter min/mag: point/point 4140 swizzle: xyzw 4141 addr=01230000 (flags=820), size=64x128, pitch=16448, format=FMT_1_REVERSE 4142 mipaddr=01240000 (flags=200) 41430110b568: 0000: c0062d00 00010000 80804800 01230820 000fe03f 00000d11 000001c0 01240200 4144t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4145 VGT_INDX_OFFSET: 0 41460110b588: 0000: c0012d00 00040102 00000000 4147t0 write TC_CNTL_STATUS (0e00) 4148NEEDS WFI: TC_CNTL_STATUS (e00) 4149 TC_CNTL_STATUS: { L2_INVALIDATE } 41500110b594: 0000: 00000e00 00000001 4151t3 opcode: CP_WAIT_REG_EQ (52) (5 dwords) 41520110b59c: 0000: c0035200 000005d0 00000000 00001000 00000001 4153t3 opcode: CP_DRAW_INDX_BIN (34) (7 dwords) 41540110b5b0: 0000: c0053400 00000000 0003c004 00000000 00000003 01009040 00000006 4155t0 write CP_SCRATCH_REG7 (057f) 4156NEEDS WFI: CP_SCRATCH_REG7 (57f) 4157 CP_SCRATCH_REG7: 59 4158 :0,0,69,59 41590110b5cc: 0000: 0000057f 0000003b 4160t3 opcode: CP_DRAW_INDX_BIN (34) (7 dwords) 41610110b5d4: 0000: c0053400 00000000 0006c004 00000000 00000006 0112d4e0 0000000c 4162t0 write CP_SCRATCH_REG7 (057f) 4163NEEDS WFI: CP_SCRATCH_REG7 (57f) 4164 CP_SCRATCH_REG7: 60 4165 :0,0,69,60 41660110b5f0: 0000: 0000057f 0000003c 4167t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 41680110b5f8: 0000: c0002600 00000000 4169t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 4170 { EVENT = CACHE_FLUSH } 4171 event CACHE_FLUSH 41720110b600: 0000: c0004600 00000006 4173t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 4174 { EVENT = CACHE_FLUSH } 4175 event CACHE_FLUSH 41760110b608: 0000: c0004600 00000006 4177t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 4178 { EVENT = CACHE_FLUSH } 4179 event CACHE_FLUSH 41800110b610: 0000: c0004600 00000006 4181t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 4182 { EVENT = CACHE_FLUSH } 4183 event CACHE_FLUSH 41840110b618: 0000: c0004600 00000006 4185t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 4186 { EVENT = CACHE_FLUSH } 4187 event CACHE_FLUSH 41880110b620: 0000: c0004600 00000006 4189t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 4190 { EVENT = CACHE_FLUSH } 4191 event CACHE_FLUSH 41920110b628: 0000: c0004600 00000006 4193t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 4194 { EVENT = CACHE_FLUSH } 4195 event CACHE_FLUSH 41960110b630: 0000: c0004600 00000006 4197t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 4198 { EVENT = CACHE_FLUSH } 4199 event CACHE_FLUSH 42000110b638: 0000: c0004600 00000006 4201t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 4202 { EVENT = CACHE_FLUSH } 4203 event CACHE_FLUSH 42040110b640: 0000: c0004600 00000006 4205t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 4206 { EVENT = CACHE_FLUSH } 4207 event CACHE_FLUSH 42080110b648: 0000: c0004600 00000006 4209t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 4210 { EVENT = CACHE_FLUSH } 4211 event CACHE_FLUSH 42120110b650: 0000: c0004600 00000006 4213t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 4214 { EVENT = CACHE_FLUSH } 4215 event CACHE_FLUSH 42160110b658: 0000: c0004600 00000006 42170110a2cc: 0000: c0013700 0110b000 00000198 4218t2 nop 4219t0 write CP_SCRATCH_REG6 (057e) 4220 CP_SCRATCH_REG6: 71 4221 :0,0,71,60 42220110a2e4: 0000: 0000057e 00000047 4223t3 opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords) 4224 ibaddr:0125e000 4225 ibsize:00000064 4226t3 opcode: CP_SET_CONSTANT (2d) (4 dwords) 4227 set shader const 009c 42280125e000: 0000: c0022d00 0001009c 01009003 00000024 4229t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4230 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 } 42310125e010: 0000: c0012d00 00040080 00000000 4232t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4233 VGT_INDX_OFFSET: 0 42340125e01c: 0000: c0012d00 00040102 00000000 4235t3 opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords) 4236 vertex shader, start=0000, size=000c 4237 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0) 4238 1002 0003 1000 EXEC ADDR(0x2) CNT(0x1) 4239 02: 19a80000 00392a88 0000000c (S)FETCH: VERTEX R0.xyz1 = R0.x FMT_32_32_32_FLOAT UNSIGNED STRIDE(12) CONST(26, 0) 4240 0000 0000 c200 ALLOC POSITION SIZE(0x0) 4241 1003 0002 2000 EXEC_END ADDR(0x3) CNT(0x1) 4242 03: 000f803e 00000000 c2000000 (S)ALU: MAXv export62 = R0, R0 ; gl_Position 42430125e028: 0000: c00d2b00 00000000 0000000c 00000000 1002c400 10000003 00000000 1003c200 42440125e048: 0020: 20000002 19a80000 00392a88 0000000c 000f803e 00000000 c2000000 4245t3 opcode: CP_IM_LOAD_IMMEDIATE (2b) (9 dwords) 4246 fragment shader, start=0000, size=0006 4247 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0) 4248 1001 0002 2000 EXEC_END ADDR(0x1) CNT(0x1) 4249 01: 000f8000 00000000 02000000 (S)ALU: MAXv export0 = C0, C0 ; gl_FragColor 42500125e064: 0000: c0072b00 00000001 00000006 00000000 1001c400 20000002 000f8000 00000000 42510125e084: 0020: 02000000 4252t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4253 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 } 42540125e088: 0000: c0012d00 00040181 00000006 4255t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4256 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 128 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 } 42570125e094: 0000: c0012d00 00040180 10038002 4258t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4259 PA_SC_AA_MASK: 0xffff 42600125e0a0: 0000: c0012d00 00040312 0000ffff 4261t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4262 RB_DEPTHCONTROL: { EARLY_Z_ENABLE | ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP } 42630125e0ac: 0000: c0012d00 00040200 00000008 4264t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4265 PA_SU_SC_MODE_CNTL: { POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | PROVOKING_VTX_LAST } 42660125e0b8: 0000: c0012d00 00040205 00080240 4267t3 opcode: CP_SET_CONSTANT (2d) (4 dwords) 4268 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 4269 PA_SC_WINDOW_SCISSOR_BR: { X = 256 | Y = 256 } 42700125e0c4: 0000: c0022d00 00040081 00000000 01000100 4271t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4272 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL } 42730125e0d4: 0000: c0012d00 00040204 00000000 4274t3 opcode: CP_SET_CONSTANT (2d) (6 dwords) 4275 PA_CL_VPORT_XSCALE: 64.000000 4276 PA_CL_VPORT_XOFFSET: 64.000000 4277 PA_CL_VPORT_YSCALE: 64.000000 4278 PA_CL_VPORT_YOFFSET: 64.000000 42790125e0e0: 0000: c0042d00 0004010f 42800000 42800000 42800000 42800000 4280t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4281 RB_MODECONTROL: { EDRAM_MODE = EDRAM_COPY } 42820125e0f8: 0000: c0012d00 00040208 00000006 4283t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4284 RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 0 | BASE = 0x10000 } 42850125e104: 0000: c0012d00 00040001 00010005 4286t3 opcode: CP_SET_CONSTANT (2d) (6 dwords) 4287 RB_COPY_CONTROL: { COPY_SAMPLE_SELECT = SAMPLE_0 | CLEAR_MASK = 0 } 4288 RB_COPY_DEST_BASE: 0x10ca000 4289 RB_COPY_DEST_PITCH: 256 4290 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | LINEAR | FORMAT = COLORX_8_8_8_8 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 42910125e110: 0000: c0042d00 00040318 00000000 010ca000 00000008 0003c058 4292t0 write CP_SCRATCH_REG7 (057f) 4293 CP_SCRATCH_REG7: 63 4294 :0,0,71,63 42950125e128: 0000: 0000057f 0000003f 4296t3 opcode: CP_DRAW_INDX (22) (3 dwords) 4297 { VIZ_QUERY = 0 } 4298 { PRIM_TYPE = DI_PT_RECTLIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | NUM_INSTANCES = 0 | 0x30000 } 4299 draw: 0 4300 prim_type: DI_PT_RECTLIST (8) 4301 source_select: DI_SRC_SEL_AUTO_INDEX (2) 4302 num_indices: 1407 4303 draw[12] register values 4304!+ 00000047 CP_SCRATCH_REG6: 71 4305 :0,0,71,63 4306!+ 0000003f CP_SCRATCH_REG7: 63 4307 :0,0,71,63 4308 + 00000001 TC_CNTL_STATUS: { L2_INVALIDATE } 4309!+ 00000080 RB_SURFACE_INFO: { SURFACE_PITCH = 128 | MSAA_SAMPLES = 0 } 4310!+ 00010005 RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 0 | BASE = 0x10000 } 4311 + 00010001 RB_DEPTH_INFO: { DEPTH_FORMAT = DEPTHX_24_8 | DEPTH_BASE = 65536 } 4312 + 00000000 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 } 4313 + 00000000 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 4314!+ 01000100 PA_SC_WINDOW_SCISSOR_BR: { X = 256 | Y = 256 } 4315 + 00000000 VGT_INDX_OFFSET: 0 4316 + 0000000f RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 4317 + 00000000 RB_BLEND_RED: 0 4318 + 00000000 RB_BLEND_GREEN: 0 4319 + 00000000 RB_BLEND_BLUE: 0 4320!+ 00000000 RB_BLEND_ALPHA: 0 4321!+ 00000000 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 4322!+ 00000000 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 4323 + 00000000 RB_ALPHA_REF: 0 4324!+ 42800000 PA_CL_VPORT_XSCALE: 64.000000 4325!+ 42800000 PA_CL_VPORT_XOFFSET: 64.000000 4326!+ 42800000 PA_CL_VPORT_YSCALE: 64.000000 4327!+ 42800000 PA_CL_VPORT_YOFFSET: 64.000000 4328!+ 3f000000 PA_CL_VPORT_ZSCALE: 0.500000 4329!+ 3f000000 PA_CL_VPORT_ZOFFSET: 0.500000 4330 + 10038002 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 128 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 } 4331 + 00000006 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 } 4332!+ 00000008 RB_DEPTHCONTROL: { EARLY_Z_ENABLE | ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP } 4333 + 00000000 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO } 4334!+ 00001c20 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_ALWAYS | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 } 4335 + 00000000 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL } 4336!+ 00080240 PA_SU_SC_MODE_CNTL: { POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | PROVOKING_VTX_LAST } 4337!+ 00000006 RB_MODECONTROL: { EDRAM_MODE = EDRAM_COPY } 4338!+ 00080008 PA_SU_POINT_SIZE: { HEIGHT = 0.500000 | WIDTH = 0.500000 } 4339!+ 00080008 PA_SU_POINT_MINMAX: { MIN = 0.500000 | MAX = 0.500000 } 4340!+ 00000008 PA_SU_LINE_CNTL: { WIDTH = 0.500000 } 4341 + 00000000 PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER } 4342!+ 00000000 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 } 4343 + 00000001 PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH } 4344 + 3f800000 PA_CL_GB_VERT_CLIP_ADJ: 1.000000 4345 + 3f800000 PA_CL_GB_VERT_DISC_ADJ: 1.000000 4346 + 3f800000 PA_CL_GB_HORZ_CLIP_ADJ: 1.000000 4347 + 3f800000 PA_CL_GB_HORZ_DISC_ADJ: 1.000000 4348 + 0000ffff PA_SC_AA_MASK: 0xffff 4349 + 00000000 RB_COPY_CONTROL: { COPY_SAMPLE_SELECT = SAMPLE_0 | CLEAR_MASK = 0 } 4350!+ 010ca000 RB_COPY_DEST_BASE: 0x10ca000 4351!+ 00000008 RB_COPY_DEST_PITCH: 256 4352!+ 0003c058 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | LINEAR | FORMAT = COLORX_8_8_8_8 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 43530125e130: 0000: c0012200 00000000 00030088 4354t0 write CP_SCRATCH_REG7 (057f) 4355NEEDS WFI: CP_SCRATCH_REG7 (57f) 4356 CP_SCRATCH_REG7: 64 4357 :0,0,71,64 43580125e13c: 0000: 0000057f 00000040 4359t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4360 RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 0 | BASE = 0 } 43610125e144: 0000: c0012d00 00040001 00000005 4362t3 opcode: CP_SET_CONSTANT (2d) (6 dwords) 4363 RB_COPY_CONTROL: { COPY_SAMPLE_SELECT = SAMPLE_0 | CLEAR_MASK = 0 } 4364 RB_COPY_DEST_BASE: 0x108a000 4365 RB_COPY_DEST_PITCH: 256 4366 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_8_8_8_8 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 43670125e150: 0000: c0042d00 00040318 00000000 0108a000 00000008 0003c050 4368t0 write CP_SCRATCH_REG7 (057f) 4369NEEDS WFI: CP_SCRATCH_REG7 (57f) 4370 CP_SCRATCH_REG7: 65 4371 :0,0,71,65 43720125e168: 0000: 0000057f 00000041 4373t3 opcode: CP_DRAW_INDX (22) (3 dwords) 4374 { VIZ_QUERY = 0 } 4375 { PRIM_TYPE = DI_PT_RECTLIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | NUM_INSTANCES = 0 | 0x30000 } 4376 draw: 1 4377 prim_type: DI_PT_RECTLIST (8) 4378 source_select: DI_SRC_SEL_AUTO_INDEX (2) 4379 num_indices: 1407 4380 draw[13] register values 4381!+ 00000041 CP_SCRATCH_REG7: 65 4382 :0,0,71,65 4383!+ 00000005 RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 0 | BASE = 0 } 4384 + 00000000 RB_COPY_CONTROL: { COPY_SAMPLE_SELECT = SAMPLE_0 | CLEAR_MASK = 0 } 4385!+ 0108a000 RB_COPY_DEST_BASE: 0x108a000 4386 + 00000008 RB_COPY_DEST_PITCH: 256 4387!+ 0003c050 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_8_8_8_8 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 43880125e170: 0000: c0012200 00000000 00030088 4389t0 write CP_SCRATCH_REG7 (057f) 4390NEEDS WFI: CP_SCRATCH_REG7 (57f) 4391 CP_SCRATCH_REG7: 66 4392 :0,0,71,66 43930125e17c: 0000: 0000057f 00000042 4394t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4395 RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH } 43960125e184: 0000: c0012d00 00040208 00000004 43970110a2ec: 0000: c0013700 0125e000 00000064 4398t2 nop 4399t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4400 RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 1 | BASE = 0 } 44010110a304: 0000: c0012d00 00040001 00000205 4402t3 opcode: CP_SET_CONSTANT (2d) (4 dwords) 4403 PA_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } 4404 PA_SC_SCREEN_SCISSOR_BR: { X = 128 | Y = 128 } 44050110a310: 0000: c0022d00 0004000e 00000000 00800080 4406t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4407 RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 1 | BASE = 0 } 44080110a320: 0000: c0012d00 00040001 00000205 4409t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4410 PA_SC_WINDOW_OFFSET: { X = -128 | Y = 0 } 44110110a32c: 0000: c0012d00 00040080 00007f80 4412t3 opcode: CP_MEM_WRITE (3d) (3 dwords) 4413 { ADDR_LO = 0x100903c } 4414 { ADDR_HI = 0x800080 } 4415 gpuaddr:0100903c 44160110a340: 0.000000 44170110a338: 0000: c0013d00 0100903c 00800080 4418t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4419 RB_COPY_DEST_OFFSET: { X = 128 | Y = 0 } 44200110a344: 0000: c0012d00 0004031c 00000080 4421t3 opcode: CP_SET_CONSTANT (2d) (6 dwords) 44220110a358: 128.000000 0.000000 0.000000 0.000000 44230110a350: 0000: c0042d00 00000580 43000000 00000000 00000000 00000000 4424t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4425 VGT_CURRENT_BIN_ID_MIN: { COLUMN = 2 | ROW = 1 | GUARD_BAND_MASK = 0 } 44260110a368: 0000: c0012d00 00040207 0000000a 4427t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4428 VGT_CURRENT_BIN_ID_MAX: { COLUMN = 2 | ROW = 1 | GUARD_BAND_MASK = 0 } 44290110a374: 0000: c0012d00 00040203 0000000a 4430t3 opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords) 44310110a380: 0000: c0004b00 0111d000 4432t0 write CP_SCRATCH_REG6 (057e) 4433NEEDS WFI: CP_SCRATCH_REG6 (57e) 4434 CP_SCRATCH_REG6: 73 4435 :0,0,73,66 44360110a388: 0000: 0000057e 00000049 4437t3 opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords) 4438 ibaddr:0110b000 4439 ibsize:00000198 44400110a390: 0000: c0013700 0110b000 00000198 4441t2 nop 4442t0 write CP_SCRATCH_REG6 (057e) 4443NEEDS WFI: CP_SCRATCH_REG6 (57e) 4444 CP_SCRATCH_REG6: 75 4445 :0,0,75,66 44460110a3a8: 0000: 0000057e 0000004b 4447t3 opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords) 4448 ibaddr:0125e000 4449 ibsize:00000064 44500110a3b0: 0000: c0013700 0125e000 00000064 4451t2 nop 4452t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4453 RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 1 | BASE = 0 } 44540110a3c8: 0000: c0012d00 00040001 00000205 4455t3 opcode: CP_SET_CONSTANT (2d) (4 dwords) 4456 PA_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } 4457 PA_SC_SCREEN_SCISSOR_BR: { X = 128 | Y = 128 } 44580110a3d4: 0000: c0022d00 0004000e 00000000 00800080 4459t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4460 RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 1 | BASE = 0 } 44610110a3e4: 0000: c0012d00 00040001 00000205 4462t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4463 PA_SC_WINDOW_OFFSET: { X = 0 | Y = -128 } 44640110a3f0: 0000: c0012d00 00040080 7f800000 4465t3 opcode: CP_MEM_WRITE (3d) (3 dwords) 4466 { ADDR_LO = 0x100903c } 4467 { ADDR_HI = 0x800080 } 4468 gpuaddr:0100903c 44690110a404: 0.000000 44700110a3fc: 0000: c0013d00 0100903c 00800080 4471t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4472 RB_COPY_DEST_OFFSET: { X = 0 | Y = 128 } 44730110a408: 0000: c0012d00 0004031c 00100000 4474t3 opcode: CP_SET_CONSTANT (2d) (6 dwords) 44750110a41c: 0.000000 128.000000 0.000000 0.000000 44760110a414: 0000: c0042d00 00000580 00000000 43000000 00000000 00000000 4477t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4478 VGT_CURRENT_BIN_ID_MIN: { COLUMN = 1 | ROW = 2 | GUARD_BAND_MASK = 0 } 44790110a42c: 0000: c0012d00 00040207 00000011 4480t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4481 VGT_CURRENT_BIN_ID_MAX: { COLUMN = 1 | ROW = 2 | GUARD_BAND_MASK = 0 } 44820110a438: 0000: c0012d00 00040203 00000011 4483t3 opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords) 44840110a444: 0000: c0004b00 0111d000 4485t0 write CP_SCRATCH_REG6 (057e) 4486NEEDS WFI: CP_SCRATCH_REG6 (57e) 4487 CP_SCRATCH_REG6: 77 4488 :0,0,77,66 44890110a44c: 0000: 0000057e 0000004d 4490t3 opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords) 4491 ibaddr:0110b000 4492 ibsize:00000198 44930110a454: 0000: c0013700 0110b000 00000198 4494t2 nop 4495t0 write CP_SCRATCH_REG6 (057e) 4496NEEDS WFI: CP_SCRATCH_REG6 (57e) 4497 CP_SCRATCH_REG6: 79 4498 :0,0,79,66 44990110a46c: 0000: 0000057e 0000004f 4500t3 opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords) 4501 ibaddr:0125e000 4502 ibsize:00000064 45030110a474: 0000: c0013700 0125e000 00000064 4504t2 nop 4505t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4506 RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 1 | BASE = 0 } 45070110a48c: 0000: c0012d00 00040001 00000205 4508t3 opcode: CP_SET_CONSTANT (2d) (4 dwords) 4509 PA_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } 4510 PA_SC_SCREEN_SCISSOR_BR: { X = 128 | Y = 128 } 45110110a498: 0000: c0022d00 0004000e 00000000 00800080 4512t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4513 RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 1 | BASE = 0 } 45140110a4a8: 0000: c0012d00 00040001 00000205 4515t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4516 PA_SC_WINDOW_OFFSET: { X = -128 | Y = -128 } 45170110a4b4: 0000: c0012d00 00040080 7f807f80 4518t3 opcode: CP_MEM_WRITE (3d) (3 dwords) 4519 { ADDR_LO = 0x100903c } 4520 { ADDR_HI = 0x800080 } 4521 gpuaddr:0100903c 45220110a4c8: 0.000000 45230110a4c0: 0000: c0013d00 0100903c 00800080 4524t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4525 RB_COPY_DEST_OFFSET: { X = 128 | Y = 128 } 45260110a4cc: 0000: c0012d00 0004031c 00100080 4527t3 opcode: CP_SET_CONSTANT (2d) (6 dwords) 45280110a4e0: 128.000000 128.000000 0.000000 0.000000 45290110a4d8: 0000: c0042d00 00000580 43000000 43000000 00000000 00000000 4530t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4531 VGT_CURRENT_BIN_ID_MIN: { COLUMN = 2 | ROW = 2 | GUARD_BAND_MASK = 0 } 45320110a4f0: 0000: c0012d00 00040207 00000012 4533t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4534 VGT_CURRENT_BIN_ID_MAX: { COLUMN = 2 | ROW = 2 | GUARD_BAND_MASK = 0 } 45350110a4fc: 0000: c0012d00 00040203 00000012 4536t3 opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords) 45370110a508: 0000: c0004b00 0111d000 4538t0 write CP_SCRATCH_REG6 (057e) 4539NEEDS WFI: CP_SCRATCH_REG6 (57e) 4540 CP_SCRATCH_REG6: 81 4541 :0,0,81,66 45420110a510: 0000: 0000057e 00000051 4543t3 opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords) 4544 ibaddr:0110b000 4545 ibsize:00000198 45460110a518: 0000: c0013700 0110b000 00000198 4547t2 nop 4548t0 write CP_SCRATCH_REG6 (057e) 4549NEEDS WFI: CP_SCRATCH_REG6 (57e) 4550 CP_SCRATCH_REG6: 83 4551 :0,0,83,66 45520110a530: 0000: 0000057e 00000053 4553t3 opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords) 4554 ibaddr:0125e000 4555 ibsize:00000064 45560110a538: 0000: c0013700 0125e000 00000064 4557t2 nop 4558############################################################ 4559vertices: 0 4560cmd: deqp-gles2/185: fence=1260 4561############################################################ 4562cmdstream: 124 dwords 4563t0 write RB_BC_CONTROL (0f01) 4564NEEDS WFI: RB_BC_CONTROL (f01) 4565 RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 } 45660122f000: 0000: 00000f01 1c004046 4567t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4568 PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 } 45690122f008: 0000: c0012d00 00040293 00000020 4570t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4571 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 } 45720122f014: 0000: c0012d00 00040316 00000002 4573t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4574 VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 } 45750122f020: 0000: c0012d00 00040317 00000002 4576t0 write CP_PERFMON_CNTL (0444) 4577NEEDS WFI: CP_PERFMON_CNTL (444) 4578 CP_PERFMON_CNTL: 0 45790122f02c: 0000: 00000444 00000000 4580t0 write RBBM_PM_OVERRIDE1 (039c) 4581NEEDS WFI: RBBM_PM_OVERRIDE1 (39c) 4582 RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE } 4583NEEDS WFI: RBBM_PM_OVERRIDE2 (39d) 4584 RBBM_PM_OVERRIDE2: 0xfff 45850122f034: 0000: 0001039c ffffffff 00000fff 4586t0 write TP0_CHICKEN (0e1e) 4587NEEDS WFI: TP0_CHICKEN (e1e) 4588 TP0_CHICKEN: 0x2 45890122f040: 0000: 00000e1e 00000002 4590t3 opcode: CP_INVALIDATE_STATE (3b) (2 dwords) 45910122f048: 0000: c0003b00 00007fff 4592t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4593 SQ_VS_CONST: { BASE = 32 | SIZE = 256 } 45940122f050: 0000: c0012d00 00040307 00100020 4595t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4596 SQ_PS_CONST: { BASE = 288 | SIZE = 224 } 45970122f05c: 0000: c0012d00 00040308 000e0120 4598t3 opcode: CP_SET_CONSTANT (2d) (4 dwords) 4599 VGT_MAX_VTX_INDX: 0xffffffff 4600 VGT_MIN_VTX_INDX: 0 46010122f068: 0000: c0022d00 00040100 ffffffff 00000000 4602t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4603 VGT_INDX_OFFSET: 0 46040122f078: 0000: c0012d00 00040102 00000000 4605t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4606 SQ_CONTEXT_MISC: { SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 } 46070122f084: 0000: c0012d00 00040181 00000004 4608t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4609 SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 } 46100122f090: 0000: c0012d00 00040182 ffffffff 4611t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4612 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 } 46130122f09c: 0000: c0012d00 00040301 00000000 4614t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4615 PA_SC_LINE_CNTL: { BRES_CNTL = 0 } 46160122f0a8: 0000: c0012d00 00040300 00000000 4617t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4618 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 } 46190122f0b4: 0000: c0012d00 00040080 00000000 4620t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4621 RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH } 46220122f0c0: 0000: c0012d00 00040208 00000004 4623t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4624 RB_SAMPLE_POS: 0x88888888 46250122f0cc: 0000: c0012d00 0004020a 88888888 4626t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4627 RB_COLOR_DEST_MASK: 0xffffffff 46280122f0d8: 0000: c0012d00 00040326 ffffffff 4629t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4630 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 46310122f0e4: 0000: c0012d00 0004031b 0003c000 4632t3 opcode: CP_SET_CONSTANT (2d) (4 dwords) 4633 SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 } 4634 SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 } 46350122f0f0: 0000: c0022d00 00040183 00000000 00000000 4636t3 opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords) 46370122f100: 0000: c0004b00 00000000 4638t3 opcode: CP_WAIT_REG_EQ (52) (5 dwords) 46390122f108: 0000: c0035200 000005d0 00000000 5f601000 00000001 4640t0 write SQ_INST_STORE_MANAGMENT (0d02) 4641NEEDS WFI: SQ_INST_STORE_MANAGMENT (d02) 4642 SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 } 46430122f11c: 0000: 00000d02 00000180 4644t3 opcode: CP_INVALIDATE_STATE (3b) (2 dwords) 46450122f124: 0000: c0003b00 00000300 4646t3 opcode: CP_SET_SHADER_BASES (4a) (2 dwords) 46470122f12c: 0000: c0004a00 80000180 4648t3 opcode: CP_SET_CONSTANT (2d) (14 dwords) 46490122f13c: 0.000000 0.000000 0.000000 0.000000 20000.000000 1.000000 0.500000 0.000000 46500122f15c: 2.000000 0.750000 0.375000 0.250000 46510122f134: 0000: c00c2d00 00000000 00000000 00000000 00000000 00000000 469c4000 3f800000 46520122f154: 0020: 3f000000 00000000 40000000 3f400000 3ec00000 3e800000 4653t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4654 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 46550122f16c: 0000: c0012d00 00040104 0000000f 4656t3 opcode: CP_SET_CONSTANT (2d) (6 dwords) 4657 RB_BLEND_RED: 0 4658 RB_BLEND_GREEN: 0 4659 RB_BLEND_BLUE: 0 4660 RB_BLEND_ALPHA: 0xff 46610122f178: 0000: c0042d00 00040105 00000000 00000000 00000000 000000ff 4662t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4663 PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT } 46640122f190: 0000: c0012d00 00040206 0000043f 4665t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4666 RB_SURFACE_INFO: { SURFACE_PITCH = 64 | MSAA_SAMPLES = 0 } 46670122f19c: 0000: c0012d00 00040000 00000040 4668t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4669 RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | LINEAR | ENDIAN = 0 | SWAP = 1 | BASE = 0x1256000 } 46700122f1a8: 0000: c0012d00 00040001 01256245 4671t3 opcode: CP_SET_CONSTANT (2d) (4 dwords) 4672 PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 } 4673 PA_SC_SCREEN_SCISSOR_BR: { X = 64 | Y = 128 } 46740122f1b4: 0000: c0022d00 0004000e 80000000 00800040 4675t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4676 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 } 46770122f1c4: 0000: c0012d00 00040080 00000000 4678t0 write CP_SCRATCH_REG6 (057e) 4679NEEDS WFI: CP_SCRATCH_REG6 (57e) 4680 CP_SCRATCH_REG6: 89 4681 :0,0,89,66 46820122f1d0: 0000: 0000057e 00000059 4683t3 opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords) 4684 ibaddr:0122e000 4685 ibsize:000000b6 4686t3 opcode: CP_SET_CONSTANT (2d) (6 dwords) 4687 set shader const 0078 46880122e000: 0000: c0042d00 00010078 0112d4ef 00100000 0112d4ef 00100000 4689t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4690 PA_SC_AA_MASK: 0xffff 46910122e018: 0000: c0012d00 00040312 0000ffff 4692t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4693 RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP } 46940122e024: 0000: c0012d00 00040200 00000000 4695t3 opcode: CP_SET_CONSTANT (2d) (5 dwords) 4696 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 4697 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 4698 RB_ALPHA_REF: 0 46990122e030: 0000: c0032d00 0004010c 00000000 00000000 00000000 4700t3 opcode: CP_SET_CONSTANT (2d) (4 dwords) 4701 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL } 4702 PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST } 47030122e044: 0000: c0022d00 00040204 00000000 00090244 4704t3 opcode: CP_SET_CONSTANT (2d) (6 dwords) 4705 PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 } 4706 PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 } 4707 PA_SU_LINE_CNTL: { WIDTH = 0.000000 } 4708 PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER } 47090122e054: 0000: c0042d00 00040280 00000000 00000000 00000000 00000000 4710t3 opcode: CP_SET_CONSTANT (2d) (7 dwords) 4711 PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH } 4712 PA_CL_GB_VERT_CLIP_ADJ: 1.000000 4713 PA_CL_GB_VERT_DISC_ADJ: 1.000000 4714 PA_CL_GB_HORZ_CLIP_ADJ: 1.000000 4715 PA_CL_GB_HORZ_DISC_ADJ: 1.000000 47160122e06c: 0000: c0052d00 00040302 00000001 3f800000 3f800000 3f800000 3f800000 4717t3 opcode: CP_SET_CONSTANT (2d) (4 dwords) 4718 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 4719 PA_SC_WINDOW_SCISSOR_BR: { X = 64 | Y = 128 } 47200122e088: 0000: c0022d00 00040081 00000000 00800040 4721t3 opcode: CP_SET_CONSTANT (2d) (8 dwords) 4722 PA_CL_VPORT_XSCALE: 32.000000 4723 PA_CL_VPORT_XOFFSET: 32.000000 4724 PA_CL_VPORT_YSCALE: 64.000000 4725 PA_CL_VPORT_YOFFSET: 64.000000 4726 PA_CL_VPORT_ZSCALE: 0.000000 4727 PA_CL_VPORT_ZOFFSET: 0.000000 47280122e098: 0000: c0062d00 0004010f 42000000 42000000 42800000 42800000 00000000 00000000 4729t3 opcode: CP_SET_CONSTANT (2d) (10 dwords) 47300122e0c0: 32.000000 64.000000 0.000000 0.000000 32.000000 64.000000 0.000000 0.000000 47310122e0b8: 0000: c0082d00 00000184 42000000 42800000 00000000 00000000 42000000 42800000 4732* 4733t3 opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords) 4734 vertex shader, start=0000, size=0015 4735 2003 0007 1000 EXEC ADDR(0x3) CNT(0x2) 4736 03: 19481000 00262688 00000020 (S)FETCH: VERTEX R1.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) CONST(20, 0) 4737 04: 13480000 40262688 00001020 FETCH: VERTEX R0.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) OFFSET(16) CONST(20, 1) 4738 0000 0000 c200 ALLOC POSITION SIZE(0x0) 4739 1005 0002 1000 EXEC ADDR(0x5) CNT(0x1) 4740 05: 000f803e 00000000 c2010100 (S)ALU: MAXv export62 = R1, R1 ; gl_Position 4741 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0) 4742 1006 0000 2000 EXEC_END ADDR(0x6) CNT(0x1) 4743 06: 000f8000 00000000 c2000000 ALU: MAXv export0 = R0, R0 4744 0000 0000 0000 NOP 47450122e0e0: 0000: c0162b00 00000000 00000015 00072003 00001000 c2000000 00021005 00001000 47460122e100: 0020: c4000000 00001006 00002000 00000000 19481000 00262688 00000020 13480000 47470122e120: 0040: 40262688 00001020 000f803e 00000000 c2010100 000f8000 00000000 c2000000 4748t3 opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords) 4749 fragment shader, start=0000, size=000c 4750 1002 0003 1000 EXEC ADDR(0x2) CNT(0x1) 4751 02: 90000001 1ffff688 00000002 (S)FETCH: SAMPLE R0.xyzw = R0.xyz CONST(0) LOCATION(CENTER) 4752 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0) 4753 1003 0002 2000 EXEC_END ADDR(0x3) CNT(0x1) 4754 03: 000f8000 00000000 c2000000 (S)ALU: MAXv export0 = R0, R0 ; gl_FragColor 4755 0000 0000 0000 NOP 47560122e140: 0000: c00d2b00 00000001 0000000c 00031002 00001000 c4000000 00021003 00002000 47570122e160: 0020: 00000000 90000001 1ffff688 00000002 000f8000 00000000 c2000000 4758t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4759 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 } 47600122e17c: 0000: c0012d00 00040181 00000106 4761t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4762 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 } 47630122e188: 0000: c0012d00 00040180 10030002 4764t3 opcode: CP_SET_CONSTANT (2d) (6 dwords) 47650122e19c: 0.000000 0.000000 0.000000 0.000000 47660122e194: 0000: c0042d00 00000080 00000000 00000000 00000000 00000000 4767t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4768 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 } 47690122e1ac: 0000: c0012d00 00040202 00000c20 4770t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4771 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO } 47720122e1b8: 0000: c0012d00 00040201 00000000 4773t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4774 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 47750122e1c4: 0000: c0012d00 00040104 0000000f 4776t3 opcode: CP_SET_CONSTANT (2d) (6 dwords) 4777 RB_BLEND_RED: 0 4778 RB_BLEND_GREEN: 0 4779 RB_BLEND_BLUE: 0 4780 RB_BLEND_ALPHA: 0 47810122e1d0: 0000: c0042d00 00040105 00000000 00000000 00000000 00000000 4782t3 opcode: CP_SET_CONSTANT (2d) (8 dwords) 4783 set texture const 0000 4784 clamp x/y/z: clamp-last-texel/clamp-last-texel/clamp-last-texel 4785 filter min/mag: point/point 4786 swizzle: zyxw 4787 addr=0108a000 (flags=806), size=256x256, pitch=16640, format=FMT_8_8_8_8 4788 mipaddr=00000000 (flags=200) 47890122e1e8: 0000: c0062d00 00010000 82024800 0108a806 001fe0ff 00000c14 00000000 00000200 4790t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4791 VGT_INDX_OFFSET: 0 47920122e208: 0000: c0012d00 00040102 00000000 4793t0 write TC_CNTL_STATUS (0e00) 4794NEEDS WFI: TC_CNTL_STATUS (e00) 4795 TC_CNTL_STATUS: { L2_INVALIDATE } 47960122e214: 0000: 00000e00 00000001 4797t3 opcode: CP_WAIT_REG_EQ (52) (5 dwords) 47980122e21c: 0000: c0035200 000005d0 00000000 00001000 00000001 4799t3 opcode: CP_DRAW_INDX_BIN (34) (7 dwords) 48000122e230: 0000: c0053400 00000000 0003c004 00000000 00000003 01009040 00000006 4801t0 write CP_SCRATCH_REG7 (057f) 4802NEEDS WFI: CP_SCRATCH_REG7 (57f) 4803 CP_SCRATCH_REG7: 85 4804 :0,0,89,85 48050122e24c: 0000: 0000057f 00000055 4806t3 opcode: CP_NOP (10) (2 dwords) 48070122e254: 0000: c0001000 00000000 4808t3 opcode: CP_DRAW_INDX (22) (3 dwords) 4809 { VIZ_QUERY = 0 } 4810 { PRIM_TYPE = DI_PT_TRIFAN | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | NUM_INSTANCES = 0 | 0x40000 } 4811 draw: 0 4812 prim_type: DI_PT_TRIFAN (5) 4813 source_select: DI_SRC_SEL_AUTO_INDEX (2) 4814 num_indices: 1407 4815 draw[14] register values 4816 + ffffffff RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE } 4817 + 00000fff RBBM_PM_OVERRIDE2: 0xfff 4818 + 00000000 CP_PERFMON_CNTL: 0 4819!+ 00000059 CP_SCRATCH_REG6: 89 4820 :0,0,89,85 4821!+ 00000055 CP_SCRATCH_REG7: 85 4822 :0,0,89,85 4823 + 00000180 SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 } 4824 + 00000001 TC_CNTL_STATUS: { L2_INVALIDATE } 4825 + 00000002 TP0_CHICKEN: 0x2 4826 + 1c004046 RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 } 4827!+ 00000040 RB_SURFACE_INFO: { SURFACE_PITCH = 64 | MSAA_SAMPLES = 0 } 4828!+ 01256245 RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | LINEAR | ENDIAN = 0 | SWAP = 1 | BASE = 0x1256000 } 4829!+ 80000000 PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 } 4830!+ 00800040 PA_SC_SCREEN_SCISSOR_BR: { X = 64 | Y = 128 } 4831 + 00000000 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 } 4832 + 00000000 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 4833!+ 00800040 PA_SC_WINDOW_SCISSOR_BR: { X = 64 | Y = 128 } 4834 + ffffffff VGT_MAX_VTX_INDX: 0xffffffff 4835 + 00000000 VGT_MIN_VTX_INDX: 0 4836 + 00000000 VGT_INDX_OFFSET: 0 4837 + 0000000f RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 4838 + 00000000 RB_BLEND_RED: 0 4839 + 00000000 RB_BLEND_GREEN: 0 4840 + 00000000 RB_BLEND_BLUE: 0 4841 + 00000000 RB_BLEND_ALPHA: 0 4842 + 00000000 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 4843 + 00000000 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 4844 + 00000000 RB_ALPHA_REF: 0 4845!+ 42000000 PA_CL_VPORT_XSCALE: 32.000000 4846!+ 42000000 PA_CL_VPORT_XOFFSET: 32.000000 4847 + 42800000 PA_CL_VPORT_YSCALE: 64.000000 4848 + 42800000 PA_CL_VPORT_YOFFSET: 64.000000 4849!+ 00000000 PA_CL_VPORT_ZSCALE: 0.000000 4850!+ 00000000 PA_CL_VPORT_ZOFFSET: 0.000000 4851!+ 10030002 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 } 4852!+ 00000106 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 } 4853 + ffffffff SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 } 4854 + 00000000 SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 } 4855 + 00000000 SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 } 4856!+ 00000000 RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP } 4857 + 00000000 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO } 4858!+ 00000c20 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 } 4859!+ 00000012 VGT_CURRENT_BIN_ID_MAX: { COLUMN = 2 | ROW = 2 | GUARD_BAND_MASK = 0 } 4860 + 00000000 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL } 4861!+ 00090244 PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST } 4862 + 0000043f PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT } 4863!+ 00000012 VGT_CURRENT_BIN_ID_MIN: { COLUMN = 2 | ROW = 2 | GUARD_BAND_MASK = 0 } 4864!+ 00000004 RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH } 4865 + 88888888 RB_SAMPLE_POS: 0x88888888 4866!+ 00000000 PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 } 4867!+ 00000000 PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 } 4868!+ 00000000 PA_SU_LINE_CNTL: { WIDTH = 0.000000 } 4869 + 00000000 PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER } 4870 + 00000020 PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 } 4871 + 00000000 PA_SC_LINE_CNTL: { BRES_CNTL = 0 } 4872 + 00000000 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 } 4873 + 00000001 PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH } 4874 + 3f800000 PA_CL_GB_VERT_CLIP_ADJ: 1.000000 4875 + 3f800000 PA_CL_GB_VERT_DISC_ADJ: 1.000000 4876 + 3f800000 PA_CL_GB_HORZ_CLIP_ADJ: 1.000000 4877 + 3f800000 PA_CL_GB_HORZ_DISC_ADJ: 1.000000 4878 + 00100020 SQ_VS_CONST: { BASE = 32 | SIZE = 256 } 4879 + 000e0120 SQ_PS_CONST: { BASE = 288 | SIZE = 224 } 4880 + 0000ffff PA_SC_AA_MASK: 0xffff 4881 + 00000002 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 } 4882 + 00000002 VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 } 4883!+ 0003c000 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 4884!+ 00100080 RB_COPY_DEST_OFFSET: { X = 128 | Y = 128 } 4885 + ffffffff RB_COLOR_DEST_MASK: 0xffffffff 48860122e25c: 0000: c0012200 00000000 00040085 4887t0 write CP_SCRATCH_REG7 (057f) 4888NEEDS WFI: CP_SCRATCH_REG7 (57f) 4889 CP_SCRATCH_REG7: 86 4890 :0,0,89,86 48910122e268: 0000: 0000057f 00000056 4892t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 48930122e270: 0000: c0002600 00000000 4894t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 4895 { EVENT = CACHE_FLUSH } 4896 event CACHE_FLUSH 48970122e278: 0000: c0004600 00000006 4898t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 4899 { EVENT = CACHE_FLUSH } 4900 event CACHE_FLUSH 49010122e280: 0000: c0004600 00000006 4902t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 4903 { EVENT = CACHE_FLUSH } 4904 event CACHE_FLUSH 49050122e288: 0000: c0004600 00000006 4906t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 4907 { EVENT = CACHE_FLUSH } 4908 event CACHE_FLUSH 49090122e290: 0000: c0004600 00000006 4910t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 4911 { EVENT = CACHE_FLUSH } 4912 event CACHE_FLUSH 49130122e298: 0000: c0004600 00000006 4914t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 4915 { EVENT = CACHE_FLUSH } 4916 event CACHE_FLUSH 49170122e2a0: 0000: c0004600 00000006 4918t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 4919 { EVENT = CACHE_FLUSH } 4920 event CACHE_FLUSH 49210122e2a8: 0000: c0004600 00000006 4922t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 4923 { EVENT = CACHE_FLUSH } 4924 event CACHE_FLUSH 49250122e2b0: 0000: c0004600 00000006 4926t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 4927 { EVENT = CACHE_FLUSH } 4928 event CACHE_FLUSH 49290122e2b8: 0000: c0004600 00000006 4930t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 4931 { EVENT = CACHE_FLUSH } 4932 event CACHE_FLUSH 49330122e2c0: 0000: c0004600 00000006 4934t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 4935 { EVENT = CACHE_FLUSH } 4936 event CACHE_FLUSH 49370122e2c8: 0000: c0004600 00000006 4938t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 4939 { EVENT = CACHE_FLUSH } 4940 event CACHE_FLUSH 49410122e2d0: 0000: c0004600 00000006 49420122f1d8: 0000: c0013700 0122e000 000000b6 4943t2 nop 4944############################################################ 4945vertices: 0 4946cmd: deqp-gles2/185: fence=1261 4947############################################################ 4948cmdstream: 124 dwords 4949t0 write RB_BC_CONTROL (0f01) 4950 RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 } 49510110c000: 0000: 00000f01 1c004046 4952t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4953 PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 } 49540110c008: 0000: c0012d00 00040293 00000020 4955t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4956 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 } 49570110c014: 0000: c0012d00 00040316 00000002 4958t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4959 VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 } 49600110c020: 0000: c0012d00 00040317 00000002 4961t0 write CP_PERFMON_CNTL (0444) 4962 CP_PERFMON_CNTL: 0 49630110c02c: 0000: 00000444 00000000 4964t0 write RBBM_PM_OVERRIDE1 (039c) 4965 RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE } 4966 RBBM_PM_OVERRIDE2: 0xfff 49670110c034: 0000: 0001039c ffffffff 00000fff 4968t0 write TP0_CHICKEN (0e1e) 4969 TP0_CHICKEN: 0x2 49700110c040: 0000: 00000e1e 00000002 4971t3 opcode: CP_INVALIDATE_STATE (3b) (2 dwords) 49720110c048: 0000: c0003b00 00007fff 4973t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4974 SQ_VS_CONST: { BASE = 32 | SIZE = 256 } 49750110c050: 0000: c0012d00 00040307 00100020 4976t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4977 SQ_PS_CONST: { BASE = 288 | SIZE = 224 } 49780110c05c: 0000: c0012d00 00040308 000e0120 4979t3 opcode: CP_SET_CONSTANT (2d) (4 dwords) 4980 VGT_MAX_VTX_INDX: 0xffffffff 4981 VGT_MIN_VTX_INDX: 0 49820110c068: 0000: c0022d00 00040100 ffffffff 00000000 4983t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4984 VGT_INDX_OFFSET: 0 49850110c078: 0000: c0012d00 00040102 00000000 4986t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4987 SQ_CONTEXT_MISC: { SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 } 49880110c084: 0000: c0012d00 00040181 00000004 4989t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4990 SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 } 49910110c090: 0000: c0012d00 00040182 ffffffff 4992t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4993 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 } 49940110c09c: 0000: c0012d00 00040301 00000000 4995t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4996 PA_SC_LINE_CNTL: { BRES_CNTL = 0 } 49970110c0a8: 0000: c0012d00 00040300 00000000 4998t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 4999 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 } 50000110c0b4: 0000: c0012d00 00040080 00000000 5001t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5002 RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH } 50030110c0c0: 0000: c0012d00 00040208 00000004 5004t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5005 RB_SAMPLE_POS: 0x88888888 50060110c0cc: 0000: c0012d00 0004020a 88888888 5007t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5008 RB_COLOR_DEST_MASK: 0xffffffff 50090110c0d8: 0000: c0012d00 00040326 ffffffff 5010t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5011 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 50120110c0e4: 0000: c0012d00 0004031b 0003c000 5013t3 opcode: CP_SET_CONSTANT (2d) (4 dwords) 5014 SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 } 5015 SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 } 50160110c0f0: 0000: c0022d00 00040183 00000000 00000000 5017t3 opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords) 50180110c100: 0000: c0004b00 00000000 5019t3 opcode: CP_WAIT_REG_EQ (52) (5 dwords) 50200110c108: 0000: c0035200 000005d0 00000000 5f601000 00000001 5021t0 write SQ_INST_STORE_MANAGMENT (0d02) 5022 SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 } 50230110c11c: 0000: 00000d02 00000180 5024t3 opcode: CP_INVALIDATE_STATE (3b) (2 dwords) 50250110c124: 0000: c0003b00 00000300 5026t3 opcode: CP_SET_SHADER_BASES (4a) (2 dwords) 50270110c12c: 0000: c0004a00 80000180 5028t3 opcode: CP_SET_CONSTANT (2d) (14 dwords) 50290110c13c: 0.000000 0.000000 0.000000 0.000000 20000.000000 1.000000 0.500000 0.000000 50300110c15c: 2.000000 0.750000 0.375000 0.250000 50310110c134: 0000: c00c2d00 00000000 00000000 00000000 00000000 00000000 469c4000 3f800000 50320110c154: 0020: 3f000000 00000000 40000000 3f400000 3ec00000 3e800000 5033t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5034 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 50350110c16c: 0000: c0012d00 00040104 0000000f 5036t3 opcode: CP_SET_CONSTANT (2d) (6 dwords) 5037 RB_BLEND_RED: 0 5038 RB_BLEND_GREEN: 0 5039 RB_BLEND_BLUE: 0 5040 RB_BLEND_ALPHA: 0xff 50410110c178: 0000: c0042d00 00040105 00000000 00000000 00000000 000000ff 5042t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5043 PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT } 50440110c190: 0000: c0012d00 00040206 0000043f 5045t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5046 RB_SURFACE_INFO: { SURFACE_PITCH = 256 | MSAA_SAMPLES = 0 } 50470110c19c: 0000: c0012d00 00040000 00000100 5048t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5049 RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 1 | BASE = 0x108a000 } 50500110c1a8: 0000: c0012d00 00040001 0108a205 5051t3 opcode: CP_SET_CONSTANT (2d) (4 dwords) 5052 PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 } 5053 PA_SC_SCREEN_SCISSOR_BR: { X = 256 | Y = 256 } 50540110c1b4: 0000: c0022d00 0004000e 80000000 01000100 5055t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5056 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 } 50570110c1c4: 0000: c0012d00 00040080 00000000 5058t0 write CP_SCRATCH_REG6 (057e) 5059 CP_SCRATCH_REG6: 95 5060 :0,0,95,86 50610110c1d0: 0000: 0000057e 0000005f 5062t3 opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords) 5063 ibaddr:0110b000 5064 ibsize:000000b8 5065t3 opcode: CP_SET_CONSTANT (2d) (6 dwords) 5066 set shader const 0078 50670110b000: 0000: c0042d00 00010078 0112d56f 00100000 0112d5af 00100000 5068t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5069 PA_SC_AA_MASK: 0xffff 50700110b018: 0000: c0012d00 00040312 0000ffff 5071t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5072 RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP } 50730110b024: 0000: c0012d00 00040200 00000000 5074t3 opcode: CP_SET_CONSTANT (2d) (5 dwords) 5075 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 5076 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 5077 RB_ALPHA_REF: 0 50780110b030: 0000: c0032d00 0004010c 00000000 00000000 00000000 5079t3 opcode: CP_SET_CONSTANT (2d) (4 dwords) 5080 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL } 5081 PA_SU_SC_MODE_CNTL: { POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST } 50820110b044: 0000: c0022d00 00040204 00000000 00090240 5083t3 opcode: CP_SET_CONSTANT (2d) (6 dwords) 5084 PA_SU_POINT_SIZE: { HEIGHT = 0.500000 | WIDTH = 0.500000 } 5085 PA_SU_POINT_MINMAX: { MIN = 0.500000 | MAX = 0.500000 } 5086 PA_SU_LINE_CNTL: { WIDTH = 0.500000 } 5087 PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER } 50880110b054: 0000: c0042d00 00040280 00080008 00080008 00000008 00000000 5089t3 opcode: CP_SET_CONSTANT (2d) (7 dwords) 5090 PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH } 5091 PA_CL_GB_VERT_CLIP_ADJ: 1.000000 5092 PA_CL_GB_VERT_DISC_ADJ: 1.000000 5093 PA_CL_GB_HORZ_CLIP_ADJ: 1.000000 5094 PA_CL_GB_HORZ_DISC_ADJ: 1.000000 50950110b06c: 0000: c0052d00 00040302 00000001 3f800000 3f800000 3f800000 3f800000 5096t3 opcode: CP_SET_CONSTANT (2d) (4 dwords) 5097 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 5098 PA_SC_WINDOW_SCISSOR_BR: { X = 256 | Y = 256 } 50990110b088: 0000: c0022d00 00040081 00000000 01000100 5100t3 opcode: CP_SET_CONSTANT (2d) (8 dwords) 5101 PA_CL_VPORT_XSCALE: 128.000000 5102 PA_CL_VPORT_XOFFSET: 128.000000 5103 PA_CL_VPORT_YSCALE: -128.000000 5104 PA_CL_VPORT_YOFFSET: 128.000000 5105 PA_CL_VPORT_ZSCALE: 0.500000 5106 PA_CL_VPORT_ZOFFSET: 0.500000 51070110b098: 0000: c0062d00 0004010f 43000000 43000000 c3000000 43000000 3f000000 3f000000 5108t3 opcode: CP_SET_CONSTANT (2d) (10 dwords) 51090110b0c0: 128.000000 128.000000 0.500000 0.000000 128.000000 -128.000000 0.500000 0.000000 51100110b0b8: 0000: c0082d00 00000184 43000000 43000000 3f000000 00000000 43000000 c3000000 51110110b0d8: 0020: 3f000000 00000000 5112t3 opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords) 5113 vertex shader, start=0000, size=0015 5114 2003 0007 1000 EXEC ADDR(0x3) CNT(0x2) 5115 03: 19481000 00262688 00000010 (S)FETCH: VERTEX R1.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(16) CONST(20, 0) 5116 04: 13480000 40252fc8 00000008 FETCH: VERTEX R0.xy__ = R0.x FMT_32_32_FLOAT UNSIGNED STRIDE(8) CONST(20, 1) 5117 0000 0000 c200 ALLOC POSITION SIZE(0x0) 5118 1005 0002 1000 EXEC ADDR(0x5) CNT(0x1) 5119 05: 000f803e 00000000 c2010100 (S)ALU: MAXv export62 = R1, R1 ; gl_Position 5120 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0) 5121 1006 0000 2000 EXEC_END ADDR(0x6) CNT(0x1) 5122 06: 00038000 00000000 c2000000 ALU: MAXv export0.xy__ = R0, R0 5123 0000 0000 0000 NOP 51240110b0e0: 0000: c0162b00 00000000 00000015 00072003 00001000 c2000000 00021005 00001000 51250110b100: 0020: c4000000 00001006 00002000 00000000 19481000 00262688 00000010 13480000 51260110b120: 0040: 40252fc8 00000008 000f803e 00000000 c2010100 00038000 00000000 c2000000 5127t3 opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords) 5128 fragment shader, start=0000, size=000c 5129 1002 0003 1000 EXEC ADDR(0x2) CNT(0x1) 5130 02: 90000001 1ffff688 00000002 (S)FETCH: SAMPLE R0.xyzw = R0.xyz CONST(0) LOCATION(CENTER) 5131 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0) 5132 1003 0002 2000 EXEC_END ADDR(0x3) CNT(0x1) 5133 03: 000f8000 00000000 c2000000 (S)ALU: MAXv export0 = R0, R0 ; gl_FragColor 5134 0000 0000 0000 NOP 51350110b140: 0000: c00d2b00 00000001 0000000c 00031002 00001000 c4000000 00021003 00002000 51360110b160: 0020: 00000000 90000001 1ffff688 00000002 000f8000 00000000 c2000000 5137t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5138 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 } 51390110b17c: 0000: c0012d00 00040181 00000106 5140t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5141 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 } 51420110b188: 0000: c0012d00 00040180 10030002 5143t3 opcode: CP_SET_CONSTANT (2d) (6 dwords) 51440110b19c: 0.000000 0.000000 0.000000 0.000000 51450110b194: 0000: c0042d00 00000080 00000000 00000000 00000000 00000000 5146t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5147 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_ALWAYS | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 } 51480110b1ac: 0000: c0012d00 00040202 00001c20 5149t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5150 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO } 51510110b1b8: 0000: c0012d00 00040201 00000000 5152t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5153 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 51540110b1c4: 0000: c0012d00 00040104 0000000f 5155t3 opcode: CP_SET_CONSTANT (2d) (6 dwords) 5156 RB_BLEND_RED: 0 5157 RB_BLEND_GREEN: 0 5158 RB_BLEND_BLUE: 0 5159 RB_BLEND_ALPHA: 0 51600110b1d0: 0000: c0042d00 00040105 00000000 00000000 00000000 00000000 5161t3 opcode: CP_SET_CONSTANT (2d) (8 dwords) 5162 set texture const 0000 5163 clamp x/y/z: clamp-last-texel/clamp-last-texel/wrap 5164 filter min/mag: point/point 5165 swizzle: xyzw 5166 addr=01230000 (flags=820), size=64x128, pitch=16448, format=FMT_1_REVERSE 5167 mipaddr=01240000 (flags=200) 51680110b1e8: 0000: c0062d00 00010000 80804800 01230820 000fe03f 00000d11 000001c0 01240200 5169t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5170 VGT_INDX_OFFSET: 0 51710110b208: 0000: c0012d00 00040102 00000000 5172t0 write TC_CNTL_STATUS (0e00) 5173 TC_CNTL_STATUS: { L2_INVALIDATE } 51740110b214: 0000: 00000e00 00000001 5175t3 opcode: CP_WAIT_REG_EQ (52) (5 dwords) 51760110b21c: 0000: c0035200 000005d0 00000000 00001000 00000001 5177t3 opcode: CP_DRAW_INDX_BIN (34) (7 dwords) 51780110b230: 0000: c0053400 00000000 0003c004 00000000 00000003 01009040 00000006 5179t0 write CP_SCRATCH_REG7 (057f) 5180 CP_SCRATCH_REG7: 91 5181 :0,0,95,91 51820110b24c: 0000: 0000057f 0000005b 5183t3 opcode: CP_NOP (10) (2 dwords) 51840110b254: 0000: c0001000 00000000 5185t3 opcode: CP_DRAW_INDX (22) (5 dwords) 5186 { VIZ_QUERY = 0 } 5187 { PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_DMA | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | NUM_INSTANCES = 0 | 0x60000 } 5188 { NUM_INDICES = 18011596 } 5189 { INDX_BASE = 0xc } 5190 draw: 0 5191 prim_type: DI_PT_TRILIST (4) 5192 source_select: DI_SRC_SEL_DMA (0) 5193 num_indices: 18011596 5194 draw[15] register values 5195 + ffffffff RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE } 5196 + 00000fff RBBM_PM_OVERRIDE2: 0xfff 5197 + 00000000 CP_PERFMON_CNTL: 0 5198!+ 0000005f CP_SCRATCH_REG6: 95 5199 :0,0,95,91 5200!+ 0000005b CP_SCRATCH_REG7: 91 5201 :0,0,95,91 5202 + 00000180 SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 } 5203 + 00000001 TC_CNTL_STATUS: { L2_INVALIDATE } 5204 + 00000002 TP0_CHICKEN: 0x2 5205 + 1c004046 RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 } 5206!+ 00000100 RB_SURFACE_INFO: { SURFACE_PITCH = 256 | MSAA_SAMPLES = 0 } 5207!+ 0108a205 RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 1 | BASE = 0x108a000 } 5208 + 80000000 PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 } 5209!+ 01000100 PA_SC_SCREEN_SCISSOR_BR: { X = 256 | Y = 256 } 5210 + 00000000 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 } 5211 + 00000000 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 5212!+ 01000100 PA_SC_WINDOW_SCISSOR_BR: { X = 256 | Y = 256 } 5213 + ffffffff VGT_MAX_VTX_INDX: 0xffffffff 5214 + 00000000 VGT_MIN_VTX_INDX: 0 5215 + 00000000 VGT_INDX_OFFSET: 0 5216 + 0000000f RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 5217 + 00000000 RB_BLEND_RED: 0 5218 + 00000000 RB_BLEND_GREEN: 0 5219 + 00000000 RB_BLEND_BLUE: 0 5220 + 00000000 RB_BLEND_ALPHA: 0 5221 + 00000000 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 5222 + 00000000 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 5223 + 00000000 RB_ALPHA_REF: 0 5224!+ 43000000 PA_CL_VPORT_XSCALE: 128.000000 5225!+ 43000000 PA_CL_VPORT_XOFFSET: 128.000000 5226!+ c3000000 PA_CL_VPORT_YSCALE: -128.000000 5227!+ 43000000 PA_CL_VPORT_YOFFSET: 128.000000 5228!+ 3f000000 PA_CL_VPORT_ZSCALE: 0.500000 5229!+ 3f000000 PA_CL_VPORT_ZOFFSET: 0.500000 5230 + 10030002 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 } 5231 + 00000106 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 } 5232 + ffffffff SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 } 5233 + 00000000 SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 } 5234 + 00000000 SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 } 5235 + 00000000 RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP } 5236 + 00000000 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO } 5237!+ 00001c20 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_ALWAYS | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 } 5238 + 00000000 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL } 5239!+ 00090240 PA_SU_SC_MODE_CNTL: { POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST } 5240 + 0000043f PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT } 5241 + 00000004 RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH } 5242 + 88888888 RB_SAMPLE_POS: 0x88888888 5243!+ 00080008 PA_SU_POINT_SIZE: { HEIGHT = 0.500000 | WIDTH = 0.500000 } 5244!+ 00080008 PA_SU_POINT_MINMAX: { MIN = 0.500000 | MAX = 0.500000 } 5245!+ 00000008 PA_SU_LINE_CNTL: { WIDTH = 0.500000 } 5246 + 00000000 PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER } 5247 + 00000020 PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 } 5248 + 00000000 PA_SC_LINE_CNTL: { BRES_CNTL = 0 } 5249 + 00000000 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 } 5250 + 00000001 PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH } 5251 + 3f800000 PA_CL_GB_VERT_CLIP_ADJ: 1.000000 5252 + 3f800000 PA_CL_GB_VERT_DISC_ADJ: 1.000000 5253 + 3f800000 PA_CL_GB_HORZ_CLIP_ADJ: 1.000000 5254 + 3f800000 PA_CL_GB_HORZ_DISC_ADJ: 1.000000 5255 + 00100020 SQ_VS_CONST: { BASE = 32 | SIZE = 256 } 5256 + 000e0120 SQ_PS_CONST: { BASE = 288 | SIZE = 224 } 5257 + 0000ffff PA_SC_AA_MASK: 0xffff 5258 + 00000002 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 } 5259 + 00000002 VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 } 5260 + 0003c000 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 5261 + ffffffff RB_COLOR_DEST_MASK: 0xffffffff 52620110b25c: 0000: c0032200 00000000 00060004 0112d5cc 0000000c 5263t0 write CP_SCRATCH_REG7 (057f) 5264NEEDS WFI: CP_SCRATCH_REG7 (57f) 5265 CP_SCRATCH_REG7: 92 5266 :0,0,95,92 52670110b270: 0000: 0000057f 0000005c 5268t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 52690110b278: 0000: c0002600 00000000 5270t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 5271 { EVENT = CACHE_FLUSH } 5272 event CACHE_FLUSH 52730110b280: 0000: c0004600 00000006 5274t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 5275 { EVENT = CACHE_FLUSH } 5276 event CACHE_FLUSH 52770110b288: 0000: c0004600 00000006 5278t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 5279 { EVENT = CACHE_FLUSH } 5280 event CACHE_FLUSH 52810110b290: 0000: c0004600 00000006 5282t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 5283 { EVENT = CACHE_FLUSH } 5284 event CACHE_FLUSH 52850110b298: 0000: c0004600 00000006 5286t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 5287 { EVENT = CACHE_FLUSH } 5288 event CACHE_FLUSH 52890110b2a0: 0000: c0004600 00000006 5290t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 5291 { EVENT = CACHE_FLUSH } 5292 event CACHE_FLUSH 52930110b2a8: 0000: c0004600 00000006 5294t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 5295 { EVENT = CACHE_FLUSH } 5296 event CACHE_FLUSH 52970110b2b0: 0000: c0004600 00000006 5298t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 5299 { EVENT = CACHE_FLUSH } 5300 event CACHE_FLUSH 53010110b2b8: 0000: c0004600 00000006 5302t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 5303 { EVENT = CACHE_FLUSH } 5304 event CACHE_FLUSH 53050110b2c0: 0000: c0004600 00000006 5306t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 5307 { EVENT = CACHE_FLUSH } 5308 event CACHE_FLUSH 53090110b2c8: 0000: c0004600 00000006 5310t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 5311 { EVENT = CACHE_FLUSH } 5312 event CACHE_FLUSH 53130110b2d0: 0000: c0004600 00000006 5314t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 5315 { EVENT = CACHE_FLUSH } 5316 event CACHE_FLUSH 53170110b2d8: 0000: c0004600 00000006 53180110c1d8: 0000: c0013700 0110b000 000000b8 5319t2 nop 5320############################################################ 5321vertices: 0 5322cmd: deqp-gles2/185: fence=1262 5323############################################################ 5324cmdstream: 124 dwords 5325t0 write RB_BC_CONTROL (0f01) 5326 RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 } 53270122d000: 0000: 00000f01 1c004046 5328t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5329 PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 } 53300122d008: 0000: c0012d00 00040293 00000020 5331t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5332 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 } 53330122d014: 0000: c0012d00 00040316 00000002 5334t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5335 VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 } 53360122d020: 0000: c0012d00 00040317 00000002 5337t0 write CP_PERFMON_CNTL (0444) 5338 CP_PERFMON_CNTL: 0 53390122d02c: 0000: 00000444 00000000 5340t0 write RBBM_PM_OVERRIDE1 (039c) 5341 RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE } 5342 RBBM_PM_OVERRIDE2: 0xfff 53430122d034: 0000: 0001039c ffffffff 00000fff 5344t0 write TP0_CHICKEN (0e1e) 5345 TP0_CHICKEN: 0x2 53460122d040: 0000: 00000e1e 00000002 5347t3 opcode: CP_INVALIDATE_STATE (3b) (2 dwords) 53480122d048: 0000: c0003b00 00007fff 5349t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5350 SQ_VS_CONST: { BASE = 32 | SIZE = 256 } 53510122d050: 0000: c0012d00 00040307 00100020 5352t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5353 SQ_PS_CONST: { BASE = 288 | SIZE = 224 } 53540122d05c: 0000: c0012d00 00040308 000e0120 5355t3 opcode: CP_SET_CONSTANT (2d) (4 dwords) 5356 VGT_MAX_VTX_INDX: 0xffffffff 5357 VGT_MIN_VTX_INDX: 0 53580122d068: 0000: c0022d00 00040100 ffffffff 00000000 5359t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5360 VGT_INDX_OFFSET: 0 53610122d078: 0000: c0012d00 00040102 00000000 5362t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5363 SQ_CONTEXT_MISC: { SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 } 53640122d084: 0000: c0012d00 00040181 00000004 5365t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5366 SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 } 53670122d090: 0000: c0012d00 00040182 ffffffff 5368t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5369 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 } 53700122d09c: 0000: c0012d00 00040301 00000000 5371t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5372 PA_SC_LINE_CNTL: { BRES_CNTL = 0 } 53730122d0a8: 0000: c0012d00 00040300 00000000 5374t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5375 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 } 53760122d0b4: 0000: c0012d00 00040080 00000000 5377t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5378 RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH } 53790122d0c0: 0000: c0012d00 00040208 00000004 5380t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5381 RB_SAMPLE_POS: 0x88888888 53820122d0cc: 0000: c0012d00 0004020a 88888888 5383t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5384 RB_COLOR_DEST_MASK: 0xffffffff 53850122d0d8: 0000: c0012d00 00040326 ffffffff 5386t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5387 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 53880122d0e4: 0000: c0012d00 0004031b 0003c000 5389t3 opcode: CP_SET_CONSTANT (2d) (4 dwords) 5390 SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 } 5391 SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 } 53920122d0f0: 0000: c0022d00 00040183 00000000 00000000 5393t3 opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords) 53940122d100: 0000: c0004b00 00000000 5395t3 opcode: CP_WAIT_REG_EQ (52) (5 dwords) 53960122d108: 0000: c0035200 000005d0 00000000 5f601000 00000001 5397t0 write SQ_INST_STORE_MANAGMENT (0d02) 5398 SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 } 53990122d11c: 0000: 00000d02 00000180 5400t3 opcode: CP_INVALIDATE_STATE (3b) (2 dwords) 54010122d124: 0000: c0003b00 00000300 5402t3 opcode: CP_SET_SHADER_BASES (4a) (2 dwords) 54030122d12c: 0000: c0004a00 80000180 5404t3 opcode: CP_SET_CONSTANT (2d) (14 dwords) 54050122d13c: 0.000000 0.000000 0.000000 0.000000 20000.000000 1.000000 0.500000 0.000000 54060122d15c: 2.000000 0.750000 0.375000 0.250000 54070122d134: 0000: c00c2d00 00000000 00000000 00000000 00000000 00000000 469c4000 3f800000 54080122d154: 0020: 3f000000 00000000 40000000 3f400000 3ec00000 3e800000 5409t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5410 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 54110122d16c: 0000: c0012d00 00040104 0000000f 5412t3 opcode: CP_SET_CONSTANT (2d) (6 dwords) 5413 RB_BLEND_RED: 0 5414 RB_BLEND_GREEN: 0 5415 RB_BLEND_BLUE: 0 5416 RB_BLEND_ALPHA: 0xff 54170122d178: 0000: c0042d00 00040105 00000000 00000000 00000000 000000ff 5418t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5419 PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT } 54200122d190: 0000: c0012d00 00040206 0000043f 5421t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5422 RB_SURFACE_INFO: { SURFACE_PITCH = 32 | MSAA_SAMPLES = 0 } 54230122d19c: 0000: c0012d00 00040000 00000020 5424t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5425 RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | LINEAR | ENDIAN = 0 | SWAP = 1 | BASE = 0x1254000 } 54260122d1a8: 0000: c0012d00 00040001 01254245 5427t3 opcode: CP_SET_CONSTANT (2d) (4 dwords) 5428 PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 } 5429 PA_SC_SCREEN_SCISSOR_BR: { X = 32 | Y = 64 } 54300122d1b4: 0000: c0022d00 0004000e 80000000 00400020 5431t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5432 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 } 54330122d1c4: 0000: c0012d00 00040080 00000000 5434t0 write CP_SCRATCH_REG6 (057e) 5435 CP_SCRATCH_REG6: 101 5436 :0,0,101,92 54370122d1d0: 0000: 0000057e 00000065 5438t3 opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords) 5439 ibaddr:0122e000 5440 ibsize:000000b6 5441t3 opcode: CP_SET_CONSTANT (2d) (6 dwords) 5442 set shader const 0078 54430122e000: 0000: c0042d00 00010078 0112d5db 00100000 0112d5db 00100000 5444t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5445 PA_SC_AA_MASK: 0xffff 54460122e018: 0000: c0012d00 00040312 0000ffff 5447t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5448 RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP } 54490122e024: 0000: c0012d00 00040200 00000000 5450t3 opcode: CP_SET_CONSTANT (2d) (5 dwords) 5451 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 5452 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 5453 RB_ALPHA_REF: 0 54540122e030: 0000: c0032d00 0004010c 00000000 00000000 00000000 5455t3 opcode: CP_SET_CONSTANT (2d) (4 dwords) 5456 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL } 5457 PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST } 54580122e044: 0000: c0022d00 00040204 00000000 00090244 5459t3 opcode: CP_SET_CONSTANT (2d) (6 dwords) 5460 PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 } 5461 PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 } 5462 PA_SU_LINE_CNTL: { WIDTH = 0.000000 } 5463 PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER } 54640122e054: 0000: c0042d00 00040280 00000000 00000000 00000000 00000000 5465t3 opcode: CP_SET_CONSTANT (2d) (7 dwords) 5466 PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH } 5467 PA_CL_GB_VERT_CLIP_ADJ: 1.000000 5468 PA_CL_GB_VERT_DISC_ADJ: 1.000000 5469 PA_CL_GB_HORZ_CLIP_ADJ: 1.000000 5470 PA_CL_GB_HORZ_DISC_ADJ: 1.000000 54710122e06c: 0000: c0052d00 00040302 00000001 3f800000 3f800000 3f800000 3f800000 5472t3 opcode: CP_SET_CONSTANT (2d) (4 dwords) 5473 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 5474 PA_SC_WINDOW_SCISSOR_BR: { X = 32 | Y = 64 } 54750122e088: 0000: c0022d00 00040081 00000000 00400020 5476t3 opcode: CP_SET_CONSTANT (2d) (8 dwords) 5477 PA_CL_VPORT_XSCALE: 16.000000 5478 PA_CL_VPORT_XOFFSET: 16.000000 5479 PA_CL_VPORT_YSCALE: 32.000000 5480 PA_CL_VPORT_YOFFSET: 32.000000 5481 PA_CL_VPORT_ZSCALE: 0.000000 5482 PA_CL_VPORT_ZOFFSET: 0.000000 54830122e098: 0000: c0062d00 0004010f 41800000 41800000 42000000 42000000 00000000 00000000 5484t3 opcode: CP_SET_CONSTANT (2d) (10 dwords) 54850122e0c0: 16.000000 32.000000 0.000000 0.000000 16.000000 32.000000 0.000000 0.000000 54860122e0b8: 0000: c0082d00 00000184 41800000 42000000 00000000 00000000 41800000 42000000 5487* 5488t3 opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords) 5489 vertex shader, start=0000, size=0015 5490 2003 0007 1000 EXEC ADDR(0x3) CNT(0x2) 5491 03: 19481000 00262688 00000020 (S)FETCH: VERTEX R1.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) CONST(20, 0) 5492 04: 13480000 40262688 00001020 FETCH: VERTEX R0.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) OFFSET(16) CONST(20, 1) 5493 0000 0000 c200 ALLOC POSITION SIZE(0x0) 5494 1005 0002 1000 EXEC ADDR(0x5) CNT(0x1) 5495 05: 000f803e 00000000 c2010100 (S)ALU: MAXv export62 = R1, R1 ; gl_Position 5496 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0) 5497 1006 0000 2000 EXEC_END ADDR(0x6) CNT(0x1) 5498 06: 000f8000 00000000 c2000000 ALU: MAXv export0 = R0, R0 5499 0000 0000 0000 NOP 55000122e0e0: 0000: c0162b00 00000000 00000015 00072003 00001000 c2000000 00021005 00001000 55010122e100: 0020: c4000000 00001006 00002000 00000000 19481000 00262688 00000020 13480000 55020122e120: 0040: 40262688 00001020 000f803e 00000000 c2010100 000f8000 00000000 c2000000 5503t3 opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords) 5504 fragment shader, start=0000, size=000c 5505 1002 0003 1000 EXEC ADDR(0x2) CNT(0x1) 5506 02: 90000001 1ffff688 00000002 (S)FETCH: SAMPLE R0.xyzw = R0.xyz CONST(0) LOCATION(CENTER) 5507 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0) 5508 1003 0002 2000 EXEC_END ADDR(0x3) CNT(0x1) 5509 03: 000f8000 00000000 c2000000 (S)ALU: MAXv export0 = R0, R0 ; gl_FragColor 5510 0000 0000 0000 NOP 55110122e140: 0000: c00d2b00 00000001 0000000c 00031002 00001000 c4000000 00021003 00002000 55120122e160: 0020: 00000000 90000001 1ffff688 00000002 000f8000 00000000 c2000000 5513t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5514 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 } 55150122e17c: 0000: c0012d00 00040181 00000106 5516t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5517 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 } 55180122e188: 0000: c0012d00 00040180 10030002 5519t3 opcode: CP_SET_CONSTANT (2d) (6 dwords) 55200122e19c: 0.000000 0.000000 0.000000 0.000000 55210122e194: 0000: c0042d00 00000080 00000000 00000000 00000000 00000000 5522t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5523 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 } 55240122e1ac: 0000: c0012d00 00040202 00000c20 5525t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5526 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO } 55270122e1b8: 0000: c0012d00 00040201 00000000 5528t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5529 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 55300122e1c4: 0000: c0012d00 00040104 0000000f 5531t3 opcode: CP_SET_CONSTANT (2d) (6 dwords) 5532 RB_BLEND_RED: 0 5533 RB_BLEND_GREEN: 0 5534 RB_BLEND_BLUE: 0 5535 RB_BLEND_ALPHA: 0 55360122e1d0: 0000: c0042d00 00040105 00000000 00000000 00000000 00000000 5537t3 opcode: CP_SET_CONSTANT (2d) (8 dwords) 5538 set texture const 0000 5539 clamp x/y/z: clamp-last-texel/clamp-last-texel/clamp-last-texel 5540 filter min/mag: point/point 5541 swizzle: zyxw 5542 addr=0108a000 (flags=806), size=256x256, pitch=16640, format=FMT_8_8_8_8 5543 mipaddr=00000000 (flags=200) 55440122e1e8: 0000: c0062d00 00010000 82024800 0108a806 001fe0ff 00000c14 00000000 00000200 5545t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5546 VGT_INDX_OFFSET: 0 55470122e208: 0000: c0012d00 00040102 00000000 5548t0 write TC_CNTL_STATUS (0e00) 5549 TC_CNTL_STATUS: { L2_INVALIDATE } 55500122e214: 0000: 00000e00 00000001 5551t3 opcode: CP_WAIT_REG_EQ (52) (5 dwords) 55520122e21c: 0000: c0035200 000005d0 00000000 00001000 00000001 5553t3 opcode: CP_DRAW_INDX_BIN (34) (7 dwords) 55540122e230: 0000: c0053400 00000000 0003c004 00000000 00000003 01009040 00000006 5555t0 write CP_SCRATCH_REG7 (057f) 5556 CP_SCRATCH_REG7: 97 5557 :0,0,101,97 55580122e24c: 0000: 0000057f 00000061 5559t3 opcode: CP_NOP (10) (2 dwords) 55600122e254: 0000: c0001000 00000000 5561t3 opcode: CP_DRAW_INDX (22) (3 dwords) 5562 { VIZ_QUERY = 0 } 5563 { PRIM_TYPE = DI_PT_TRIFAN | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | NUM_INSTANCES = 0 | 0x40000 } 5564 draw: 0 5565 prim_type: DI_PT_TRIFAN (5) 5566 source_select: DI_SRC_SEL_AUTO_INDEX (2) 5567 num_indices: 1407 5568 draw[16] register values 5569 + ffffffff RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE } 5570 + 00000fff RBBM_PM_OVERRIDE2: 0xfff 5571 + 00000000 CP_PERFMON_CNTL: 0 5572!+ 00000065 CP_SCRATCH_REG6: 101 5573 :0,0,101,97 5574!+ 00000061 CP_SCRATCH_REG7: 97 5575 :0,0,101,97 5576 + 00000180 SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 } 5577 + 00000001 TC_CNTL_STATUS: { L2_INVALIDATE } 5578 + 00000002 TP0_CHICKEN: 0x2 5579 + 1c004046 RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 } 5580!+ 00000020 RB_SURFACE_INFO: { SURFACE_PITCH = 32 | MSAA_SAMPLES = 0 } 5581!+ 01254245 RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | LINEAR | ENDIAN = 0 | SWAP = 1 | BASE = 0x1254000 } 5582 + 80000000 PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 } 5583!+ 00400020 PA_SC_SCREEN_SCISSOR_BR: { X = 32 | Y = 64 } 5584 + 00000000 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 } 5585 + 00000000 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 5586!+ 00400020 PA_SC_WINDOW_SCISSOR_BR: { X = 32 | Y = 64 } 5587 + ffffffff VGT_MAX_VTX_INDX: 0xffffffff 5588 + 00000000 VGT_MIN_VTX_INDX: 0 5589 + 00000000 VGT_INDX_OFFSET: 0 5590 + 0000000f RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 5591 + 00000000 RB_BLEND_RED: 0 5592 + 00000000 RB_BLEND_GREEN: 0 5593 + 00000000 RB_BLEND_BLUE: 0 5594 + 00000000 RB_BLEND_ALPHA: 0 5595 + 00000000 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 5596 + 00000000 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 5597 + 00000000 RB_ALPHA_REF: 0 5598!+ 41800000 PA_CL_VPORT_XSCALE: 16.000000 5599!+ 41800000 PA_CL_VPORT_XOFFSET: 16.000000 5600!+ 42000000 PA_CL_VPORT_YSCALE: 32.000000 5601!+ 42000000 PA_CL_VPORT_YOFFSET: 32.000000 5602!+ 00000000 PA_CL_VPORT_ZSCALE: 0.000000 5603!+ 00000000 PA_CL_VPORT_ZOFFSET: 0.000000 5604 + 10030002 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 } 5605 + 00000106 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 } 5606 + ffffffff SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 } 5607 + 00000000 SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 } 5608 + 00000000 SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 } 5609 + 00000000 RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP } 5610 + 00000000 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO } 5611!+ 00000c20 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 } 5612 + 00000000 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL } 5613!+ 00090244 PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST } 5614 + 0000043f PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT } 5615 + 00000004 RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH } 5616 + 88888888 RB_SAMPLE_POS: 0x88888888 5617!+ 00000000 PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 } 5618!+ 00000000 PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 } 5619!+ 00000000 PA_SU_LINE_CNTL: { WIDTH = 0.000000 } 5620 + 00000000 PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER } 5621 + 00000020 PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 } 5622 + 00000000 PA_SC_LINE_CNTL: { BRES_CNTL = 0 } 5623 + 00000000 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 } 5624 + 00000001 PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH } 5625 + 3f800000 PA_CL_GB_VERT_CLIP_ADJ: 1.000000 5626 + 3f800000 PA_CL_GB_VERT_DISC_ADJ: 1.000000 5627 + 3f800000 PA_CL_GB_HORZ_CLIP_ADJ: 1.000000 5628 + 3f800000 PA_CL_GB_HORZ_DISC_ADJ: 1.000000 5629 + 00100020 SQ_VS_CONST: { BASE = 32 | SIZE = 256 } 5630 + 000e0120 SQ_PS_CONST: { BASE = 288 | SIZE = 224 } 5631 + 0000ffff PA_SC_AA_MASK: 0xffff 5632 + 00000002 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 } 5633 + 00000002 VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 } 5634 + 0003c000 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 5635 + ffffffff RB_COLOR_DEST_MASK: 0xffffffff 56360122e25c: 0000: c0012200 00000000 00040085 5637t0 write CP_SCRATCH_REG7 (057f) 5638NEEDS WFI: CP_SCRATCH_REG7 (57f) 5639 CP_SCRATCH_REG7: 98 5640 :0,0,101,98 56410122e268: 0000: 0000057f 00000062 5642t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 56430122e270: 0000: c0002600 00000000 5644t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 5645 { EVENT = CACHE_FLUSH } 5646 event CACHE_FLUSH 56470122e278: 0000: c0004600 00000006 5648t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 5649 { EVENT = CACHE_FLUSH } 5650 event CACHE_FLUSH 56510122e280: 0000: c0004600 00000006 5652t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 5653 { EVENT = CACHE_FLUSH } 5654 event CACHE_FLUSH 56550122e288: 0000: c0004600 00000006 5656t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 5657 { EVENT = CACHE_FLUSH } 5658 event CACHE_FLUSH 56590122e290: 0000: c0004600 00000006 5660t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 5661 { EVENT = CACHE_FLUSH } 5662 event CACHE_FLUSH 56630122e298: 0000: c0004600 00000006 5664t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 5665 { EVENT = CACHE_FLUSH } 5666 event CACHE_FLUSH 56670122e2a0: 0000: c0004600 00000006 5668t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 5669 { EVENT = CACHE_FLUSH } 5670 event CACHE_FLUSH 56710122e2a8: 0000: c0004600 00000006 5672t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 5673 { EVENT = CACHE_FLUSH } 5674 event CACHE_FLUSH 56750122e2b0: 0000: c0004600 00000006 5676t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 5677 { EVENT = CACHE_FLUSH } 5678 event CACHE_FLUSH 56790122e2b8: 0000: c0004600 00000006 5680t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 5681 { EVENT = CACHE_FLUSH } 5682 event CACHE_FLUSH 56830122e2c0: 0000: c0004600 00000006 5684t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 5685 { EVENT = CACHE_FLUSH } 5686 event CACHE_FLUSH 56870122e2c8: 0000: c0004600 00000006 5688t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 5689 { EVENT = CACHE_FLUSH } 5690 event CACHE_FLUSH 56910122e2d0: 0000: c0004600 00000006 56920122d1d8: 0000: c0013700 0122e000 000000b6 5693t2 nop 5694############################################################ 5695vertices: 0 5696cmd: deqp-gles2/185: fence=1263 5697############################################################ 5698cmdstream: 124 dwords 5699t0 write RB_BC_CONTROL (0f01) 5700 RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 } 57010110a000: 0000: 00000f01 1c004046 5702t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5703 PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 } 57040110a008: 0000: c0012d00 00040293 00000020 5705t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5706 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 } 57070110a014: 0000: c0012d00 00040316 00000002 5708t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5709 VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 } 57100110a020: 0000: c0012d00 00040317 00000002 5711t0 write CP_PERFMON_CNTL (0444) 5712 CP_PERFMON_CNTL: 0 57130110a02c: 0000: 00000444 00000000 5714t0 write RBBM_PM_OVERRIDE1 (039c) 5715 RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE } 5716 RBBM_PM_OVERRIDE2: 0xfff 57170110a034: 0000: 0001039c ffffffff 00000fff 5718t0 write TP0_CHICKEN (0e1e) 5719 TP0_CHICKEN: 0x2 57200110a040: 0000: 00000e1e 00000002 5721t3 opcode: CP_INVALIDATE_STATE (3b) (2 dwords) 57220110a048: 0000: c0003b00 00007fff 5723t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5724 SQ_VS_CONST: { BASE = 32 | SIZE = 256 } 57250110a050: 0000: c0012d00 00040307 00100020 5726t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5727 SQ_PS_CONST: { BASE = 288 | SIZE = 224 } 57280110a05c: 0000: c0012d00 00040308 000e0120 5729t3 opcode: CP_SET_CONSTANT (2d) (4 dwords) 5730 VGT_MAX_VTX_INDX: 0xffffffff 5731 VGT_MIN_VTX_INDX: 0 57320110a068: 0000: c0022d00 00040100 ffffffff 00000000 5733t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5734 VGT_INDX_OFFSET: 0 57350110a078: 0000: c0012d00 00040102 00000000 5736t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5737 SQ_CONTEXT_MISC: { SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 } 57380110a084: 0000: c0012d00 00040181 00000004 5739t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5740 SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 } 57410110a090: 0000: c0012d00 00040182 ffffffff 5742t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5743 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 } 57440110a09c: 0000: c0012d00 00040301 00000000 5745t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5746 PA_SC_LINE_CNTL: { BRES_CNTL = 0 } 57470110a0a8: 0000: c0012d00 00040300 00000000 5748t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5749 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 } 57500110a0b4: 0000: c0012d00 00040080 00000000 5751t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5752 RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH } 57530110a0c0: 0000: c0012d00 00040208 00000004 5754t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5755 RB_SAMPLE_POS: 0x88888888 57560110a0cc: 0000: c0012d00 0004020a 88888888 5757t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5758 RB_COLOR_DEST_MASK: 0xffffffff 57590110a0d8: 0000: c0012d00 00040326 ffffffff 5760t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5761 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 57620110a0e4: 0000: c0012d00 0004031b 0003c000 5763t3 opcode: CP_SET_CONSTANT (2d) (4 dwords) 5764 SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 } 5765 SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 } 57660110a0f0: 0000: c0022d00 00040183 00000000 00000000 5767t3 opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords) 57680110a100: 0000: c0004b00 00000000 5769t3 opcode: CP_WAIT_REG_EQ (52) (5 dwords) 57700110a108: 0000: c0035200 000005d0 00000000 5f601000 00000001 5771t0 write SQ_INST_STORE_MANAGMENT (0d02) 5772 SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 } 57730110a11c: 0000: 00000d02 00000180 5774t3 opcode: CP_INVALIDATE_STATE (3b) (2 dwords) 57750110a124: 0000: c0003b00 00000300 5776t3 opcode: CP_SET_SHADER_BASES (4a) (2 dwords) 57770110a12c: 0000: c0004a00 80000180 5778t3 opcode: CP_SET_CONSTANT (2d) (14 dwords) 57790110a13c: 0.000000 0.000000 0.000000 0.000000 20000.000000 1.000000 0.500000 0.000000 57800110a15c: 2.000000 0.750000 0.375000 0.250000 57810110a134: 0000: c00c2d00 00000000 00000000 00000000 00000000 00000000 469c4000 3f800000 57820110a154: 0020: 3f000000 00000000 40000000 3f400000 3ec00000 3e800000 5783t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5784 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 57850110a16c: 0000: c0012d00 00040104 0000000f 5786t3 opcode: CP_SET_CONSTANT (2d) (6 dwords) 5787 RB_BLEND_RED: 0 5788 RB_BLEND_GREEN: 0 5789 RB_BLEND_BLUE: 0 5790 RB_BLEND_ALPHA: 0xff 57910110a178: 0000: c0042d00 00040105 00000000 00000000 00000000 000000ff 5792t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5793 PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT } 57940110a190: 0000: c0012d00 00040206 0000043f 5795t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5796 RB_SURFACE_INFO: { SURFACE_PITCH = 256 | MSAA_SAMPLES = 0 } 57970110a19c: 0000: c0012d00 00040000 00000100 5798t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5799 RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 1 | BASE = 0x108a000 } 58000110a1a8: 0000: c0012d00 00040001 0108a205 5801t3 opcode: CP_SET_CONSTANT (2d) (4 dwords) 5802 PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 } 5803 PA_SC_SCREEN_SCISSOR_BR: { X = 256 | Y = 256 } 58040110a1b4: 0000: c0022d00 0004000e 80000000 01000100 5805t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5806 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 } 58070110a1c4: 0000: c0012d00 00040080 00000000 5808t0 write CP_SCRATCH_REG6 (057e) 5809 CP_SCRATCH_REG6: 107 5810 :0,0,107,98 58110110a1d0: 0000: 0000057e 0000006b 5812t3 opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords) 5813 ibaddr:0110b000 5814 ibsize:000000b8 5815t3 opcode: CP_SET_CONSTANT (2d) (6 dwords) 5816 set shader const 0078 58170110b000: 0000: c0042d00 00010078 0112d65b 00100000 0112d69b 00100000 5818t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5819 PA_SC_AA_MASK: 0xffff 58200110b018: 0000: c0012d00 00040312 0000ffff 5821t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5822 RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP } 58230110b024: 0000: c0012d00 00040200 00000000 5824t3 opcode: CP_SET_CONSTANT (2d) (5 dwords) 5825 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 5826 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 5827 RB_ALPHA_REF: 0 58280110b030: 0000: c0032d00 0004010c 00000000 00000000 00000000 5829t3 opcode: CP_SET_CONSTANT (2d) (4 dwords) 5830 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL } 5831 PA_SU_SC_MODE_CNTL: { POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST } 58320110b044: 0000: c0022d00 00040204 00000000 00090240 5833t3 opcode: CP_SET_CONSTANT (2d) (6 dwords) 5834 PA_SU_POINT_SIZE: { HEIGHT = 0.500000 | WIDTH = 0.500000 } 5835 PA_SU_POINT_MINMAX: { MIN = 0.500000 | MAX = 0.500000 } 5836 PA_SU_LINE_CNTL: { WIDTH = 0.500000 } 5837 PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER } 58380110b054: 0000: c0042d00 00040280 00080008 00080008 00000008 00000000 5839t3 opcode: CP_SET_CONSTANT (2d) (7 dwords) 5840 PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH } 5841 PA_CL_GB_VERT_CLIP_ADJ: 1.000000 5842 PA_CL_GB_VERT_DISC_ADJ: 1.000000 5843 PA_CL_GB_HORZ_CLIP_ADJ: 1.000000 5844 PA_CL_GB_HORZ_DISC_ADJ: 1.000000 58450110b06c: 0000: c0052d00 00040302 00000001 3f800000 3f800000 3f800000 3f800000 5846t3 opcode: CP_SET_CONSTANT (2d) (4 dwords) 5847 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 5848 PA_SC_WINDOW_SCISSOR_BR: { X = 256 | Y = 256 } 58490110b088: 0000: c0022d00 00040081 00000000 01000100 5850t3 opcode: CP_SET_CONSTANT (2d) (8 dwords) 5851 PA_CL_VPORT_XSCALE: 128.000000 5852 PA_CL_VPORT_XOFFSET: 128.000000 5853 PA_CL_VPORT_YSCALE: -128.000000 5854 PA_CL_VPORT_YOFFSET: 128.000000 5855 PA_CL_VPORT_ZSCALE: 0.500000 5856 PA_CL_VPORT_ZOFFSET: 0.500000 58570110b098: 0000: c0062d00 0004010f 43000000 43000000 c3000000 43000000 3f000000 3f000000 5858t3 opcode: CP_SET_CONSTANT (2d) (10 dwords) 58590110b0c0: 128.000000 128.000000 0.500000 0.000000 128.000000 -128.000000 0.500000 0.000000 58600110b0b8: 0000: c0082d00 00000184 43000000 43000000 3f000000 00000000 43000000 c3000000 58610110b0d8: 0020: 3f000000 00000000 5862t3 opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords) 5863 vertex shader, start=0000, size=0015 5864 2003 0007 1000 EXEC ADDR(0x3) CNT(0x2) 5865 03: 19481000 00262688 00000010 (S)FETCH: VERTEX R1.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(16) CONST(20, 0) 5866 04: 13480000 40252fc8 00000008 FETCH: VERTEX R0.xy__ = R0.x FMT_32_32_FLOAT UNSIGNED STRIDE(8) CONST(20, 1) 5867 0000 0000 c200 ALLOC POSITION SIZE(0x0) 5868 1005 0002 1000 EXEC ADDR(0x5) CNT(0x1) 5869 05: 000f803e 00000000 c2010100 (S)ALU: MAXv export62 = R1, R1 ; gl_Position 5870 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0) 5871 1006 0000 2000 EXEC_END ADDR(0x6) CNT(0x1) 5872 06: 00038000 00000000 c2000000 ALU: MAXv export0.xy__ = R0, R0 5873 0000 0000 0000 NOP 58740110b0e0: 0000: c0162b00 00000000 00000015 00072003 00001000 c2000000 00021005 00001000 58750110b100: 0020: c4000000 00001006 00002000 00000000 19481000 00262688 00000010 13480000 58760110b120: 0040: 40252fc8 00000008 000f803e 00000000 c2010100 00038000 00000000 c2000000 5877t3 opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords) 5878 fragment shader, start=0000, size=000c 5879 1002 0003 1000 EXEC ADDR(0x2) CNT(0x1) 5880 02: 90000001 1ffff688 00000002 (S)FETCH: SAMPLE R0.xyzw = R0.xyz CONST(0) LOCATION(CENTER) 5881 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0) 5882 1003 0002 2000 EXEC_END ADDR(0x3) CNT(0x1) 5883 03: 000f8000 00000000 c2000000 (S)ALU: MAXv export0 = R0, R0 ; gl_FragColor 5884 0000 0000 0000 NOP 58850110b140: 0000: c00d2b00 00000001 0000000c 00031002 00001000 c4000000 00021003 00002000 58860110b160: 0020: 00000000 90000001 1ffff688 00000002 000f8000 00000000 c2000000 5887t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5888 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 } 58890110b17c: 0000: c0012d00 00040181 00000106 5890t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5891 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 } 58920110b188: 0000: c0012d00 00040180 10030002 5893t3 opcode: CP_SET_CONSTANT (2d) (6 dwords) 58940110b19c: 0.000000 0.000000 0.000000 0.000000 58950110b194: 0000: c0042d00 00000080 00000000 00000000 00000000 00000000 5896t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5897 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_ALWAYS | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 } 58980110b1ac: 0000: c0012d00 00040202 00001c20 5899t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5900 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO } 59010110b1b8: 0000: c0012d00 00040201 00000000 5902t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5903 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 59040110b1c4: 0000: c0012d00 00040104 0000000f 5905t3 opcode: CP_SET_CONSTANT (2d) (6 dwords) 5906 RB_BLEND_RED: 0 5907 RB_BLEND_GREEN: 0 5908 RB_BLEND_BLUE: 0 5909 RB_BLEND_ALPHA: 0 59100110b1d0: 0000: c0042d00 00040105 00000000 00000000 00000000 00000000 5911t3 opcode: CP_SET_CONSTANT (2d) (8 dwords) 5912 set texture const 0000 5913 clamp x/y/z: clamp-last-texel/clamp-last-texel/wrap 5914 filter min/mag: point/point 5915 swizzle: xyzw 5916 addr=01230000 (flags=820), size=64x128, pitch=16448, format=FMT_1_REVERSE 5917 mipaddr=01240000 (flags=200) 59180110b1e8: 0000: c0062d00 00010000 80804800 01230820 000fe03f 00000d11 000001c0 01240200 5919t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 5920 VGT_INDX_OFFSET: 0 59210110b208: 0000: c0012d00 00040102 00000000 5922t0 write TC_CNTL_STATUS (0e00) 5923 TC_CNTL_STATUS: { L2_INVALIDATE } 59240110b214: 0000: 00000e00 00000001 5925t3 opcode: CP_WAIT_REG_EQ (52) (5 dwords) 59260110b21c: 0000: c0035200 000005d0 00000000 00001000 00000001 5927t3 opcode: CP_DRAW_INDX_BIN (34) (7 dwords) 59280110b230: 0000: c0053400 00000000 0003c004 00000000 00000003 01009040 00000006 5929t0 write CP_SCRATCH_REG7 (057f) 5930 CP_SCRATCH_REG7: 103 5931 :0,0,107,103 59320110b24c: 0000: 0000057f 00000067 5933t3 opcode: CP_NOP (10) (2 dwords) 59340110b254: 0000: c0001000 00000000 5935t3 opcode: CP_DRAW_INDX (22) (5 dwords) 5936 { VIZ_QUERY = 0 } 5937 { PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_DMA | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | NUM_INSTANCES = 0 | 0x60000 } 5938 { NUM_INDICES = 18011832 } 5939 { INDX_BASE = 0xc } 5940 draw: 0 5941 prim_type: DI_PT_TRILIST (4) 5942 source_select: DI_SRC_SEL_DMA (0) 5943 num_indices: 18011832 5944 draw[17] register values 5945 + ffffffff RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE } 5946 + 00000fff RBBM_PM_OVERRIDE2: 0xfff 5947 + 00000000 CP_PERFMON_CNTL: 0 5948!+ 0000006b CP_SCRATCH_REG6: 107 5949 :0,0,107,103 5950!+ 00000067 CP_SCRATCH_REG7: 103 5951 :0,0,107,103 5952 + 00000180 SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 } 5953 + 00000001 TC_CNTL_STATUS: { L2_INVALIDATE } 5954 + 00000002 TP0_CHICKEN: 0x2 5955 + 1c004046 RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 } 5956!+ 00000100 RB_SURFACE_INFO: { SURFACE_PITCH = 256 | MSAA_SAMPLES = 0 } 5957!+ 0108a205 RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 1 | BASE = 0x108a000 } 5958 + 80000000 PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 } 5959!+ 01000100 PA_SC_SCREEN_SCISSOR_BR: { X = 256 | Y = 256 } 5960 + 00000000 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 } 5961 + 00000000 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 5962!+ 01000100 PA_SC_WINDOW_SCISSOR_BR: { X = 256 | Y = 256 } 5963 + ffffffff VGT_MAX_VTX_INDX: 0xffffffff 5964 + 00000000 VGT_MIN_VTX_INDX: 0 5965 + 00000000 VGT_INDX_OFFSET: 0 5966 + 0000000f RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 5967 + 00000000 RB_BLEND_RED: 0 5968 + 00000000 RB_BLEND_GREEN: 0 5969 + 00000000 RB_BLEND_BLUE: 0 5970 + 00000000 RB_BLEND_ALPHA: 0 5971 + 00000000 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 5972 + 00000000 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 5973 + 00000000 RB_ALPHA_REF: 0 5974!+ 43000000 PA_CL_VPORT_XSCALE: 128.000000 5975!+ 43000000 PA_CL_VPORT_XOFFSET: 128.000000 5976!+ c3000000 PA_CL_VPORT_YSCALE: -128.000000 5977!+ 43000000 PA_CL_VPORT_YOFFSET: 128.000000 5978!+ 3f000000 PA_CL_VPORT_ZSCALE: 0.500000 5979!+ 3f000000 PA_CL_VPORT_ZOFFSET: 0.500000 5980 + 10030002 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 } 5981 + 00000106 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 } 5982 + ffffffff SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 } 5983 + 00000000 SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 } 5984 + 00000000 SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 } 5985 + 00000000 RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP } 5986 + 00000000 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO } 5987!+ 00001c20 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_ALWAYS | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 } 5988 + 00000000 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL } 5989!+ 00090240 PA_SU_SC_MODE_CNTL: { POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST } 5990 + 0000043f PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT } 5991 + 00000004 RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH } 5992 + 88888888 RB_SAMPLE_POS: 0x88888888 5993!+ 00080008 PA_SU_POINT_SIZE: { HEIGHT = 0.500000 | WIDTH = 0.500000 } 5994!+ 00080008 PA_SU_POINT_MINMAX: { MIN = 0.500000 | MAX = 0.500000 } 5995!+ 00000008 PA_SU_LINE_CNTL: { WIDTH = 0.500000 } 5996 + 00000000 PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER } 5997 + 00000020 PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 } 5998 + 00000000 PA_SC_LINE_CNTL: { BRES_CNTL = 0 } 5999 + 00000000 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 } 6000 + 00000001 PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH } 6001 + 3f800000 PA_CL_GB_VERT_CLIP_ADJ: 1.000000 6002 + 3f800000 PA_CL_GB_VERT_DISC_ADJ: 1.000000 6003 + 3f800000 PA_CL_GB_HORZ_CLIP_ADJ: 1.000000 6004 + 3f800000 PA_CL_GB_HORZ_DISC_ADJ: 1.000000 6005 + 00100020 SQ_VS_CONST: { BASE = 32 | SIZE = 256 } 6006 + 000e0120 SQ_PS_CONST: { BASE = 288 | SIZE = 224 } 6007 + 0000ffff PA_SC_AA_MASK: 0xffff 6008 + 00000002 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 } 6009 + 00000002 VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 } 6010 + 0003c000 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 6011 + ffffffff RB_COLOR_DEST_MASK: 0xffffffff 60120110b25c: 0000: c0032200 00000000 00060004 0112d6b8 0000000c 6013t0 write CP_SCRATCH_REG7 (057f) 6014NEEDS WFI: CP_SCRATCH_REG7 (57f) 6015 CP_SCRATCH_REG7: 104 6016 :0,0,107,104 60170110b270: 0000: 0000057f 00000068 6018t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 60190110b278: 0000: c0002600 00000000 6020t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 6021 { EVENT = CACHE_FLUSH } 6022 event CACHE_FLUSH 60230110b280: 0000: c0004600 00000006 6024t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 6025 { EVENT = CACHE_FLUSH } 6026 event CACHE_FLUSH 60270110b288: 0000: c0004600 00000006 6028t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 6029 { EVENT = CACHE_FLUSH } 6030 event CACHE_FLUSH 60310110b290: 0000: c0004600 00000006 6032t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 6033 { EVENT = CACHE_FLUSH } 6034 event CACHE_FLUSH 60350110b298: 0000: c0004600 00000006 6036t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 6037 { EVENT = CACHE_FLUSH } 6038 event CACHE_FLUSH 60390110b2a0: 0000: c0004600 00000006 6040t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 6041 { EVENT = CACHE_FLUSH } 6042 event CACHE_FLUSH 60430110b2a8: 0000: c0004600 00000006 6044t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 6045 { EVENT = CACHE_FLUSH } 6046 event CACHE_FLUSH 60470110b2b0: 0000: c0004600 00000006 6048t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 6049 { EVENT = CACHE_FLUSH } 6050 event CACHE_FLUSH 60510110b2b8: 0000: c0004600 00000006 6052t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 6053 { EVENT = CACHE_FLUSH } 6054 event CACHE_FLUSH 60550110b2c0: 0000: c0004600 00000006 6056t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 6057 { EVENT = CACHE_FLUSH } 6058 event CACHE_FLUSH 60590110b2c8: 0000: c0004600 00000006 6060t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 6061 { EVENT = CACHE_FLUSH } 6062 event CACHE_FLUSH 60630110b2d0: 0000: c0004600 00000006 6064t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 6065 { EVENT = CACHE_FLUSH } 6066 event CACHE_FLUSH 60670110b2d8: 0000: c0004600 00000006 60680110a1d8: 0000: c0013700 0110b000 000000b8 6069t2 nop 6070############################################################ 6071vertices: 0 6072cmd: deqp-gles2/185: fence=1264 6073############################################################ 6074cmdstream: 124 dwords 6075t0 write RB_BC_CONTROL (0f01) 6076 RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 } 60770122f000: 0000: 00000f01 1c004046 6078t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6079 PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 } 60800122f008: 0000: c0012d00 00040293 00000020 6081t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6082 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 } 60830122f014: 0000: c0012d00 00040316 00000002 6084t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6085 VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 } 60860122f020: 0000: c0012d00 00040317 00000002 6087t0 write CP_PERFMON_CNTL (0444) 6088 CP_PERFMON_CNTL: 0 60890122f02c: 0000: 00000444 00000000 6090t0 write RBBM_PM_OVERRIDE1 (039c) 6091 RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE } 6092 RBBM_PM_OVERRIDE2: 0xfff 60930122f034: 0000: 0001039c ffffffff 00000fff 6094t0 write TP0_CHICKEN (0e1e) 6095 TP0_CHICKEN: 0x2 60960122f040: 0000: 00000e1e 00000002 6097t3 opcode: CP_INVALIDATE_STATE (3b) (2 dwords) 60980122f048: 0000: c0003b00 00007fff 6099t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6100 SQ_VS_CONST: { BASE = 32 | SIZE = 256 } 61010122f050: 0000: c0012d00 00040307 00100020 6102t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6103 SQ_PS_CONST: { BASE = 288 | SIZE = 224 } 61040122f05c: 0000: c0012d00 00040308 000e0120 6105t3 opcode: CP_SET_CONSTANT (2d) (4 dwords) 6106 VGT_MAX_VTX_INDX: 0xffffffff 6107 VGT_MIN_VTX_INDX: 0 61080122f068: 0000: c0022d00 00040100 ffffffff 00000000 6109t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6110 VGT_INDX_OFFSET: 0 61110122f078: 0000: c0012d00 00040102 00000000 6112t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6113 SQ_CONTEXT_MISC: { SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 } 61140122f084: 0000: c0012d00 00040181 00000004 6115t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6116 SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 } 61170122f090: 0000: c0012d00 00040182 ffffffff 6118t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6119 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 } 61200122f09c: 0000: c0012d00 00040301 00000000 6121t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6122 PA_SC_LINE_CNTL: { BRES_CNTL = 0 } 61230122f0a8: 0000: c0012d00 00040300 00000000 6124t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6125 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 } 61260122f0b4: 0000: c0012d00 00040080 00000000 6127t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6128 RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH } 61290122f0c0: 0000: c0012d00 00040208 00000004 6130t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6131 RB_SAMPLE_POS: 0x88888888 61320122f0cc: 0000: c0012d00 0004020a 88888888 6133t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6134 RB_COLOR_DEST_MASK: 0xffffffff 61350122f0d8: 0000: c0012d00 00040326 ffffffff 6136t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6137 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 61380122f0e4: 0000: c0012d00 0004031b 0003c000 6139t3 opcode: CP_SET_CONSTANT (2d) (4 dwords) 6140 SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 } 6141 SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 } 61420122f0f0: 0000: c0022d00 00040183 00000000 00000000 6143t3 opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords) 61440122f100: 0000: c0004b00 00000000 6145t3 opcode: CP_WAIT_REG_EQ (52) (5 dwords) 61460122f108: 0000: c0035200 000005d0 00000000 5f601000 00000001 6147t0 write SQ_INST_STORE_MANAGMENT (0d02) 6148 SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 } 61490122f11c: 0000: 00000d02 00000180 6150t3 opcode: CP_INVALIDATE_STATE (3b) (2 dwords) 61510122f124: 0000: c0003b00 00000300 6152t3 opcode: CP_SET_SHADER_BASES (4a) (2 dwords) 61530122f12c: 0000: c0004a00 80000180 6154t3 opcode: CP_SET_CONSTANT (2d) (14 dwords) 61550122f13c: 0.000000 0.000000 0.000000 0.000000 20000.000000 1.000000 0.500000 0.000000 61560122f15c: 2.000000 0.750000 0.375000 0.250000 61570122f134: 0000: c00c2d00 00000000 00000000 00000000 00000000 00000000 469c4000 3f800000 61580122f154: 0020: 3f000000 00000000 40000000 3f400000 3ec00000 3e800000 6159t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6160 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 61610122f16c: 0000: c0012d00 00040104 0000000f 6162t3 opcode: CP_SET_CONSTANT (2d) (6 dwords) 6163 RB_BLEND_RED: 0 6164 RB_BLEND_GREEN: 0 6165 RB_BLEND_BLUE: 0 6166 RB_BLEND_ALPHA: 0xff 61670122f178: 0000: c0042d00 00040105 00000000 00000000 00000000 000000ff 6168t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6169 PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT } 61700122f190: 0000: c0012d00 00040206 0000043f 6171t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6172 RB_SURFACE_INFO: { SURFACE_PITCH = 32 | MSAA_SAMPLES = 0 } 61730122f19c: 0000: c0012d00 00040000 00000020 6174t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6175 RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | LINEAR | ENDIAN = 0 | SWAP = 1 | BASE = 0x1266000 } 61760122f1a8: 0000: c0012d00 00040001 01266245 6177t3 opcode: CP_SET_CONSTANT (2d) (4 dwords) 6178 PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 } 6179 PA_SC_SCREEN_SCISSOR_BR: { X = 16 | Y = 32 } 61800122f1b4: 0000: c0022d00 0004000e 80000000 00200010 6181t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6182 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 } 61830122f1c4: 0000: c0012d00 00040080 00000000 6184t0 write CP_SCRATCH_REG6 (057e) 6185 CP_SCRATCH_REG6: 113 6186 :0,0,113,104 61870122f1d0: 0000: 0000057e 00000071 6188t3 opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords) 6189 ibaddr:0122e000 6190 ibsize:000000b6 6191t3 opcode: CP_SET_CONSTANT (2d) (6 dwords) 6192 set shader const 0078 61930122e000: 0000: c0042d00 00010078 0112d6c7 00100000 0112d6c7 00100000 6194t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6195 PA_SC_AA_MASK: 0xffff 61960122e018: 0000: c0012d00 00040312 0000ffff 6197t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6198 RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP } 61990122e024: 0000: c0012d00 00040200 00000000 6200t3 opcode: CP_SET_CONSTANT (2d) (5 dwords) 6201 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 6202 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 6203 RB_ALPHA_REF: 0 62040122e030: 0000: c0032d00 0004010c 00000000 00000000 00000000 6205t3 opcode: CP_SET_CONSTANT (2d) (4 dwords) 6206 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL } 6207 PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST } 62080122e044: 0000: c0022d00 00040204 00000000 00090244 6209t3 opcode: CP_SET_CONSTANT (2d) (6 dwords) 6210 PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 } 6211 PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 } 6212 PA_SU_LINE_CNTL: { WIDTH = 0.000000 } 6213 PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER } 62140122e054: 0000: c0042d00 00040280 00000000 00000000 00000000 00000000 6215t3 opcode: CP_SET_CONSTANT (2d) (7 dwords) 6216 PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH } 6217 PA_CL_GB_VERT_CLIP_ADJ: 1.000000 6218 PA_CL_GB_VERT_DISC_ADJ: 1.000000 6219 PA_CL_GB_HORZ_CLIP_ADJ: 1.000000 6220 PA_CL_GB_HORZ_DISC_ADJ: 1.000000 62210122e06c: 0000: c0052d00 00040302 00000001 3f800000 3f800000 3f800000 3f800000 6222t3 opcode: CP_SET_CONSTANT (2d) (4 dwords) 6223 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 6224 PA_SC_WINDOW_SCISSOR_BR: { X = 16 | Y = 32 } 62250122e088: 0000: c0022d00 00040081 00000000 00200010 6226t3 opcode: CP_SET_CONSTANT (2d) (8 dwords) 6227 PA_CL_VPORT_XSCALE: 8.000000 6228 PA_CL_VPORT_XOFFSET: 8.000000 6229 PA_CL_VPORT_YSCALE: 16.000000 6230 PA_CL_VPORT_YOFFSET: 16.000000 6231 PA_CL_VPORT_ZSCALE: 0.000000 6232 PA_CL_VPORT_ZOFFSET: 0.000000 62330122e098: 0000: c0062d00 0004010f 41000000 41000000 41800000 41800000 00000000 00000000 6234t3 opcode: CP_SET_CONSTANT (2d) (10 dwords) 62350122e0c0: 8.000000 16.000000 0.000000 0.000000 8.000000 16.000000 0.000000 0.000000 62360122e0b8: 0000: c0082d00 00000184 41000000 41800000 00000000 00000000 41000000 41800000 6237* 6238t3 opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords) 6239 vertex shader, start=0000, size=0015 6240 2003 0007 1000 EXEC ADDR(0x3) CNT(0x2) 6241 03: 19481000 00262688 00000020 (S)FETCH: VERTEX R1.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) CONST(20, 0) 6242 04: 13480000 40262688 00001020 FETCH: VERTEX R0.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) OFFSET(16) CONST(20, 1) 6243 0000 0000 c200 ALLOC POSITION SIZE(0x0) 6244 1005 0002 1000 EXEC ADDR(0x5) CNT(0x1) 6245 05: 000f803e 00000000 c2010100 (S)ALU: MAXv export62 = R1, R1 ; gl_Position 6246 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0) 6247 1006 0000 2000 EXEC_END ADDR(0x6) CNT(0x1) 6248 06: 000f8000 00000000 c2000000 ALU: MAXv export0 = R0, R0 6249 0000 0000 0000 NOP 62500122e0e0: 0000: c0162b00 00000000 00000015 00072003 00001000 c2000000 00021005 00001000 62510122e100: 0020: c4000000 00001006 00002000 00000000 19481000 00262688 00000020 13480000 62520122e120: 0040: 40262688 00001020 000f803e 00000000 c2010100 000f8000 00000000 c2000000 6253t3 opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords) 6254 fragment shader, start=0000, size=000c 6255 1002 0003 1000 EXEC ADDR(0x2) CNT(0x1) 6256 02: 90000001 1ffff688 00000002 (S)FETCH: SAMPLE R0.xyzw = R0.xyz CONST(0) LOCATION(CENTER) 6257 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0) 6258 1003 0002 2000 EXEC_END ADDR(0x3) CNT(0x1) 6259 03: 000f8000 00000000 c2000000 (S)ALU: MAXv export0 = R0, R0 ; gl_FragColor 6260 0000 0000 0000 NOP 62610122e140: 0000: c00d2b00 00000001 0000000c 00031002 00001000 c4000000 00021003 00002000 62620122e160: 0020: 00000000 90000001 1ffff688 00000002 000f8000 00000000 c2000000 6263t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6264 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 } 62650122e17c: 0000: c0012d00 00040181 00000106 6266t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6267 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 } 62680122e188: 0000: c0012d00 00040180 10030002 6269t3 opcode: CP_SET_CONSTANT (2d) (6 dwords) 62700122e19c: 0.000000 0.000000 0.000000 0.000000 62710122e194: 0000: c0042d00 00000080 00000000 00000000 00000000 00000000 6272t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6273 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 } 62740122e1ac: 0000: c0012d00 00040202 00000c20 6275t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6276 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO } 62770122e1b8: 0000: c0012d00 00040201 00000000 6278t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6279 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 62800122e1c4: 0000: c0012d00 00040104 0000000f 6281t3 opcode: CP_SET_CONSTANT (2d) (6 dwords) 6282 RB_BLEND_RED: 0 6283 RB_BLEND_GREEN: 0 6284 RB_BLEND_BLUE: 0 6285 RB_BLEND_ALPHA: 0 62860122e1d0: 0000: c0042d00 00040105 00000000 00000000 00000000 00000000 6287t3 opcode: CP_SET_CONSTANT (2d) (8 dwords) 6288 set texture const 0000 6289 clamp x/y/z: clamp-last-texel/clamp-last-texel/clamp-last-texel 6290 filter min/mag: point/point 6291 swizzle: zyxw 6292 addr=0108a000 (flags=806), size=256x256, pitch=16640, format=FMT_8_8_8_8 6293 mipaddr=00000000 (flags=200) 62940122e1e8: 0000: c0062d00 00010000 82024800 0108a806 001fe0ff 00000c14 00000000 00000200 6295t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6296 VGT_INDX_OFFSET: 0 62970122e208: 0000: c0012d00 00040102 00000000 6298t0 write TC_CNTL_STATUS (0e00) 6299 TC_CNTL_STATUS: { L2_INVALIDATE } 63000122e214: 0000: 00000e00 00000001 6301t3 opcode: CP_WAIT_REG_EQ (52) (5 dwords) 63020122e21c: 0000: c0035200 000005d0 00000000 00001000 00000001 6303t3 opcode: CP_DRAW_INDX_BIN (34) (7 dwords) 63040122e230: 0000: c0053400 00000000 0003c004 00000000 00000003 01009040 00000006 6305t0 write CP_SCRATCH_REG7 (057f) 6306 CP_SCRATCH_REG7: 109 6307 :0,0,113,109 63080122e24c: 0000: 0000057f 0000006d 6309t3 opcode: CP_NOP (10) (2 dwords) 63100122e254: 0000: c0001000 00000000 6311t3 opcode: CP_DRAW_INDX (22) (3 dwords) 6312 { VIZ_QUERY = 0 } 6313 { PRIM_TYPE = DI_PT_TRIFAN | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | NUM_INSTANCES = 0 | 0x40000 } 6314 draw: 0 6315 prim_type: DI_PT_TRIFAN (5) 6316 source_select: DI_SRC_SEL_AUTO_INDEX (2) 6317 num_indices: 1407 6318 draw[18] register values 6319 + ffffffff RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE } 6320 + 00000fff RBBM_PM_OVERRIDE2: 0xfff 6321 + 00000000 CP_PERFMON_CNTL: 0 6322!+ 00000071 CP_SCRATCH_REG6: 113 6323 :0,0,113,109 6324!+ 0000006d CP_SCRATCH_REG7: 109 6325 :0,0,113,109 6326 + 00000180 SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 } 6327 + 00000001 TC_CNTL_STATUS: { L2_INVALIDATE } 6328 + 00000002 TP0_CHICKEN: 0x2 6329 + 1c004046 RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 } 6330!+ 00000020 RB_SURFACE_INFO: { SURFACE_PITCH = 32 | MSAA_SAMPLES = 0 } 6331!+ 01266245 RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | LINEAR | ENDIAN = 0 | SWAP = 1 | BASE = 0x1266000 } 6332 + 80000000 PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 } 6333!+ 00200010 PA_SC_SCREEN_SCISSOR_BR: { X = 16 | Y = 32 } 6334 + 00000000 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 } 6335 + 00000000 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 6336!+ 00200010 PA_SC_WINDOW_SCISSOR_BR: { X = 16 | Y = 32 } 6337 + ffffffff VGT_MAX_VTX_INDX: 0xffffffff 6338 + 00000000 VGT_MIN_VTX_INDX: 0 6339 + 00000000 VGT_INDX_OFFSET: 0 6340 + 0000000f RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 6341 + 00000000 RB_BLEND_RED: 0 6342 + 00000000 RB_BLEND_GREEN: 0 6343 + 00000000 RB_BLEND_BLUE: 0 6344 + 00000000 RB_BLEND_ALPHA: 0 6345 + 00000000 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 6346 + 00000000 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 6347 + 00000000 RB_ALPHA_REF: 0 6348!+ 41000000 PA_CL_VPORT_XSCALE: 8.000000 6349!+ 41000000 PA_CL_VPORT_XOFFSET: 8.000000 6350!+ 41800000 PA_CL_VPORT_YSCALE: 16.000000 6351!+ 41800000 PA_CL_VPORT_YOFFSET: 16.000000 6352!+ 00000000 PA_CL_VPORT_ZSCALE: 0.000000 6353!+ 00000000 PA_CL_VPORT_ZOFFSET: 0.000000 6354 + 10030002 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 } 6355 + 00000106 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 } 6356 + ffffffff SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 } 6357 + 00000000 SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 } 6358 + 00000000 SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 } 6359 + 00000000 RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP } 6360 + 00000000 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO } 6361!+ 00000c20 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 } 6362 + 00000000 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL } 6363!+ 00090244 PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST } 6364 + 0000043f PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT } 6365 + 00000004 RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH } 6366 + 88888888 RB_SAMPLE_POS: 0x88888888 6367!+ 00000000 PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 } 6368!+ 00000000 PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 } 6369!+ 00000000 PA_SU_LINE_CNTL: { WIDTH = 0.000000 } 6370 + 00000000 PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER } 6371 + 00000020 PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 } 6372 + 00000000 PA_SC_LINE_CNTL: { BRES_CNTL = 0 } 6373 + 00000000 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 } 6374 + 00000001 PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH } 6375 + 3f800000 PA_CL_GB_VERT_CLIP_ADJ: 1.000000 6376 + 3f800000 PA_CL_GB_VERT_DISC_ADJ: 1.000000 6377 + 3f800000 PA_CL_GB_HORZ_CLIP_ADJ: 1.000000 6378 + 3f800000 PA_CL_GB_HORZ_DISC_ADJ: 1.000000 6379 + 00100020 SQ_VS_CONST: { BASE = 32 | SIZE = 256 } 6380 + 000e0120 SQ_PS_CONST: { BASE = 288 | SIZE = 224 } 6381 + 0000ffff PA_SC_AA_MASK: 0xffff 6382 + 00000002 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 } 6383 + 00000002 VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 } 6384 + 0003c000 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 6385 + ffffffff RB_COLOR_DEST_MASK: 0xffffffff 63860122e25c: 0000: c0012200 00000000 00040085 6387t0 write CP_SCRATCH_REG7 (057f) 6388NEEDS WFI: CP_SCRATCH_REG7 (57f) 6389 CP_SCRATCH_REG7: 110 6390 :0,0,113,110 63910122e268: 0000: 0000057f 0000006e 6392t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 63930122e270: 0000: c0002600 00000000 6394t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 6395 { EVENT = CACHE_FLUSH } 6396 event CACHE_FLUSH 63970122e278: 0000: c0004600 00000006 6398t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 6399 { EVENT = CACHE_FLUSH } 6400 event CACHE_FLUSH 64010122e280: 0000: c0004600 00000006 6402t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 6403 { EVENT = CACHE_FLUSH } 6404 event CACHE_FLUSH 64050122e288: 0000: c0004600 00000006 6406t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 6407 { EVENT = CACHE_FLUSH } 6408 event CACHE_FLUSH 64090122e290: 0000: c0004600 00000006 6410t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 6411 { EVENT = CACHE_FLUSH } 6412 event CACHE_FLUSH 64130122e298: 0000: c0004600 00000006 6414t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 6415 { EVENT = CACHE_FLUSH } 6416 event CACHE_FLUSH 64170122e2a0: 0000: c0004600 00000006 6418t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 6419 { EVENT = CACHE_FLUSH } 6420 event CACHE_FLUSH 64210122e2a8: 0000: c0004600 00000006 6422t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 6423 { EVENT = CACHE_FLUSH } 6424 event CACHE_FLUSH 64250122e2b0: 0000: c0004600 00000006 6426t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 6427 { EVENT = CACHE_FLUSH } 6428 event CACHE_FLUSH 64290122e2b8: 0000: c0004600 00000006 6430t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 6431 { EVENT = CACHE_FLUSH } 6432 event CACHE_FLUSH 64330122e2c0: 0000: c0004600 00000006 6434t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 6435 { EVENT = CACHE_FLUSH } 6436 event CACHE_FLUSH 64370122e2c8: 0000: c0004600 00000006 6438t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 6439 { EVENT = CACHE_FLUSH } 6440 event CACHE_FLUSH 64410122e2d0: 0000: c0004600 00000006 64420122f1d8: 0000: c0013700 0122e000 000000b6 6443t2 nop 6444############################################################ 6445vertices: 0 6446cmd: deqp-gles2/185: fence=1265 6447############################################################ 6448cmdstream: 124 dwords 6449t0 write RB_BC_CONTROL (0f01) 6450 RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 } 64510110c000: 0000: 00000f01 1c004046 6452t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6453 PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 } 64540110c008: 0000: c0012d00 00040293 00000020 6455t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6456 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 } 64570110c014: 0000: c0012d00 00040316 00000002 6458t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6459 VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 } 64600110c020: 0000: c0012d00 00040317 00000002 6461t0 write CP_PERFMON_CNTL (0444) 6462 CP_PERFMON_CNTL: 0 64630110c02c: 0000: 00000444 00000000 6464t0 write RBBM_PM_OVERRIDE1 (039c) 6465 RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE } 6466 RBBM_PM_OVERRIDE2: 0xfff 64670110c034: 0000: 0001039c ffffffff 00000fff 6468t0 write TP0_CHICKEN (0e1e) 6469 TP0_CHICKEN: 0x2 64700110c040: 0000: 00000e1e 00000002 6471t3 opcode: CP_INVALIDATE_STATE (3b) (2 dwords) 64720110c048: 0000: c0003b00 00007fff 6473t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6474 SQ_VS_CONST: { BASE = 32 | SIZE = 256 } 64750110c050: 0000: c0012d00 00040307 00100020 6476t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6477 SQ_PS_CONST: { BASE = 288 | SIZE = 224 } 64780110c05c: 0000: c0012d00 00040308 000e0120 6479t3 opcode: CP_SET_CONSTANT (2d) (4 dwords) 6480 VGT_MAX_VTX_INDX: 0xffffffff 6481 VGT_MIN_VTX_INDX: 0 64820110c068: 0000: c0022d00 00040100 ffffffff 00000000 6483t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6484 VGT_INDX_OFFSET: 0 64850110c078: 0000: c0012d00 00040102 00000000 6486t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6487 SQ_CONTEXT_MISC: { SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 } 64880110c084: 0000: c0012d00 00040181 00000004 6489t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6490 SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 } 64910110c090: 0000: c0012d00 00040182 ffffffff 6492t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6493 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 } 64940110c09c: 0000: c0012d00 00040301 00000000 6495t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6496 PA_SC_LINE_CNTL: { BRES_CNTL = 0 } 64970110c0a8: 0000: c0012d00 00040300 00000000 6498t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6499 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 } 65000110c0b4: 0000: c0012d00 00040080 00000000 6501t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6502 RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH } 65030110c0c0: 0000: c0012d00 00040208 00000004 6504t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6505 RB_SAMPLE_POS: 0x88888888 65060110c0cc: 0000: c0012d00 0004020a 88888888 6507t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6508 RB_COLOR_DEST_MASK: 0xffffffff 65090110c0d8: 0000: c0012d00 00040326 ffffffff 6510t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6511 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 65120110c0e4: 0000: c0012d00 0004031b 0003c000 6513t3 opcode: CP_SET_CONSTANT (2d) (4 dwords) 6514 SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 } 6515 SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 } 65160110c0f0: 0000: c0022d00 00040183 00000000 00000000 6517t3 opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords) 65180110c100: 0000: c0004b00 00000000 6519t3 opcode: CP_WAIT_REG_EQ (52) (5 dwords) 65200110c108: 0000: c0035200 000005d0 00000000 5f601000 00000001 6521t0 write SQ_INST_STORE_MANAGMENT (0d02) 6522 SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 } 65230110c11c: 0000: 00000d02 00000180 6524t3 opcode: CP_INVALIDATE_STATE (3b) (2 dwords) 65250110c124: 0000: c0003b00 00000300 6526t3 opcode: CP_SET_SHADER_BASES (4a) (2 dwords) 65270110c12c: 0000: c0004a00 80000180 6528t3 opcode: CP_SET_CONSTANT (2d) (14 dwords) 65290110c13c: 0.000000 0.000000 0.000000 0.000000 20000.000000 1.000000 0.500000 0.000000 65300110c15c: 2.000000 0.750000 0.375000 0.250000 65310110c134: 0000: c00c2d00 00000000 00000000 00000000 00000000 00000000 469c4000 3f800000 65320110c154: 0020: 3f000000 00000000 40000000 3f400000 3ec00000 3e800000 6533t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6534 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 65350110c16c: 0000: c0012d00 00040104 0000000f 6536t3 opcode: CP_SET_CONSTANT (2d) (6 dwords) 6537 RB_BLEND_RED: 0 6538 RB_BLEND_GREEN: 0 6539 RB_BLEND_BLUE: 0 6540 RB_BLEND_ALPHA: 0xff 65410110c178: 0000: c0042d00 00040105 00000000 00000000 00000000 000000ff 6542t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6543 PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT } 65440110c190: 0000: c0012d00 00040206 0000043f 6545t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6546 RB_SURFACE_INFO: { SURFACE_PITCH = 256 | MSAA_SAMPLES = 0 } 65470110c19c: 0000: c0012d00 00040000 00000100 6548t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6549 RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 1 | BASE = 0x108a000 } 65500110c1a8: 0000: c0012d00 00040001 0108a205 6551t3 opcode: CP_SET_CONSTANT (2d) (4 dwords) 6552 PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 } 6553 PA_SC_SCREEN_SCISSOR_BR: { X = 256 | Y = 256 } 65540110c1b4: 0000: c0022d00 0004000e 80000000 01000100 6555t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6556 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 } 65570110c1c4: 0000: c0012d00 00040080 00000000 6558t0 write CP_SCRATCH_REG6 (057e) 6559 CP_SCRATCH_REG6: 119 6560 :0,0,119,110 65610110c1d0: 0000: 0000057e 00000077 6562t3 opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords) 6563 ibaddr:0110b000 6564 ibsize:000000b8 6565t3 opcode: CP_SET_CONSTANT (2d) (6 dwords) 6566 set shader const 0078 65670110b000: 0000: c0042d00 00010078 0112d747 00100000 0112d787 00100000 6568t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6569 PA_SC_AA_MASK: 0xffff 65700110b018: 0000: c0012d00 00040312 0000ffff 6571t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6572 RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP } 65730110b024: 0000: c0012d00 00040200 00000000 6574t3 opcode: CP_SET_CONSTANT (2d) (5 dwords) 6575 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 6576 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 6577 RB_ALPHA_REF: 0 65780110b030: 0000: c0032d00 0004010c 00000000 00000000 00000000 6579t3 opcode: CP_SET_CONSTANT (2d) (4 dwords) 6580 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL } 6581 PA_SU_SC_MODE_CNTL: { POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST } 65820110b044: 0000: c0022d00 00040204 00000000 00090240 6583t3 opcode: CP_SET_CONSTANT (2d) (6 dwords) 6584 PA_SU_POINT_SIZE: { HEIGHT = 0.500000 | WIDTH = 0.500000 } 6585 PA_SU_POINT_MINMAX: { MIN = 0.500000 | MAX = 0.500000 } 6586 PA_SU_LINE_CNTL: { WIDTH = 0.500000 } 6587 PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER } 65880110b054: 0000: c0042d00 00040280 00080008 00080008 00000008 00000000 6589t3 opcode: CP_SET_CONSTANT (2d) (7 dwords) 6590 PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH } 6591 PA_CL_GB_VERT_CLIP_ADJ: 1.000000 6592 PA_CL_GB_VERT_DISC_ADJ: 1.000000 6593 PA_CL_GB_HORZ_CLIP_ADJ: 1.000000 6594 PA_CL_GB_HORZ_DISC_ADJ: 1.000000 65950110b06c: 0000: c0052d00 00040302 00000001 3f800000 3f800000 3f800000 3f800000 6596t3 opcode: CP_SET_CONSTANT (2d) (4 dwords) 6597 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 6598 PA_SC_WINDOW_SCISSOR_BR: { X = 256 | Y = 256 } 65990110b088: 0000: c0022d00 00040081 00000000 01000100 6600t3 opcode: CP_SET_CONSTANT (2d) (8 dwords) 6601 PA_CL_VPORT_XSCALE: 128.000000 6602 PA_CL_VPORT_XOFFSET: 128.000000 6603 PA_CL_VPORT_YSCALE: -128.000000 6604 PA_CL_VPORT_YOFFSET: 128.000000 6605 PA_CL_VPORT_ZSCALE: 0.500000 6606 PA_CL_VPORT_ZOFFSET: 0.500000 66070110b098: 0000: c0062d00 0004010f 43000000 43000000 c3000000 43000000 3f000000 3f000000 6608t3 opcode: CP_SET_CONSTANT (2d) (10 dwords) 66090110b0c0: 128.000000 128.000000 0.500000 0.000000 128.000000 -128.000000 0.500000 0.000000 66100110b0b8: 0000: c0082d00 00000184 43000000 43000000 3f000000 00000000 43000000 c3000000 66110110b0d8: 0020: 3f000000 00000000 6612t3 opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords) 6613 vertex shader, start=0000, size=0015 6614 2003 0007 1000 EXEC ADDR(0x3) CNT(0x2) 6615 03: 19481000 00262688 00000010 (S)FETCH: VERTEX R1.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(16) CONST(20, 0) 6616 04: 13480000 40252fc8 00000008 FETCH: VERTEX R0.xy__ = R0.x FMT_32_32_FLOAT UNSIGNED STRIDE(8) CONST(20, 1) 6617 0000 0000 c200 ALLOC POSITION SIZE(0x0) 6618 1005 0002 1000 EXEC ADDR(0x5) CNT(0x1) 6619 05: 000f803e 00000000 c2010100 (S)ALU: MAXv export62 = R1, R1 ; gl_Position 6620 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0) 6621 1006 0000 2000 EXEC_END ADDR(0x6) CNT(0x1) 6622 06: 00038000 00000000 c2000000 ALU: MAXv export0.xy__ = R0, R0 6623 0000 0000 0000 NOP 66240110b0e0: 0000: c0162b00 00000000 00000015 00072003 00001000 c2000000 00021005 00001000 66250110b100: 0020: c4000000 00001006 00002000 00000000 19481000 00262688 00000010 13480000 66260110b120: 0040: 40252fc8 00000008 000f803e 00000000 c2010100 00038000 00000000 c2000000 6627t3 opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords) 6628 fragment shader, start=0000, size=000c 6629 1002 0003 1000 EXEC ADDR(0x2) CNT(0x1) 6630 02: 90000001 1ffff688 00000002 (S)FETCH: SAMPLE R0.xyzw = R0.xyz CONST(0) LOCATION(CENTER) 6631 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0) 6632 1003 0002 2000 EXEC_END ADDR(0x3) CNT(0x1) 6633 03: 000f8000 00000000 c2000000 (S)ALU: MAXv export0 = R0, R0 ; gl_FragColor 6634 0000 0000 0000 NOP 66350110b140: 0000: c00d2b00 00000001 0000000c 00031002 00001000 c4000000 00021003 00002000 66360110b160: 0020: 00000000 90000001 1ffff688 00000002 000f8000 00000000 c2000000 6637t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6638 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 } 66390110b17c: 0000: c0012d00 00040181 00000106 6640t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6641 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 } 66420110b188: 0000: c0012d00 00040180 10030002 6643t3 opcode: CP_SET_CONSTANT (2d) (6 dwords) 66440110b19c: 0.000000 0.000000 0.000000 0.000000 66450110b194: 0000: c0042d00 00000080 00000000 00000000 00000000 00000000 6646t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6647 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_ALWAYS | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 } 66480110b1ac: 0000: c0012d00 00040202 00001c20 6649t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6650 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO } 66510110b1b8: 0000: c0012d00 00040201 00000000 6652t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6653 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 66540110b1c4: 0000: c0012d00 00040104 0000000f 6655t3 opcode: CP_SET_CONSTANT (2d) (6 dwords) 6656 RB_BLEND_RED: 0 6657 RB_BLEND_GREEN: 0 6658 RB_BLEND_BLUE: 0 6659 RB_BLEND_ALPHA: 0 66600110b1d0: 0000: c0042d00 00040105 00000000 00000000 00000000 00000000 6661t3 opcode: CP_SET_CONSTANT (2d) (8 dwords) 6662 set texture const 0000 6663 clamp x/y/z: clamp-last-texel/clamp-last-texel/wrap 6664 filter min/mag: point/point 6665 swizzle: xyzw 6666 addr=01230000 (flags=820), size=64x128, pitch=16448, format=FMT_1_REVERSE 6667 mipaddr=01240000 (flags=200) 66680110b1e8: 0000: c0062d00 00010000 80804800 01230820 000fe03f 00000d11 000001c0 01240200 6669t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6670 VGT_INDX_OFFSET: 0 66710110b208: 0000: c0012d00 00040102 00000000 6672t0 write TC_CNTL_STATUS (0e00) 6673 TC_CNTL_STATUS: { L2_INVALIDATE } 66740110b214: 0000: 00000e00 00000001 6675t3 opcode: CP_WAIT_REG_EQ (52) (5 dwords) 66760110b21c: 0000: c0035200 000005d0 00000000 00001000 00000001 6677t3 opcode: CP_DRAW_INDX_BIN (34) (7 dwords) 66780110b230: 0000: c0053400 00000000 0003c004 00000000 00000003 01009040 00000006 6679t0 write CP_SCRATCH_REG7 (057f) 6680 CP_SCRATCH_REG7: 115 6681 :0,0,119,115 66820110b24c: 0000: 0000057f 00000073 6683t3 opcode: CP_NOP (10) (2 dwords) 66840110b254: 0000: c0001000 00000000 6685t3 opcode: CP_DRAW_INDX (22) (5 dwords) 6686 { VIZ_QUERY = 0 } 6687 { PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_DMA | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | NUM_INSTANCES = 0 | 0x60000 } 6688 { NUM_INDICES = 18012068 } 6689 { INDX_BASE = 0xc } 6690 draw: 0 6691 prim_type: DI_PT_TRILIST (4) 6692 source_select: DI_SRC_SEL_DMA (0) 6693 num_indices: 18012068 6694 draw[19] register values 6695 + ffffffff RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE } 6696 + 00000fff RBBM_PM_OVERRIDE2: 0xfff 6697 + 00000000 CP_PERFMON_CNTL: 0 6698!+ 00000077 CP_SCRATCH_REG6: 119 6699 :0,0,119,115 6700!+ 00000073 CP_SCRATCH_REG7: 115 6701 :0,0,119,115 6702 + 00000180 SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 } 6703 + 00000001 TC_CNTL_STATUS: { L2_INVALIDATE } 6704 + 00000002 TP0_CHICKEN: 0x2 6705 + 1c004046 RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 } 6706!+ 00000100 RB_SURFACE_INFO: { SURFACE_PITCH = 256 | MSAA_SAMPLES = 0 } 6707!+ 0108a205 RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 1 | BASE = 0x108a000 } 6708 + 80000000 PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 } 6709!+ 01000100 PA_SC_SCREEN_SCISSOR_BR: { X = 256 | Y = 256 } 6710 + 00000000 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 } 6711 + 00000000 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 6712!+ 01000100 PA_SC_WINDOW_SCISSOR_BR: { X = 256 | Y = 256 } 6713 + ffffffff VGT_MAX_VTX_INDX: 0xffffffff 6714 + 00000000 VGT_MIN_VTX_INDX: 0 6715 + 00000000 VGT_INDX_OFFSET: 0 6716 + 0000000f RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 6717 + 00000000 RB_BLEND_RED: 0 6718 + 00000000 RB_BLEND_GREEN: 0 6719 + 00000000 RB_BLEND_BLUE: 0 6720 + 00000000 RB_BLEND_ALPHA: 0 6721 + 00000000 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 6722 + 00000000 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 6723 + 00000000 RB_ALPHA_REF: 0 6724!+ 43000000 PA_CL_VPORT_XSCALE: 128.000000 6725!+ 43000000 PA_CL_VPORT_XOFFSET: 128.000000 6726!+ c3000000 PA_CL_VPORT_YSCALE: -128.000000 6727!+ 43000000 PA_CL_VPORT_YOFFSET: 128.000000 6728!+ 3f000000 PA_CL_VPORT_ZSCALE: 0.500000 6729!+ 3f000000 PA_CL_VPORT_ZOFFSET: 0.500000 6730 + 10030002 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 } 6731 + 00000106 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 } 6732 + ffffffff SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 } 6733 + 00000000 SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 } 6734 + 00000000 SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 } 6735 + 00000000 RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP } 6736 + 00000000 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO } 6737!+ 00001c20 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_ALWAYS | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 } 6738 + 00000000 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL } 6739!+ 00090240 PA_SU_SC_MODE_CNTL: { POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST } 6740 + 0000043f PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT } 6741 + 00000004 RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH } 6742 + 88888888 RB_SAMPLE_POS: 0x88888888 6743!+ 00080008 PA_SU_POINT_SIZE: { HEIGHT = 0.500000 | WIDTH = 0.500000 } 6744!+ 00080008 PA_SU_POINT_MINMAX: { MIN = 0.500000 | MAX = 0.500000 } 6745!+ 00000008 PA_SU_LINE_CNTL: { WIDTH = 0.500000 } 6746 + 00000000 PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER } 6747 + 00000020 PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 } 6748 + 00000000 PA_SC_LINE_CNTL: { BRES_CNTL = 0 } 6749 + 00000000 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 } 6750 + 00000001 PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH } 6751 + 3f800000 PA_CL_GB_VERT_CLIP_ADJ: 1.000000 6752 + 3f800000 PA_CL_GB_VERT_DISC_ADJ: 1.000000 6753 + 3f800000 PA_CL_GB_HORZ_CLIP_ADJ: 1.000000 6754 + 3f800000 PA_CL_GB_HORZ_DISC_ADJ: 1.000000 6755 + 00100020 SQ_VS_CONST: { BASE = 32 | SIZE = 256 } 6756 + 000e0120 SQ_PS_CONST: { BASE = 288 | SIZE = 224 } 6757 + 0000ffff PA_SC_AA_MASK: 0xffff 6758 + 00000002 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 } 6759 + 00000002 VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 } 6760 + 0003c000 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 6761 + ffffffff RB_COLOR_DEST_MASK: 0xffffffff 67620110b25c: 0000: c0032200 00000000 00060004 0112d7a4 0000000c 6763t0 write CP_SCRATCH_REG7 (057f) 6764NEEDS WFI: CP_SCRATCH_REG7 (57f) 6765 CP_SCRATCH_REG7: 116 6766 :0,0,119,116 67670110b270: 0000: 0000057f 00000074 6768t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 67690110b278: 0000: c0002600 00000000 6770t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 6771 { EVENT = CACHE_FLUSH } 6772 event CACHE_FLUSH 67730110b280: 0000: c0004600 00000006 6774t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 6775 { EVENT = CACHE_FLUSH } 6776 event CACHE_FLUSH 67770110b288: 0000: c0004600 00000006 6778t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 6779 { EVENT = CACHE_FLUSH } 6780 event CACHE_FLUSH 67810110b290: 0000: c0004600 00000006 6782t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 6783 { EVENT = CACHE_FLUSH } 6784 event CACHE_FLUSH 67850110b298: 0000: c0004600 00000006 6786t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 6787 { EVENT = CACHE_FLUSH } 6788 event CACHE_FLUSH 67890110b2a0: 0000: c0004600 00000006 6790t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 6791 { EVENT = CACHE_FLUSH } 6792 event CACHE_FLUSH 67930110b2a8: 0000: c0004600 00000006 6794t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 6795 { EVENT = CACHE_FLUSH } 6796 event CACHE_FLUSH 67970110b2b0: 0000: c0004600 00000006 6798t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 6799 { EVENT = CACHE_FLUSH } 6800 event CACHE_FLUSH 68010110b2b8: 0000: c0004600 00000006 6802t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 6803 { EVENT = CACHE_FLUSH } 6804 event CACHE_FLUSH 68050110b2c0: 0000: c0004600 00000006 6806t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 6807 { EVENT = CACHE_FLUSH } 6808 event CACHE_FLUSH 68090110b2c8: 0000: c0004600 00000006 6810t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 6811 { EVENT = CACHE_FLUSH } 6812 event CACHE_FLUSH 68130110b2d0: 0000: c0004600 00000006 6814t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 6815 { EVENT = CACHE_FLUSH } 6816 event CACHE_FLUSH 68170110b2d8: 0000: c0004600 00000006 68180110c1d8: 0000: c0013700 0110b000 000000b8 6819t2 nop 6820############################################################ 6821vertices: 0 6822cmd: deqp-gles2/185: fence=1266 6823############################################################ 6824cmdstream: 124 dwords 6825t0 write RB_BC_CONTROL (0f01) 6826 RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 } 68270122d000: 0000: 00000f01 1c004046 6828t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6829 PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 } 68300122d008: 0000: c0012d00 00040293 00000020 6831t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6832 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 } 68330122d014: 0000: c0012d00 00040316 00000002 6834t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6835 VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 } 68360122d020: 0000: c0012d00 00040317 00000002 6837t0 write CP_PERFMON_CNTL (0444) 6838 CP_PERFMON_CNTL: 0 68390122d02c: 0000: 00000444 00000000 6840t0 write RBBM_PM_OVERRIDE1 (039c) 6841 RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE } 6842 RBBM_PM_OVERRIDE2: 0xfff 68430122d034: 0000: 0001039c ffffffff 00000fff 6844t0 write TP0_CHICKEN (0e1e) 6845 TP0_CHICKEN: 0x2 68460122d040: 0000: 00000e1e 00000002 6847t3 opcode: CP_INVALIDATE_STATE (3b) (2 dwords) 68480122d048: 0000: c0003b00 00007fff 6849t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6850 SQ_VS_CONST: { BASE = 32 | SIZE = 256 } 68510122d050: 0000: c0012d00 00040307 00100020 6852t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6853 SQ_PS_CONST: { BASE = 288 | SIZE = 224 } 68540122d05c: 0000: c0012d00 00040308 000e0120 6855t3 opcode: CP_SET_CONSTANT (2d) (4 dwords) 6856 VGT_MAX_VTX_INDX: 0xffffffff 6857 VGT_MIN_VTX_INDX: 0 68580122d068: 0000: c0022d00 00040100 ffffffff 00000000 6859t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6860 VGT_INDX_OFFSET: 0 68610122d078: 0000: c0012d00 00040102 00000000 6862t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6863 SQ_CONTEXT_MISC: { SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 } 68640122d084: 0000: c0012d00 00040181 00000004 6865t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6866 SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 } 68670122d090: 0000: c0012d00 00040182 ffffffff 6868t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6869 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 } 68700122d09c: 0000: c0012d00 00040301 00000000 6871t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6872 PA_SC_LINE_CNTL: { BRES_CNTL = 0 } 68730122d0a8: 0000: c0012d00 00040300 00000000 6874t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6875 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 } 68760122d0b4: 0000: c0012d00 00040080 00000000 6877t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6878 RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH } 68790122d0c0: 0000: c0012d00 00040208 00000004 6880t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6881 RB_SAMPLE_POS: 0x88888888 68820122d0cc: 0000: c0012d00 0004020a 88888888 6883t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6884 RB_COLOR_DEST_MASK: 0xffffffff 68850122d0d8: 0000: c0012d00 00040326 ffffffff 6886t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6887 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 68880122d0e4: 0000: c0012d00 0004031b 0003c000 6889t3 opcode: CP_SET_CONSTANT (2d) (4 dwords) 6890 SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 } 6891 SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 } 68920122d0f0: 0000: c0022d00 00040183 00000000 00000000 6893t3 opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords) 68940122d100: 0000: c0004b00 00000000 6895t3 opcode: CP_WAIT_REG_EQ (52) (5 dwords) 68960122d108: 0000: c0035200 000005d0 00000000 5f601000 00000001 6897t0 write SQ_INST_STORE_MANAGMENT (0d02) 6898 SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 } 68990122d11c: 0000: 00000d02 00000180 6900t3 opcode: CP_INVALIDATE_STATE (3b) (2 dwords) 69010122d124: 0000: c0003b00 00000300 6902t3 opcode: CP_SET_SHADER_BASES (4a) (2 dwords) 69030122d12c: 0000: c0004a00 80000180 6904t3 opcode: CP_SET_CONSTANT (2d) (14 dwords) 69050122d13c: 0.000000 0.000000 0.000000 0.000000 20000.000000 1.000000 0.500000 0.000000 69060122d15c: 2.000000 0.750000 0.375000 0.250000 69070122d134: 0000: c00c2d00 00000000 00000000 00000000 00000000 00000000 469c4000 3f800000 69080122d154: 0020: 3f000000 00000000 40000000 3f400000 3ec00000 3e800000 6909t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6910 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 69110122d16c: 0000: c0012d00 00040104 0000000f 6912t3 opcode: CP_SET_CONSTANT (2d) (6 dwords) 6913 RB_BLEND_RED: 0 6914 RB_BLEND_GREEN: 0 6915 RB_BLEND_BLUE: 0 6916 RB_BLEND_ALPHA: 0xff 69170122d178: 0000: c0042d00 00040105 00000000 00000000 00000000 000000ff 6918t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6919 PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT } 69200122d190: 0000: c0012d00 00040206 0000043f 6921t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6922 RB_SURFACE_INFO: { SURFACE_PITCH = 32 | MSAA_SAMPLES = 0 } 69230122d19c: 0000: c0012d00 00040000 00000020 6924t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6925 RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | LINEAR | ENDIAN = 0 | SWAP = 1 | BASE = 0x1266000 } 69260122d1a8: 0000: c0012d00 00040001 01266245 6927t3 opcode: CP_SET_CONSTANT (2d) (4 dwords) 6928 PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 } 6929 PA_SC_SCREEN_SCISSOR_BR: { X = 8 | Y = 16 } 69300122d1b4: 0000: c0022d00 0004000e 80000000 00100008 6931t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6932 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 } 69330122d1c4: 0000: c0012d00 00040080 00000000 6934t0 write CP_SCRATCH_REG6 (057e) 6935 CP_SCRATCH_REG6: 125 6936 :0,0,125,116 69370122d1d0: 0000: 0000057e 0000007d 6938t3 opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords) 6939 ibaddr:0122e000 6940 ibsize:000000b6 6941t3 opcode: CP_SET_CONSTANT (2d) (6 dwords) 6942 set shader const 0078 69430122e000: 0000: c0042d00 00010078 0112d7b3 00100000 0112d7b3 00100000 6944t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6945 PA_SC_AA_MASK: 0xffff 69460122e018: 0000: c0012d00 00040312 0000ffff 6947t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 6948 RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP } 69490122e024: 0000: c0012d00 00040200 00000000 6950t3 opcode: CP_SET_CONSTANT (2d) (5 dwords) 6951 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 6952 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 6953 RB_ALPHA_REF: 0 69540122e030: 0000: c0032d00 0004010c 00000000 00000000 00000000 6955t3 opcode: CP_SET_CONSTANT (2d) (4 dwords) 6956 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL } 6957 PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST } 69580122e044: 0000: c0022d00 00040204 00000000 00090244 6959t3 opcode: CP_SET_CONSTANT (2d) (6 dwords) 6960 PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 } 6961 PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 } 6962 PA_SU_LINE_CNTL: { WIDTH = 0.000000 } 6963 PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER } 69640122e054: 0000: c0042d00 00040280 00000000 00000000 00000000 00000000 6965t3 opcode: CP_SET_CONSTANT (2d) (7 dwords) 6966 PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH } 6967 PA_CL_GB_VERT_CLIP_ADJ: 1.000000 6968 PA_CL_GB_VERT_DISC_ADJ: 1.000000 6969 PA_CL_GB_HORZ_CLIP_ADJ: 1.000000 6970 PA_CL_GB_HORZ_DISC_ADJ: 1.000000 69710122e06c: 0000: c0052d00 00040302 00000001 3f800000 3f800000 3f800000 3f800000 6972t3 opcode: CP_SET_CONSTANT (2d) (4 dwords) 6973 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 6974 PA_SC_WINDOW_SCISSOR_BR: { X = 8 | Y = 16 } 69750122e088: 0000: c0022d00 00040081 00000000 00100008 6976t3 opcode: CP_SET_CONSTANT (2d) (8 dwords) 6977 PA_CL_VPORT_XSCALE: 4.000000 6978 PA_CL_VPORT_XOFFSET: 4.000000 6979 PA_CL_VPORT_YSCALE: 8.000000 6980 PA_CL_VPORT_YOFFSET: 8.000000 6981 PA_CL_VPORT_ZSCALE: 0.000000 6982 PA_CL_VPORT_ZOFFSET: 0.000000 69830122e098: 0000: c0062d00 0004010f 40800000 40800000 41000000 41000000 00000000 00000000 6984t3 opcode: CP_SET_CONSTANT (2d) (10 dwords) 69850122e0c0: 4.000000 8.000000 0.000000 0.000000 4.000000 8.000000 0.000000 0.000000 69860122e0b8: 0000: c0082d00 00000184 40800000 41000000 00000000 00000000 40800000 41000000 6987* 6988t3 opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords) 6989 vertex shader, start=0000, size=0015 6990 2003 0007 1000 EXEC ADDR(0x3) CNT(0x2) 6991 03: 19481000 00262688 00000020 (S)FETCH: VERTEX R1.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) CONST(20, 0) 6992 04: 13480000 40262688 00001020 FETCH: VERTEX R0.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) OFFSET(16) CONST(20, 1) 6993 0000 0000 c200 ALLOC POSITION SIZE(0x0) 6994 1005 0002 1000 EXEC ADDR(0x5) CNT(0x1) 6995 05: 000f803e 00000000 c2010100 (S)ALU: MAXv export62 = R1, R1 ; gl_Position 6996 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0) 6997 1006 0000 2000 EXEC_END ADDR(0x6) CNT(0x1) 6998 06: 000f8000 00000000 c2000000 ALU: MAXv export0 = R0, R0 6999 0000 0000 0000 NOP 70000122e0e0: 0000: c0162b00 00000000 00000015 00072003 00001000 c2000000 00021005 00001000 70010122e100: 0020: c4000000 00001006 00002000 00000000 19481000 00262688 00000020 13480000 70020122e120: 0040: 40262688 00001020 000f803e 00000000 c2010100 000f8000 00000000 c2000000 7003t3 opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords) 7004 fragment shader, start=0000, size=000c 7005 1002 0003 1000 EXEC ADDR(0x2) CNT(0x1) 7006 02: 90000001 1ffff688 00000002 (S)FETCH: SAMPLE R0.xyzw = R0.xyz CONST(0) LOCATION(CENTER) 7007 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0) 7008 1003 0002 2000 EXEC_END ADDR(0x3) CNT(0x1) 7009 03: 000f8000 00000000 c2000000 (S)ALU: MAXv export0 = R0, R0 ; gl_FragColor 7010 0000 0000 0000 NOP 70110122e140: 0000: c00d2b00 00000001 0000000c 00031002 00001000 c4000000 00021003 00002000 70120122e160: 0020: 00000000 90000001 1ffff688 00000002 000f8000 00000000 c2000000 7013t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7014 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 } 70150122e17c: 0000: c0012d00 00040181 00000106 7016t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7017 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 } 70180122e188: 0000: c0012d00 00040180 10030002 7019t3 opcode: CP_SET_CONSTANT (2d) (6 dwords) 70200122e19c: 0.000000 0.000000 0.000000 0.000000 70210122e194: 0000: c0042d00 00000080 00000000 00000000 00000000 00000000 7022t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7023 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 } 70240122e1ac: 0000: c0012d00 00040202 00000c20 7025t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7026 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO } 70270122e1b8: 0000: c0012d00 00040201 00000000 7028t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7029 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 70300122e1c4: 0000: c0012d00 00040104 0000000f 7031t3 opcode: CP_SET_CONSTANT (2d) (6 dwords) 7032 RB_BLEND_RED: 0 7033 RB_BLEND_GREEN: 0 7034 RB_BLEND_BLUE: 0 7035 RB_BLEND_ALPHA: 0 70360122e1d0: 0000: c0042d00 00040105 00000000 00000000 00000000 00000000 7037t3 opcode: CP_SET_CONSTANT (2d) (8 dwords) 7038 set texture const 0000 7039 clamp x/y/z: clamp-last-texel/clamp-last-texel/clamp-last-texel 7040 filter min/mag: point/point 7041 swizzle: zyxw 7042 addr=0108a000 (flags=806), size=256x256, pitch=16640, format=FMT_8_8_8_8 7043 mipaddr=00000000 (flags=200) 70440122e1e8: 0000: c0062d00 00010000 82024800 0108a806 001fe0ff 00000c14 00000000 00000200 7045t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7046 VGT_INDX_OFFSET: 0 70470122e208: 0000: c0012d00 00040102 00000000 7048t0 write TC_CNTL_STATUS (0e00) 7049 TC_CNTL_STATUS: { L2_INVALIDATE } 70500122e214: 0000: 00000e00 00000001 7051t3 opcode: CP_WAIT_REG_EQ (52) (5 dwords) 70520122e21c: 0000: c0035200 000005d0 00000000 00001000 00000001 7053t3 opcode: CP_DRAW_INDX_BIN (34) (7 dwords) 70540122e230: 0000: c0053400 00000000 0003c004 00000000 00000003 01009040 00000006 7055t0 write CP_SCRATCH_REG7 (057f) 7056 CP_SCRATCH_REG7: 121 7057 :0,0,125,121 70580122e24c: 0000: 0000057f 00000079 7059t3 opcode: CP_NOP (10) (2 dwords) 70600122e254: 0000: c0001000 00000000 7061t3 opcode: CP_DRAW_INDX (22) (3 dwords) 7062 { VIZ_QUERY = 0 } 7063 { PRIM_TYPE = DI_PT_TRIFAN | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | NUM_INSTANCES = 0 | 0x40000 } 7064 draw: 0 7065 prim_type: DI_PT_TRIFAN (5) 7066 source_select: DI_SRC_SEL_AUTO_INDEX (2) 7067 num_indices: 1407 7068 draw[20] register values 7069 + ffffffff RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE } 7070 + 00000fff RBBM_PM_OVERRIDE2: 0xfff 7071 + 00000000 CP_PERFMON_CNTL: 0 7072!+ 0000007d CP_SCRATCH_REG6: 125 7073 :0,0,125,121 7074!+ 00000079 CP_SCRATCH_REG7: 121 7075 :0,0,125,121 7076 + 00000180 SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 } 7077 + 00000001 TC_CNTL_STATUS: { L2_INVALIDATE } 7078 + 00000002 TP0_CHICKEN: 0x2 7079 + 1c004046 RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 } 7080!+ 00000020 RB_SURFACE_INFO: { SURFACE_PITCH = 32 | MSAA_SAMPLES = 0 } 7081!+ 01266245 RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | LINEAR | ENDIAN = 0 | SWAP = 1 | BASE = 0x1266000 } 7082 + 80000000 PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 } 7083!+ 00100008 PA_SC_SCREEN_SCISSOR_BR: { X = 8 | Y = 16 } 7084 + 00000000 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 } 7085 + 00000000 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 7086!+ 00100008 PA_SC_WINDOW_SCISSOR_BR: { X = 8 | Y = 16 } 7087 + ffffffff VGT_MAX_VTX_INDX: 0xffffffff 7088 + 00000000 VGT_MIN_VTX_INDX: 0 7089 + 00000000 VGT_INDX_OFFSET: 0 7090 + 0000000f RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 7091 + 00000000 RB_BLEND_RED: 0 7092 + 00000000 RB_BLEND_GREEN: 0 7093 + 00000000 RB_BLEND_BLUE: 0 7094 + 00000000 RB_BLEND_ALPHA: 0 7095 + 00000000 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 7096 + 00000000 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 7097 + 00000000 RB_ALPHA_REF: 0 7098!+ 40800000 PA_CL_VPORT_XSCALE: 4.000000 7099!+ 40800000 PA_CL_VPORT_XOFFSET: 4.000000 7100!+ 41000000 PA_CL_VPORT_YSCALE: 8.000000 7101!+ 41000000 PA_CL_VPORT_YOFFSET: 8.000000 7102!+ 00000000 PA_CL_VPORT_ZSCALE: 0.000000 7103!+ 00000000 PA_CL_VPORT_ZOFFSET: 0.000000 7104 + 10030002 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 } 7105 + 00000106 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 } 7106 + ffffffff SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 } 7107 + 00000000 SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 } 7108 + 00000000 SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 } 7109 + 00000000 RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP } 7110 + 00000000 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO } 7111!+ 00000c20 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 } 7112 + 00000000 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL } 7113!+ 00090244 PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST } 7114 + 0000043f PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT } 7115 + 00000004 RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH } 7116 + 88888888 RB_SAMPLE_POS: 0x88888888 7117!+ 00000000 PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 } 7118!+ 00000000 PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 } 7119!+ 00000000 PA_SU_LINE_CNTL: { WIDTH = 0.000000 } 7120 + 00000000 PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER } 7121 + 00000020 PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 } 7122 + 00000000 PA_SC_LINE_CNTL: { BRES_CNTL = 0 } 7123 + 00000000 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 } 7124 + 00000001 PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH } 7125 + 3f800000 PA_CL_GB_VERT_CLIP_ADJ: 1.000000 7126 + 3f800000 PA_CL_GB_VERT_DISC_ADJ: 1.000000 7127 + 3f800000 PA_CL_GB_HORZ_CLIP_ADJ: 1.000000 7128 + 3f800000 PA_CL_GB_HORZ_DISC_ADJ: 1.000000 7129 + 00100020 SQ_VS_CONST: { BASE = 32 | SIZE = 256 } 7130 + 000e0120 SQ_PS_CONST: { BASE = 288 | SIZE = 224 } 7131 + 0000ffff PA_SC_AA_MASK: 0xffff 7132 + 00000002 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 } 7133 + 00000002 VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 } 7134 + 0003c000 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 7135 + ffffffff RB_COLOR_DEST_MASK: 0xffffffff 71360122e25c: 0000: c0012200 00000000 00040085 7137t0 write CP_SCRATCH_REG7 (057f) 7138NEEDS WFI: CP_SCRATCH_REG7 (57f) 7139 CP_SCRATCH_REG7: 122 7140 :0,0,125,122 71410122e268: 0000: 0000057f 0000007a 7142t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 71430122e270: 0000: c0002600 00000000 7144t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 7145 { EVENT = CACHE_FLUSH } 7146 event CACHE_FLUSH 71470122e278: 0000: c0004600 00000006 7148t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 7149 { EVENT = CACHE_FLUSH } 7150 event CACHE_FLUSH 71510122e280: 0000: c0004600 00000006 7152t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 7153 { EVENT = CACHE_FLUSH } 7154 event CACHE_FLUSH 71550122e288: 0000: c0004600 00000006 7156t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 7157 { EVENT = CACHE_FLUSH } 7158 event CACHE_FLUSH 71590122e290: 0000: c0004600 00000006 7160t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 7161 { EVENT = CACHE_FLUSH } 7162 event CACHE_FLUSH 71630122e298: 0000: c0004600 00000006 7164t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 7165 { EVENT = CACHE_FLUSH } 7166 event CACHE_FLUSH 71670122e2a0: 0000: c0004600 00000006 7168t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 7169 { EVENT = CACHE_FLUSH } 7170 event CACHE_FLUSH 71710122e2a8: 0000: c0004600 00000006 7172t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 7173 { EVENT = CACHE_FLUSH } 7174 event CACHE_FLUSH 71750122e2b0: 0000: c0004600 00000006 7176t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 7177 { EVENT = CACHE_FLUSH } 7178 event CACHE_FLUSH 71790122e2b8: 0000: c0004600 00000006 7180t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 7181 { EVENT = CACHE_FLUSH } 7182 event CACHE_FLUSH 71830122e2c0: 0000: c0004600 00000006 7184t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 7185 { EVENT = CACHE_FLUSH } 7186 event CACHE_FLUSH 71870122e2c8: 0000: c0004600 00000006 7188t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 7189 { EVENT = CACHE_FLUSH } 7190 event CACHE_FLUSH 71910122e2d0: 0000: c0004600 00000006 71920122d1d8: 0000: c0013700 0122e000 000000b6 7193t2 nop 7194############################################################ 7195vertices: 0 7196cmd: deqp-gles2/185: fence=1267 7197############################################################ 7198cmdstream: 124 dwords 7199t0 write RB_BC_CONTROL (0f01) 7200 RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 } 72010110a000: 0000: 00000f01 1c004046 7202t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7203 PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 } 72040110a008: 0000: c0012d00 00040293 00000020 7205t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7206 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 } 72070110a014: 0000: c0012d00 00040316 00000002 7208t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7209 VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 } 72100110a020: 0000: c0012d00 00040317 00000002 7211t0 write CP_PERFMON_CNTL (0444) 7212 CP_PERFMON_CNTL: 0 72130110a02c: 0000: 00000444 00000000 7214t0 write RBBM_PM_OVERRIDE1 (039c) 7215 RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE } 7216 RBBM_PM_OVERRIDE2: 0xfff 72170110a034: 0000: 0001039c ffffffff 00000fff 7218t0 write TP0_CHICKEN (0e1e) 7219 TP0_CHICKEN: 0x2 72200110a040: 0000: 00000e1e 00000002 7221t3 opcode: CP_INVALIDATE_STATE (3b) (2 dwords) 72220110a048: 0000: c0003b00 00007fff 7223t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7224 SQ_VS_CONST: { BASE = 32 | SIZE = 256 } 72250110a050: 0000: c0012d00 00040307 00100020 7226t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7227 SQ_PS_CONST: { BASE = 288 | SIZE = 224 } 72280110a05c: 0000: c0012d00 00040308 000e0120 7229t3 opcode: CP_SET_CONSTANT (2d) (4 dwords) 7230 VGT_MAX_VTX_INDX: 0xffffffff 7231 VGT_MIN_VTX_INDX: 0 72320110a068: 0000: c0022d00 00040100 ffffffff 00000000 7233t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7234 VGT_INDX_OFFSET: 0 72350110a078: 0000: c0012d00 00040102 00000000 7236t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7237 SQ_CONTEXT_MISC: { SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 } 72380110a084: 0000: c0012d00 00040181 00000004 7239t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7240 SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 } 72410110a090: 0000: c0012d00 00040182 ffffffff 7242t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7243 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 } 72440110a09c: 0000: c0012d00 00040301 00000000 7245t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7246 PA_SC_LINE_CNTL: { BRES_CNTL = 0 } 72470110a0a8: 0000: c0012d00 00040300 00000000 7248t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7249 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 } 72500110a0b4: 0000: c0012d00 00040080 00000000 7251t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7252 RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH } 72530110a0c0: 0000: c0012d00 00040208 00000004 7254t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7255 RB_SAMPLE_POS: 0x88888888 72560110a0cc: 0000: c0012d00 0004020a 88888888 7257t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7258 RB_COLOR_DEST_MASK: 0xffffffff 72590110a0d8: 0000: c0012d00 00040326 ffffffff 7260t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7261 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 72620110a0e4: 0000: c0012d00 0004031b 0003c000 7263t3 opcode: CP_SET_CONSTANT (2d) (4 dwords) 7264 SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 } 7265 SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 } 72660110a0f0: 0000: c0022d00 00040183 00000000 00000000 7267t3 opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords) 72680110a100: 0000: c0004b00 00000000 7269t3 opcode: CP_WAIT_REG_EQ (52) (5 dwords) 72700110a108: 0000: c0035200 000005d0 00000000 5f601000 00000001 7271t0 write SQ_INST_STORE_MANAGMENT (0d02) 7272 SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 } 72730110a11c: 0000: 00000d02 00000180 7274t3 opcode: CP_INVALIDATE_STATE (3b) (2 dwords) 72750110a124: 0000: c0003b00 00000300 7276t3 opcode: CP_SET_SHADER_BASES (4a) (2 dwords) 72770110a12c: 0000: c0004a00 80000180 7278t3 opcode: CP_SET_CONSTANT (2d) (14 dwords) 72790110a13c: 0.000000 0.000000 0.000000 0.000000 20000.000000 1.000000 0.500000 0.000000 72800110a15c: 2.000000 0.750000 0.375000 0.250000 72810110a134: 0000: c00c2d00 00000000 00000000 00000000 00000000 00000000 469c4000 3f800000 72820110a154: 0020: 3f000000 00000000 40000000 3f400000 3ec00000 3e800000 7283t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7284 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 72850110a16c: 0000: c0012d00 00040104 0000000f 7286t3 opcode: CP_SET_CONSTANT (2d) (6 dwords) 7287 RB_BLEND_RED: 0 7288 RB_BLEND_GREEN: 0 7289 RB_BLEND_BLUE: 0 7290 RB_BLEND_ALPHA: 0xff 72910110a178: 0000: c0042d00 00040105 00000000 00000000 00000000 000000ff 7292t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7293 PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT } 72940110a190: 0000: c0012d00 00040206 0000043f 7295t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7296 RB_SURFACE_INFO: { SURFACE_PITCH = 256 | MSAA_SAMPLES = 0 } 72970110a19c: 0000: c0012d00 00040000 00000100 7298t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7299 RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 1 | BASE = 0x108a000 } 73000110a1a8: 0000: c0012d00 00040001 0108a205 7301t3 opcode: CP_SET_CONSTANT (2d) (4 dwords) 7302 PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 } 7303 PA_SC_SCREEN_SCISSOR_BR: { X = 256 | Y = 256 } 73040110a1b4: 0000: c0022d00 0004000e 80000000 01000100 7305t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7306 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 } 73070110a1c4: 0000: c0012d00 00040080 00000000 7308t0 write CP_SCRATCH_REG6 (057e) 7309 CP_SCRATCH_REG6: 131 7310 :0,0,131,122 73110110a1d0: 0000: 0000057e 00000083 7312t3 opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords) 7313 ibaddr:0110b000 7314 ibsize:000000b8 7315t3 opcode: CP_SET_CONSTANT (2d) (6 dwords) 7316 set shader const 0078 73170110b000: 0000: c0042d00 00010078 0112d833 00100000 0112d873 00100000 7318t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7319 PA_SC_AA_MASK: 0xffff 73200110b018: 0000: c0012d00 00040312 0000ffff 7321t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7322 RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP } 73230110b024: 0000: c0012d00 00040200 00000000 7324t3 opcode: CP_SET_CONSTANT (2d) (5 dwords) 7325 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 7326 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 7327 RB_ALPHA_REF: 0 73280110b030: 0000: c0032d00 0004010c 00000000 00000000 00000000 7329t3 opcode: CP_SET_CONSTANT (2d) (4 dwords) 7330 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL } 7331 PA_SU_SC_MODE_CNTL: { POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST } 73320110b044: 0000: c0022d00 00040204 00000000 00090240 7333t3 opcode: CP_SET_CONSTANT (2d) (6 dwords) 7334 PA_SU_POINT_SIZE: { HEIGHT = 0.500000 | WIDTH = 0.500000 } 7335 PA_SU_POINT_MINMAX: { MIN = 0.500000 | MAX = 0.500000 } 7336 PA_SU_LINE_CNTL: { WIDTH = 0.500000 } 7337 PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER } 73380110b054: 0000: c0042d00 00040280 00080008 00080008 00000008 00000000 7339t3 opcode: CP_SET_CONSTANT (2d) (7 dwords) 7340 PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH } 7341 PA_CL_GB_VERT_CLIP_ADJ: 1.000000 7342 PA_CL_GB_VERT_DISC_ADJ: 1.000000 7343 PA_CL_GB_HORZ_CLIP_ADJ: 1.000000 7344 PA_CL_GB_HORZ_DISC_ADJ: 1.000000 73450110b06c: 0000: c0052d00 00040302 00000001 3f800000 3f800000 3f800000 3f800000 7346t3 opcode: CP_SET_CONSTANT (2d) (4 dwords) 7347 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 7348 PA_SC_WINDOW_SCISSOR_BR: { X = 256 | Y = 256 } 73490110b088: 0000: c0022d00 00040081 00000000 01000100 7350t3 opcode: CP_SET_CONSTANT (2d) (8 dwords) 7351 PA_CL_VPORT_XSCALE: 128.000000 7352 PA_CL_VPORT_XOFFSET: 128.000000 7353 PA_CL_VPORT_YSCALE: -128.000000 7354 PA_CL_VPORT_YOFFSET: 128.000000 7355 PA_CL_VPORT_ZSCALE: 0.500000 7356 PA_CL_VPORT_ZOFFSET: 0.500000 73570110b098: 0000: c0062d00 0004010f 43000000 43000000 c3000000 43000000 3f000000 3f000000 7358t3 opcode: CP_SET_CONSTANT (2d) (10 dwords) 73590110b0c0: 128.000000 128.000000 0.500000 0.000000 128.000000 -128.000000 0.500000 0.000000 73600110b0b8: 0000: c0082d00 00000184 43000000 43000000 3f000000 00000000 43000000 c3000000 73610110b0d8: 0020: 3f000000 00000000 7362t3 opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords) 7363 vertex shader, start=0000, size=0015 7364 2003 0007 1000 EXEC ADDR(0x3) CNT(0x2) 7365 03: 19481000 00262688 00000010 (S)FETCH: VERTEX R1.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(16) CONST(20, 0) 7366 04: 13480000 40252fc8 00000008 FETCH: VERTEX R0.xy__ = R0.x FMT_32_32_FLOAT UNSIGNED STRIDE(8) CONST(20, 1) 7367 0000 0000 c200 ALLOC POSITION SIZE(0x0) 7368 1005 0002 1000 EXEC ADDR(0x5) CNT(0x1) 7369 05: 000f803e 00000000 c2010100 (S)ALU: MAXv export62 = R1, R1 ; gl_Position 7370 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0) 7371 1006 0000 2000 EXEC_END ADDR(0x6) CNT(0x1) 7372 06: 00038000 00000000 c2000000 ALU: MAXv export0.xy__ = R0, R0 7373 0000 0000 0000 NOP 73740110b0e0: 0000: c0162b00 00000000 00000015 00072003 00001000 c2000000 00021005 00001000 73750110b100: 0020: c4000000 00001006 00002000 00000000 19481000 00262688 00000010 13480000 73760110b120: 0040: 40252fc8 00000008 000f803e 00000000 c2010100 00038000 00000000 c2000000 7377t3 opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords) 7378 fragment shader, start=0000, size=000c 7379 1002 0003 1000 EXEC ADDR(0x2) CNT(0x1) 7380 02: 90000001 1ffff688 00000002 (S)FETCH: SAMPLE R0.xyzw = R0.xyz CONST(0) LOCATION(CENTER) 7381 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0) 7382 1003 0002 2000 EXEC_END ADDR(0x3) CNT(0x1) 7383 03: 000f8000 00000000 c2000000 (S)ALU: MAXv export0 = R0, R0 ; gl_FragColor 7384 0000 0000 0000 NOP 73850110b140: 0000: c00d2b00 00000001 0000000c 00031002 00001000 c4000000 00021003 00002000 73860110b160: 0020: 00000000 90000001 1ffff688 00000002 000f8000 00000000 c2000000 7387t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7388 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 } 73890110b17c: 0000: c0012d00 00040181 00000106 7390t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7391 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 } 73920110b188: 0000: c0012d00 00040180 10030002 7393t3 opcode: CP_SET_CONSTANT (2d) (6 dwords) 73940110b19c: 0.000000 0.000000 0.000000 0.000000 73950110b194: 0000: c0042d00 00000080 00000000 00000000 00000000 00000000 7396t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7397 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_ALWAYS | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 } 73980110b1ac: 0000: c0012d00 00040202 00001c20 7399t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7400 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO } 74010110b1b8: 0000: c0012d00 00040201 00000000 7402t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7403 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 74040110b1c4: 0000: c0012d00 00040104 0000000f 7405t3 opcode: CP_SET_CONSTANT (2d) (6 dwords) 7406 RB_BLEND_RED: 0 7407 RB_BLEND_GREEN: 0 7408 RB_BLEND_BLUE: 0 7409 RB_BLEND_ALPHA: 0 74100110b1d0: 0000: c0042d00 00040105 00000000 00000000 00000000 00000000 7411t3 opcode: CP_SET_CONSTANT (2d) (8 dwords) 7412 set texture const 0000 7413 clamp x/y/z: clamp-last-texel/clamp-last-texel/wrap 7414 filter min/mag: point/point 7415 swizzle: xyzw 7416 addr=01230000 (flags=820), size=64x128, pitch=16448, format=FMT_1_REVERSE 7417 mipaddr=01240000 (flags=200) 74180110b1e8: 0000: c0062d00 00010000 80804800 01230820 000fe03f 00000d11 000001c0 01240200 7419t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7420 VGT_INDX_OFFSET: 0 74210110b208: 0000: c0012d00 00040102 00000000 7422t0 write TC_CNTL_STATUS (0e00) 7423 TC_CNTL_STATUS: { L2_INVALIDATE } 74240110b214: 0000: 00000e00 00000001 7425t3 opcode: CP_WAIT_REG_EQ (52) (5 dwords) 74260110b21c: 0000: c0035200 000005d0 00000000 00001000 00000001 7427t3 opcode: CP_DRAW_INDX_BIN (34) (7 dwords) 74280110b230: 0000: c0053400 00000000 0003c004 00000000 00000003 01009040 00000006 7429t0 write CP_SCRATCH_REG7 (057f) 7430 CP_SCRATCH_REG7: 127 7431 :0,0,131,127 74320110b24c: 0000: 0000057f 0000007f 7433t3 opcode: CP_NOP (10) (2 dwords) 74340110b254: 0000: c0001000 00000000 7435t3 opcode: CP_DRAW_INDX (22) (5 dwords) 7436 { VIZ_QUERY = 0 } 7437 { PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_DMA | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | NUM_INSTANCES = 0 | 0x60000 } 7438 { NUM_INDICES = 18012304 } 7439 { INDX_BASE = 0xc } 7440 draw: 0 7441 prim_type: DI_PT_TRILIST (4) 7442 source_select: DI_SRC_SEL_DMA (0) 7443 num_indices: 18012304 7444 draw[21] register values 7445 + ffffffff RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE } 7446 + 00000fff RBBM_PM_OVERRIDE2: 0xfff 7447 + 00000000 CP_PERFMON_CNTL: 0 7448!+ 00000083 CP_SCRATCH_REG6: 131 7449 :0,0,131,127 7450!+ 0000007f CP_SCRATCH_REG7: 127 7451 :0,0,131,127 7452 + 00000180 SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 } 7453 + 00000001 TC_CNTL_STATUS: { L2_INVALIDATE } 7454 + 00000002 TP0_CHICKEN: 0x2 7455 + 1c004046 RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 } 7456!+ 00000100 RB_SURFACE_INFO: { SURFACE_PITCH = 256 | MSAA_SAMPLES = 0 } 7457!+ 0108a205 RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 1 | BASE = 0x108a000 } 7458 + 80000000 PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 } 7459!+ 01000100 PA_SC_SCREEN_SCISSOR_BR: { X = 256 | Y = 256 } 7460 + 00000000 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 } 7461 + 00000000 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 7462!+ 01000100 PA_SC_WINDOW_SCISSOR_BR: { X = 256 | Y = 256 } 7463 + ffffffff VGT_MAX_VTX_INDX: 0xffffffff 7464 + 00000000 VGT_MIN_VTX_INDX: 0 7465 + 00000000 VGT_INDX_OFFSET: 0 7466 + 0000000f RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 7467 + 00000000 RB_BLEND_RED: 0 7468 + 00000000 RB_BLEND_GREEN: 0 7469 + 00000000 RB_BLEND_BLUE: 0 7470 + 00000000 RB_BLEND_ALPHA: 0 7471 + 00000000 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 7472 + 00000000 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 7473 + 00000000 RB_ALPHA_REF: 0 7474!+ 43000000 PA_CL_VPORT_XSCALE: 128.000000 7475!+ 43000000 PA_CL_VPORT_XOFFSET: 128.000000 7476!+ c3000000 PA_CL_VPORT_YSCALE: -128.000000 7477!+ 43000000 PA_CL_VPORT_YOFFSET: 128.000000 7478!+ 3f000000 PA_CL_VPORT_ZSCALE: 0.500000 7479!+ 3f000000 PA_CL_VPORT_ZOFFSET: 0.500000 7480 + 10030002 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 } 7481 + 00000106 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 } 7482 + ffffffff SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 } 7483 + 00000000 SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 } 7484 + 00000000 SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 } 7485 + 00000000 RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP } 7486 + 00000000 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO } 7487!+ 00001c20 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_ALWAYS | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 } 7488 + 00000000 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL } 7489!+ 00090240 PA_SU_SC_MODE_CNTL: { POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST } 7490 + 0000043f PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT } 7491 + 00000004 RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH } 7492 + 88888888 RB_SAMPLE_POS: 0x88888888 7493!+ 00080008 PA_SU_POINT_SIZE: { HEIGHT = 0.500000 | WIDTH = 0.500000 } 7494!+ 00080008 PA_SU_POINT_MINMAX: { MIN = 0.500000 | MAX = 0.500000 } 7495!+ 00000008 PA_SU_LINE_CNTL: { WIDTH = 0.500000 } 7496 + 00000000 PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER } 7497 + 00000020 PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 } 7498 + 00000000 PA_SC_LINE_CNTL: { BRES_CNTL = 0 } 7499 + 00000000 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 } 7500 + 00000001 PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH } 7501 + 3f800000 PA_CL_GB_VERT_CLIP_ADJ: 1.000000 7502 + 3f800000 PA_CL_GB_VERT_DISC_ADJ: 1.000000 7503 + 3f800000 PA_CL_GB_HORZ_CLIP_ADJ: 1.000000 7504 + 3f800000 PA_CL_GB_HORZ_DISC_ADJ: 1.000000 7505 + 00100020 SQ_VS_CONST: { BASE = 32 | SIZE = 256 } 7506 + 000e0120 SQ_PS_CONST: { BASE = 288 | SIZE = 224 } 7507 + 0000ffff PA_SC_AA_MASK: 0xffff 7508 + 00000002 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 } 7509 + 00000002 VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 } 7510 + 0003c000 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 7511 + ffffffff RB_COLOR_DEST_MASK: 0xffffffff 75120110b25c: 0000: c0032200 00000000 00060004 0112d890 0000000c 7513t0 write CP_SCRATCH_REG7 (057f) 7514NEEDS WFI: CP_SCRATCH_REG7 (57f) 7515 CP_SCRATCH_REG7: 128 7516 :0,0,131,128 75170110b270: 0000: 0000057f 00000080 7518t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 75190110b278: 0000: c0002600 00000000 7520t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 7521 { EVENT = CACHE_FLUSH } 7522 event CACHE_FLUSH 75230110b280: 0000: c0004600 00000006 7524t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 7525 { EVENT = CACHE_FLUSH } 7526 event CACHE_FLUSH 75270110b288: 0000: c0004600 00000006 7528t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 7529 { EVENT = CACHE_FLUSH } 7530 event CACHE_FLUSH 75310110b290: 0000: c0004600 00000006 7532t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 7533 { EVENT = CACHE_FLUSH } 7534 event CACHE_FLUSH 75350110b298: 0000: c0004600 00000006 7536t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 7537 { EVENT = CACHE_FLUSH } 7538 event CACHE_FLUSH 75390110b2a0: 0000: c0004600 00000006 7540t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 7541 { EVENT = CACHE_FLUSH } 7542 event CACHE_FLUSH 75430110b2a8: 0000: c0004600 00000006 7544t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 7545 { EVENT = CACHE_FLUSH } 7546 event CACHE_FLUSH 75470110b2b0: 0000: c0004600 00000006 7548t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 7549 { EVENT = CACHE_FLUSH } 7550 event CACHE_FLUSH 75510110b2b8: 0000: c0004600 00000006 7552t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 7553 { EVENT = CACHE_FLUSH } 7554 event CACHE_FLUSH 75550110b2c0: 0000: c0004600 00000006 7556t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 7557 { EVENT = CACHE_FLUSH } 7558 event CACHE_FLUSH 75590110b2c8: 0000: c0004600 00000006 7560t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 7561 { EVENT = CACHE_FLUSH } 7562 event CACHE_FLUSH 75630110b2d0: 0000: c0004600 00000006 7564t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 7565 { EVENT = CACHE_FLUSH } 7566 event CACHE_FLUSH 75670110b2d8: 0000: c0004600 00000006 75680110a1d8: 0000: c0013700 0110b000 000000b8 7569t2 nop 7570############################################################ 7571vertices: 0 7572cmd: deqp-gles2/185: fence=1268 7573############################################################ 7574cmdstream: 124 dwords 7575t0 write RB_BC_CONTROL (0f01) 7576 RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 } 75770122f000: 0000: 00000f01 1c004046 7578t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7579 PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 } 75800122f008: 0000: c0012d00 00040293 00000020 7581t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7582 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 } 75830122f014: 0000: c0012d00 00040316 00000002 7584t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7585 VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 } 75860122f020: 0000: c0012d00 00040317 00000002 7587t0 write CP_PERFMON_CNTL (0444) 7588 CP_PERFMON_CNTL: 0 75890122f02c: 0000: 00000444 00000000 7590t0 write RBBM_PM_OVERRIDE1 (039c) 7591 RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE } 7592 RBBM_PM_OVERRIDE2: 0xfff 75930122f034: 0000: 0001039c ffffffff 00000fff 7594t0 write TP0_CHICKEN (0e1e) 7595 TP0_CHICKEN: 0x2 75960122f040: 0000: 00000e1e 00000002 7597t3 opcode: CP_INVALIDATE_STATE (3b) (2 dwords) 75980122f048: 0000: c0003b00 00007fff 7599t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7600 SQ_VS_CONST: { BASE = 32 | SIZE = 256 } 76010122f050: 0000: c0012d00 00040307 00100020 7602t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7603 SQ_PS_CONST: { BASE = 288 | SIZE = 224 } 76040122f05c: 0000: c0012d00 00040308 000e0120 7605t3 opcode: CP_SET_CONSTANT (2d) (4 dwords) 7606 VGT_MAX_VTX_INDX: 0xffffffff 7607 VGT_MIN_VTX_INDX: 0 76080122f068: 0000: c0022d00 00040100 ffffffff 00000000 7609t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7610 VGT_INDX_OFFSET: 0 76110122f078: 0000: c0012d00 00040102 00000000 7612t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7613 SQ_CONTEXT_MISC: { SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 } 76140122f084: 0000: c0012d00 00040181 00000004 7615t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7616 SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 } 76170122f090: 0000: c0012d00 00040182 ffffffff 7618t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7619 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 } 76200122f09c: 0000: c0012d00 00040301 00000000 7621t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7622 PA_SC_LINE_CNTL: { BRES_CNTL = 0 } 76230122f0a8: 0000: c0012d00 00040300 00000000 7624t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7625 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 } 76260122f0b4: 0000: c0012d00 00040080 00000000 7627t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7628 RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH } 76290122f0c0: 0000: c0012d00 00040208 00000004 7630t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7631 RB_SAMPLE_POS: 0x88888888 76320122f0cc: 0000: c0012d00 0004020a 88888888 7633t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7634 RB_COLOR_DEST_MASK: 0xffffffff 76350122f0d8: 0000: c0012d00 00040326 ffffffff 7636t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7637 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 76380122f0e4: 0000: c0012d00 0004031b 0003c000 7639t3 opcode: CP_SET_CONSTANT (2d) (4 dwords) 7640 SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 } 7641 SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 } 76420122f0f0: 0000: c0022d00 00040183 00000000 00000000 7643t3 opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords) 76440122f100: 0000: c0004b00 00000000 7645t3 opcode: CP_WAIT_REG_EQ (52) (5 dwords) 76460122f108: 0000: c0035200 000005d0 00000000 5f601000 00000001 7647t0 write SQ_INST_STORE_MANAGMENT (0d02) 7648 SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 } 76490122f11c: 0000: 00000d02 00000180 7650t3 opcode: CP_INVALIDATE_STATE (3b) (2 dwords) 76510122f124: 0000: c0003b00 00000300 7652t3 opcode: CP_SET_SHADER_BASES (4a) (2 dwords) 76530122f12c: 0000: c0004a00 80000180 7654t3 opcode: CP_SET_CONSTANT (2d) (14 dwords) 76550122f13c: 0.000000 0.000000 0.000000 0.000000 20000.000000 1.000000 0.500000 0.000000 76560122f15c: 2.000000 0.750000 0.375000 0.250000 76570122f134: 0000: c00c2d00 00000000 00000000 00000000 00000000 00000000 469c4000 3f800000 76580122f154: 0020: 3f000000 00000000 40000000 3f400000 3ec00000 3e800000 7659t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7660 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 76610122f16c: 0000: c0012d00 00040104 0000000f 7662t3 opcode: CP_SET_CONSTANT (2d) (6 dwords) 7663 RB_BLEND_RED: 0 7664 RB_BLEND_GREEN: 0 7665 RB_BLEND_BLUE: 0 7666 RB_BLEND_ALPHA: 0xff 76670122f178: 0000: c0042d00 00040105 00000000 00000000 00000000 000000ff 7668t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7669 PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT } 76700122f190: 0000: c0012d00 00040206 0000043f 7671t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7672 RB_SURFACE_INFO: { SURFACE_PITCH = 32 | MSAA_SAMPLES = 0 } 76730122f19c: 0000: c0012d00 00040000 00000020 7674t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7675 RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | LINEAR | ENDIAN = 0 | SWAP = 1 | BASE = 0x1266000 } 76760122f1a8: 0000: c0012d00 00040001 01266245 7677t3 opcode: CP_SET_CONSTANT (2d) (4 dwords) 7678 PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 } 7679 PA_SC_SCREEN_SCISSOR_BR: { X = 4 | Y = 8 } 76800122f1b4: 0000: c0022d00 0004000e 80000000 00080004 7681t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7682 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 } 76830122f1c4: 0000: c0012d00 00040080 00000000 7684t0 write CP_SCRATCH_REG6 (057e) 7685 CP_SCRATCH_REG6: 137 7686 :0,0,137,128 76870122f1d0: 0000: 0000057e 00000089 7688t3 opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords) 7689 ibaddr:0122e000 7690 ibsize:000000b6 7691t3 opcode: CP_SET_CONSTANT (2d) (6 dwords) 7692 set shader const 0078 76930122e000: 0000: c0042d00 00010078 0112d89f 00100000 0112d89f 00100000 7694t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7695 PA_SC_AA_MASK: 0xffff 76960122e018: 0000: c0012d00 00040312 0000ffff 7697t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7698 RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP } 76990122e024: 0000: c0012d00 00040200 00000000 7700t3 opcode: CP_SET_CONSTANT (2d) (5 dwords) 7701 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 7702 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 7703 RB_ALPHA_REF: 0 77040122e030: 0000: c0032d00 0004010c 00000000 00000000 00000000 7705t3 opcode: CP_SET_CONSTANT (2d) (4 dwords) 7706 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL } 7707 PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST } 77080122e044: 0000: c0022d00 00040204 00000000 00090244 7709t3 opcode: CP_SET_CONSTANT (2d) (6 dwords) 7710 PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 } 7711 PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 } 7712 PA_SU_LINE_CNTL: { WIDTH = 0.000000 } 7713 PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER } 77140122e054: 0000: c0042d00 00040280 00000000 00000000 00000000 00000000 7715t3 opcode: CP_SET_CONSTANT (2d) (7 dwords) 7716 PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH } 7717 PA_CL_GB_VERT_CLIP_ADJ: 1.000000 7718 PA_CL_GB_VERT_DISC_ADJ: 1.000000 7719 PA_CL_GB_HORZ_CLIP_ADJ: 1.000000 7720 PA_CL_GB_HORZ_DISC_ADJ: 1.000000 77210122e06c: 0000: c0052d00 00040302 00000001 3f800000 3f800000 3f800000 3f800000 7722t3 opcode: CP_SET_CONSTANT (2d) (4 dwords) 7723 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 7724 PA_SC_WINDOW_SCISSOR_BR: { X = 4 | Y = 8 } 77250122e088: 0000: c0022d00 00040081 00000000 00080004 7726t3 opcode: CP_SET_CONSTANT (2d) (8 dwords) 7727 PA_CL_VPORT_XSCALE: 2.000000 7728 PA_CL_VPORT_XOFFSET: 2.000000 7729 PA_CL_VPORT_YSCALE: 4.000000 7730 PA_CL_VPORT_YOFFSET: 4.000000 7731 PA_CL_VPORT_ZSCALE: 0.000000 7732 PA_CL_VPORT_ZOFFSET: 0.000000 77330122e098: 0000: c0062d00 0004010f 40000000 40000000 40800000 40800000 00000000 00000000 7734t3 opcode: CP_SET_CONSTANT (2d) (10 dwords) 77350122e0c0: 2.000000 4.000000 0.000000 0.000000 2.000000 4.000000 0.000000 0.000000 77360122e0b8: 0000: c0082d00 00000184 40000000 40800000 00000000 00000000 40000000 40800000 7737* 7738t3 opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords) 7739 vertex shader, start=0000, size=0015 7740 2003 0007 1000 EXEC ADDR(0x3) CNT(0x2) 7741 03: 19481000 00262688 00000020 (S)FETCH: VERTEX R1.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) CONST(20, 0) 7742 04: 13480000 40262688 00001020 FETCH: VERTEX R0.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) OFFSET(16) CONST(20, 1) 7743 0000 0000 c200 ALLOC POSITION SIZE(0x0) 7744 1005 0002 1000 EXEC ADDR(0x5) CNT(0x1) 7745 05: 000f803e 00000000 c2010100 (S)ALU: MAXv export62 = R1, R1 ; gl_Position 7746 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0) 7747 1006 0000 2000 EXEC_END ADDR(0x6) CNT(0x1) 7748 06: 000f8000 00000000 c2000000 ALU: MAXv export0 = R0, R0 7749 0000 0000 0000 NOP 77500122e0e0: 0000: c0162b00 00000000 00000015 00072003 00001000 c2000000 00021005 00001000 77510122e100: 0020: c4000000 00001006 00002000 00000000 19481000 00262688 00000020 13480000 77520122e120: 0040: 40262688 00001020 000f803e 00000000 c2010100 000f8000 00000000 c2000000 7753t3 opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords) 7754 fragment shader, start=0000, size=000c 7755 1002 0003 1000 EXEC ADDR(0x2) CNT(0x1) 7756 02: 90000001 1ffff688 00000002 (S)FETCH: SAMPLE R0.xyzw = R0.xyz CONST(0) LOCATION(CENTER) 7757 0000 0000 c400 ALLOC PARAM/PIXEL SIZE(0x0) 7758 1003 0002 2000 EXEC_END ADDR(0x3) CNT(0x1) 7759 03: 000f8000 00000000 c2000000 (S)ALU: MAXv export0 = R0, R0 ; gl_FragColor 7760 0000 0000 0000 NOP 77610122e140: 0000: c00d2b00 00000001 0000000c 00031002 00001000 c4000000 00021003 00002000 77620122e160: 0020: 00000000 90000001 1ffff688 00000002 000f8000 00000000 c2000000 7763t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7764 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 } 77650122e17c: 0000: c0012d00 00040181 00000106 7766t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7767 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 } 77680122e188: 0000: c0012d00 00040180 10030002 7769t3 opcode: CP_SET_CONSTANT (2d) (6 dwords) 77700122e19c: 0.000000 0.000000 0.000000 0.000000 77710122e194: 0000: c0042d00 00000080 00000000 00000000 00000000 00000000 7772t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7773 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 } 77740122e1ac: 0000: c0012d00 00040202 00000c20 7775t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7776 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO } 77770122e1b8: 0000: c0012d00 00040201 00000000 7778t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7779 RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 77800122e1c4: 0000: c0012d00 00040104 0000000f 7781t3 opcode: CP_SET_CONSTANT (2d) (6 dwords) 7782 RB_BLEND_RED: 0 7783 RB_BLEND_GREEN: 0 7784 RB_BLEND_BLUE: 0 7785 RB_BLEND_ALPHA: 0 77860122e1d0: 0000: c0042d00 00040105 00000000 00000000 00000000 00000000 7787t3 opcode: CP_SET_CONSTANT (2d) (8 dwords) 7788 set texture const 0000 7789 clamp x/y/z: clamp-last-texel/clamp-last-texel/clamp-last-texel 7790 filter min/mag: point/point 7791 swizzle: zyxw 7792 addr=0108a000 (flags=806), size=256x256, pitch=16640, format=FMT_8_8_8_8 7793 mipaddr=00000000 (flags=200) 77940122e1e8: 0000: c0062d00 00010000 82024800 0108a806 001fe0ff 00000c14 00000000 00000200 7795t3 opcode: CP_SET_CONSTANT (2d) (3 dwords) 7796 VGT_INDX_OFFSET: 0 77970122e208: 0000: c0012d00 00040102 00000000 7798t0 write TC_CNTL_STATUS (0e00) 7799 TC_CNTL_STATUS: { L2_INVALIDATE } 78000122e214: 0000: 00000e00 00000001 7801t3 opcode: CP_WAIT_REG_EQ (52) (5 dwords) 78020122e21c: 0000: c0035200 000005d0 00000000 00001000 00000001 7803t3 opcode: CP_DRAW_INDX_BIN (34) (7 dwords) 78040122e230: 0000: c0053400 00000000 0003c004 00000000 00000003 01009040 00000006 7805t0 write CP_SCRATCH_REG7 (057f) 7806 CP_SCRATCH_REG7: 133 7807 :0,0,137,133 78080122e24c: 0000: 0000057f 00000085 7809t3 opcode: CP_NOP (10) (2 dwords) 78100122e254: 0000: c0001000 00000000 7811t3 opcode: CP_DRAW_INDX (22) (3 dwords) 7812 { VIZ_QUERY = 0 } 7813 { PRIM_TYPE = DI_PT_TRIFAN | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | NUM_INSTANCES = 0 | 0x40000 } 7814 draw: 0 7815 prim_type: DI_PT_TRIFAN (5) 7816 source_select: DI_SRC_SEL_AUTO_INDEX (2) 7817 num_indices: 1407 7818 draw[22] register values 7819 + ffffffff RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE } 7820 + 00000fff RBBM_PM_OVERRIDE2: 0xfff 7821 + 00000000 CP_PERFMON_CNTL: 0 7822!+ 00000089 CP_SCRATCH_REG6: 137 7823 :0,0,137,133 7824!+ 00000085 CP_SCRATCH_REG7: 133 7825 :0,0,137,133 7826 + 00000180 SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 } 7827 + 00000001 TC_CNTL_STATUS: { L2_INVALIDATE } 7828 + 00000002 TP0_CHICKEN: 0x2 7829 + 1c004046 RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 } 7830!+ 00000020 RB_SURFACE_INFO: { SURFACE_PITCH = 32 | MSAA_SAMPLES = 0 } 7831!+ 01266245 RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | LINEAR | ENDIAN = 0 | SWAP = 1 | BASE = 0x1266000 } 7832 + 80000000 PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 } 7833!+ 00080004 PA_SC_SCREEN_SCISSOR_BR: { X = 4 | Y = 8 } 7834 + 00000000 PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 } 7835 + 00000000 PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 7836!+ 00080004 PA_SC_WINDOW_SCISSOR_BR: { X = 4 | Y = 8 } 7837 + ffffffff VGT_MAX_VTX_INDX: 0xffffffff 7838 + 00000000 VGT_MIN_VTX_INDX: 0 7839 + 00000000 VGT_INDX_OFFSET: 0 7840 + 0000000f RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 7841 + 00000000 RB_BLEND_RED: 0 7842 + 00000000 RB_BLEND_GREEN: 0 7843 + 00000000 RB_BLEND_BLUE: 0 7844 + 00000000 RB_BLEND_ALPHA: 0 7845 + 00000000 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 7846 + 00000000 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 7847 + 00000000 RB_ALPHA_REF: 0 7848!+ 40000000 PA_CL_VPORT_XSCALE: 2.000000 7849!+ 40000000 PA_CL_VPORT_XOFFSET: 2.000000 7850!+ 40800000 PA_CL_VPORT_YSCALE: 4.000000 7851!+ 40800000 PA_CL_VPORT_YOFFSET: 4.000000 7852!+ 00000000 PA_CL_VPORT_ZSCALE: 0.000000 7853!+ 00000000 PA_CL_VPORT_ZOFFSET: 0.000000 7854 + 10030002 SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 } 7855 + 00000106 SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 } 7856 + ffffffff SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 } 7857 + 00000000 SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 } 7858 + 00000000 SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 } 7859 + 00000000 RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP } 7860 + 00000000 RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO } 7861!+ 00000c20 RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 } 7862 + 00000000 PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL } 7863!+ 00090244 PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST } 7864 + 0000043f PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT } 7865 + 00000004 RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH } 7866 + 88888888 RB_SAMPLE_POS: 0x88888888 7867!+ 00000000 PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 } 7868!+ 00000000 PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 } 7869!+ 00000000 PA_SU_LINE_CNTL: { WIDTH = 0.000000 } 7870 + 00000000 PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER } 7871 + 00000020 PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 } 7872 + 00000000 PA_SC_LINE_CNTL: { BRES_CNTL = 0 } 7873 + 00000000 PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 } 7874 + 00000001 PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH } 7875 + 3f800000 PA_CL_GB_VERT_CLIP_ADJ: 1.000000 7876 + 3f800000 PA_CL_GB_VERT_DISC_ADJ: 1.000000 7877 + 3f800000 PA_CL_GB_HORZ_CLIP_ADJ: 1.000000 7878 + 3f800000 PA_CL_GB_HORZ_DISC_ADJ: 1.000000 7879 + 00100020 SQ_VS_CONST: { BASE = 32 | SIZE = 256 } 7880 + 000e0120 SQ_PS_CONST: { BASE = 288 | SIZE = 224 } 7881 + 0000ffff PA_SC_AA_MASK: 0xffff 7882 + 00000002 VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 } 7883 + 00000002 VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 } 7884 + 0003c000 RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA } 7885 + ffffffff RB_COLOR_DEST_MASK: 0xffffffff 78860122e25c: 0000: c0012200 00000000 00040085 7887t0 write CP_SCRATCH_REG7 (057f) 7888NEEDS WFI: CP_SCRATCH_REG7 (57f) 7889 CP_SCRATCH_REG7: 134 7890 :0,0,137,134 78910122e268: 0000: 0000057f 00000086 7892t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 78930122e270: 0000: c0002600 00000000 7894t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 7895 { EVENT = CACHE_FLUSH } 7896 event CACHE_FLUSH 78970122e278: 0000: c0004600 00000006 7898t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 7899 { EVENT = CACHE_FLUSH } 7900 event CACHE_FLUSH 79010122e280: 0000: c0004600 00000006 7902t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 7903 { EVENT = CACHE_FLUSH } 7904 event CACHE_FLUSH 79050122e288: 0000: c0004600 00000006 7906t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 7907 { EVENT = CACHE_FLUSH } 7908 event CACHE_FLUSH 79090122e290: 0000: c0004600 00000006 7910t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 7911 { EVENT = CACHE_FLUSH } 7912 event CACHE_FLUSH 79130122e298: 0000: c0004600 00000006 7914t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 7915 { EVENT = CACHE_FLUSH } 7916 event CACHE_FLUSH 79170122e2a0: 0000: c0004600 00000006 7918t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 7919 { EVENT = CACHE_FLUSH } 7920 event CACHE_FLUSH 79210122e2a8: 0000: c0004600 00000006 7922t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 7923 { EVENT = CACHE_FLUSH } 7924 event CACHE_FLUSH 79250122e2b0: 0000: c0004600 00000006 7926t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 7927 { EVENT = CACHE_FLUSH } 7928 event CACHE_FLUSH 79290122e2b8: 0000: c0004600 00000006 7930t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 7931 { EVENT = CACHE_FLUSH } 7932 event CACHE_FLUSH 79330122e2c0: 0000: c0004600 00000006 7934t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 7935 { EVENT = CACHE_FLUSH } 7936 event CACHE_FLUSH 79370122e2c8: 0000: c0004600 00000006 7938t3 opcode: CP_EVENT_WRITE (46) (2 dwords) 7939 { EVENT = CACHE_FLUSH } 7940 event CACHE_FLUSH 79410122e2d0: 0000: c0004600 00000006 79420122f1d8: 0000: c0013700 0122e000 000000b6 7943t2 nop 7944############################################################ 7945vertices: 0 7946