1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_pipe.h"
24 #include "r600_public.h"
25 #include "r600_isa.h"
26 #include "evergreen_compute.h"
27 #include "r600d.h"
28
29 #include "sb/sb_public.h"
30
31 #include <errno.h>
32 #include "pipe/p_shader_tokens.h"
33 #include "util/u_debug.h"
34 #include "util/u_memory.h"
35 #include "util/u_screen.h"
36 #include "util/u_simple_shaders.h"
37 #include "util/u_upload_mgr.h"
38 #include "util/u_math.h"
39 #include "vl/vl_decoder.h"
40 #include "vl/vl_video_buffer.h"
41 #include "radeon_video.h"
42 #include "radeon_uvd.h"
43 #include "util/os_time.h"
44
45 static const struct debug_named_value r600_debug_options[] = {
46 /* features */
47 { "nocpdma", DBG_NO_CP_DMA, "Disable CP DMA" },
48
49 /* shader backend */
50 { "nosb", DBG_NO_SB, "Disable sb backend for graphics shaders" },
51 { "sbdry", DBG_SB_DRY_RUN, "Don't use optimized bytecode (just print the dumps)" },
52 { "sbstat", DBG_SB_STAT, "Print optimization statistics for shaders" },
53 { "sbdump", DBG_SB_DUMP, "Print IR dumps after some optimization passes" },
54 { "sbnofallback", DBG_SB_NO_FALLBACK, "Abort on errors instead of fallback" },
55 { "sbdisasm", DBG_SB_DISASM, "Use sb disassembler for shader dumps" },
56 { "sbsafemath", DBG_SB_SAFEMATH, "Disable unsafe math optimizations" },
57 { "nirsb", DBG_NIR_SB, "Enable NIR with SB optimizer"},
58
59 DEBUG_NAMED_VALUE_END /* must be last */
60 };
61
62 /*
63 * pipe_context
64 */
65
r600_destroy_context(struct pipe_context * context)66 static void r600_destroy_context(struct pipe_context *context)
67 {
68 struct r600_context *rctx = (struct r600_context *)context;
69 unsigned sh, i;
70
71 r600_isa_destroy(rctx->isa);
72
73 r600_sb_context_destroy(rctx->sb_context);
74
75 for (sh = 0; sh < (rctx->b.gfx_level < EVERGREEN ? R600_NUM_HW_STAGES : EG_NUM_HW_STAGES); sh++) {
76 r600_resource_reference(&rctx->scratch_buffers[sh].buffer, NULL);
77 }
78 r600_resource_reference(&rctx->dummy_cmask, NULL);
79 r600_resource_reference(&rctx->dummy_fmask, NULL);
80
81 if (rctx->append_fence)
82 pipe_resource_reference((struct pipe_resource**)&rctx->append_fence, NULL);
83 for (sh = 0; sh < PIPE_SHADER_TYPES; sh++) {
84 rctx->b.b.set_constant_buffer(&rctx->b.b, sh, R600_BUFFER_INFO_CONST_BUFFER, false, NULL);
85 free(rctx->driver_consts[sh].constants);
86 }
87
88 if (rctx->fixed_func_tcs_shader)
89 rctx->b.b.delete_tcs_state(&rctx->b.b, rctx->fixed_func_tcs_shader);
90
91 if (rctx->dummy_pixel_shader) {
92 rctx->b.b.delete_fs_state(&rctx->b.b, rctx->dummy_pixel_shader);
93 }
94 if (rctx->custom_dsa_flush) {
95 rctx->b.b.delete_depth_stencil_alpha_state(&rctx->b.b, rctx->custom_dsa_flush);
96 }
97 if (rctx->custom_blend_resolve) {
98 rctx->b.b.delete_blend_state(&rctx->b.b, rctx->custom_blend_resolve);
99 }
100 if (rctx->custom_blend_decompress) {
101 rctx->b.b.delete_blend_state(&rctx->b.b, rctx->custom_blend_decompress);
102 }
103 if (rctx->custom_blend_fastclear) {
104 rctx->b.b.delete_blend_state(&rctx->b.b, rctx->custom_blend_fastclear);
105 }
106 util_unreference_framebuffer_state(&rctx->framebuffer.state);
107
108 if (rctx->gs_rings.gsvs_ring.buffer)
109 pipe_resource_reference(&rctx->gs_rings.gsvs_ring.buffer, NULL);
110
111 if (rctx->gs_rings.esgs_ring.buffer)
112 pipe_resource_reference(&rctx->gs_rings.esgs_ring.buffer, NULL);
113
114 for (sh = 0; sh < PIPE_SHADER_TYPES; ++sh)
115 for (i = 0; i < PIPE_MAX_CONSTANT_BUFFERS; ++i)
116 rctx->b.b.set_constant_buffer(context, sh, i, false, NULL);
117
118 if (rctx->blitter) {
119 util_blitter_destroy(rctx->blitter);
120 }
121 u_suballocator_destroy(&rctx->allocator_fetch_shader);
122
123 r600_release_command_buffer(&rctx->start_cs_cmd);
124
125 FREE(rctx->start_compute_cs_cmd.buf);
126
127 r600_common_context_cleanup(&rctx->b);
128
129 r600_resource_reference(&rctx->trace_buf, NULL);
130 r600_resource_reference(&rctx->last_trace_buf, NULL);
131 radeon_clear_saved_cs(&rctx->last_gfx);
132
133 FREE(rctx);
134 }
135
r600_create_context(struct pipe_screen * screen,void * priv,unsigned flags)136 static struct pipe_context *r600_create_context(struct pipe_screen *screen,
137 void *priv, unsigned flags)
138 {
139 struct r600_context *rctx = CALLOC_STRUCT(r600_context);
140 struct r600_screen* rscreen = (struct r600_screen *)screen;
141 struct radeon_winsys *ws = rscreen->b.ws;
142
143 if (!rctx)
144 return NULL;
145
146 rctx->b.b.screen = screen;
147 assert(!priv);
148 rctx->b.b.priv = NULL; /* for threaded_context_unwrap_sync */
149 rctx->b.b.destroy = r600_destroy_context;
150 rctx->b.set_atom_dirty = (void *)r600_set_atom_dirty;
151
152 if (!r600_common_context_init(&rctx->b, &rscreen->b, flags))
153 goto fail;
154
155 rctx->screen = rscreen;
156 list_inithead(&rctx->texture_buffers);
157
158 r600_init_blit_functions(rctx);
159
160 if (rscreen->b.info.ip[AMD_IP_UVD].num_queues) {
161 rctx->b.b.create_video_codec = r600_uvd_create_decoder;
162 rctx->b.b.create_video_buffer = r600_video_buffer_create;
163 } else {
164 rctx->b.b.create_video_codec = vl_create_decoder;
165 rctx->b.b.create_video_buffer = vl_video_buffer_create;
166 }
167
168 if (getenv("R600_TRACE"))
169 rctx->is_debug = true;
170 r600_init_common_state_functions(rctx);
171
172 switch (rctx->b.gfx_level) {
173 case R600:
174 case R700:
175 r600_init_state_functions(rctx);
176 r600_init_atom_start_cs(rctx);
177 rctx->custom_dsa_flush = r600_create_db_flush_dsa(rctx);
178 rctx->custom_blend_resolve = rctx->b.gfx_level == R700 ? r700_create_resolve_blend(rctx)
179 : r600_create_resolve_blend(rctx);
180 rctx->custom_blend_decompress = r600_create_decompress_blend(rctx);
181 rctx->has_vertex_cache = !(rctx->b.family == CHIP_RV610 ||
182 rctx->b.family == CHIP_RV620 ||
183 rctx->b.family == CHIP_RS780 ||
184 rctx->b.family == CHIP_RS880 ||
185 rctx->b.family == CHIP_RV710);
186 break;
187 case EVERGREEN:
188 case CAYMAN:
189 evergreen_init_state_functions(rctx);
190 evergreen_init_atom_start_cs(rctx);
191 evergreen_init_atom_start_compute_cs(rctx);
192 rctx->custom_dsa_flush = evergreen_create_db_flush_dsa(rctx);
193 rctx->custom_blend_resolve = evergreen_create_resolve_blend(rctx);
194 rctx->custom_blend_decompress = evergreen_create_decompress_blend(rctx);
195 rctx->custom_blend_fastclear = evergreen_create_fastclear_blend(rctx);
196 rctx->has_vertex_cache = !(rctx->b.family == CHIP_CEDAR ||
197 rctx->b.family == CHIP_PALM ||
198 rctx->b.family == CHIP_SUMO ||
199 rctx->b.family == CHIP_SUMO2 ||
200 rctx->b.family == CHIP_CAICOS ||
201 rctx->b.family == CHIP_CAYMAN ||
202 rctx->b.family == CHIP_ARUBA);
203
204 rctx->append_fence = pipe_buffer_create(rctx->b.b.screen, PIPE_BIND_CUSTOM,
205 PIPE_USAGE_DEFAULT, 32);
206 break;
207 default:
208 R600_ERR("Unsupported gfx level %d.\n", rctx->b.gfx_level);
209 goto fail;
210 }
211
212 ws->cs_create(&rctx->b.gfx.cs, rctx->b.ctx, AMD_IP_GFX,
213 r600_context_gfx_flush, rctx, false);
214 rctx->b.gfx.flush = r600_context_gfx_flush;
215
216 u_suballocator_init(&rctx->allocator_fetch_shader, &rctx->b.b, 64 * 1024,
217 0, PIPE_USAGE_DEFAULT, 0, FALSE);
218
219 rctx->isa = calloc(1, sizeof(struct r600_isa));
220 if (!rctx->isa || r600_isa_init(rctx, rctx->isa))
221 goto fail;
222
223 if (rscreen->b.debug_flags & DBG_FORCE_DMA)
224 rctx->b.b.resource_copy_region = rctx->b.dma_copy;
225
226 rctx->blitter = util_blitter_create(&rctx->b.b);
227 if (rctx->blitter == NULL)
228 goto fail;
229 util_blitter_set_texture_multisample(rctx->blitter, rscreen->has_msaa);
230 rctx->blitter->draw_rectangle = r600_draw_rectangle;
231
232 r600_begin_new_cs(rctx);
233
234 rctx->dummy_pixel_shader =
235 util_make_fragment_cloneinput_shader(&rctx->b.b, 0,
236 TGSI_SEMANTIC_GENERIC,
237 TGSI_INTERPOLATE_CONSTANT);
238 rctx->b.b.bind_fs_state(&rctx->b.b, rctx->dummy_pixel_shader);
239
240 return &rctx->b.b;
241
242 fail:
243 r600_destroy_context(&rctx->b.b);
244 return NULL;
245 }
246
is_nir_enabled(struct r600_common_screen * screen)247 static bool is_nir_enabled(struct r600_common_screen *screen) {
248 return (screen->debug_flags & DBG_NIR_PREFERRED); /* &&
249 screen->family >= CHIP_CEDAR);*/
250 }
251
252 /*
253 * pipe_screen
254 */
255
r600_get_param(struct pipe_screen * pscreen,enum pipe_cap param)256 static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
257 {
258 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
259 enum radeon_family family = rscreen->b.family;
260
261 switch (param) {
262 /* Supported features (boolean caps). */
263 case PIPE_CAP_NPOT_TEXTURES:
264 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
265 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
266 case PIPE_CAP_ANISOTROPIC_FILTER:
267 case PIPE_CAP_POINT_SPRITE:
268 case PIPE_CAP_OCCLUSION_QUERY:
269 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
270 case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
271 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
272 case PIPE_CAP_TEXTURE_SWIZZLE:
273 case PIPE_CAP_DEPTH_CLIP_DISABLE:
274 case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
275 case PIPE_CAP_SHADER_STENCIL_EXPORT:
276 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
277 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
278 case PIPE_CAP_FS_COORD_ORIGIN_UPPER_LEFT:
279 case PIPE_CAP_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
280 case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
281 case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES:
282 case PIPE_CAP_SEAMLESS_CUBE_MAP:
283 case PIPE_CAP_PRIMITIVE_RESTART:
284 case PIPE_CAP_PRIMITIVE_RESTART_FIXED_INDEX:
285 case PIPE_CAP_CONDITIONAL_RENDER:
286 case PIPE_CAP_TEXTURE_BARRIER:
287 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
288 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
289 case PIPE_CAP_VS_INSTANCEID:
290 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
291 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
292 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
293 case PIPE_CAP_START_INSTANCE:
294 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
295 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
296 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
297 case PIPE_CAP_TEXTURE_MULTISAMPLE:
298 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
299 case PIPE_CAP_VS_WINDOW_SPACE_POSITION:
300 case PIPE_CAP_VS_LAYER_VIEWPORT:
301 case PIPE_CAP_SAMPLE_SHADING:
302 case PIPE_CAP_CLIP_HALFZ:
303 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
304 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
305 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
306 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
307 case PIPE_CAP_TEXTURE_QUERY_SAMPLES:
308 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
309 case PIPE_CAP_INVALIDATE_BUFFER:
310 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
311 case PIPE_CAP_QUERY_MEMORY_INFO:
312 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
313 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
314 case PIPE_CAP_CLEAR_TEXTURE:
315 case PIPE_CAP_LEGACY_MATH_RULES:
316 case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
317 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
318 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
319 return 1;
320
321 case PIPE_CAP_NIR_ATOMICS_AS_DEREF:
322 return rscreen->b.debug_flags & DBG_NIR_PREFERRED;
323
324 case PIPE_CAP_TEXTURE_TRANSFER_MODES:
325 return PIPE_TEXTURE_TRANSFER_BLIT;
326
327 case PIPE_CAP_SHAREABLE_SHADERS:
328 return 0;
329
330 case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET:
331 /* Optimal number for good TexSubImage performance on Polaris10. */
332 return 64 * 1024 * 1024;
333
334 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
335 return 1;
336
337 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
338 return !R600_BIG_ENDIAN && rscreen->b.info.has_userptr;
339
340 case PIPE_CAP_COMPUTE:
341 return rscreen->b.gfx_level > R700;
342
343 case PIPE_CAP_TGSI_TEXCOORD:
344 return 1;
345
346 case PIPE_CAP_NIR_IMAGES_AS_DEREF:
347 case PIPE_CAP_FAKE_SW_MSAA:
348 return 0;
349
350 case PIPE_CAP_MAX_TEXEL_BUFFER_ELEMENTS_UINT:
351 return MIN2(rscreen->b.info.max_heap_size_kb * 1024ull / 4, INT_MAX);
352
353 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
354 return R600_MAP_BUFFER_ALIGNMENT;
355
356 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
357 return 256;
358
359 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
360 return 4;
361 case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
362 if (!is_nir_enabled(&rscreen->b))
363 return 140;
364 FALLTHROUGH;
365 case PIPE_CAP_GLSL_FEATURE_LEVEL:
366 if (family >= CHIP_CEDAR)
367 return is_nir_enabled(&rscreen->b) ? 450 : 430;
368 return 330;
369
370 /* Supported except the original R600. */
371 case PIPE_CAP_INDEP_BLEND_ENABLE:
372 case PIPE_CAP_INDEP_BLEND_FUNC:
373 /* R600 doesn't support per-MRT blends */
374 return family == CHIP_R600 ? 0 : 1;
375
376 /* Supported on Evergreen. */
377 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
378 case PIPE_CAP_CUBE_MAP_ARRAY:
379 case PIPE_CAP_TEXTURE_GATHER_SM5:
380 case PIPE_CAP_TEXTURE_QUERY_LOD:
381 case PIPE_CAP_FS_FINE_DERIVATIVE:
382 case PIPE_CAP_SAMPLER_VIEW_TARGET:
383 case PIPE_CAP_SHADER_PACK_HALF_FLOAT:
384 case PIPE_CAP_SHADER_CLOCK:
385 case PIPE_CAP_SHADER_ARRAY_COMPONENTS:
386 case PIPE_CAP_QUERY_BUFFER_OBJECT:
387 case PIPE_CAP_IMAGE_STORE_FORMATTED:
388 return family >= CHIP_CEDAR ? 1 : 0;
389 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
390 return family >= CHIP_CEDAR ? 4 : 0;
391 case PIPE_CAP_DRAW_INDIRECT:
392 /* kernel command checker support is also required */
393 return family >= CHIP_CEDAR;
394
395 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
396 return family >= CHIP_CEDAR ? 0 : 1;
397
398 case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
399 return 8;
400
401 case PIPE_CAP_MAX_GS_INVOCATIONS:
402 return 32;
403
404 /* shader buffer objects */
405 case PIPE_CAP_MAX_SHADER_BUFFER_SIZE_UINT:
406 return 1 << 27;
407 case PIPE_CAP_MAX_COMBINED_SHADER_BUFFERS:
408 return 8;
409
410 case PIPE_CAP_INT64:
411 case PIPE_CAP_DOUBLES:
412 if (rscreen->b.family == CHIP_ARUBA ||
413 rscreen->b.family == CHIP_CAYMAN ||
414 rscreen->b.family == CHIP_CYPRESS ||
415 rscreen->b.family == CHIP_HEMLOCK)
416 return 1;
417 if (is_nir_enabled(&rscreen->b) &&
418 rscreen->b.family >= CHIP_CEDAR)
419 return 1;
420 return 0;
421
422 case PIPE_CAP_TWO_SIDED_COLOR:
423 return !is_nir_enabled(&rscreen->b);
424 case PIPE_CAP_INT64_DIVMOD:
425 /* it is actually not supported, but the nir lowering handles this corectly wheras
426 * the glsl lowering path seems to not initialize the buildins correctly.
427 */
428 return is_nir_enabled(&rscreen->b);
429 case PIPE_CAP_CULL_DISTANCE:
430 return 1;
431
432 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
433 if (family >= CHIP_CEDAR)
434 return 256;
435 return 0;
436
437 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
438 if (family >= CHIP_CEDAR)
439 return 30;
440 else
441 return 0;
442 /* Stream output. */
443 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
444 return rscreen->b.has_streamout ? 4 : 0;
445 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
446 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
447 return rscreen->b.has_streamout ? 1 : 0;
448 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
449 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
450 return 32*4;
451
452 /* Geometry shader output. */
453 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
454 return 1024;
455 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
456 return 16384;
457 case PIPE_CAP_MAX_VERTEX_STREAMS:
458 return family >= CHIP_CEDAR ? 4 : 1;
459
460 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
461 /* Should be 2047, but 2048 is a requirement for GL 4.4 */
462 return 2048;
463
464 /* Texturing. */
465 case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
466 if (family >= CHIP_CEDAR)
467 return 16384;
468 else
469 return 8192;
470 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
471 if (family >= CHIP_CEDAR)
472 return 15;
473 else
474 return 14;
475 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
476 /* textures support 8192, but layered rendering supports 2048 */
477 return 12;
478 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
479 /* textures support 8192, but layered rendering supports 2048 */
480 return 2048;
481
482 /* Render targets. */
483 case PIPE_CAP_MAX_RENDER_TARGETS:
484 /* XXX some r6xx are buggy and can only do 4 */
485 return 8;
486
487 case PIPE_CAP_MAX_VIEWPORTS:
488 return R600_MAX_VIEWPORTS;
489 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
490 case PIPE_CAP_RASTERIZER_SUBPIXEL_BITS:
491 return 8;
492
493 /* Timer queries, present when the clock frequency is non zero. */
494 case PIPE_CAP_QUERY_TIME_ELAPSED:
495 case PIPE_CAP_QUERY_TIMESTAMP:
496 return rscreen->b.info.clock_crystal_freq != 0;
497
498 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
499 case PIPE_CAP_MIN_TEXEL_OFFSET:
500 return -8;
501
502 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
503 case PIPE_CAP_MAX_TEXEL_OFFSET:
504 return 7;
505
506 case PIPE_CAP_MAX_VARYINGS:
507 return 32;
508
509 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
510 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600;
511 case PIPE_CAP_ENDIANNESS:
512 return PIPE_ENDIAN_LITTLE;
513
514 case PIPE_CAP_VENDOR_ID:
515 return ATI_VENDOR_ID;
516 case PIPE_CAP_DEVICE_ID:
517 return rscreen->b.info.pci_id;
518 case PIPE_CAP_ACCELERATED:
519 return 1;
520 case PIPE_CAP_VIDEO_MEMORY:
521 return rscreen->b.info.vram_size_kb >> 10;
522 case PIPE_CAP_UMA:
523 return 0;
524 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
525 return rscreen->b.gfx_level >= R700;
526 case PIPE_CAP_PCI_GROUP:
527 return rscreen->b.info.pci_domain;
528 case PIPE_CAP_PCI_BUS:
529 return rscreen->b.info.pci_bus;
530 case PIPE_CAP_PCI_DEVICE:
531 return rscreen->b.info.pci_dev;
532 case PIPE_CAP_PCI_FUNCTION:
533 return rscreen->b.info.pci_func;
534
535 case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTERS:
536 if (rscreen->b.family >= CHIP_CEDAR && rscreen->has_atomics)
537 return 8;
538 return 0;
539 case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTER_BUFFERS:
540 if (rscreen->b.family >= CHIP_CEDAR && rscreen->has_atomics)
541 return EG_MAX_ATOMIC_BUFFERS;
542 return 0;
543
544 default:
545 return u_pipe_screen_get_param_defaults(pscreen, param);
546 }
547 }
548
r600_get_shader_param(struct pipe_screen * pscreen,enum pipe_shader_type shader,enum pipe_shader_cap param)549 static int r600_get_shader_param(struct pipe_screen* pscreen,
550 enum pipe_shader_type shader,
551 enum pipe_shader_cap param)
552 {
553 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
554
555 switch(shader)
556 {
557 case PIPE_SHADER_FRAGMENT:
558 case PIPE_SHADER_VERTEX:
559 break;
560 case PIPE_SHADER_GEOMETRY:
561 break;
562 case PIPE_SHADER_TESS_CTRL:
563 case PIPE_SHADER_TESS_EVAL:
564 case PIPE_SHADER_COMPUTE:
565 if (rscreen->b.family >= CHIP_CEDAR)
566 break;
567 FALLTHROUGH;
568 default:
569 return 0;
570 }
571
572 switch (param) {
573 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
574 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
575 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
576 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
577 return 16384;
578 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
579 return 32;
580 case PIPE_SHADER_CAP_MAX_INPUTS:
581 return shader == PIPE_SHADER_VERTEX ? 16 : 32;
582 case PIPE_SHADER_CAP_MAX_OUTPUTS:
583 return shader == PIPE_SHADER_FRAGMENT ? 8 : 32;
584 case PIPE_SHADER_CAP_MAX_TEMPS:
585 return 256; /* Max native temporaries. */
586 case PIPE_SHADER_CAP_MAX_CONST_BUFFER0_SIZE:
587 if (shader == PIPE_SHADER_COMPUTE) {
588 uint64_t max_const_buffer_size;
589 enum pipe_shader_ir ir_type = is_nir_enabled(&rscreen->b) ?
590 PIPE_SHADER_IR_NIR: PIPE_SHADER_IR_TGSI;
591 pscreen->get_compute_param(pscreen, ir_type,
592 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
593 &max_const_buffer_size);
594 return MIN2(max_const_buffer_size, INT_MAX);
595
596 } else {
597 return R600_MAX_CONST_BUFFER_SIZE;
598 }
599 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
600 return R600_MAX_USER_CONST_BUFFERS;
601 case PIPE_SHADER_CAP_CONT_SUPPORTED:
602 return 1;
603 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
604 return 1;
605 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
606 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
607 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
608 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
609 return 1;
610 case PIPE_SHADER_CAP_SUBROUTINES:
611 case PIPE_SHADER_CAP_INT64_ATOMICS:
612 case PIPE_SHADER_CAP_FP16:
613 case PIPE_SHADER_CAP_FP16_DERIVATIVES:
614 case PIPE_SHADER_CAP_FP16_CONST_BUFFERS:
615 case PIPE_SHADER_CAP_INT16:
616 case PIPE_SHADER_CAP_GLSL_16BIT_CONSTS:
617 return 0;
618 case PIPE_SHADER_CAP_INTEGERS:
619 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
620 return 1;
621 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
622 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
623 return 16;
624 case PIPE_SHADER_CAP_PREFERRED_IR:
625 if (rscreen->b.debug_flags & DBG_USE_TGSI)
626 return PIPE_SHADER_IR_TGSI;
627 return PIPE_SHADER_IR_NIR;
628 case PIPE_SHADER_CAP_SUPPORTED_IRS: {
629 int ir = 0;
630 if (shader == PIPE_SHADER_COMPUTE)
631 ir = 1 << PIPE_SHADER_IR_NATIVE;
632 ir |= 1 << PIPE_SHADER_IR_TGSI;
633 if (is_nir_enabled(&rscreen->b)) {
634 ir |= 1 << PIPE_SHADER_IR_NIR;
635 }
636 return ir;
637 }
638 case PIPE_SHADER_CAP_DROUND_SUPPORTED:
639 case PIPE_SHADER_CAP_DFRACEXP_DLDEXP_SUPPORTED:
640 case PIPE_SHADER_CAP_LDEXP_SUPPORTED:
641 return 0;
642 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
643 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
644 if (rscreen->b.family >= CHIP_CEDAR &&
645 (shader == PIPE_SHADER_FRAGMENT || shader == PIPE_SHADER_COMPUTE))
646 return 8;
647 return 0;
648 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
649 if (rscreen->b.family >= CHIP_CEDAR && rscreen->has_atomics)
650 return 8;
651 return 0;
652 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
653 /* having to allocate the atomics out amongst shaders stages is messy,
654 so give compute 8 buffers and all the others one */
655 if (rscreen->b.family >= CHIP_CEDAR && rscreen->has_atomics) {
656 return EG_MAX_ATOMIC_BUFFERS;
657 }
658 return 0;
659 }
660 return 0;
661 }
662
r600_destroy_screen(struct pipe_screen * pscreen)663 static void r600_destroy_screen(struct pipe_screen* pscreen)
664 {
665 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
666
667 if (!rscreen)
668 return;
669
670 if (!rscreen->b.ws->unref(rscreen->b.ws))
671 return;
672
673 if (rscreen->global_pool) {
674 compute_memory_pool_delete(rscreen->global_pool);
675 }
676
677 r600_destroy_common_screen(&rscreen->b);
678 }
679
r600_resource_create(struct pipe_screen * screen,const struct pipe_resource * templ)680 static struct pipe_resource *r600_resource_create(struct pipe_screen *screen,
681 const struct pipe_resource *templ)
682 {
683 if (templ->target == PIPE_BUFFER &&
684 (templ->bind & PIPE_BIND_GLOBAL))
685 return r600_compute_global_buffer_create(screen, templ);
686
687 return r600_resource_create_common(screen, templ);
688 }
689
r600_screen_create(struct radeon_winsys * ws,const struct pipe_screen_config * config)690 struct pipe_screen *r600_screen_create(struct radeon_winsys *ws,
691 const struct pipe_screen_config *config)
692 {
693 struct r600_screen *rscreen = CALLOC_STRUCT(r600_screen);
694
695 if (!rscreen) {
696 return NULL;
697 }
698
699 /* Set functions first. */
700 rscreen->b.b.context_create = r600_create_context;
701 rscreen->b.b.destroy = r600_destroy_screen;
702 rscreen->b.b.get_param = r600_get_param;
703 rscreen->b.b.get_shader_param = r600_get_shader_param;
704 rscreen->b.b.resource_create = r600_resource_create;
705
706 if (!r600_common_screen_init(&rscreen->b, ws)) {
707 FREE(rscreen);
708 return NULL;
709 }
710
711 if (rscreen->b.info.gfx_level >= EVERGREEN) {
712 rscreen->b.b.is_format_supported = evergreen_is_format_supported;
713 } else {
714 rscreen->b.b.is_format_supported = r600_is_format_supported;
715 }
716
717 rscreen->b.debug_flags |= debug_get_flags_option("R600_DEBUG", r600_debug_options, 0);
718 if (debug_get_bool_option("R600_DEBUG_COMPUTE", FALSE))
719 rscreen->b.debug_flags |= DBG_COMPUTE;
720 if (debug_get_bool_option("R600_DUMP_SHADERS", FALSE))
721 rscreen->b.debug_flags |= DBG_ALL_SHADERS | DBG_FS;
722 if (!debug_get_bool_option("R600_HYPERZ", TRUE))
723 rscreen->b.debug_flags |= DBG_NO_HYPERZ;
724
725 if (rscreen->b.family == CHIP_UNKNOWN) {
726 fprintf(stderr, "r600: Unknown chipset 0x%04X\n", rscreen->b.info.pci_id);
727 FREE(rscreen);
728 return NULL;
729 }
730
731 rscreen->b.has_streamout = true;
732
733 rscreen->has_msaa = true;
734
735 /* MSAA support. */
736 switch (rscreen->b.gfx_level) {
737 case R600:
738 case R700:
739 rscreen->has_compressed_msaa_texturing = false;
740 break;
741 case EVERGREEN:
742 rscreen->has_compressed_msaa_texturing = true;
743 break;
744 case CAYMAN:
745 rscreen->has_compressed_msaa_texturing = true;
746 break;
747 default:
748 rscreen->has_compressed_msaa_texturing = false;
749 }
750
751 rscreen->b.has_cp_dma = !(rscreen->b.debug_flags & DBG_NO_CP_DMA);
752
753 rscreen->b.barrier_flags.cp_to_L2 =
754 R600_CONTEXT_INV_VERTEX_CACHE |
755 R600_CONTEXT_INV_TEX_CACHE |
756 R600_CONTEXT_INV_CONST_CACHE;
757 rscreen->b.barrier_flags.compute_to_L2 = R600_CONTEXT_CS_PARTIAL_FLUSH | R600_CONTEXT_FLUSH_AND_INV;
758
759 rscreen->global_pool = compute_memory_pool_new(rscreen);
760
761 /* Create the auxiliary context. This must be done last. */
762 rscreen->b.aux_context = rscreen->b.b.context_create(&rscreen->b.b, NULL, 0);
763
764 rscreen->has_atomics = true;
765 #if 0 /* This is for testing whether aux_context and buffer clearing work correctly. */
766 struct pipe_resource templ = {};
767
768 templ.width0 = 4;
769 templ.height0 = 2048;
770 templ.depth0 = 1;
771 templ.array_size = 1;
772 templ.target = PIPE_TEXTURE_2D;
773 templ.format = PIPE_FORMAT_R8G8B8A8_UNORM;
774 templ.usage = PIPE_USAGE_DEFAULT;
775
776 struct r600_resource *res = r600_resource(rscreen->screen.resource_create(&rscreen->screen, &templ));
777 unsigned char *map = ws->buffer_map(res->buf, NULL, PIPE_MAP_WRITE);
778
779 memset(map, 0, 256);
780
781 r600_screen_clear_buffer(rscreen, &res->b.b, 4, 4, 0xCC);
782 r600_screen_clear_buffer(rscreen, &res->b.b, 8, 4, 0xDD);
783 r600_screen_clear_buffer(rscreen, &res->b.b, 12, 4, 0xEE);
784 r600_screen_clear_buffer(rscreen, &res->b.b, 20, 4, 0xFF);
785 r600_screen_clear_buffer(rscreen, &res->b.b, 32, 20, 0x87);
786
787 ws->buffer_wait(res->buf, RADEON_USAGE_WRITE);
788
789 int i;
790 for (i = 0; i < 256; i++) {
791 printf("%02X", map[i]);
792 if (i % 16 == 15)
793 printf("\n");
794 }
795 #endif
796
797 if (rscreen->b.debug_flags & DBG_TEST_DMA)
798 r600_test_dma(&rscreen->b);
799
800 r600_query_fix_enabled_rb_mask(&rscreen->b);
801 return &rscreen->b.b;
802 }
803