1 /**************************************************************************
2 *
3 * Copyright 2017 Advanced Micro Devices, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28 #include "pipe/p_video_codec.h"
29 #include "radeon_vcn_enc.h"
30 #include "radeon_video.h"
31 #include "si_pipe.h"
32 #include "util/u_video.h"
33
34 #include <stdio.h>
35
36 #define RENCODE_FW_INTERFACE_MAJOR_VERSION 1
37 #define RENCODE_FW_INTERFACE_MINOR_VERSION 1
38
39 #define RENCODE_IB_PARAM_SESSION_INFO 0x00000001
40 #define RENCODE_IB_PARAM_TASK_INFO 0x00000002
41 #define RENCODE_IB_PARAM_SESSION_INIT 0x00000003
42 #define RENCODE_IB_PARAM_LAYER_CONTROL 0x00000004
43 #define RENCODE_IB_PARAM_LAYER_SELECT 0x00000005
44 #define RENCODE_IB_PARAM_RATE_CONTROL_SESSION_INIT 0x00000006
45 #define RENCODE_IB_PARAM_RATE_CONTROL_LAYER_INIT 0x00000007
46 #define RENCODE_IB_PARAM_RATE_CONTROL_PER_PICTURE 0x00000008
47 #define RENCODE_IB_PARAM_QUALITY_PARAMS 0x00000009
48 #define RENCODE_IB_PARAM_DIRECT_OUTPUT_NALU 0x0000000a
49 #define RENCODE_IB_PARAM_SLICE_HEADER 0x0000000b
50 #define RENCODE_IB_PARAM_INPUT_FORMAT 0x0000000c
51 #define RENCODE_IB_PARAM_OUTPUT_FORMAT 0x0000000d
52 #define RENCODE_IB_PARAM_ENCODE_PARAMS 0x0000000f
53 #define RENCODE_IB_PARAM_INTRA_REFRESH 0x00000010
54 #define RENCODE_IB_PARAM_ENCODE_CONTEXT_BUFFER 0x00000011
55 #define RENCODE_IB_PARAM_VIDEO_BITSTREAM_BUFFER 0x00000012
56 #define RENCODE_IB_PARAM_FEEDBACK_BUFFER 0x00000015
57
58 #define RENCODE_HEVC_IB_PARAM_SLICE_CONTROL 0x00100001
59 #define RENCODE_HEVC_IB_PARAM_SPEC_MISC 0x00100002
60 #define RENCODE_HEVC_IB_PARAM_LOOP_FILTER 0x00100003
61
62 #define RENCODE_H264_IB_PARAM_SLICE_CONTROL 0x00200001
63 #define RENCODE_H264_IB_PARAM_SPEC_MISC 0x00200002
64 #define RENCODE_H264_IB_PARAM_ENCODE_PARAMS 0x00200003
65 #define RENCODE_H264_IB_PARAM_DEBLOCKING_FILTER 0x00200004
66
67 #define RENCODE_COLOR_VOLUME_G22_BT709 0
68 #define RENCODE_COLOR_VOLUME_G10_BT2020 3
69
70 #define RENCODE_COLOR_BIT_DEPTH_8_BIT 0
71 #define RENCODE_COLOR_BIT_DEPTH_10_BIT 1
72
73 #define RENCODE_COLOR_PACKING_FORMAT_NV12 0
74 #define RENCODE_COLOR_PACKING_FORMAT_P010 1
75
radeon_enc_op_balance(struct radeon_encoder * enc)76 static void radeon_enc_op_balance(struct radeon_encoder *enc)
77 {
78 RADEON_ENC_BEGIN(RENCODE_IB_OP_SET_BALANCE_ENCODING_MODE);
79 RADEON_ENC_END();
80 }
81
radeon_enc_slice_header_hevc(struct radeon_encoder * enc)82 static void radeon_enc_slice_header_hevc(struct radeon_encoder *enc)
83 {
84 uint32_t instruction[RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS] = {0};
85 uint32_t num_bits[RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS] = {0};
86 unsigned int inst_index = 0;
87 unsigned int cdw_start = 0;
88 unsigned int cdw_filled = 0;
89 unsigned int bits_copied = 0;
90 RADEON_ENC_BEGIN(enc->cmd.slice_header);
91 radeon_enc_reset(enc);
92 radeon_enc_set_emulation_prevention(enc, false);
93
94 cdw_start = enc->cs.current.cdw;
95 radeon_enc_code_fixed_bits(enc, 0x0, 1);
96 radeon_enc_code_fixed_bits(enc, enc->enc_pic.nal_unit_type, 6);
97 radeon_enc_code_fixed_bits(enc, 0x0, 6);
98 radeon_enc_code_fixed_bits(enc, 0x1, 3);
99
100 radeon_enc_flush_headers(enc);
101 instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
102 num_bits[inst_index] = enc->bits_output - bits_copied;
103 bits_copied = enc->bits_output;
104 inst_index++;
105
106 instruction[inst_index] = RENCODE_HEVC_HEADER_INSTRUCTION_FIRST_SLICE;
107 inst_index++;
108
109 if ((enc->enc_pic.nal_unit_type >= 16) && (enc->enc_pic.nal_unit_type <= 23))
110 radeon_enc_code_fixed_bits(enc, 0x0, 1);
111
112 radeon_enc_code_ue(enc, 0x0);
113
114 radeon_enc_flush_headers(enc);
115 instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
116 num_bits[inst_index] = enc->bits_output - bits_copied;
117 bits_copied = enc->bits_output;
118 inst_index++;
119
120 instruction[inst_index] = RENCODE_HEVC_HEADER_INSTRUCTION_SLICE_SEGMENT;
121 inst_index++;
122
123 instruction[inst_index] = RENCODE_HEVC_HEADER_INSTRUCTION_DEPENDENT_SLICE_END;
124 inst_index++;
125
126 switch (enc->enc_pic.picture_type) {
127 case PIPE_H2645_ENC_PICTURE_TYPE_I:
128 case PIPE_H2645_ENC_PICTURE_TYPE_IDR:
129 radeon_enc_code_ue(enc, 0x2);
130 break;
131 case PIPE_H2645_ENC_PICTURE_TYPE_P:
132 case PIPE_H2645_ENC_PICTURE_TYPE_SKIP:
133 radeon_enc_code_ue(enc, 0x1);
134 break;
135 case PIPE_H2645_ENC_PICTURE_TYPE_B:
136 radeon_enc_code_ue(enc, 0x0);
137 break;
138 default:
139 radeon_enc_code_ue(enc, 0x1);
140 }
141
142 if ((enc->enc_pic.nal_unit_type != 19) && (enc->enc_pic.nal_unit_type != 20)) {
143 radeon_enc_code_fixed_bits(enc, enc->enc_pic.pic_order_cnt, enc->enc_pic.log2_max_poc);
144 if (enc->enc_pic.picture_type == PIPE_H2645_ENC_PICTURE_TYPE_P)
145 radeon_enc_code_fixed_bits(enc, 0x1, 1);
146 else {
147 radeon_enc_code_fixed_bits(enc, 0x0, 1);
148 radeon_enc_code_fixed_bits(enc, 0x0, 1);
149 radeon_enc_code_ue(enc, 0x0);
150 radeon_enc_code_ue(enc, 0x0);
151 }
152 }
153
154 if (enc->enc_pic.sample_adaptive_offset_enabled_flag) {
155 radeon_enc_flush_headers(enc);
156 instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
157 num_bits[inst_index] = enc->bits_output - bits_copied;
158 bits_copied = enc->bits_output;
159 inst_index++;
160
161 instruction[inst_index] = RENCODE_HEVC_HEADER_INSTRUCTION_SAO_ENABLE;
162 inst_index++;
163 }
164
165 if ((enc->enc_pic.picture_type == PIPE_H2645_ENC_PICTURE_TYPE_P) ||
166 (enc->enc_pic.picture_type == PIPE_H2645_ENC_PICTURE_TYPE_B)) {
167 radeon_enc_code_fixed_bits(enc, 0x0, 1);
168 radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_spec_misc.cabac_init_flag, 1);
169 radeon_enc_code_ue(enc, 5 - enc->enc_pic.max_num_merge_cand);
170 }
171
172 radeon_enc_flush_headers(enc);
173 instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
174 num_bits[inst_index] = enc->bits_output - bits_copied;
175 bits_copied = enc->bits_output;
176 inst_index++;
177
178 instruction[inst_index] = RENCODE_HEVC_HEADER_INSTRUCTION_SLICE_QP_DELTA;
179 inst_index++;
180
181 if ((enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled) &&
182 (!enc->enc_pic.hevc_deblock.deblocking_filter_disabled ||
183 enc->enc_pic.sample_adaptive_offset_enabled_flag)) {
184 if (enc->enc_pic.sample_adaptive_offset_enabled_flag) {
185 radeon_enc_flush_headers(enc);
186 instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
187 num_bits[inst_index] = enc->bits_output - bits_copied;
188 bits_copied = enc->bits_output;
189 inst_index++;
190
191 instruction[inst_index] = RENCODE_HEVC_HEADER_INSTRUCTION_LOOP_FILTER_ACROSS_SLICES_ENABLE;
192 inst_index++;
193 }
194 else
195 radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled, 1);
196 }
197
198 radeon_enc_flush_headers(enc);
199 instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
200 num_bits[inst_index] = enc->bits_output - bits_copied;
201 bits_copied = enc->bits_output;
202 inst_index++;
203 instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_END;
204
205 cdw_filled = enc->cs.current.cdw - cdw_start;
206 for (int i = 0; i < RENCODE_SLICE_HEADER_TEMPLATE_MAX_TEMPLATE_SIZE_IN_DWORDS - cdw_filled; i++)
207 RADEON_ENC_CS(0x00000000);
208
209 for (int j = 0; j < RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS; j++) {
210 RADEON_ENC_CS(instruction[j]);
211 RADEON_ENC_CS(num_bits[j]);
212 }
213
214 RADEON_ENC_END();
215 }
216
radeon_enc_loop_filter_hevc(struct radeon_encoder * enc)217 static void radeon_enc_loop_filter_hevc(struct radeon_encoder *enc)
218 {
219 RADEON_ENC_BEGIN(enc->cmd.deblocking_filter_hevc);
220 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled);
221 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.deblocking_filter_disabled);
222 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.beta_offset_div2);
223 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.tc_offset_div2);
224 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.cb_qp_offset);
225 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.cr_qp_offset);
226 RADEON_ENC_CS(!enc->enc_pic.sample_adaptive_offset_enabled_flag);
227 RADEON_ENC_END();
228 }
229
radeon_enc_nalu_sps_hevc(struct radeon_encoder * enc)230 static void radeon_enc_nalu_sps_hevc(struct radeon_encoder *enc)
231 {
232 RADEON_ENC_BEGIN(enc->cmd.nalu);
233 RADEON_ENC_CS(RENCODE_DIRECT_OUTPUT_NALU_TYPE_SPS);
234 uint32_t *size_in_bytes = &enc->cs.current.buf[enc->cs.current.cdw++];
235 int i;
236
237 radeon_enc_reset(enc);
238 radeon_enc_set_emulation_prevention(enc, false);
239 radeon_enc_code_fixed_bits(enc, 0x00000001, 32);
240 radeon_enc_code_fixed_bits(enc, 0x4201, 16);
241 radeon_enc_byte_align(enc);
242 radeon_enc_set_emulation_prevention(enc, true);
243 radeon_enc_code_fixed_bits(enc, 0x0, 4);
244 radeon_enc_code_fixed_bits(enc, enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1, 3);
245 radeon_enc_code_fixed_bits(enc, 0x1, 1);
246 radeon_enc_code_fixed_bits(enc, 0x0, 2);
247 radeon_enc_code_fixed_bits(enc, enc->enc_pic.general_tier_flag, 1);
248 radeon_enc_code_fixed_bits(enc, enc->enc_pic.general_profile_idc, 5);
249
250 if (enc->enc_pic.general_profile_idc == 2)
251 radeon_enc_code_fixed_bits(enc, 0x20000000, 32);
252 else
253 radeon_enc_code_fixed_bits(enc, 0x60000000, 32);
254
255 radeon_enc_code_fixed_bits(enc, 0xb0000000, 32);
256 radeon_enc_code_fixed_bits(enc, 0x0, 16);
257 radeon_enc_code_fixed_bits(enc, enc->enc_pic.general_level_idc, 8);
258
259 for (i = 0; i < (enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1); i++)
260 radeon_enc_code_fixed_bits(enc, 0x0, 2);
261
262 if ((enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1) > 0) {
263 for (i = (enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1); i < 8; i++)
264 radeon_enc_code_fixed_bits(enc, 0x0, 2);
265 }
266
267 radeon_enc_code_ue(enc, 0x0);
268 radeon_enc_code_ue(enc, enc->enc_pic.chroma_format_idc);
269 radeon_enc_code_ue(enc, enc->enc_pic.session_init.aligned_picture_width);
270 radeon_enc_code_ue(enc, enc->enc_pic.session_init.aligned_picture_height);
271
272 if ((enc->enc_pic.crop_left != 0) || (enc->enc_pic.crop_right != 0) ||
273 (enc->enc_pic.crop_top != 0) || (enc->enc_pic.crop_bottom != 0)) {
274 radeon_enc_code_fixed_bits(enc, 0x1, 1);
275 radeon_enc_code_ue(enc, enc->enc_pic.crop_left);
276 radeon_enc_code_ue(enc, enc->enc_pic.crop_right);
277 radeon_enc_code_ue(enc, enc->enc_pic.crop_top);
278 radeon_enc_code_ue(enc, enc->enc_pic.crop_bottom);
279 } else if (enc->enc_pic.session_init.padding_width != 0 ||
280 enc->enc_pic.session_init.padding_height != 0) {
281 radeon_enc_code_fixed_bits(enc, 0x1, 1);
282 radeon_enc_code_ue(enc, enc->enc_pic.session_init.padding_width / 2);
283 radeon_enc_code_ue(enc, enc->enc_pic.session_init.padding_width / 2);
284 radeon_enc_code_ue(enc, enc->enc_pic.session_init.padding_height / 2);
285 radeon_enc_code_ue(enc, enc->enc_pic.session_init.padding_height / 2);
286 } else
287 radeon_enc_code_fixed_bits(enc, 0x0, 1);
288
289 radeon_enc_code_ue(enc, enc->enc_pic.bit_depth_luma_minus8);
290 radeon_enc_code_ue(enc, enc->enc_pic.bit_depth_chroma_minus8);
291 radeon_enc_code_ue(enc, enc->enc_pic.log2_max_poc - 4);
292 radeon_enc_code_fixed_bits(enc, 0x0, 1);
293 radeon_enc_code_ue(enc, 1);
294 radeon_enc_code_ue(enc, 0x0);
295 radeon_enc_code_ue(enc, 0x0);
296 radeon_enc_code_ue(enc, enc->enc_pic.hevc_spec_misc.log2_min_luma_coding_block_size_minus3);
297 // Only support CTBSize 64
298 radeon_enc_code_ue(enc,
299 6 - (enc->enc_pic.hevc_spec_misc.log2_min_luma_coding_block_size_minus3 + 3));
300 radeon_enc_code_ue(enc, enc->enc_pic.log2_min_transform_block_size_minus2);
301 radeon_enc_code_ue(enc, enc->enc_pic.log2_diff_max_min_transform_block_size);
302 radeon_enc_code_ue(enc, enc->enc_pic.max_transform_hierarchy_depth_inter);
303 radeon_enc_code_ue(enc, enc->enc_pic.max_transform_hierarchy_depth_intra);
304
305 radeon_enc_code_fixed_bits(enc, 0x0, 1);
306 radeon_enc_code_fixed_bits(enc, !enc->enc_pic.hevc_spec_misc.amp_disabled, 1);
307 radeon_enc_code_fixed_bits(enc, enc->enc_pic.sample_adaptive_offset_enabled_flag, 1);
308 radeon_enc_code_fixed_bits(enc, enc->enc_pic.pcm_enabled_flag, 1);
309
310 radeon_enc_code_ue(enc, 1);
311 radeon_enc_code_ue(enc, 1);
312 radeon_enc_code_ue(enc, 0);
313 radeon_enc_code_ue(enc, 0);
314 radeon_enc_code_fixed_bits(enc, 0x1, 1);
315
316 radeon_enc_code_fixed_bits(enc, 0x0, 1);
317
318 radeon_enc_code_fixed_bits(enc, 0, 1);
319 radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_spec_misc.strong_intra_smoothing_enabled, 1);
320
321 radeon_enc_code_fixed_bits(enc, 0x0, 1);
322
323 radeon_enc_code_fixed_bits(enc, 0x0, 1);
324
325 radeon_enc_code_fixed_bits(enc, 0x1, 1);
326
327 radeon_enc_byte_align(enc);
328 radeon_enc_flush_headers(enc);
329 *size_in_bytes = (enc->bits_output + 7) / 8;
330 RADEON_ENC_END();
331 }
332
radeon_enc_nalu_pps_hevc(struct radeon_encoder * enc)333 static void radeon_enc_nalu_pps_hevc(struct radeon_encoder *enc)
334 {
335 RADEON_ENC_BEGIN(enc->cmd.nalu);
336 RADEON_ENC_CS(RENCODE_DIRECT_OUTPUT_NALU_TYPE_PPS);
337 uint32_t *size_in_bytes = &enc->cs.current.buf[enc->cs.current.cdw++];
338 radeon_enc_reset(enc);
339 radeon_enc_set_emulation_prevention(enc, false);
340 radeon_enc_code_fixed_bits(enc, 0x00000001, 32);
341 radeon_enc_code_fixed_bits(enc, 0x4401, 16);
342 radeon_enc_byte_align(enc);
343 radeon_enc_set_emulation_prevention(enc, true);
344 radeon_enc_code_ue(enc, 0x0);
345 radeon_enc_code_ue(enc, 0x0);
346 radeon_enc_code_fixed_bits(enc, 0x1, 1);
347 radeon_enc_code_fixed_bits(enc, 0x0, 4);
348 radeon_enc_code_fixed_bits(enc, 0x0, 1);
349 radeon_enc_code_fixed_bits(enc, 0x1, 1);
350 radeon_enc_code_ue(enc, 0x0);
351 radeon_enc_code_ue(enc, 0x0);
352 radeon_enc_code_se(enc, 0x0);
353 radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_spec_misc.constrained_intra_pred_flag, 1);
354 radeon_enc_code_fixed_bits(enc, 0x0, 1);
355 if (enc->enc_pic.rc_session_init.rate_control_method == RENCODE_RATE_CONTROL_METHOD_NONE)
356 radeon_enc_code_fixed_bits(enc, 0x0, 1);
357 else {
358 radeon_enc_code_fixed_bits(enc, 0x1, 1);
359 radeon_enc_code_ue(enc, 0x0);
360 }
361 radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.cb_qp_offset);
362 radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.cr_qp_offset);
363 radeon_enc_code_fixed_bits(enc, 0x0, 1);
364 radeon_enc_code_fixed_bits(enc, 0x0, 2);
365 radeon_enc_code_fixed_bits(enc, 0x0, 1);
366 radeon_enc_code_fixed_bits(enc, 0x0, 1);
367 radeon_enc_code_fixed_bits(enc, 0x0, 1);
368 radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled, 1);
369 radeon_enc_code_fixed_bits(enc, 0x1, 1);
370 radeon_enc_code_fixed_bits(enc, 0x0, 1);
371 radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_deblock.deblocking_filter_disabled, 1);
372
373 if (!enc->enc_pic.hevc_deblock.deblocking_filter_disabled) {
374 radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.beta_offset_div2);
375 radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.tc_offset_div2);
376 }
377
378 radeon_enc_code_fixed_bits(enc, 0x0, 1);
379 radeon_enc_code_fixed_bits(enc, 0x0, 1);
380 radeon_enc_code_ue(enc, enc->enc_pic.log2_parallel_merge_level_minus2);
381 radeon_enc_code_fixed_bits(enc, 0x0, 2);
382
383 radeon_enc_code_fixed_bits(enc, 0x1, 1);
384
385 radeon_enc_byte_align(enc);
386 radeon_enc_flush_headers(enc);
387 *size_in_bytes = (enc->bits_output + 7) / 8;
388 RADEON_ENC_END();
389 }
390
radeon_enc_input_format(struct radeon_encoder * enc)391 static void radeon_enc_input_format(struct radeon_encoder *enc)
392 {
393 RADEON_ENC_BEGIN(enc->cmd.input_format);
394 if (enc->base.profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10) {
395 RADEON_ENC_CS(RENCODE_COLOR_VOLUME_G10_BT2020);
396 RADEON_ENC_CS(0);
397 RADEON_ENC_CS(0);
398 RADEON_ENC_CS(0);
399 RADEON_ENC_CS(0);
400 RADEON_ENC_CS(RENCODE_COLOR_BIT_DEPTH_10_BIT);
401 RADEON_ENC_CS(RENCODE_COLOR_PACKING_FORMAT_P010);
402 } else {
403 RADEON_ENC_CS(RENCODE_COLOR_VOLUME_G22_BT709);
404 RADEON_ENC_CS(0);
405 RADEON_ENC_CS(0);
406 RADEON_ENC_CS(0);
407 RADEON_ENC_CS(0);
408 RADEON_ENC_CS(RENCODE_COLOR_BIT_DEPTH_8_BIT);
409 RADEON_ENC_CS(RENCODE_COLOR_PACKING_FORMAT_NV12);
410 }
411 RADEON_ENC_END();
412 }
413
radeon_enc_output_format(struct radeon_encoder * enc)414 static void radeon_enc_output_format(struct radeon_encoder *enc)
415 {
416 RADEON_ENC_BEGIN(enc->cmd.output_format);
417 if (enc->base.profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10) {
418 RADEON_ENC_CS(RENCODE_COLOR_VOLUME_G10_BT2020);
419 RADEON_ENC_CS(0);
420 RADEON_ENC_CS(0);
421 RADEON_ENC_CS(RENCODE_COLOR_BIT_DEPTH_10_BIT);
422 } else {
423 RADEON_ENC_CS(RENCODE_COLOR_VOLUME_G22_BT709);
424 RADEON_ENC_CS(0);
425 RADEON_ENC_CS(0);
426 RADEON_ENC_CS(RENCODE_COLOR_BIT_DEPTH_8_BIT);
427 }
428 RADEON_ENC_END();
429 }
430
encode(struct radeon_encoder * enc)431 static void encode(struct radeon_encoder *enc)
432 {
433 enc->before_encode(enc);
434 enc->session_info(enc);
435 enc->total_task_size = 0;
436 enc->task_info(enc, enc->need_feedback);
437
438 enc->encode_headers(enc);
439 enc->ctx(enc);
440 enc->bitstream(enc);
441 enc->feedback(enc);
442 enc->intra_refresh(enc);
443 enc->input_format(enc);
444 enc->output_format(enc);
445
446 enc->op_preset(enc);
447 enc->op_enc(enc);
448 *enc->p_task_size = (enc->total_task_size);
449 }
450
radeon_enc_2_0_init(struct radeon_encoder * enc)451 void radeon_enc_2_0_init(struct radeon_encoder *enc)
452 {
453 radeon_enc_1_2_init(enc);
454 enc->encode = encode;
455 enc->input_format = radeon_enc_input_format;
456 enc->output_format = radeon_enc_output_format;
457
458 if (u_reduce_video_profile(enc->base.profile) == PIPE_VIDEO_FORMAT_HEVC) {
459 enc->deblocking_filter = radeon_enc_loop_filter_hevc;
460 enc->nalu_sps = radeon_enc_nalu_sps_hevc;
461 enc->nalu_pps = radeon_enc_nalu_pps_hevc;
462 enc->slice_header = radeon_enc_slice_header_hevc;
463 enc->op_preset = radeon_enc_op_balance;
464 }
465
466 enc->cmd.session_info = RENCODE_IB_PARAM_SESSION_INFO;
467 enc->cmd.task_info = RENCODE_IB_PARAM_TASK_INFO;
468 enc->cmd.session_init = RENCODE_IB_PARAM_SESSION_INIT;
469 enc->cmd.layer_control = RENCODE_IB_PARAM_LAYER_CONTROL;
470 enc->cmd.layer_select = RENCODE_IB_PARAM_LAYER_SELECT;
471 enc->cmd.rc_session_init = RENCODE_IB_PARAM_RATE_CONTROL_SESSION_INIT;
472 enc->cmd.rc_layer_init = RENCODE_IB_PARAM_RATE_CONTROL_LAYER_INIT;
473 enc->cmd.rc_per_pic = RENCODE_IB_PARAM_RATE_CONTROL_PER_PICTURE;
474 enc->cmd.quality_params = RENCODE_IB_PARAM_QUALITY_PARAMS;
475 enc->cmd.nalu = RENCODE_IB_PARAM_DIRECT_OUTPUT_NALU;
476 enc->cmd.slice_header = RENCODE_IB_PARAM_SLICE_HEADER;
477 enc->cmd.input_format = RENCODE_IB_PARAM_INPUT_FORMAT;
478 enc->cmd.output_format = RENCODE_IB_PARAM_OUTPUT_FORMAT;
479 enc->cmd.enc_params = RENCODE_IB_PARAM_ENCODE_PARAMS;
480 enc->cmd.intra_refresh = RENCODE_IB_PARAM_INTRA_REFRESH;
481 enc->cmd.ctx = RENCODE_IB_PARAM_ENCODE_CONTEXT_BUFFER;
482 enc->cmd.bitstream = RENCODE_IB_PARAM_VIDEO_BITSTREAM_BUFFER;
483 enc->cmd.feedback = RENCODE_IB_PARAM_FEEDBACK_BUFFER;
484 enc->cmd.slice_control_hevc = RENCODE_HEVC_IB_PARAM_SLICE_CONTROL;
485 enc->cmd.spec_misc_hevc = RENCODE_HEVC_IB_PARAM_SPEC_MISC;
486 enc->cmd.deblocking_filter_hevc = RENCODE_HEVC_IB_PARAM_LOOP_FILTER;
487 enc->cmd.slice_control_h264 = RENCODE_H264_IB_PARAM_SLICE_CONTROL;
488 enc->cmd.spec_misc_h264 = RENCODE_H264_IB_PARAM_SPEC_MISC;
489 enc->cmd.enc_params_h264 = RENCODE_H264_IB_PARAM_ENCODE_PARAMS;
490 enc->cmd.deblocking_filter_h264 = RENCODE_H264_IB_PARAM_DEBLOCKING_FILTER;
491
492 enc->enc_pic.session_info.interface_version =
493 ((RENCODE_FW_INTERFACE_MAJOR_VERSION << RENCODE_IF_MAJOR_VERSION_SHIFT) |
494 (RENCODE_FW_INTERFACE_MINOR_VERSION << RENCODE_IF_MINOR_VERSION_SHIFT));
495 }
496