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1 /*
2  * Copyright © 2015 Broadcom
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21  * IN THE SOFTWARE.
22  */
23 
24 #include "vc4_qir.h"
25 #include "kernel/vc4_packet.h"
26 #include "compiler/nir/nir_builder.h"
27 
28 /** @file vc4_nir_lower_txf_ms.c
29  * Walks the NIR generated by TGSI-to-NIR to lower its nir_texop_txf_ms
30  * coordinates to do the math necessary and use a plain nir_texop_txf instead.
31  *
32  * MSAA textures are laid out as 32x32-aligned blocks of RGBA8888 or Z24S8.
33  * We can't load them through the normal sampler path because of the lack of
34  * linear support in the hardware.  So, we treat MSAA textures as a giant UBO
35  * and do the math in the shader.
36  */
37 
38 static nir_ssa_def *
vc4_nir_lower_txf_ms_instr(nir_builder * b,nir_instr * instr,void * data)39 vc4_nir_lower_txf_ms_instr(nir_builder *b, nir_instr *instr, void *data)
40 {
41         nir_tex_instr *txf_ms = nir_instr_as_tex(instr);
42         const struct vc4_compile *c = data;
43 
44         nir_tex_instr *txf = nir_tex_instr_create(c->s, 1);
45         txf->op = nir_texop_txf;
46         txf->texture_index = txf_ms->texture_index;
47         txf->coord_components = txf_ms->coord_components;
48         txf->is_shadow = txf_ms->is_shadow;
49         txf->is_new_style_shadow = txf_ms->is_new_style_shadow;
50         txf->dest_type = txf_ms->dest_type;
51 
52         nir_ssa_def *coord = NULL, *sample_index = NULL;
53         for (int i = 0; i < txf_ms->num_srcs; i++) {
54                 assert(txf_ms->src[i].src.is_ssa);
55 
56                 switch (txf_ms->src[i].src_type) {
57                 case nir_tex_src_coord:
58                         coord = txf_ms->src[i].src.ssa;
59                         break;
60                 case nir_tex_src_ms_index:
61                         sample_index = txf_ms->src[i].src.ssa;
62                         break;
63                 default:
64                         unreachable("Unknown txf_ms src\n");
65                 }
66         }
67         assert(coord);
68         assert(sample_index);
69 
70         nir_ssa_def *x = nir_channel(b, coord, 0);
71         nir_ssa_def *y = nir_channel(b, coord, 1);
72 
73         uint32_t tile_w = 32;
74         uint32_t tile_h = 32;
75         uint32_t tile_w_shift = 5;
76         uint32_t tile_h_shift = 5;
77         uint32_t tile_size = (tile_h * tile_w *
78                               VC4_MAX_SAMPLES * sizeof(uint32_t));
79         unsigned unit = txf_ms->texture_index;
80         uint32_t w = align(c->key->tex[unit].msaa_width, tile_w);
81         uint32_t w_tiles = w / tile_w;
82 
83         nir_ssa_def *x_tile = nir_ushr(b, x, nir_imm_int(b, tile_w_shift));
84         nir_ssa_def *y_tile = nir_ushr(b, y, nir_imm_int(b, tile_h_shift));
85         nir_ssa_def *tile_addr = nir_iadd(b,
86                                           nir_imul(b, x_tile,
87                                                    nir_imm_int(b, tile_size)),
88                                           nir_imul(b, y_tile,
89                                                    nir_imm_int(b, (w_tiles *
90                                                                    tile_size))));
91         nir_ssa_def *x_subspan = nir_iand(b, x,
92                                           nir_imm_int(b, (tile_w - 1) & ~1));
93         nir_ssa_def *y_subspan = nir_iand(b, y,
94                                           nir_imm_int(b, (tile_h - 1) & ~1));
95         nir_ssa_def *subspan_addr = nir_iadd(b,
96                                              nir_imul(b, x_subspan,
97                                                       nir_imm_int(b, 2 * VC4_MAX_SAMPLES * sizeof(uint32_t))),
98                                              nir_imul(b, y_subspan,
99                                                       nir_imm_int(b,
100                                                                   tile_w *
101                                                                   VC4_MAX_SAMPLES *
102                                                                   sizeof(uint32_t))));
103 
104         nir_ssa_def *pixel_addr = nir_ior(b,
105                                           nir_iand(b,
106                                                    nir_ishl(b, x,
107                                                             nir_imm_int(b, 2)),
108                                                    nir_imm_int(b, (1 << 2))),
109                                           nir_iand(b,
110                                                    nir_ishl(b, y,
111                                                             nir_imm_int(b, 3)),
112                                                    nir_imm_int(b, (1 << 3))));
113 
114         nir_ssa_def *sample_addr = nir_ishl(b, sample_index, nir_imm_int(b, 4));
115 
116         nir_ssa_def *addr = nir_iadd(b,
117                                      nir_ior(b, sample_addr, pixel_addr),
118                                      nir_iadd(b, subspan_addr, tile_addr));
119 
120         txf->src[0].src_type = nir_tex_src_coord;
121         txf->src[0].src = nir_src_for_ssa(nir_vec2(b, addr, nir_imm_int(b, 0)));
122         nir_ssa_dest_init(&txf->instr, &txf->dest, 4, 32, NULL);
123         nir_builder_instr_insert(b, &txf->instr);
124 
125         return &txf->dest.ssa;
126 }
127 
128 static bool
vc4_nir_lower_txf_ms_filter(const nir_instr * instr,const void * data)129 vc4_nir_lower_txf_ms_filter(const nir_instr *instr, const void *data)
130 {
131         return (instr->type == nir_instr_type_tex &&
132                 nir_instr_as_tex(instr)->op == nir_texop_txf_ms);
133 }
134 
135 void
vc4_nir_lower_txf_ms(nir_shader * s,struct vc4_compile * c)136 vc4_nir_lower_txf_ms(nir_shader *s, struct vc4_compile *c)
137 {
138         nir_shader_lower_instructions(s,
139                                       vc4_nir_lower_txf_ms_filter,
140                                       vc4_nir_lower_txf_ms_instr,
141                                       c);
142 }
143