1 /*
2 * Copyright © 2019 Red Hat.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 /* use a gallium context to execute a command buffer */
25
26 #include "lvp_private.h"
27
28 #include "pipe/p_context.h"
29 #include "pipe/p_state.h"
30 #include "lvp_conv.h"
31
32 #include "pipe/p_shader_tokens.h"
33 #include "tgsi/tgsi_text.h"
34 #include "tgsi/tgsi_parse.h"
35 #include "tgsi/tgsi_from_mesa.h"
36
37 #include "util/format/u_format.h"
38 #include "util/u_surface.h"
39 #include "util/u_sampler.h"
40 #include "util/u_box.h"
41 #include "util/u_inlines.h"
42 #include "util/u_memory.h"
43 #include "util/u_prim.h"
44 #include "util/u_prim_restart.h"
45 #include "util/format/u_format_zs.h"
46 #include "util/ptralloc.h"
47 #include "tgsi/tgsi_from_mesa.h"
48
49 #include "vk_cmd_enqueue_entrypoints.h"
50 #include "vk_util.h"
51
52 #define VK_PROTOTYPES
53 #include <vulkan/vulkan.h>
54
55 #define DOUBLE_EQ(a, b) (fabs((a) - (b)) < DBL_EPSILON)
56
57 enum gs_output {
58 GS_OUTPUT_NONE,
59 GS_OUTPUT_NOT_LINES,
60 GS_OUTPUT_LINES,
61 };
62
63 struct lvp_render_attachment {
64 struct lvp_image_view *imgv;
65 VkResolveModeFlags resolve_mode;
66 struct lvp_image_view *resolve_imgv;
67 VkAttachmentLoadOp load_op;
68 VkClearValue clear_value;
69 };
70
71 struct rendering_state {
72 struct pipe_context *pctx;
73 struct u_upload_mgr *uploader;
74 struct cso_context *cso;
75
76 bool blend_dirty;
77 bool rs_dirty;
78 bool dsa_dirty;
79 bool stencil_ref_dirty;
80 bool clip_state_dirty;
81 bool blend_color_dirty;
82 bool ve_dirty;
83 bool vb_dirty;
84 bool constbuf_dirty[PIPE_SHADER_TYPES];
85 bool pcbuf_dirty[PIPE_SHADER_TYPES];
86 bool has_pcbuf[PIPE_SHADER_TYPES];
87 bool inlines_dirty[PIPE_SHADER_TYPES];
88 bool vp_dirty;
89 bool scissor_dirty;
90 bool ib_dirty;
91 bool sample_mask_dirty;
92 bool min_samples_dirty;
93 struct pipe_draw_indirect_info indirect_info;
94 struct pipe_draw_info info;
95
96 struct pipe_grid_info dispatch_info;
97 struct pipe_framebuffer_state framebuffer;
98
99 struct pipe_blend_state blend_state;
100 struct {
101 float offset_units;
102 float offset_scale;
103 float offset_clamp;
104 bool enabled;
105 } depth_bias;
106 struct pipe_rasterizer_state rs_state;
107 struct pipe_depth_stencil_alpha_state dsa_state;
108
109 struct pipe_blend_color blend_color;
110 struct pipe_stencil_ref stencil_ref;
111 struct pipe_clip_state clip_state;
112
113 int num_scissors;
114 struct pipe_scissor_state scissors[16];
115
116 int num_viewports;
117 struct pipe_viewport_state viewports[16];
118 struct {
119 float min, max;
120 } depth[16];
121
122 uint8_t patch_vertices;
123 ubyte index_size;
124 unsigned index_offset;
125 struct pipe_resource *index_buffer;
126 struct pipe_constant_buffer const_buffer[PIPE_SHADER_TYPES][16];
127 int num_const_bufs[PIPE_SHADER_TYPES];
128 int num_vb;
129 unsigned start_vb;
130 struct pipe_vertex_buffer vb[PIPE_MAX_ATTRIBS];
131 struct cso_velems_state velem;
132
133 struct lvp_access_info access[MESA_SHADER_STAGES];
134 struct pipe_sampler_view *sv[PIPE_SHADER_TYPES][PIPE_MAX_SHADER_SAMPLER_VIEWS];
135 int num_sampler_views[PIPE_SHADER_TYPES];
136 struct pipe_sampler_state ss[PIPE_SHADER_TYPES][PIPE_MAX_SAMPLERS];
137 /* cso_context api is stupid */
138 const struct pipe_sampler_state *cso_ss_ptr[PIPE_SHADER_TYPES][PIPE_MAX_SAMPLERS];
139 int num_sampler_states[PIPE_SHADER_TYPES];
140 bool sv_dirty[PIPE_SHADER_TYPES];
141 bool ss_dirty[PIPE_SHADER_TYPES];
142
143 struct pipe_image_view iv[PIPE_SHADER_TYPES][PIPE_MAX_SHADER_IMAGES];
144 int num_shader_images[PIPE_SHADER_TYPES];
145 struct pipe_shader_buffer sb[PIPE_SHADER_TYPES][PIPE_MAX_SHADER_BUFFERS];
146 int num_shader_buffers[PIPE_SHADER_TYPES];
147 bool iv_dirty[PIPE_SHADER_TYPES];
148 bool sb_dirty[PIPE_SHADER_TYPES];
149 bool disable_multisample;
150 enum gs_output gs_output_lines : 2;
151
152 uint32_t color_write_disables:8;
153 uint32_t pad:13;
154
155 void *ss_cso[PIPE_SHADER_TYPES][PIPE_MAX_SAMPLERS];
156 void *velems_cso;
157
158 uint8_t push_constants[128 * 4];
159 uint16_t push_size[2]; //gfx, compute
160 struct {
161 void *block[MAX_PER_STAGE_DESCRIPTOR_UNIFORM_BLOCKS * MAX_SETS];
162 uint16_t size[MAX_PER_STAGE_DESCRIPTOR_UNIFORM_BLOCKS * MAX_SETS];
163 uint16_t count;
164 } uniform_blocks[PIPE_SHADER_TYPES];
165
166 VkRect2D render_area;
167 bool suspending;
168 uint32_t color_att_count;
169 struct lvp_render_attachment *color_att;
170 struct lvp_render_attachment depth_att;
171 struct lvp_render_attachment stencil_att;
172 struct lvp_image_view *ds_imgv;
173 struct lvp_image_view *ds_resolve_imgv;
174 uint32_t forced_sample_count;
175 VkResolveModeFlagBits forced_depth_resolve_mode;
176 VkResolveModeFlagBits forced_stencil_resolve_mode;
177
178 uint32_t sample_mask;
179 unsigned min_samples;
180
181 uint32_t num_so_targets;
182 struct pipe_stream_output_target *so_targets[PIPE_MAX_SO_BUFFERS];
183 uint32_t so_offsets[PIPE_MAX_SO_BUFFERS];
184
185 struct lvp_pipeline *pipeline[2];
186 };
187
188 ALWAYS_INLINE static void
assert_subresource_layers(const struct pipe_resource * pres,const VkImageSubresourceLayers * layers,const VkOffset3D * offsets)189 assert_subresource_layers(const struct pipe_resource *pres, const VkImageSubresourceLayers *layers, const VkOffset3D *offsets)
190 {
191 #ifndef NDEBUG
192 if (pres->target == PIPE_TEXTURE_3D) {
193 assert(layers->baseArrayLayer == 0);
194 assert(layers->layerCount == 1);
195 assert(offsets[0].z <= pres->depth0);
196 assert(offsets[1].z <= pres->depth0);
197 } else {
198 assert(layers->baseArrayLayer < pres->array_size);
199 assert(layers->baseArrayLayer + layers->layerCount <= pres->array_size);
200 assert(offsets[0].z == 0);
201 assert(offsets[1].z == 1);
202 }
203 #endif
204 }
205
finish_fence(struct rendering_state * state)206 static void finish_fence(struct rendering_state *state)
207 {
208 struct pipe_fence_handle *handle = NULL;
209
210 state->pctx->flush(state->pctx, &handle, 0);
211
212 state->pctx->screen->fence_finish(state->pctx->screen,
213 NULL,
214 handle, PIPE_TIMEOUT_INFINITE);
215 state->pctx->screen->fence_reference(state->pctx->screen,
216 &handle, NULL);
217 }
218
219 static unsigned
get_pcbuf_size(struct rendering_state * state,enum pipe_shader_type pstage)220 get_pcbuf_size(struct rendering_state *state, enum pipe_shader_type pstage)
221 {
222 bool is_compute = pstage == PIPE_SHADER_COMPUTE;
223 return state->has_pcbuf[pstage] ? state->push_size[is_compute] : 0;
224 }
225
226 static unsigned
calc_ubo0_size(struct rendering_state * state,enum pipe_shader_type pstage)227 calc_ubo0_size(struct rendering_state *state, enum pipe_shader_type pstage)
228 {
229 unsigned size = get_pcbuf_size(state, pstage);
230 for (unsigned i = 0; i < state->uniform_blocks[pstage].count; i++)
231 size += state->uniform_blocks[pstage].size[i];
232 return size;
233 }
234
235 static void
fill_ubo0(struct rendering_state * state,uint8_t * mem,enum pipe_shader_type pstage)236 fill_ubo0(struct rendering_state *state, uint8_t *mem, enum pipe_shader_type pstage)
237 {
238 unsigned push_size = get_pcbuf_size(state, pstage);
239 if (push_size)
240 memcpy(mem, state->push_constants, push_size);
241
242 mem += push_size;
243 for (unsigned i = 0; i < state->uniform_blocks[pstage].count; i++) {
244 unsigned size = state->uniform_blocks[pstage].size[i];
245 memcpy(mem, state->uniform_blocks[pstage].block[i], size);
246 mem += size;
247 }
248 }
249
250 static void
update_pcbuf(struct rendering_state * state,enum pipe_shader_type pstage)251 update_pcbuf(struct rendering_state *state, enum pipe_shader_type pstage)
252 {
253 uint8_t *mem;
254 struct pipe_constant_buffer cbuf;
255 unsigned size = calc_ubo0_size(state, pstage);
256 cbuf.buffer_size = size;
257 cbuf.buffer = NULL;
258 cbuf.user_buffer = NULL;
259 u_upload_alloc(state->uploader, 0, size, 64, &cbuf.buffer_offset, &cbuf.buffer, (void**)&mem);
260 fill_ubo0(state, mem, pstage);
261 state->pctx->set_constant_buffer(state->pctx, pstage, 0, true, &cbuf);
262 state->pcbuf_dirty[pstage] = false;
263 }
264
265 static void
update_inline_shader_state(struct rendering_state * state,enum pipe_shader_type sh,bool pcbuf_dirty,bool constbuf_dirty)266 update_inline_shader_state(struct rendering_state *state, enum pipe_shader_type sh, bool pcbuf_dirty, bool constbuf_dirty)
267 {
268 bool is_compute = sh == PIPE_SHADER_COMPUTE;
269 uint32_t inline_uniforms[MAX_INLINABLE_UNIFORMS];
270 unsigned stage = tgsi_processor_to_shader_stage(sh);
271 state->inlines_dirty[sh] = false;
272 if (!state->pipeline[is_compute]->inlines[stage].can_inline)
273 return;
274 struct lvp_pipeline *pipeline = state->pipeline[is_compute];
275 /* these buffers have already been flushed in llvmpipe, so they're safe to read */
276 nir_shader *nir = nir_shader_clone(pipeline->pipeline_nir[stage], pipeline->pipeline_nir[stage]);
277 nir_function_impl *impl = nir_shader_get_entrypoint(nir);
278 unsigned ssa_alloc = impl->ssa_alloc;
279 unsigned count = pipeline->inlines[stage].count[0];
280 if (count && pcbuf_dirty) {
281 unsigned push_size = get_pcbuf_size(state, sh);
282 for (unsigned i = 0; i < count; i++) {
283 unsigned offset = pipeline->inlines[stage].uniform_offsets[0][i];
284 if (offset < push_size) {
285 memcpy(&inline_uniforms[i], &state->push_constants[offset], sizeof(uint32_t));
286 } else {
287 for (unsigned i = 0; i < state->uniform_blocks[sh].count; i++) {
288 if (offset < push_size + state->uniform_blocks[sh].size[i]) {
289 unsigned ubo_offset = offset - push_size;
290 uint8_t *block = state->uniform_blocks[sh].block[i];
291 memcpy(&inline_uniforms[i], &block[ubo_offset], sizeof(uint32_t));
292 break;
293 }
294 push_size += state->uniform_blocks[sh].size[i];
295 }
296 }
297 }
298 NIR_PASS_V(nir, lvp_inline_uniforms, pipeline, inline_uniforms, 0);
299 }
300 if (constbuf_dirty) {
301 struct pipe_box box = {0};
302 u_foreach_bit(slot, pipeline->inlines[stage].can_inline) {
303 unsigned count = pipeline->inlines[stage].count[slot];
304 struct pipe_constant_buffer *cbuf = &state->const_buffer[sh][slot - 1];
305 struct pipe_resource *pres = cbuf->buffer;
306 box.x = cbuf->buffer_offset;
307 box.width = cbuf->buffer_size - cbuf->buffer_offset;
308 struct pipe_transfer *xfer;
309 uint8_t *map = state->pctx->buffer_map(state->pctx, pres, 0, PIPE_MAP_READ, &box, &xfer);
310 for (unsigned i = 0; i < count; i++) {
311 unsigned offset = pipeline->inlines[stage].uniform_offsets[slot][i];
312 memcpy(&inline_uniforms[i], map + offset, sizeof(uint32_t));
313 }
314 state->pctx->buffer_unmap(state->pctx, xfer);
315 NIR_PASS_V(nir, lvp_inline_uniforms, pipeline, inline_uniforms, slot);
316 }
317 }
318 lvp_shader_optimize(nir);
319 impl = nir_shader_get_entrypoint(nir);
320 void *shader_state;
321 if (ssa_alloc - impl->ssa_alloc < ssa_alloc / 2 &&
322 !pipeline->inlines[stage].must_inline) {
323 /* not enough change; don't inline further */
324 pipeline->inlines[stage].can_inline = 0;
325 ralloc_free(nir);
326 pipeline->shader_cso[sh] = lvp_pipeline_compile(pipeline, nir_shader_clone(NULL, pipeline->pipeline_nir[stage]));
327 shader_state = pipeline->shader_cso[sh];
328 } else {
329 shader_state = lvp_pipeline_compile(pipeline, nir);
330 }
331 switch (sh) {
332 case PIPE_SHADER_VERTEX:
333 state->pctx->bind_vs_state(state->pctx, shader_state);
334 break;
335 case PIPE_SHADER_TESS_CTRL:
336 state->pctx->bind_tcs_state(state->pctx, shader_state);
337 break;
338 case PIPE_SHADER_TESS_EVAL:
339 state->pctx->bind_tes_state(state->pctx, shader_state);
340 break;
341 case PIPE_SHADER_GEOMETRY:
342 state->pctx->bind_gs_state(state->pctx, shader_state);
343 break;
344 case PIPE_SHADER_FRAGMENT:
345 state->pctx->bind_fs_state(state->pctx, shader_state);
346 break;
347 case PIPE_SHADER_COMPUTE:
348 state->pctx->bind_compute_state(state->pctx, shader_state);
349 break;
350 default: break;
351 }
352 }
353
emit_compute_state(struct rendering_state * state)354 static void emit_compute_state(struct rendering_state *state)
355 {
356 if (state->iv_dirty[PIPE_SHADER_COMPUTE]) {
357 state->pctx->set_shader_images(state->pctx, PIPE_SHADER_COMPUTE,
358 0, state->num_shader_images[PIPE_SHADER_COMPUTE],
359 0, state->iv[PIPE_SHADER_COMPUTE]);
360 state->iv_dirty[PIPE_SHADER_COMPUTE] = false;
361 }
362
363 bool pcbuf_dirty = state->pcbuf_dirty[PIPE_SHADER_COMPUTE];
364 if (state->pcbuf_dirty[PIPE_SHADER_COMPUTE])
365 update_pcbuf(state, PIPE_SHADER_COMPUTE);
366
367 bool constbuf_dirty = state->constbuf_dirty[PIPE_SHADER_COMPUTE];
368 if (state->constbuf_dirty[PIPE_SHADER_COMPUTE]) {
369 for (unsigned i = 0; i < state->num_const_bufs[PIPE_SHADER_COMPUTE]; i++)
370 state->pctx->set_constant_buffer(state->pctx, PIPE_SHADER_COMPUTE,
371 i + 1, false, &state->const_buffer[PIPE_SHADER_COMPUTE][i]);
372 state->constbuf_dirty[PIPE_SHADER_COMPUTE] = false;
373 }
374
375 if (state->inlines_dirty[PIPE_SHADER_COMPUTE])
376 update_inline_shader_state(state, PIPE_SHADER_COMPUTE, pcbuf_dirty, constbuf_dirty);
377
378 if (state->sb_dirty[PIPE_SHADER_COMPUTE]) {
379 state->pctx->set_shader_buffers(state->pctx, PIPE_SHADER_COMPUTE,
380 0, state->num_shader_buffers[PIPE_SHADER_COMPUTE],
381 state->sb[PIPE_SHADER_COMPUTE], state->access[MESA_SHADER_COMPUTE].buffers_written);
382 state->sb_dirty[PIPE_SHADER_COMPUTE] = false;
383 }
384
385 if (state->sv_dirty[PIPE_SHADER_COMPUTE]) {
386 state->pctx->set_sampler_views(state->pctx, PIPE_SHADER_COMPUTE, 0, state->num_sampler_views[PIPE_SHADER_COMPUTE],
387 0, false, state->sv[PIPE_SHADER_COMPUTE]);
388 state->sv_dirty[PIPE_SHADER_COMPUTE] = false;
389 }
390
391 if (state->ss_dirty[PIPE_SHADER_COMPUTE]) {
392 for (unsigned i = 0; i < state->num_sampler_states[PIPE_SHADER_COMPUTE]; i++) {
393 if (state->ss_cso[PIPE_SHADER_COMPUTE][i])
394 state->pctx->delete_sampler_state(state->pctx, state->ss_cso[PIPE_SHADER_COMPUTE][i]);
395 state->ss_cso[PIPE_SHADER_COMPUTE][i] = state->pctx->create_sampler_state(state->pctx, &state->ss[PIPE_SHADER_COMPUTE][i]);
396 }
397 state->pctx->bind_sampler_states(state->pctx, PIPE_SHADER_COMPUTE, 0, state->num_sampler_states[PIPE_SHADER_COMPUTE], state->ss_cso[PIPE_SHADER_COMPUTE]);
398 state->ss_dirty[PIPE_SHADER_COMPUTE] = false;
399 }
400 }
401
emit_state(struct rendering_state * state)402 static void emit_state(struct rendering_state *state)
403 {
404 int sh;
405 if (state->blend_dirty) {
406 uint32_t mask = 0;
407 /* zero out the colormask values for disabled attachments */
408 if (state->color_write_disables) {
409 u_foreach_bit(att, state->color_write_disables) {
410 mask |= state->blend_state.rt[att].colormask << (att * 4);
411 state->blend_state.rt[att].colormask = 0;
412 }
413 }
414 cso_set_blend(state->cso, &state->blend_state);
415 /* reset colormasks using saved bitmask */
416 if (state->color_write_disables) {
417 const uint32_t att_mask = BITFIELD_MASK(4);
418 u_foreach_bit(att, state->color_write_disables) {
419 state->blend_state.rt[att].colormask = (mask >> (att * 4)) & att_mask;
420 }
421 }
422 state->blend_dirty = false;
423 }
424
425 if (state->rs_dirty) {
426 bool ms = state->rs_state.multisample;
427 if (state->disable_multisample &&
428 (state->gs_output_lines == GS_OUTPUT_LINES ||
429 (state->gs_output_lines == GS_OUTPUT_NONE && u_reduced_prim(state->info.mode) == PIPE_PRIM_LINES)))
430 state->rs_state.multisample = false;
431 assert(offsetof(struct pipe_rasterizer_state, offset_clamp) - offsetof(struct pipe_rasterizer_state, offset_units) == sizeof(float) * 2);
432 if (state->depth_bias.enabled) {
433 memcpy(&state->rs_state.offset_units, &state->depth_bias, sizeof(float) * 3);
434 state->rs_state.offset_tri = true;
435 state->rs_state.offset_line = true;
436 state->rs_state.offset_point = true;
437 } else {
438 memset(&state->rs_state.offset_units, 0, sizeof(float) * 3);
439 state->rs_state.offset_tri = false;
440 state->rs_state.offset_line = false;
441 state->rs_state.offset_point = false;
442 }
443 cso_set_rasterizer(state->cso, &state->rs_state);
444 state->rs_dirty = false;
445 state->rs_state.multisample = ms;
446 }
447
448 if (state->dsa_dirty) {
449 cso_set_depth_stencil_alpha(state->cso, &state->dsa_state);
450 state->dsa_dirty = false;
451 }
452
453 if (state->sample_mask_dirty) {
454 cso_set_sample_mask(state->cso, state->sample_mask);
455 state->sample_mask_dirty = false;
456 }
457
458 if (state->min_samples_dirty) {
459 cso_set_min_samples(state->cso, state->min_samples);
460 state->min_samples_dirty = false;
461 }
462
463 if (state->blend_color_dirty) {
464 state->pctx->set_blend_color(state->pctx, &state->blend_color);
465 state->blend_color_dirty = false;
466 }
467
468 if (state->stencil_ref_dirty) {
469 cso_set_stencil_ref(state->cso, state->stencil_ref);
470 state->stencil_ref_dirty = false;
471 }
472
473 if (state->vb_dirty) {
474 cso_set_vertex_buffers(state->cso, state->start_vb, state->num_vb, 0, false, state->vb);
475 state->vb_dirty = false;
476 }
477
478 if (state->ve_dirty) {
479 cso_set_vertex_elements(state->cso, &state->velem);
480 state->ve_dirty = false;
481 }
482
483 bool constbuf_dirty[PIPE_SHADER_TYPES] = {false};
484 bool pcbuf_dirty[PIPE_SHADER_TYPES] = {false};
485 for (sh = 0; sh < PIPE_SHADER_COMPUTE; sh++) {
486 constbuf_dirty[sh] = state->constbuf_dirty[sh];
487 if (state->constbuf_dirty[sh]) {
488 for (unsigned idx = 0; idx < state->num_const_bufs[sh]; idx++)
489 state->pctx->set_constant_buffer(state->pctx, sh,
490 idx + 1, false, &state->const_buffer[sh][idx]);
491 }
492 state->constbuf_dirty[sh] = false;
493 }
494
495 for (sh = 0; sh < PIPE_SHADER_COMPUTE; sh++) {
496 pcbuf_dirty[sh] = state->pcbuf_dirty[sh];
497 if (state->pcbuf_dirty[sh])
498 update_pcbuf(state, sh);
499 }
500
501 for (sh = 0; sh < PIPE_SHADER_COMPUTE; sh++) {
502 if (state->inlines_dirty[sh])
503 update_inline_shader_state(state, sh, pcbuf_dirty[sh], constbuf_dirty[sh]);
504 }
505
506 for (sh = 0; sh < PIPE_SHADER_COMPUTE; sh++) {
507 if (state->sb_dirty[sh]) {
508 state->pctx->set_shader_buffers(state->pctx, sh,
509 0, state->num_shader_buffers[sh],
510 state->sb[sh], state->access[tgsi_processor_to_shader_stage(sh)].buffers_written);
511 }
512 }
513
514 for (sh = 0; sh < PIPE_SHADER_COMPUTE; sh++) {
515 if (state->iv_dirty[sh]) {
516 state->pctx->set_shader_images(state->pctx, sh,
517 0, state->num_shader_images[sh], 0,
518 state->iv[sh]);
519 }
520 }
521
522 for (sh = 0; sh < PIPE_SHADER_COMPUTE; sh++) {
523
524 if (!state->sv_dirty[sh])
525 continue;
526
527 state->pctx->set_sampler_views(state->pctx, sh, 0, state->num_sampler_views[sh],
528 0, false, state->sv[sh]);
529 state->sv_dirty[sh] = false;
530 }
531
532 for (sh = 0; sh < PIPE_SHADER_COMPUTE; sh++) {
533 if (!state->ss_dirty[sh])
534 continue;
535
536 cso_set_samplers(state->cso, sh, state->num_sampler_states[sh], state->cso_ss_ptr[sh]);
537 }
538
539 if (state->vp_dirty) {
540 state->pctx->set_viewport_states(state->pctx, 0, state->num_viewports, state->viewports);
541 state->vp_dirty = false;
542 }
543
544 if (state->scissor_dirty) {
545 state->pctx->set_scissor_states(state->pctx, 0, state->num_scissors, state->scissors);
546 state->scissor_dirty = false;
547 }
548 }
549
handle_compute_pipeline(struct vk_cmd_queue_entry * cmd,struct rendering_state * state)550 static void handle_compute_pipeline(struct vk_cmd_queue_entry *cmd,
551 struct rendering_state *state)
552 {
553 LVP_FROM_HANDLE(lvp_pipeline, pipeline, cmd->u.bind_pipeline.pipeline);
554
555 if ((pipeline->layout->push_constant_stages & VK_SHADER_STAGE_COMPUTE_BIT) > 0)
556 state->has_pcbuf[PIPE_SHADER_COMPUTE] = pipeline->layout->push_constant_size > 0;
557 state->uniform_blocks[PIPE_SHADER_COMPUTE].count = pipeline->layout->stage[MESA_SHADER_COMPUTE].uniform_block_count;
558 for (unsigned j = 0; j < pipeline->layout->stage[MESA_SHADER_COMPUTE].uniform_block_count; j++)
559 state->uniform_blocks[PIPE_SHADER_COMPUTE].size[j] = pipeline->layout->stage[MESA_SHADER_COMPUTE].uniform_block_sizes[j];
560 if (!state->has_pcbuf[PIPE_SHADER_COMPUTE] && !pipeline->layout->stage[MESA_SHADER_COMPUTE].uniform_block_count)
561 state->pcbuf_dirty[PIPE_SHADER_COMPUTE] = false;
562
563 state->iv_dirty[MESA_SHADER_COMPUTE] |= state->num_shader_images[MESA_SHADER_COMPUTE] &&
564 (state->access[MESA_SHADER_COMPUTE].images_read != pipeline->access[MESA_SHADER_COMPUTE].images_read ||
565 state->access[MESA_SHADER_COMPUTE].images_written != pipeline->access[MESA_SHADER_COMPUTE].images_written);
566 state->sb_dirty[MESA_SHADER_COMPUTE] |= state->num_shader_buffers[MESA_SHADER_COMPUTE] &&
567 state->access[MESA_SHADER_COMPUTE].buffers_written != pipeline->access[MESA_SHADER_COMPUTE].buffers_written;
568 memcpy(&state->access[MESA_SHADER_COMPUTE], &pipeline->access[MESA_SHADER_COMPUTE], sizeof(struct lvp_access_info));
569
570 state->dispatch_info.block[0] = pipeline->pipeline_nir[MESA_SHADER_COMPUTE]->info.workgroup_size[0];
571 state->dispatch_info.block[1] = pipeline->pipeline_nir[MESA_SHADER_COMPUTE]->info.workgroup_size[1];
572 state->dispatch_info.block[2] = pipeline->pipeline_nir[MESA_SHADER_COMPUTE]->info.workgroup_size[2];
573 state->inlines_dirty[PIPE_SHADER_COMPUTE] = pipeline->inlines[MESA_SHADER_COMPUTE].can_inline;
574 if (!pipeline->inlines[MESA_SHADER_COMPUTE].can_inline)
575 state->pctx->bind_compute_state(state->pctx, pipeline->shader_cso[PIPE_SHADER_COMPUTE]);
576 }
577
578 static void
set_viewport_depth_xform(struct rendering_state * state,unsigned idx)579 set_viewport_depth_xform(struct rendering_state *state, unsigned idx)
580 {
581 double n = state->depth[idx].min;
582 double f = state->depth[idx].max;
583
584 if (!state->rs_state.clip_halfz) {
585 state->viewports[idx].scale[2] = 0.5 * (f - n);
586 state->viewports[idx].translate[2] = 0.5 * (n + f);
587 } else {
588 state->viewports[idx].scale[2] = (f - n);
589 state->viewports[idx].translate[2] = n;
590 }
591 }
592
593 static void
get_viewport_xform(struct rendering_state * state,const VkViewport * viewport,unsigned idx)594 get_viewport_xform(struct rendering_state *state,
595 const VkViewport *viewport,
596 unsigned idx)
597 {
598 float x = viewport->x;
599 float y = viewport->y;
600 float half_width = 0.5f * viewport->width;
601 float half_height = 0.5f * viewport->height;
602
603 state->viewports[idx].scale[0] = half_width;
604 state->viewports[idx].translate[0] = half_width + x;
605 state->viewports[idx].scale[1] = half_height;
606 state->viewports[idx].translate[1] = half_height + y;
607
608 memcpy(&state->depth[idx].min, &viewport->minDepth, sizeof(float) * 2);
609 }
610
handle_graphics_pipeline(struct vk_cmd_queue_entry * cmd,struct rendering_state * state)611 static void handle_graphics_pipeline(struct vk_cmd_queue_entry *cmd,
612 struct rendering_state *state)
613 {
614 LVP_FROM_HANDLE(lvp_pipeline, pipeline, cmd->u.bind_pipeline.pipeline);
615 const struct vk_graphics_pipeline_state *ps = &pipeline->graphics_state;
616 unsigned fb_samples = 0;
617
618 for (enum pipe_shader_type sh = PIPE_SHADER_VERTEX; sh < PIPE_SHADER_COMPUTE; sh++) {
619 state->iv_dirty[sh] |= state->num_shader_images[sh] &&
620 (state->access[sh].images_read != pipeline->access[sh].images_read ||
621 state->access[sh].images_written != pipeline->access[sh].images_written);
622 state->sb_dirty[sh] |= state->num_shader_buffers[sh] && state->access[sh].buffers_written != pipeline->access[sh].buffers_written;
623 }
624 memcpy(state->access, pipeline->access, sizeof(struct lvp_access_info) * 5); //4 vertex stages + fragment
625
626 for (enum pipe_shader_type sh = PIPE_SHADER_VERTEX; sh < PIPE_SHADER_COMPUTE; sh++)
627 state->has_pcbuf[sh] = false;
628
629 for (unsigned i = 0; i < MESA_SHADER_COMPUTE; i++) {
630 enum pipe_shader_type sh = pipe_shader_type_from_mesa(i);
631 state->uniform_blocks[sh].count = pipeline->layout->stage[i].uniform_block_count;
632 for (unsigned j = 0; j < pipeline->layout->stage[i].uniform_block_count; j++)
633 state->uniform_blocks[sh].size[j] = pipeline->layout->stage[i].uniform_block_sizes[j];
634 }
635 u_foreach_bit(stage, pipeline->layout->push_constant_stages) {
636 enum pipe_shader_type sh = pipe_shader_type_from_mesa(stage);
637 state->has_pcbuf[sh] = pipeline->layout->push_constant_size > 0;
638 if (!state->has_pcbuf[sh] && !state->uniform_blocks[sh].count)
639 state->pcbuf_dirty[sh] = false;
640 }
641
642 bool has_stage[PIPE_SHADER_TYPES] = { false };
643
644 state->pctx->bind_gs_state(state->pctx, NULL);
645 if (state->pctx->bind_tcs_state)
646 state->pctx->bind_tcs_state(state->pctx, NULL);
647 if (state->pctx->bind_tes_state)
648 state->pctx->bind_tes_state(state->pctx, NULL);
649 state->gs_output_lines = GS_OUTPUT_NONE;
650 {
651 u_foreach_bit(b, pipeline->graphics_state.shader_stages) {
652 VkShaderStageFlagBits vk_stage = (1 << b);
653 switch (vk_stage) {
654 case VK_SHADER_STAGE_FRAGMENT_BIT:
655 state->inlines_dirty[PIPE_SHADER_FRAGMENT] = pipeline->inlines[MESA_SHADER_FRAGMENT].can_inline;
656 if (!pipeline->inlines[MESA_SHADER_FRAGMENT].can_inline)
657 state->pctx->bind_fs_state(state->pctx, pipeline->shader_cso[PIPE_SHADER_FRAGMENT]);
658 has_stage[PIPE_SHADER_FRAGMENT] = true;
659 break;
660 case VK_SHADER_STAGE_VERTEX_BIT:
661 state->inlines_dirty[PIPE_SHADER_VERTEX] = pipeline->inlines[MESA_SHADER_VERTEX].can_inline;
662 if (!pipeline->inlines[MESA_SHADER_VERTEX].can_inline)
663 state->pctx->bind_vs_state(state->pctx, pipeline->shader_cso[PIPE_SHADER_VERTEX]);
664 has_stage[PIPE_SHADER_VERTEX] = true;
665 break;
666 case VK_SHADER_STAGE_GEOMETRY_BIT:
667 state->inlines_dirty[PIPE_SHADER_GEOMETRY] = pipeline->inlines[MESA_SHADER_GEOMETRY].can_inline;
668 if (!pipeline->inlines[MESA_SHADER_GEOMETRY].can_inline)
669 state->pctx->bind_gs_state(state->pctx, pipeline->shader_cso[PIPE_SHADER_GEOMETRY]);
670 state->gs_output_lines = pipeline->gs_output_lines ? GS_OUTPUT_LINES : GS_OUTPUT_NOT_LINES;
671 has_stage[PIPE_SHADER_GEOMETRY] = true;
672 break;
673 case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT:
674 state->inlines_dirty[PIPE_SHADER_TESS_CTRL] = pipeline->inlines[MESA_SHADER_TESS_CTRL].can_inline;
675 if (!pipeline->inlines[MESA_SHADER_TESS_CTRL].can_inline)
676 state->pctx->bind_tcs_state(state->pctx, pipeline->shader_cso[PIPE_SHADER_TESS_CTRL]);
677 has_stage[PIPE_SHADER_TESS_CTRL] = true;
678 break;
679 case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT:
680 state->inlines_dirty[PIPE_SHADER_TESS_EVAL] = pipeline->inlines[MESA_SHADER_TESS_EVAL].can_inline;
681 if (!pipeline->inlines[MESA_SHADER_TESS_EVAL].can_inline)
682 state->pctx->bind_tes_state(state->pctx, pipeline->shader_cso[PIPE_SHADER_TESS_EVAL]);
683 has_stage[PIPE_SHADER_TESS_EVAL] = true;
684 break;
685 default:
686 assert(0);
687 break;
688 }
689 }
690 }
691
692 /* there should always be a dummy fs. */
693 if (!has_stage[PIPE_SHADER_FRAGMENT])
694 state->pctx->bind_fs_state(state->pctx, pipeline->shader_cso[PIPE_SHADER_FRAGMENT]);
695 if (state->pctx->bind_gs_state && !has_stage[PIPE_SHADER_GEOMETRY])
696 state->pctx->bind_gs_state(state->pctx, NULL);
697 if (state->pctx->bind_tcs_state && !has_stage[PIPE_SHADER_TESS_CTRL])
698 state->pctx->bind_tcs_state(state->pctx, NULL);
699 if (state->pctx->bind_tes_state && !has_stage[PIPE_SHADER_TESS_EVAL])
700 state->pctx->bind_tes_state(state->pctx, NULL);
701
702 /* rasterization state */
703 if (ps->rs) {
704 state->rs_state.depth_clamp = ps->rs->depth_clamp_enable;
705 state->rs_state.depth_clip_near = ps->rs->depth_clip_enable;
706
707 if (!BITSET_TEST(ps->dynamic, MESA_VK_DYNAMIC_RS_RASTERIZER_DISCARD_ENABLE))
708 state->rs_state.rasterizer_discard = ps->rs->rasterizer_discard_enable;
709
710 state->rs_state.line_smooth = pipeline->line_smooth;
711 state->rs_state.line_stipple_enable = ps->rs->line.stipple.enable;
712 state->rs_state.fill_front = vk_polygon_mode_to_pipe(ps->rs->polygon_mode);
713 state->rs_state.fill_back = vk_polygon_mode_to_pipe(ps->rs->polygon_mode);
714 state->rs_state.point_size_per_vertex = true;
715 state->rs_state.flatshade_first =
716 ps->rs->provoking_vertex == VK_PROVOKING_VERTEX_MODE_FIRST_VERTEX_EXT;
717 state->rs_state.point_quad_rasterization = true;
718 state->rs_state.half_pixel_center = true;
719 state->rs_state.scissor = true;
720 state->rs_state.no_ms_sample_mask_out = true;
721 state->rs_state.line_rectangular = pipeline->line_rectangular;
722
723 if (!BITSET_TEST(ps->dynamic, MESA_VK_DYNAMIC_RS_LINE_WIDTH))
724 state->rs_state.line_width = ps->rs->line.width;
725 if (!BITSET_TEST(ps->dynamic, MESA_VK_DYNAMIC_RS_LINE_STIPPLE)) {
726 state->rs_state.line_stipple_factor = ps->rs->line.stipple.factor - 1;
727 state->rs_state.line_stipple_pattern = ps->rs->line.stipple.pattern;
728 }
729
730 if (!BITSET_TEST(ps->dynamic, MESA_VK_DYNAMIC_RS_DEPTH_BIAS_ENABLE))
731 state->depth_bias.enabled = ps->rs->depth_bias.enable;
732 if (!BITSET_TEST(ps->dynamic, MESA_VK_DYNAMIC_RS_DEPTH_BIAS_FACTORS)) {
733 state->depth_bias.offset_units = ps->rs->depth_bias.constant;
734 state->depth_bias.offset_scale = ps->rs->depth_bias.slope;
735 state->depth_bias.offset_clamp = ps->rs->depth_bias.clamp;
736 }
737
738 if (!BITSET_TEST(ps->dynamic, MESA_VK_DYNAMIC_RS_CULL_MODE))
739 state->rs_state.cull_face = vk_cull_to_pipe(ps->rs->cull_mode);
740
741 if (!BITSET_TEST(ps->dynamic, MESA_VK_DYNAMIC_RS_FRONT_FACE))
742 state->rs_state.front_ccw = (ps->rs->front_face == VK_FRONT_FACE_COUNTER_CLOCKWISE);
743 state->rs_dirty = true;
744 }
745
746 if (ps->ds) {
747 if (!BITSET_TEST(ps->dynamic, MESA_VK_DYNAMIC_DS_DEPTH_TEST_ENABLE))
748 state->dsa_state.depth_enabled = ps->ds->depth.test_enable;
749 if (!BITSET_TEST(ps->dynamic, MESA_VK_DYNAMIC_DS_DEPTH_WRITE_ENABLE))
750 state->dsa_state.depth_writemask = ps->ds->depth.write_enable;
751 if (!BITSET_TEST(ps->dynamic, MESA_VK_DYNAMIC_DS_DEPTH_COMPARE_OP))
752 state->dsa_state.depth_func = ps->ds->depth.compare_op;
753 if (!BITSET_TEST(ps->dynamic, MESA_VK_DYNAMIC_DS_DEPTH_BOUNDS_TEST_ENABLE))
754 state->dsa_state.depth_bounds_test = ps->ds->depth.bounds_test.enable;
755
756 if (!BITSET_TEST(ps->dynamic, MESA_VK_DYNAMIC_DS_DEPTH_BOUNDS_TEST_BOUNDS)) {
757 state->dsa_state.depth_bounds_min = ps->ds->depth.bounds_test.min;
758 state->dsa_state.depth_bounds_max = ps->ds->depth.bounds_test.max;
759 }
760
761 if (!BITSET_TEST(ps->dynamic, MESA_VK_DYNAMIC_DS_STENCIL_TEST_ENABLE)) {
762 state->dsa_state.stencil[0].enabled = ps->ds->stencil.test_enable;
763 state->dsa_state.stencil[1].enabled = ps->ds->stencil.test_enable;
764 }
765
766 const struct vk_stencil_test_face_state *front = &ps->ds->stencil.front;
767 const struct vk_stencil_test_face_state *back = &ps->ds->stencil.back;
768
769 if (!BITSET_TEST(ps->dynamic, MESA_VK_DYNAMIC_DS_STENCIL_OP)) {
770 state->dsa_state.stencil[0].func = front->op.compare;
771 state->dsa_state.stencil[0].fail_op = vk_conv_stencil_op(front->op.fail);
772 state->dsa_state.stencil[0].zpass_op = vk_conv_stencil_op(front->op.pass);
773 state->dsa_state.stencil[0].zfail_op = vk_conv_stencil_op(front->op.depth_fail);
774
775 state->dsa_state.stencil[1].func = back->op.compare;
776 state->dsa_state.stencil[1].fail_op = vk_conv_stencil_op(back->op.fail);
777 state->dsa_state.stencil[1].zpass_op = vk_conv_stencil_op(back->op.pass);
778 state->dsa_state.stencil[1].zfail_op = vk_conv_stencil_op(back->op.depth_fail);
779 }
780
781 if (!BITSET_TEST(ps->dynamic, MESA_VK_DYNAMIC_DS_STENCIL_COMPARE_MASK)) {
782 state->dsa_state.stencil[0].valuemask = front->compare_mask;
783 state->dsa_state.stencil[1].valuemask = back->compare_mask;
784 }
785
786 if (!BITSET_TEST(ps->dynamic, MESA_VK_DYNAMIC_DS_STENCIL_WRITE_MASK)) {
787 state->dsa_state.stencil[0].writemask = front->write_mask;
788 state->dsa_state.stencil[1].writemask = back->write_mask;
789 }
790
791 if (!BITSET_TEST(ps->dynamic, MESA_VK_DYNAMIC_DS_STENCIL_REFERENCE)) {
792 state->stencil_ref.ref_value[0] = front->reference;
793 state->stencil_ref.ref_value[1] = back->reference;
794 state->stencil_ref_dirty = true;
795 }
796 state->dsa_dirty = true;
797 }
798
799 if (ps->cb) {
800 state->blend_state.logicop_enable = ps->cb->logic_op_enable;
801 if (ps->cb->logic_op_enable) {
802 if (!BITSET_TEST(ps->dynamic, MESA_VK_DYNAMIC_CB_LOGIC_OP))
803 state->blend_state.logicop_func = vk_conv_logic_op(ps->cb->logic_op);
804 }
805
806 if (!BITSET_TEST(ps->dynamic, MESA_VK_DYNAMIC_CB_COLOR_WRITE_ENABLES))
807 state->color_write_disables = ~ps->cb->color_write_enables;
808
809 state->blend_state.independent_blend_enable = (ps->cb->attachment_count > 1);
810
811 for (unsigned i = 0; i < ps->cb->attachment_count; i++) {
812 const struct vk_color_blend_attachment_state *att = &ps->cb->attachments[i];
813 state->blend_state.rt[i].colormask = att->write_mask;
814 state->blend_state.rt[i].blend_enable = att->blend_enable;
815 if (att->blend_enable) {
816 state->blend_state.rt[i].rgb_func = vk_conv_blend_func(att->color_blend_op);
817 state->blend_state.rt[i].rgb_src_factor = vk_conv_blend_factor(att->src_color_blend_factor);
818 state->blend_state.rt[i].rgb_dst_factor = vk_conv_blend_factor(att->dst_color_blend_factor);
819 state->blend_state.rt[i].alpha_func = vk_conv_blend_func(att->alpha_blend_op);
820 state->blend_state.rt[i].alpha_src_factor = vk_conv_blend_factor(att->src_alpha_blend_factor);
821 state->blend_state.rt[i].alpha_dst_factor = vk_conv_blend_factor(att->dst_alpha_blend_factor);
822 } else {
823 state->blend_state.rt[i].rgb_func = 0;
824 state->blend_state.rt[i].rgb_src_factor = 0;
825 state->blend_state.rt[i].rgb_dst_factor = 0;
826 state->blend_state.rt[i].alpha_func = 0;
827 state->blend_state.rt[i].alpha_src_factor = 0;
828 state->blend_state.rt[i].alpha_dst_factor = 0;
829 }
830
831 /* At least llvmpipe applies the blend factor prior to the blend function,
832 * regardless of what function is used. (like i965 hardware).
833 * It means for MIN/MAX the blend factor has to be stomped to ONE.
834 */
835 if (att->color_blend_op == VK_BLEND_OP_MIN ||
836 att->color_blend_op == VK_BLEND_OP_MAX) {
837 state->blend_state.rt[i].rgb_src_factor = PIPE_BLENDFACTOR_ONE;
838 state->blend_state.rt[i].rgb_dst_factor = PIPE_BLENDFACTOR_ONE;
839 }
840
841 if (att->alpha_blend_op == VK_BLEND_OP_MIN ||
842 att->alpha_blend_op == VK_BLEND_OP_MAX) {
843 state->blend_state.rt[i].alpha_src_factor = PIPE_BLENDFACTOR_ONE;
844 state->blend_state.rt[i].alpha_dst_factor = PIPE_BLENDFACTOR_ONE;
845 }
846 }
847 state->blend_dirty = true;
848 if (!BITSET_TEST(ps->dynamic, MESA_VK_DYNAMIC_CB_BLEND_CONSTANTS)) {
849 memcpy(state->blend_color.color, ps->cb->blend_constants, 4 * sizeof(float));
850 state->blend_color_dirty = true;
851 }
852 } else {
853 memset(&state->blend_state, 0, sizeof(state->blend_state));
854 state->blend_dirty = true;
855 }
856
857 state->disable_multisample = pipeline->disable_multisample;
858 if (ps->ms) {
859 state->rs_state.multisample = ps->ms->rasterization_samples > 1;
860 state->sample_mask = ps->ms->sample_mask;
861 state->blend_state.alpha_to_coverage = ps->ms->alpha_to_coverage_enable;
862 state->blend_state.alpha_to_one = ps->ms->alpha_to_one_enable;
863 state->blend_dirty = true;
864 state->rs_dirty = true;
865 state->min_samples = 1;
866 state->sample_mask_dirty = true;
867 fb_samples = ps->ms->rasterization_samples;
868 if (ps->ms->sample_shading_enable) {
869 state->min_samples = ceil(ps->ms->rasterization_samples *
870 ps->ms->min_sample_shading);
871 if (state->min_samples > 1)
872 state->min_samples = ps->ms->rasterization_samples;
873 if (state->min_samples < 1)
874 state->min_samples = 1;
875 }
876 if (pipeline->force_min_sample)
877 state->min_samples = ps->ms->rasterization_samples;
878 state->min_samples_dirty = true;
879 } else {
880 state->rs_state.multisample = false;
881 state->sample_mask_dirty = state->sample_mask != 0xffffffff;
882 state->sample_mask = 0xffffffff;
883 state->min_samples_dirty = state->min_samples;
884 state->min_samples = 0;
885 state->blend_dirty |= state->blend_state.alpha_to_coverage || state->blend_state.alpha_to_one;
886 state->blend_state.alpha_to_coverage = false;
887 state->blend_state.alpha_to_one = false;
888 state->rs_dirty = true;
889 }
890
891 if (!BITSET_TEST(ps->dynamic, MESA_VK_DYNAMIC_VI_BINDING_STRIDES)) {
892 u_foreach_bit(b, ps->vi->bindings_valid)
893 state->vb[b].stride = ps->vi->bindings[b].stride;
894 state->vb_dirty = true;
895 }
896
897 if (!BITSET_TEST(ps->dynamic, MESA_VK_DYNAMIC_VI)) {
898 u_foreach_bit(a, ps->vi->attributes_valid) {
899 uint32_t b = ps->vi->attributes[a].binding;
900 state->velem.velems[a].src_offset = ps->vi->attributes[a].offset;
901 state->velem.velems[a].vertex_buffer_index = b;
902 state->velem.velems[a].src_format =
903 lvp_vk_format_to_pipe_format(ps->vi->attributes[a].format);
904 state->velem.velems[a].dual_slot = false;
905
906 uint32_t d = ps->vi->bindings[b].divisor;
907 switch (ps->vi->bindings[b].input_rate) {
908 case VK_VERTEX_INPUT_RATE_VERTEX:
909 state->velem.velems[a].instance_divisor = 0;
910 break;
911 case VK_VERTEX_INPUT_RATE_INSTANCE:
912 state->velem.velems[a].instance_divisor = d ? d : UINT32_MAX;
913 break;
914 default:
915 unreachable("Invalid vertex input rate");
916 }
917 }
918
919 state->velem.count = util_last_bit(ps->vi->attributes_valid);
920 state->vb_dirty = true;
921 state->ve_dirty = true;
922 }
923
924 if (!BITSET_TEST(ps->dynamic, MESA_VK_DYNAMIC_IA_PRIMITIVE_TOPOLOGY)) {
925 state->info.mode = vk_conv_topology(ps->ia->primitive_topology);
926 state->rs_dirty = true;
927 }
928 if (!BITSET_TEST(ps->dynamic, MESA_VK_DYNAMIC_IA_PRIMITIVE_RESTART_ENABLE))
929 state->info.primitive_restart = ps->ia->primitive_restart_enable;
930
931 if (ps->ts && !BITSET_TEST(ps->dynamic, MESA_VK_DYNAMIC_TS_PATCH_CONTROL_POINTS))
932 state->patch_vertices = ps->ts->patch_control_points;
933
934 if (ps->vp) {
935 if (!BITSET_TEST(ps->dynamic, MESA_VK_DYNAMIC_VP_VIEWPORT_COUNT)) {
936 state->num_viewports = ps->vp->viewport_count;
937 state->vp_dirty = true;
938 }
939 if (!BITSET_TEST(ps->dynamic, MESA_VK_DYNAMIC_VP_SCISSOR_COUNT)) {
940 state->num_scissors = ps->vp->scissor_count;
941 state->scissor_dirty = true;
942 }
943
944 if (!BITSET_TEST(ps->dynamic, MESA_VK_DYNAMIC_VP_VIEWPORTS)) {
945 for (uint32_t i = 0; i < ps->vp->viewport_count; i++) {
946 get_viewport_xform(state, &ps->vp->viewports[i], i);
947 set_viewport_depth_xform(state, i);
948 }
949 state->vp_dirty = true;
950 }
951 if (!BITSET_TEST(ps->dynamic, MESA_VK_DYNAMIC_VP_SCISSORS)) {
952 for (uint32_t i = 0; i < ps->vp->scissor_count; i++) {
953 const VkRect2D *ss = &ps->vp->scissors[i];
954 state->scissors[i].minx = ss->offset.x;
955 state->scissors[i].miny = ss->offset.y;
956 state->scissors[i].maxx = ss->offset.x + ss->extent.width;
957 state->scissors[i].maxy = ss->offset.y + ss->extent.height;
958 }
959 state->scissor_dirty = true;
960 }
961
962 if (state->rs_state.clip_halfz != !ps->vp->negative_one_to_one) {
963 state->rs_state.clip_halfz = !ps->vp->negative_one_to_one;
964 state->rs_dirty = true;
965 for (uint32_t i = 0; i < state->num_viewports; i++)
966 set_viewport_depth_xform(state, i);
967 state->vp_dirty = true;
968 }
969 }
970
971 if (fb_samples != state->framebuffer.samples) {
972 state->framebuffer.samples = fb_samples;
973 state->pctx->set_framebuffer_state(state->pctx, &state->framebuffer);
974 }
975 }
976
977 static void
handle_pipeline_access(struct rendering_state * state,gl_shader_stage stage)978 handle_pipeline_access(struct rendering_state *state, gl_shader_stage stage)
979 {
980 enum pipe_shader_type pstage = pipe_shader_type_from_mesa(stage);
981 for (unsigned i = 0; i < PIPE_MAX_SHADER_IMAGES; i++) {
982 state->iv[pstage][i].access = 0;
983 state->iv[pstage][i].shader_access = 0;
984 }
985 u_foreach_bit(idx, state->access[stage].images_read) {
986 state->iv[pstage][idx].access |= PIPE_IMAGE_ACCESS_READ;
987 state->iv[pstage][idx].shader_access |= PIPE_IMAGE_ACCESS_READ;
988 }
989 u_foreach_bit(idx, state->access[stage].images_written) {
990 state->iv[pstage][idx].access |= PIPE_IMAGE_ACCESS_WRITE;
991 state->iv[pstage][idx].shader_access |= PIPE_IMAGE_ACCESS_WRITE;
992 }
993 }
994
handle_pipeline(struct vk_cmd_queue_entry * cmd,struct rendering_state * state)995 static void handle_pipeline(struct vk_cmd_queue_entry *cmd,
996 struct rendering_state *state)
997 {
998 LVP_FROM_HANDLE(lvp_pipeline, pipeline, cmd->u.bind_pipeline.pipeline);
999 if (pipeline->is_compute_pipeline) {
1000 handle_compute_pipeline(cmd, state);
1001 handle_pipeline_access(state, MESA_SHADER_COMPUTE);
1002 } else {
1003 handle_graphics_pipeline(cmd, state);
1004 for (unsigned i = 0; i < MESA_SHADER_COMPUTE; i++)
1005 handle_pipeline_access(state, i);
1006 }
1007 state->push_size[pipeline->is_compute_pipeline] = pipeline->layout->push_constant_size;
1008 state->pipeline[pipeline->is_compute_pipeline] = pipeline;
1009 }
1010
handle_vertex_buffers2(struct vk_cmd_queue_entry * cmd,struct rendering_state * state)1011 static void handle_vertex_buffers2(struct vk_cmd_queue_entry *cmd,
1012 struct rendering_state *state)
1013 {
1014 struct vk_cmd_bind_vertex_buffers2 *vcb = &cmd->u.bind_vertex_buffers2;
1015
1016 int i;
1017 for (i = 0; i < vcb->binding_count; i++) {
1018 int idx = i + vcb->first_binding;
1019
1020 state->vb[idx].buffer_offset = vcb->offsets[i];
1021 state->vb[idx].buffer.resource =
1022 vcb->buffers[i] ? lvp_buffer_from_handle(vcb->buffers[i])->bo : NULL;
1023
1024 if (vcb->strides)
1025 state->vb[idx].stride = vcb->strides[i];
1026 }
1027 if (vcb->first_binding < state->start_vb)
1028 state->start_vb = vcb->first_binding;
1029 if (vcb->first_binding + vcb->binding_count >= state->num_vb)
1030 state->num_vb = vcb->first_binding + vcb->binding_count;
1031 state->vb_dirty = true;
1032 }
1033
1034 struct dyn_info {
1035 struct {
1036 uint16_t const_buffer_count;
1037 uint16_t shader_buffer_count;
1038 uint16_t sampler_count;
1039 uint16_t sampler_view_count;
1040 uint16_t image_count;
1041 uint16_t uniform_block_count;
1042 } stage[MESA_SHADER_STAGES];
1043
1044 uint32_t dyn_index;
1045 const uint32_t *dynamic_offsets;
1046 uint32_t dynamic_offset_count;
1047 };
1048
fill_sampler(struct pipe_sampler_state * ss,struct lvp_sampler * samp)1049 static void fill_sampler(struct pipe_sampler_state *ss,
1050 struct lvp_sampler *samp)
1051 {
1052 ss->wrap_s = vk_conv_wrap_mode(samp->create_info.addressModeU);
1053 ss->wrap_t = vk_conv_wrap_mode(samp->create_info.addressModeV);
1054 ss->wrap_r = vk_conv_wrap_mode(samp->create_info.addressModeW);
1055 ss->min_img_filter = samp->create_info.minFilter == VK_FILTER_LINEAR ? PIPE_TEX_FILTER_LINEAR : PIPE_TEX_FILTER_NEAREST;
1056 ss->min_mip_filter = samp->create_info.mipmapMode == VK_SAMPLER_MIPMAP_MODE_LINEAR ? PIPE_TEX_MIPFILTER_LINEAR : PIPE_TEX_MIPFILTER_NEAREST;
1057 ss->mag_img_filter = samp->create_info.magFilter == VK_FILTER_LINEAR ? PIPE_TEX_FILTER_LINEAR : PIPE_TEX_FILTER_NEAREST;
1058 ss->min_lod = samp->create_info.minLod;
1059 ss->max_lod = samp->create_info.maxLod;
1060 ss->lod_bias = samp->create_info.mipLodBias;
1061 if (samp->create_info.anisotropyEnable)
1062 ss->max_anisotropy = samp->create_info.maxAnisotropy;
1063 else
1064 ss->max_anisotropy = 1;
1065 ss->normalized_coords = !samp->create_info.unnormalizedCoordinates;
1066 ss->compare_mode = samp->create_info.compareEnable ? PIPE_TEX_COMPARE_R_TO_TEXTURE : PIPE_TEX_COMPARE_NONE;
1067 ss->compare_func = samp->create_info.compareOp;
1068 ss->seamless_cube_map = !(samp->create_info.flags & VK_SAMPLER_CREATE_NON_SEAMLESS_CUBE_MAP_BIT_EXT);
1069 ss->reduction_mode = samp->reduction_mode;
1070 memcpy(&ss->border_color, &samp->border_color,
1071 sizeof(union pipe_color_union));
1072 }
1073
fill_sampler_stage(struct rendering_state * state,struct dyn_info * dyn_info,gl_shader_stage stage,enum pipe_shader_type p_stage,int array_idx,const union lvp_descriptor_info * descriptor,const struct lvp_descriptor_set_binding_layout * binding)1074 static void fill_sampler_stage(struct rendering_state *state,
1075 struct dyn_info *dyn_info,
1076 gl_shader_stage stage,
1077 enum pipe_shader_type p_stage,
1078 int array_idx,
1079 const union lvp_descriptor_info *descriptor,
1080 const struct lvp_descriptor_set_binding_layout *binding)
1081 {
1082 int ss_idx = binding->stage[stage].sampler_index;
1083 if (ss_idx == -1)
1084 return;
1085 ss_idx += array_idx;
1086 ss_idx += dyn_info->stage[stage].sampler_count;
1087 fill_sampler(&state->ss[p_stage][ss_idx], binding->immutable_samplers ? binding->immutable_samplers[array_idx] : descriptor->sampler);
1088 if (state->num_sampler_states[p_stage] <= ss_idx)
1089 state->num_sampler_states[p_stage] = ss_idx + 1;
1090 state->ss_dirty[p_stage] = true;
1091 }
1092
1093 #define fix_depth_swizzle(x) do { \
1094 if (x > PIPE_SWIZZLE_X && x < PIPE_SWIZZLE_0) \
1095 x = PIPE_SWIZZLE_0; \
1096 } while (0)
1097 #define fix_depth_swizzle_a(x) do { \
1098 if (x > PIPE_SWIZZLE_X && x < PIPE_SWIZZLE_0) \
1099 x = PIPE_SWIZZLE_1; \
1100 } while (0)
1101
fill_sampler_view_stage(struct rendering_state * state,struct dyn_info * dyn_info,gl_shader_stage stage,enum pipe_shader_type p_stage,int array_idx,const union lvp_descriptor_info * descriptor,const struct lvp_descriptor_set_binding_layout * binding)1102 static void fill_sampler_view_stage(struct rendering_state *state,
1103 struct dyn_info *dyn_info,
1104 gl_shader_stage stage,
1105 enum pipe_shader_type p_stage,
1106 int array_idx,
1107 const union lvp_descriptor_info *descriptor,
1108 const struct lvp_descriptor_set_binding_layout *binding)
1109 {
1110 int sv_idx = binding->stage[stage].sampler_view_index;
1111 if (sv_idx == -1)
1112 return;
1113 sv_idx += array_idx;
1114 sv_idx += dyn_info->stage[stage].sampler_view_count;
1115 struct lvp_image_view *iv = descriptor->iview;
1116
1117 if (iv) {
1118 struct pipe_sampler_view templ;
1119 enum pipe_format pformat;
1120 if (iv->vk.aspects == VK_IMAGE_ASPECT_DEPTH_BIT)
1121 pformat = lvp_vk_format_to_pipe_format(iv->vk.format);
1122 else if (iv->vk.aspects == VK_IMAGE_ASPECT_STENCIL_BIT)
1123 pformat = util_format_stencil_only(lvp_vk_format_to_pipe_format(iv->vk.format));
1124 else
1125 pformat = lvp_vk_format_to_pipe_format(iv->vk.format);
1126 u_sampler_view_default_template(&templ,
1127 iv->image->bo,
1128 pformat);
1129 if (iv->vk.view_type == VK_IMAGE_VIEW_TYPE_1D)
1130 templ.target = PIPE_TEXTURE_1D;
1131 if (iv->vk.view_type == VK_IMAGE_VIEW_TYPE_2D)
1132 templ.target = PIPE_TEXTURE_2D;
1133 if (iv->vk.view_type == VK_IMAGE_VIEW_TYPE_CUBE)
1134 templ.target = PIPE_TEXTURE_CUBE;
1135 if (iv->vk.view_type == VK_IMAGE_VIEW_TYPE_CUBE_ARRAY)
1136 templ.target = PIPE_TEXTURE_CUBE_ARRAY;
1137 templ.u.tex.first_layer = iv->vk.base_array_layer;
1138 templ.u.tex.last_layer = iv->vk.base_array_layer + iv->vk.layer_count - 1;
1139 templ.u.tex.first_level = iv->vk.base_mip_level;
1140 templ.u.tex.last_level = iv->vk.base_mip_level + iv->vk.level_count - 1;
1141 templ.swizzle_r = vk_conv_swizzle(iv->vk.swizzle.r);
1142 templ.swizzle_g = vk_conv_swizzle(iv->vk.swizzle.g);
1143 templ.swizzle_b = vk_conv_swizzle(iv->vk.swizzle.b);
1144 templ.swizzle_a = vk_conv_swizzle(iv->vk.swizzle.a);
1145
1146 /* depth stencil swizzles need special handling to pass VK CTS
1147 * but also for zink GL tests.
1148 * piping A swizzle into R fixes GL_ALPHA depth texture mode
1149 * only swizzling from R/0/1 (for alpha) fixes VK CTS tests
1150 * and a bunch of zink tests.
1151 */
1152 if (iv->vk.aspects == VK_IMAGE_ASPECT_DEPTH_BIT ||
1153 iv->vk.aspects == VK_IMAGE_ASPECT_STENCIL_BIT) {
1154 fix_depth_swizzle(templ.swizzle_r);
1155 fix_depth_swizzle(templ.swizzle_g);
1156 fix_depth_swizzle(templ.swizzle_b);
1157 fix_depth_swizzle_a(templ.swizzle_a);
1158 }
1159
1160 assert(sv_idx < ARRAY_SIZE(state->sv[p_stage]));
1161 if (state->sv[p_stage][sv_idx])
1162 pipe_sampler_view_reference(&state->sv[p_stage][sv_idx], NULL);
1163 state->sv[p_stage][sv_idx] = state->pctx->create_sampler_view(state->pctx, iv->image->bo, &templ);
1164 } else {
1165 state->sv[p_stage][sv_idx] = NULL;
1166 }
1167 if (state->num_sampler_views[p_stage] <= sv_idx)
1168 state->num_sampler_views[p_stage] = sv_idx + 1;
1169 state->sv_dirty[p_stage] = true;
1170 }
1171
fill_sampler_buffer_view_stage(struct rendering_state * state,struct dyn_info * dyn_info,gl_shader_stage stage,enum pipe_shader_type p_stage,int array_idx,const union lvp_descriptor_info * descriptor,const struct lvp_descriptor_set_binding_layout * binding)1172 static void fill_sampler_buffer_view_stage(struct rendering_state *state,
1173 struct dyn_info *dyn_info,
1174 gl_shader_stage stage,
1175 enum pipe_shader_type p_stage,
1176 int array_idx,
1177 const union lvp_descriptor_info *descriptor,
1178 const struct lvp_descriptor_set_binding_layout *binding)
1179 {
1180 int sv_idx = binding->stage[stage].sampler_view_index;
1181 if (sv_idx == -1)
1182 return;
1183 sv_idx += array_idx;
1184 sv_idx += dyn_info->stage[stage].sampler_view_count;
1185 struct lvp_buffer_view *bv = descriptor->buffer_view;
1186
1187 assert(sv_idx < ARRAY_SIZE(state->sv[p_stage]));
1188 if (state->sv[p_stage][sv_idx])
1189 pipe_sampler_view_reference(&state->sv[p_stage][sv_idx], NULL);
1190
1191 if (bv) {
1192 struct pipe_sampler_view templ;
1193 memset(&templ, 0, sizeof(templ));
1194 templ.target = PIPE_BUFFER;
1195 templ.swizzle_r = PIPE_SWIZZLE_X;
1196 templ.swizzle_g = PIPE_SWIZZLE_Y;
1197 templ.swizzle_b = PIPE_SWIZZLE_Z;
1198 templ.swizzle_a = PIPE_SWIZZLE_W;
1199 templ.format = bv->pformat;
1200 templ.u.buf.offset = bv->offset + bv->buffer->offset;
1201 templ.u.buf.size = bv->range == VK_WHOLE_SIZE ? (bv->buffer->size - bv->offset) : bv->range;
1202 templ.texture = bv->buffer->bo;
1203 templ.context = state->pctx;
1204 state->sv[p_stage][sv_idx] = state->pctx->create_sampler_view(state->pctx, bv->buffer->bo, &templ);
1205 }
1206
1207 if (state->num_sampler_views[p_stage] <= sv_idx)
1208 state->num_sampler_views[p_stage] = sv_idx + 1;
1209 state->sv_dirty[p_stage] = true;
1210 }
1211
fill_image_view_stage(struct rendering_state * state,struct dyn_info * dyn_info,gl_shader_stage stage,enum pipe_shader_type p_stage,int array_idx,const union lvp_descriptor_info * descriptor,const struct lvp_descriptor_set_binding_layout * binding)1212 static void fill_image_view_stage(struct rendering_state *state,
1213 struct dyn_info *dyn_info,
1214 gl_shader_stage stage,
1215 enum pipe_shader_type p_stage,
1216 int array_idx,
1217 const union lvp_descriptor_info *descriptor,
1218 const struct lvp_descriptor_set_binding_layout *binding)
1219 {
1220 struct lvp_image_view *iv = descriptor->iview;
1221 int idx = binding->stage[stage].image_index;
1222 if (idx == -1)
1223 return;
1224 idx += array_idx;
1225 idx += dyn_info->stage[stage].image_count;
1226 if (iv) {
1227 state->iv[p_stage][idx].resource = iv->image->bo;
1228 if (iv->vk.aspects == VK_IMAGE_ASPECT_DEPTH_BIT)
1229 state->iv[p_stage][idx].format = lvp_vk_format_to_pipe_format(iv->vk.format);
1230 else if (iv->vk.aspects == VK_IMAGE_ASPECT_STENCIL_BIT)
1231 state->iv[p_stage][idx].format = util_format_stencil_only(lvp_vk_format_to_pipe_format(iv->vk.format));
1232 else
1233 state->iv[p_stage][idx].format = lvp_vk_format_to_pipe_format(iv->vk.format);
1234
1235 if (iv->vk.view_type == VK_IMAGE_VIEW_TYPE_3D) {
1236 state->iv[p_stage][idx].u.tex.first_layer = 0;
1237 state->iv[p_stage][idx].u.tex.last_layer = iv->vk.extent.depth - 1;
1238 } else {
1239 state->iv[p_stage][idx].u.tex.first_layer = iv->vk.base_array_layer,
1240 state->iv[p_stage][idx].u.tex.last_layer = iv->vk.base_array_layer + iv->vk.layer_count - 1;
1241 }
1242 state->iv[p_stage][idx].u.tex.level = iv->vk.base_mip_level;
1243 } else {
1244 state->iv[p_stage][idx].resource = NULL;
1245 state->iv[p_stage][idx].format = PIPE_FORMAT_NONE;
1246 state->iv[p_stage][idx].u.tex.first_layer = 0;
1247 state->iv[p_stage][idx].u.tex.last_layer = 0;
1248 state->iv[p_stage][idx].u.tex.level = 0;
1249 }
1250
1251 if (state->num_shader_images[p_stage] <= idx)
1252 state->num_shader_images[p_stage] = idx + 1;
1253
1254 state->iv_dirty[p_stage] = true;
1255 }
1256
fill_image_buffer_view_stage(struct rendering_state * state,struct dyn_info * dyn_info,gl_shader_stage stage,enum pipe_shader_type p_stage,int array_idx,const union lvp_descriptor_info * descriptor,const struct lvp_descriptor_set_binding_layout * binding)1257 static void fill_image_buffer_view_stage(struct rendering_state *state,
1258 struct dyn_info *dyn_info,
1259 gl_shader_stage stage,
1260 enum pipe_shader_type p_stage,
1261 int array_idx,
1262 const union lvp_descriptor_info *descriptor,
1263 const struct lvp_descriptor_set_binding_layout *binding)
1264 {
1265 struct lvp_buffer_view *bv = descriptor->buffer_view;
1266 int idx = binding->stage[stage].image_index;
1267 if (idx == -1)
1268 return;
1269 idx += array_idx;
1270 idx += dyn_info->stage[stage].image_count;
1271 if (bv) {
1272 state->iv[p_stage][idx].resource = bv->buffer->bo;
1273 state->iv[p_stage][idx].format = bv->pformat;
1274 state->iv[p_stage][idx].u.buf.offset = bv->offset + bv->buffer->offset;
1275 state->iv[p_stage][idx].u.buf.size = bv->range == VK_WHOLE_SIZE ? (bv->buffer->size - bv->offset): bv->range;
1276 } else {
1277 state->iv[p_stage][idx].resource = NULL;
1278 state->iv[p_stage][idx].format = PIPE_FORMAT_NONE;
1279 state->iv[p_stage][idx].u.buf.offset = 0;
1280 state->iv[p_stage][idx].u.buf.size = 0;
1281 }
1282 if (state->num_shader_images[p_stage] <= idx)
1283 state->num_shader_images[p_stage] = idx + 1;
1284 state->iv_dirty[p_stage] = true;
1285 }
1286
handle_descriptor(struct rendering_state * state,struct dyn_info * dyn_info,const struct lvp_descriptor_set_binding_layout * binding,gl_shader_stage stage,enum pipe_shader_type p_stage,int array_idx,VkDescriptorType type,const union lvp_descriptor_info * descriptor)1287 static void handle_descriptor(struct rendering_state *state,
1288 struct dyn_info *dyn_info,
1289 const struct lvp_descriptor_set_binding_layout *binding,
1290 gl_shader_stage stage,
1291 enum pipe_shader_type p_stage,
1292 int array_idx,
1293 VkDescriptorType type,
1294 const union lvp_descriptor_info *descriptor)
1295 {
1296 bool is_dynamic = type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
1297 type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC;
1298
1299 switch (type) {
1300 case VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK: {
1301 int idx = binding->stage[stage].uniform_block_index;
1302 if (idx == -1)
1303 return;
1304 idx += dyn_info->stage[stage].uniform_block_count;
1305 assert(descriptor->uniform);
1306 state->uniform_blocks[p_stage].block[idx] = descriptor->uniform;
1307 state->pcbuf_dirty[p_stage] = true;
1308 state->inlines_dirty[p_stage] = true;
1309 break;
1310 }
1311 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT:
1312 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE: {
1313 fill_image_view_stage(state, dyn_info, stage, p_stage, array_idx, descriptor, binding);
1314 break;
1315 }
1316 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER:
1317 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC: {
1318 int idx = binding->stage[stage].const_buffer_index;
1319 if (idx == -1)
1320 return;
1321 idx += array_idx;
1322 idx += dyn_info->stage[stage].const_buffer_count;
1323 if (!descriptor->buffer) {
1324 state->const_buffer[p_stage][idx].buffer = NULL;
1325 state->const_buffer[p_stage][idx].buffer_offset = 0;
1326 state->const_buffer[p_stage][idx].buffer_size = 0;
1327 } else {
1328 state->const_buffer[p_stage][idx].buffer = descriptor->buffer->bo;
1329 state->const_buffer[p_stage][idx].buffer_offset = descriptor->offset + descriptor->buffer->offset;
1330 if (descriptor->range == VK_WHOLE_SIZE)
1331 state->const_buffer[p_stage][idx].buffer_size = descriptor->buffer->bo->width0 - state->const_buffer[p_stage][idx].buffer_offset;
1332 else
1333 state->const_buffer[p_stage][idx].buffer_size = descriptor->range;
1334 }
1335 if (is_dynamic) {
1336 uint32_t offset = dyn_info->dynamic_offsets[dyn_info->dyn_index + binding->dynamic_index + array_idx];
1337 state->const_buffer[p_stage][idx].buffer_offset += offset;
1338 }
1339 if (state->num_const_bufs[p_stage] <= idx)
1340 state->num_const_bufs[p_stage] = idx + 1;
1341 state->constbuf_dirty[p_stage] = true;
1342 state->inlines_dirty[p_stage] = true;
1343 break;
1344 }
1345 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER:
1346 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC: {
1347 int idx = binding->stage[stage].shader_buffer_index;
1348 if (idx == -1)
1349 return;
1350 idx += array_idx;
1351 idx += dyn_info->stage[stage].shader_buffer_count;
1352 if (!descriptor->buffer) {
1353 state->sb[p_stage][idx].buffer = NULL;
1354 state->sb[p_stage][idx].buffer_offset = 0;
1355 state->sb[p_stage][idx].buffer_size = 0;
1356 } else {
1357 state->sb[p_stage][idx].buffer = descriptor->buffer->bo;
1358 state->sb[p_stage][idx].buffer_offset = descriptor->offset + descriptor->buffer->offset;
1359 if (descriptor->range == VK_WHOLE_SIZE)
1360 state->sb[p_stage][idx].buffer_size = descriptor->buffer->bo->width0 - state->sb[p_stage][idx].buffer_offset;
1361 else
1362 state->sb[p_stage][idx].buffer_size = descriptor->range;
1363 }
1364 if (is_dynamic) {
1365 uint32_t offset = dyn_info->dynamic_offsets[dyn_info->dyn_index + binding->dynamic_index + array_idx];
1366 state->sb[p_stage][idx].buffer_offset += offset;
1367 }
1368 if (state->num_shader_buffers[p_stage] <= idx)
1369 state->num_shader_buffers[p_stage] = idx + 1;
1370 state->sb_dirty[p_stage] = true;
1371 break;
1372 }
1373 case VK_DESCRIPTOR_TYPE_SAMPLER:
1374 if (!descriptor->sampler)
1375 return;
1376 fill_sampler_stage(state, dyn_info, stage, p_stage, array_idx, descriptor, binding);
1377 break;
1378 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE:
1379 fill_sampler_view_stage(state, dyn_info, stage, p_stage, array_idx, descriptor, binding);
1380 break;
1381 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER:
1382 fill_sampler_stage(state, dyn_info, stage, p_stage, array_idx, descriptor, binding);
1383 fill_sampler_view_stage(state, dyn_info, stage, p_stage, array_idx, descriptor, binding);
1384 break;
1385 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER:
1386 fill_sampler_buffer_view_stage(state, dyn_info, stage, p_stage, array_idx, descriptor, binding);
1387 break;
1388 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER:
1389 fill_image_buffer_view_stage(state, dyn_info, stage, p_stage, array_idx, descriptor, binding);
1390 break;
1391 default:
1392 fprintf(stderr, "Unhandled descriptor set %d\n", type);
1393 unreachable("oops");
1394 break;
1395 }
1396 }
1397
handle_set_stage(struct rendering_state * state,struct dyn_info * dyn_info,const struct lvp_descriptor_set * set,gl_shader_stage stage,enum pipe_shader_type p_stage)1398 static void handle_set_stage(struct rendering_state *state,
1399 struct dyn_info *dyn_info,
1400 const struct lvp_descriptor_set *set,
1401 gl_shader_stage stage,
1402 enum pipe_shader_type p_stage)
1403 {
1404 int j;
1405 for (j = 0; j < set->layout->binding_count; j++) {
1406 const struct lvp_descriptor_set_binding_layout *binding;
1407 const struct lvp_descriptor *descriptor;
1408 binding = &set->layout->binding[j];
1409
1410 if (binding->valid) {
1411 unsigned array_size = binding->type == VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK ? 1 : binding->array_size;
1412 for (int i = 0; i < array_size; i++) {
1413 descriptor = &set->descriptors[binding->descriptor_index + i];
1414 handle_descriptor(state, dyn_info, binding, stage, p_stage, i, descriptor->type, &descriptor->info);
1415 }
1416 }
1417 }
1418 }
1419
increment_dyn_info(struct dyn_info * dyn_info,const struct vk_descriptor_set_layout * vk_layout,bool inc_dyn)1420 static void increment_dyn_info(struct dyn_info *dyn_info,
1421 const struct vk_descriptor_set_layout *vk_layout,
1422 bool inc_dyn)
1423 {
1424 const struct lvp_descriptor_set_layout *layout =
1425 vk_to_lvp_descriptor_set_layout(vk_layout);
1426
1427 for (gl_shader_stage stage = MESA_SHADER_VERTEX; stage < MESA_SHADER_STAGES; stage++) {
1428 dyn_info->stage[stage].const_buffer_count += layout->stage[stage].const_buffer_count;
1429 dyn_info->stage[stage].shader_buffer_count += layout->stage[stage].shader_buffer_count;
1430 dyn_info->stage[stage].sampler_count += layout->stage[stage].sampler_count;
1431 dyn_info->stage[stage].sampler_view_count += layout->stage[stage].sampler_view_count;
1432 dyn_info->stage[stage].image_count += layout->stage[stage].image_count;
1433 dyn_info->stage[stage].uniform_block_count += layout->stage[stage].uniform_block_count;
1434 }
1435 if (inc_dyn)
1436 dyn_info->dyn_index += layout->dynamic_offset_count;
1437 }
1438
handle_compute_descriptor_sets(struct vk_cmd_queue_entry * cmd,struct dyn_info * dyn_info,struct rendering_state * state)1439 static void handle_compute_descriptor_sets(struct vk_cmd_queue_entry *cmd,
1440 struct dyn_info *dyn_info,
1441 struct rendering_state *state)
1442 {
1443 struct vk_cmd_bind_descriptor_sets *bds = &cmd->u.bind_descriptor_sets;
1444 LVP_FROM_HANDLE(lvp_pipeline_layout, layout, bds->layout);
1445 int i;
1446
1447 for (i = 0; i < bds->first_set; i++) {
1448 increment_dyn_info(dyn_info, layout->vk.set_layouts[i], false);
1449 }
1450 for (i = 0; i < bds->descriptor_set_count; i++) {
1451 const struct lvp_descriptor_set *set = lvp_descriptor_set_from_handle(bds->descriptor_sets[i]);
1452
1453 if (set->layout->shader_stages & VK_SHADER_STAGE_COMPUTE_BIT)
1454 handle_set_stage(state, dyn_info, set, MESA_SHADER_COMPUTE, PIPE_SHADER_COMPUTE);
1455 increment_dyn_info(dyn_info, layout->vk.set_layouts[bds->first_set + i], true);
1456 }
1457 }
1458
handle_descriptor_sets(struct vk_cmd_queue_entry * cmd,struct rendering_state * state)1459 static void handle_descriptor_sets(struct vk_cmd_queue_entry *cmd,
1460 struct rendering_state *state)
1461 {
1462 struct vk_cmd_bind_descriptor_sets *bds = &cmd->u.bind_descriptor_sets;
1463 LVP_FROM_HANDLE(lvp_pipeline_layout, layout, bds->layout);
1464 int i;
1465 struct dyn_info dyn_info;
1466
1467 dyn_info.dyn_index = 0;
1468 dyn_info.dynamic_offsets = bds->dynamic_offsets;
1469 dyn_info.dynamic_offset_count = bds->dynamic_offset_count;
1470
1471 memset(dyn_info.stage, 0, sizeof(dyn_info.stage));
1472 if (bds->pipeline_bind_point == VK_PIPELINE_BIND_POINT_COMPUTE) {
1473 handle_compute_descriptor_sets(cmd, &dyn_info, state);
1474 return;
1475 }
1476
1477 for (i = 0; i < bds->first_set; i++) {
1478 increment_dyn_info(&dyn_info, layout->vk.set_layouts[i], false);
1479 }
1480
1481 for (i = 0; i < bds->descriptor_set_count; i++) {
1482 if (!layout->vk.set_layouts[bds->first_set + i])
1483 continue;
1484
1485 const struct lvp_descriptor_set *set = lvp_descriptor_set_from_handle(bds->descriptor_sets[i]);
1486 if (!set)
1487 continue;
1488 /* verify that there's enough total offsets */
1489 assert(set->layout->dynamic_offset_count <= dyn_info.dynamic_offset_count);
1490 /* verify there's either no offsets... */
1491 assert(!dyn_info.dynamic_offset_count ||
1492 /* or that the total number of offsets required is <= the number remaining */
1493 set->layout->dynamic_offset_count <= dyn_info.dynamic_offset_count - dyn_info.dyn_index);
1494
1495 if (set->layout->shader_stages & VK_SHADER_STAGE_VERTEX_BIT)
1496 handle_set_stage(state, &dyn_info, set, MESA_SHADER_VERTEX, PIPE_SHADER_VERTEX);
1497
1498 if (set->layout->shader_stages & VK_SHADER_STAGE_GEOMETRY_BIT)
1499 handle_set_stage(state, &dyn_info, set, MESA_SHADER_GEOMETRY, PIPE_SHADER_GEOMETRY);
1500
1501 if (set->layout->shader_stages & VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT)
1502 handle_set_stage(state, &dyn_info, set, MESA_SHADER_TESS_CTRL, PIPE_SHADER_TESS_CTRL);
1503
1504 if (set->layout->shader_stages & VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT)
1505 handle_set_stage(state, &dyn_info, set, MESA_SHADER_TESS_EVAL, PIPE_SHADER_TESS_EVAL);
1506
1507 if (set->layout->shader_stages & VK_SHADER_STAGE_FRAGMENT_BIT)
1508 handle_set_stage(state, &dyn_info, set, MESA_SHADER_FRAGMENT, PIPE_SHADER_FRAGMENT);
1509
1510 increment_dyn_info(&dyn_info, layout->vk.set_layouts[bds->first_set + i], true);
1511 }
1512 }
1513
create_img_surface_bo(struct rendering_state * state,VkImageSubresourceRange * range,struct pipe_resource * bo,enum pipe_format pformat,int width,int height,int base_layer,int layer_count,int level)1514 static struct pipe_surface *create_img_surface_bo(struct rendering_state *state,
1515 VkImageSubresourceRange *range,
1516 struct pipe_resource *bo,
1517 enum pipe_format pformat,
1518 int width,
1519 int height,
1520 int base_layer, int layer_count,
1521 int level)
1522 {
1523 struct pipe_surface template;
1524
1525 memset(&template, 0, sizeof(struct pipe_surface));
1526
1527 template.format = pformat;
1528 template.width = width;
1529 template.height = height;
1530 template.u.tex.first_layer = range->baseArrayLayer + base_layer;
1531 template.u.tex.last_layer = range->baseArrayLayer + base_layer + layer_count - 1;
1532 template.u.tex.level = range->baseMipLevel + level;
1533
1534 if (template.format == PIPE_FORMAT_NONE)
1535 return NULL;
1536 return state->pctx->create_surface(state->pctx,
1537 bo, &template);
1538
1539 }
create_img_surface(struct rendering_state * state,struct lvp_image_view * imgv,VkFormat format,int width,int height,int base_layer,int layer_count)1540 static struct pipe_surface *create_img_surface(struct rendering_state *state,
1541 struct lvp_image_view *imgv,
1542 VkFormat format, int width,
1543 int height,
1544 int base_layer, int layer_count)
1545 {
1546 VkImageSubresourceRange imgv_subres =
1547 vk_image_view_subresource_range(&imgv->vk);
1548
1549 return create_img_surface_bo(state, &imgv_subres, imgv->image->bo,
1550 lvp_vk_format_to_pipe_format(format),
1551 width, height, base_layer, layer_count, 0);
1552 }
1553
add_img_view_surface(struct rendering_state * state,struct lvp_image_view * imgv,int width,int height,int layer_count)1554 static void add_img_view_surface(struct rendering_state *state,
1555 struct lvp_image_view *imgv, int width, int height,
1556 int layer_count)
1557 {
1558 if (imgv->surface) {
1559 if (imgv->surface->width != width ||
1560 imgv->surface->height != height ||
1561 (imgv->surface->u.tex.last_layer - imgv->surface->u.tex.first_layer) != (layer_count - 1))
1562 pipe_surface_reference(&imgv->surface, NULL);
1563 }
1564
1565 if (!imgv->surface) {
1566 imgv->surface = create_img_surface(state, imgv, imgv->vk.format,
1567 width, height,
1568 0, layer_count);
1569 }
1570 }
1571
1572 static bool
render_needs_clear(struct rendering_state * state)1573 render_needs_clear(struct rendering_state *state)
1574 {
1575 for (uint32_t i = 0; i < state->color_att_count; i++) {
1576 if (state->color_att[i].load_op == VK_ATTACHMENT_LOAD_OP_CLEAR)
1577 return true;
1578 }
1579 if (state->depth_att.load_op == VK_ATTACHMENT_LOAD_OP_CLEAR)
1580 return true;
1581 if (state->stencil_att.load_op == VK_ATTACHMENT_LOAD_OP_CLEAR)
1582 return true;
1583 return false;
1584 }
1585
clear_attachment_layers(struct rendering_state * state,struct lvp_image_view * imgv,const VkRect2D * rect,unsigned base_layer,unsigned layer_count,unsigned ds_clear_flags,double dclear_val,uint32_t sclear_val,union pipe_color_union * col_val)1586 static void clear_attachment_layers(struct rendering_state *state,
1587 struct lvp_image_view *imgv,
1588 const VkRect2D *rect,
1589 unsigned base_layer, unsigned layer_count,
1590 unsigned ds_clear_flags, double dclear_val,
1591 uint32_t sclear_val,
1592 union pipe_color_union *col_val)
1593 {
1594 struct pipe_surface *clear_surf = create_img_surface(state,
1595 imgv,
1596 imgv->vk.format,
1597 state->framebuffer.width,
1598 state->framebuffer.height,
1599 base_layer,
1600 layer_count);
1601
1602 if (ds_clear_flags) {
1603 state->pctx->clear_depth_stencil(state->pctx,
1604 clear_surf,
1605 ds_clear_flags,
1606 dclear_val, sclear_val,
1607 rect->offset.x, rect->offset.y,
1608 rect->extent.width, rect->extent.height,
1609 true);
1610 } else {
1611 state->pctx->clear_render_target(state->pctx, clear_surf,
1612 col_val,
1613 rect->offset.x, rect->offset.y,
1614 rect->extent.width, rect->extent.height,
1615 true);
1616 }
1617 state->pctx->surface_destroy(state->pctx, clear_surf);
1618 }
1619
render_clear(struct rendering_state * state)1620 static void render_clear(struct rendering_state *state)
1621 {
1622 for (uint32_t i = 0; i < state->color_att_count; i++) {
1623 if (state->color_att[i].load_op != VK_ATTACHMENT_LOAD_OP_CLEAR)
1624 continue;
1625
1626 union pipe_color_union color_clear_val = { 0 };
1627 const VkClearValue value = state->color_att[i].clear_value;
1628 color_clear_val.ui[0] = value.color.uint32[0];
1629 color_clear_val.ui[1] = value.color.uint32[1];
1630 color_clear_val.ui[2] = value.color.uint32[2];
1631 color_clear_val.ui[3] = value.color.uint32[3];
1632
1633 struct lvp_image_view *imgv = state->color_att[i].imgv;
1634 assert(imgv->surface);
1635
1636 if (state->info.view_mask) {
1637 u_foreach_bit(i, state->info.view_mask)
1638 clear_attachment_layers(state, imgv, &state->render_area,
1639 i, 1, 0, 0, 0, &color_clear_val);
1640 } else {
1641 state->pctx->clear_render_target(state->pctx,
1642 imgv->surface,
1643 &color_clear_val,
1644 state->render_area.offset.x,
1645 state->render_area.offset.y,
1646 state->render_area.extent.width,
1647 state->render_area.extent.height,
1648 false);
1649 }
1650 }
1651
1652 uint32_t ds_clear_flags = 0;
1653 double dclear_val = 0;
1654 if (state->depth_att.load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1655 ds_clear_flags |= PIPE_CLEAR_DEPTH;
1656 dclear_val = state->depth_att.clear_value.depthStencil.depth;
1657 }
1658
1659 uint32_t sclear_val = 0;
1660 if (state->stencil_att.load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1661 ds_clear_flags |= PIPE_CLEAR_STENCIL;
1662 sclear_val = state->stencil_att.clear_value.depthStencil.stencil;
1663 }
1664
1665 if (ds_clear_flags) {
1666 if (state->info.view_mask) {
1667 u_foreach_bit(i, state->info.view_mask)
1668 clear_attachment_layers(state, state->ds_imgv, &state->render_area,
1669 i, 1, ds_clear_flags, dclear_val, sclear_val, NULL);
1670 } else {
1671 state->pctx->clear_depth_stencil(state->pctx,
1672 state->ds_imgv->surface,
1673 ds_clear_flags,
1674 dclear_val, sclear_val,
1675 state->render_area.offset.x,
1676 state->render_area.offset.y,
1677 state->render_area.extent.width,
1678 state->render_area.extent.height,
1679 false);
1680 }
1681 }
1682 }
1683
render_clear_fast(struct rendering_state * state)1684 static void render_clear_fast(struct rendering_state *state)
1685 {
1686 /*
1687 * the state tracker clear interface only works if all the attachments have the same
1688 * clear color.
1689 */
1690 /* llvmpipe doesn't support scissored clears yet */
1691 if (state->render_area.offset.x || state->render_area.offset.y)
1692 goto slow_clear;
1693
1694 if (state->render_area.extent.width != state->framebuffer.width ||
1695 state->render_area.extent.height != state->framebuffer.height)
1696 goto slow_clear;
1697
1698 if (state->info.view_mask)
1699 goto slow_clear;
1700
1701 uint32_t buffers = 0;
1702 bool has_color_value = false;
1703 VkClearValue color_value = {0};
1704 for (uint32_t i = 0; i < state->color_att_count; i++) {
1705 if (state->color_att[i].load_op != VK_ATTACHMENT_LOAD_OP_CLEAR)
1706 continue;
1707
1708 buffers |= (PIPE_CLEAR_COLOR0 << i);
1709
1710 if (has_color_value) {
1711 if (memcmp(&color_value, &state->color_att[i].clear_value, sizeof(VkClearValue)))
1712 goto slow_clear;
1713 } else {
1714 memcpy(&color_value, &state->color_att[i].clear_value, sizeof(VkClearValue));
1715 has_color_value = true;
1716 }
1717 }
1718
1719 double dclear_val = 0;
1720 if (state->depth_att.load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1721 buffers |= PIPE_CLEAR_DEPTH;
1722 dclear_val = state->depth_att.clear_value.depthStencil.depth;
1723 }
1724
1725 uint32_t sclear_val = 0;
1726 if (state->stencil_att.load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1727 buffers |= PIPE_CLEAR_STENCIL;
1728 sclear_val = state->stencil_att.clear_value.depthStencil.stencil;
1729 }
1730
1731 union pipe_color_union col_val;
1732 for (unsigned i = 0; i < 4; i++)
1733 col_val.ui[i] = color_value.color.uint32[i];
1734
1735 state->pctx->clear(state->pctx, buffers,
1736 NULL, &col_val,
1737 dclear_val, sclear_val);
1738 return;
1739
1740 slow_clear:
1741 render_clear(state);
1742 }
1743
1744 static struct lvp_image_view *
destroy_multisample_surface(struct rendering_state * state,struct lvp_image_view * imgv)1745 destroy_multisample_surface(struct rendering_state *state, struct lvp_image_view *imgv)
1746 {
1747 assert(imgv->image->vk.samples > 1);
1748 struct lvp_image_view *base = imgv->multisample;
1749 base->multisample = NULL;
1750 free((void*)imgv->image);
1751 pipe_surface_reference(&imgv->surface, NULL);
1752 free(imgv);
1753 return base;
1754 }
1755
1756 static void
resolve_ds(struct rendering_state * state,bool multi)1757 resolve_ds(struct rendering_state *state, bool multi)
1758 {
1759 VkResolveModeFlagBits depth_resolve_mode = multi ? state->forced_depth_resolve_mode : state->depth_att.resolve_mode;
1760 VkResolveModeFlagBits stencil_resolve_mode = multi ? state->forced_stencil_resolve_mode : state->stencil_att.resolve_mode;
1761 if (!depth_resolve_mode && !stencil_resolve_mode)
1762 return;
1763
1764 struct lvp_image_view *src_imgv = state->ds_imgv;
1765 if (multi && !src_imgv->multisample)
1766 return;
1767 if (!multi && src_imgv->image->vk.samples == 1)
1768 return;
1769
1770 assert(state->depth_att.resolve_imgv == NULL ||
1771 state->stencil_att.resolve_imgv == NULL ||
1772 state->depth_att.resolve_imgv == state->stencil_att.resolve_imgv ||
1773 multi);
1774 struct lvp_image_view *dst_imgv =
1775 multi ? src_imgv->multisample :
1776 state->depth_att.resolve_imgv ? state->depth_att.resolve_imgv :
1777 state->stencil_att.resolve_imgv;
1778
1779 int num_blits = 1;
1780 if (depth_resolve_mode != stencil_resolve_mode)
1781 num_blits = 2;
1782
1783 for (unsigned i = 0; i < num_blits; i++) {
1784 if (i == 0 && depth_resolve_mode == VK_RESOLVE_MODE_NONE)
1785 continue;
1786
1787 if (i == 1 && stencil_resolve_mode == VK_RESOLVE_MODE_NONE)
1788 continue;
1789
1790 struct pipe_blit_info info;
1791 memset(&info, 0, sizeof(info));
1792
1793 info.src.resource = src_imgv->image->bo;
1794 info.dst.resource = dst_imgv->image->bo;
1795 info.src.format = src_imgv->pformat;
1796 info.dst.format = dst_imgv->pformat;
1797 info.filter = PIPE_TEX_FILTER_NEAREST;
1798
1799 if (num_blits == 1)
1800 info.mask = PIPE_MASK_ZS;
1801 else if (i == 0)
1802 info.mask = PIPE_MASK_Z;
1803 else
1804 info.mask = PIPE_MASK_S;
1805
1806 if (i == 0 && depth_resolve_mode == VK_RESOLVE_MODE_SAMPLE_ZERO_BIT)
1807 info.sample0_only = true;
1808 if (i == 1 && stencil_resolve_mode == VK_RESOLVE_MODE_SAMPLE_ZERO_BIT)
1809 info.sample0_only = true;
1810
1811 info.src.box.x = state->render_area.offset.x;
1812 info.src.box.y = state->render_area.offset.y;
1813 info.src.box.width = state->render_area.extent.width;
1814 info.src.box.height = state->render_area.extent.height;
1815 info.src.box.depth = state->framebuffer.layers;
1816
1817 info.dst.box = info.src.box;
1818
1819 state->pctx->blit(state->pctx, &info);
1820 }
1821 if (multi)
1822 state->ds_imgv = destroy_multisample_surface(state, state->ds_imgv);
1823 }
1824
1825 static void
resolve_color(struct rendering_state * state,bool multi)1826 resolve_color(struct rendering_state *state, bool multi)
1827 {
1828 for (uint32_t i = 0; i < state->color_att_count; i++) {
1829 if (!state->color_att[i].resolve_mode &&
1830 !(multi && state->forced_sample_count && state->color_att[i].imgv))
1831 continue;
1832
1833 struct lvp_image_view *src_imgv = state->color_att[i].imgv;
1834 /* skip non-msrtss resolves during msrtss resolve */
1835 if (multi && !src_imgv->multisample)
1836 continue;
1837 struct lvp_image_view *dst_imgv = multi ? src_imgv->multisample : state->color_att[i].resolve_imgv;
1838
1839 struct pipe_blit_info info;
1840 memset(&info, 0, sizeof(info));
1841
1842 info.src.resource = src_imgv->image->bo;
1843 info.dst.resource = dst_imgv->image->bo;
1844 info.src.format = src_imgv->pformat;
1845 info.dst.format = dst_imgv->pformat;
1846 info.filter = PIPE_TEX_FILTER_NEAREST;
1847 info.mask = PIPE_MASK_RGBA;
1848 info.src.box.x = state->render_area.offset.x;
1849 info.src.box.y = state->render_area.offset.y;
1850 info.src.box.width = state->render_area.extent.width;
1851 info.src.box.height = state->render_area.extent.height;
1852 info.src.box.depth = state->framebuffer.layers;
1853
1854 info.dst.box = info.src.box;
1855
1856 info.src.level = src_imgv->vk.base_mip_level;
1857 info.dst.level = dst_imgv->vk.base_mip_level;
1858
1859 state->pctx->blit(state->pctx, &info);
1860 }
1861
1862 if (!multi)
1863 return;
1864 for (uint32_t i = 0; i < state->color_att_count; i++) {
1865 struct lvp_image_view *src_imgv = state->color_att[i].imgv;
1866 if (src_imgv && src_imgv->multisample) //check if it has a msrtss view
1867 state->color_att[i].imgv = destroy_multisample_surface(state, src_imgv);
1868 }
1869 }
1870
render_resolve(struct rendering_state * state)1871 static void render_resolve(struct rendering_state *state)
1872 {
1873 if (state->forced_sample_count) {
1874 resolve_ds(state, true);
1875 resolve_color(state, true);
1876 }
1877 resolve_ds(state, false);
1878 resolve_color(state, false);
1879 }
1880
1881 static void
replicate_attachment(struct rendering_state * state,struct lvp_image_view * src,struct lvp_image_view * dst)1882 replicate_attachment(struct rendering_state *state, struct lvp_image_view *src, struct lvp_image_view *dst)
1883 {
1884 unsigned level = dst->surface->u.tex.level;
1885 struct pipe_box box;
1886 u_box_3d(0, 0, 0,
1887 u_minify(dst->image->bo->width0, level),
1888 u_minify(dst->image->bo->height0, level),
1889 u_minify(dst->image->bo->depth0, level),
1890 &box);
1891 state->pctx->resource_copy_region(state->pctx, dst->image->bo, level, 0, 0, 0, src->image->bo, level, &box);
1892 }
1893
1894 static struct lvp_image_view *
create_multisample_surface(struct rendering_state * state,struct lvp_image_view * imgv,uint32_t samples,bool replicate)1895 create_multisample_surface(struct rendering_state *state, struct lvp_image_view *imgv, uint32_t samples, bool replicate)
1896 {
1897 assert(!imgv->multisample);
1898
1899 struct pipe_resource templ = *imgv->surface->texture;
1900 templ.nr_samples = samples;
1901 struct lvp_image *image = mem_dup(imgv->image, sizeof(struct lvp_image));
1902 image->vk.samples = samples;
1903 image->pmem = NULL;
1904 image->bo = state->pctx->screen->resource_create(state->pctx->screen, &templ);
1905
1906 struct lvp_image_view *multi = mem_dup(imgv, sizeof(struct lvp_image_view));
1907 multi->image = image;
1908 multi->surface = state->pctx->create_surface(state->pctx, image->bo, imgv->surface);
1909 struct pipe_resource *ref = image->bo;
1910 pipe_resource_reference(&ref, NULL);
1911 imgv->multisample = multi;
1912 multi->multisample = imgv;
1913 if (replicate)
1914 replicate_attachment(state, imgv, multi);
1915 return multi;
1916 }
1917
1918 static bool
att_needs_replicate(const struct rendering_state * state,const struct lvp_image_view * imgv,VkAttachmentLoadOp load_op)1919 att_needs_replicate(const struct rendering_state *state, const struct lvp_image_view *imgv, VkAttachmentLoadOp load_op)
1920 {
1921 if (load_op == VK_ATTACHMENT_LOAD_OP_LOAD || load_op == VK_ATTACHMENT_LOAD_OP_CLEAR)
1922 return true;
1923 if (state->render_area.offset.x || state->render_area.offset.y)
1924 return true;
1925 if (state->render_area.extent.width < imgv->image->vk.extent.width ||
1926 state->render_area.extent.height < imgv->image->vk.extent.height)
1927 return true;
1928 return false;
1929 }
1930
render_att_init(struct lvp_render_attachment * att,const VkRenderingAttachmentInfo * vk_att)1931 static void render_att_init(struct lvp_render_attachment* att,
1932 const VkRenderingAttachmentInfo *vk_att)
1933 {
1934 if (vk_att == NULL || vk_att->imageView == VK_NULL_HANDLE) {
1935 *att = (struct lvp_render_attachment) {
1936 .load_op = VK_ATTACHMENT_LOAD_OP_DONT_CARE,
1937 };
1938 return;
1939 }
1940
1941 *att = (struct lvp_render_attachment) {
1942 .imgv = lvp_image_view_from_handle(vk_att->imageView),
1943 .load_op = vk_att->loadOp,
1944 .clear_value = vk_att->clearValue,
1945 };
1946
1947 if (vk_att->resolveImageView && vk_att->resolveMode) {
1948 att->resolve_imgv = lvp_image_view_from_handle(vk_att->resolveImageView);
1949 att->resolve_mode = vk_att->resolveMode;
1950 }
1951 }
1952
handle_begin_rendering(struct vk_cmd_queue_entry * cmd,struct rendering_state * state)1953 static void handle_begin_rendering(struct vk_cmd_queue_entry *cmd,
1954 struct rendering_state *state)
1955 {
1956 const VkRenderingInfo *info = cmd->u.begin_rendering.rendering_info;
1957 bool resuming = (info->flags & VK_RENDERING_RESUMING_BIT) == VK_RENDERING_RESUMING_BIT;
1958 bool suspending = (info->flags & VK_RENDERING_SUSPENDING_BIT) == VK_RENDERING_SUSPENDING_BIT;
1959
1960 const VkMultisampledRenderToSingleSampledInfoEXT *ssi =
1961 vk_find_struct_const(info->pNext, MULTISAMPLED_RENDER_TO_SINGLE_SAMPLED_INFO_EXT);
1962 if (ssi && ssi->multisampledRenderToSingleSampledEnable) {
1963 state->forced_sample_count = ssi->rasterizationSamples;
1964 state->forced_depth_resolve_mode = info->pDepthAttachment ? info->pDepthAttachment->resolveMode : 0;
1965 state->forced_stencil_resolve_mode = info->pStencilAttachment ? info->pStencilAttachment->resolveMode : 0;
1966 } else {
1967 state->forced_sample_count = 0;
1968 state->forced_depth_resolve_mode = 0;
1969 state->forced_stencil_resolve_mode = 0;
1970 }
1971
1972 state->info.view_mask = info->viewMask;
1973 state->render_area = info->renderArea;
1974 state->suspending = suspending;
1975 state->framebuffer.width = info->renderArea.offset.x +
1976 info->renderArea.extent.width;
1977 state->framebuffer.height = info->renderArea.offset.y +
1978 info->renderArea.extent.height;
1979 state->framebuffer.layers = info->viewMask ? util_last_bit(info->viewMask) : info->layerCount;
1980 state->framebuffer.nr_cbufs = info->colorAttachmentCount;
1981
1982 state->color_att_count = info->colorAttachmentCount;
1983 state->color_att = realloc(state->color_att, sizeof(*state->color_att) * state->color_att_count);
1984 for (unsigned i = 0; i < info->colorAttachmentCount; i++) {
1985 render_att_init(&state->color_att[i], &info->pColorAttachments[i]);
1986 if (state->color_att[i].imgv) {
1987 struct lvp_image_view *imgv = state->color_att[i].imgv;
1988 add_img_view_surface(state, imgv,
1989 state->framebuffer.width, state->framebuffer.height,
1990 state->framebuffer.layers);
1991 if (state->forced_sample_count && imgv->image->vk.samples == 1)
1992 state->color_att[i].imgv = create_multisample_surface(state, imgv, state->forced_sample_count,
1993 att_needs_replicate(state, imgv, state->color_att[i].load_op));
1994 state->framebuffer.cbufs[i] = state->color_att[i].imgv->surface;
1995 } else {
1996 state->framebuffer.cbufs[i] = NULL;
1997 }
1998 }
1999
2000 render_att_init(&state->depth_att, info->pDepthAttachment);
2001 render_att_init(&state->stencil_att, info->pStencilAttachment);
2002 if (state->depth_att.imgv || state->stencil_att.imgv) {
2003 assert(state->depth_att.imgv == NULL ||
2004 state->stencil_att.imgv == NULL ||
2005 state->depth_att.imgv == state->stencil_att.imgv);
2006 state->ds_imgv = state->depth_att.imgv ? state->depth_att.imgv :
2007 state->stencil_att.imgv;
2008 struct lvp_image_view *imgv = state->ds_imgv;
2009 add_img_view_surface(state, imgv,
2010 state->framebuffer.width, state->framebuffer.height,
2011 state->framebuffer.layers);
2012 if (state->forced_sample_count && imgv->image->vk.samples == 1) {
2013 VkAttachmentLoadOp load_op;
2014 if (state->depth_att.load_op == VK_ATTACHMENT_LOAD_OP_CLEAR ||
2015 state->stencil_att.load_op == VK_ATTACHMENT_LOAD_OP_CLEAR)
2016 load_op = VK_ATTACHMENT_LOAD_OP_CLEAR;
2017 else if (state->depth_att.load_op == VK_ATTACHMENT_LOAD_OP_LOAD ||
2018 state->stencil_att.load_op == VK_ATTACHMENT_LOAD_OP_LOAD)
2019 load_op = VK_ATTACHMENT_LOAD_OP_LOAD;
2020 else
2021 load_op = VK_ATTACHMENT_LOAD_OP_DONT_CARE;
2022 state->ds_imgv = create_multisample_surface(state, imgv, state->forced_sample_count,
2023 att_needs_replicate(state, imgv, load_op));
2024 }
2025 state->framebuffer.zsbuf = state->ds_imgv->surface;
2026 } else {
2027 state->ds_imgv = NULL;
2028 state->framebuffer.zsbuf = NULL;
2029 }
2030
2031 state->pctx->set_framebuffer_state(state->pctx,
2032 &state->framebuffer);
2033
2034 if (!resuming && render_needs_clear(state))
2035 render_clear_fast(state);
2036 }
2037
handle_end_rendering(struct vk_cmd_queue_entry * cmd,struct rendering_state * state)2038 static void handle_end_rendering(struct vk_cmd_queue_entry *cmd,
2039 struct rendering_state *state)
2040 {
2041 if (!state->suspending)
2042 render_resolve(state);
2043 }
2044
handle_draw(struct vk_cmd_queue_entry * cmd,struct rendering_state * state)2045 static void handle_draw(struct vk_cmd_queue_entry *cmd,
2046 struct rendering_state *state)
2047 {
2048 struct pipe_draw_start_count_bias draw;
2049
2050 state->info.index_size = 0;
2051 state->info.index.resource = NULL;
2052 state->info.start_instance = cmd->u.draw.first_instance;
2053 state->info.instance_count = cmd->u.draw.instance_count;
2054
2055 draw.start = cmd->u.draw.first_vertex;
2056 draw.count = cmd->u.draw.vertex_count;
2057
2058 state->pctx->set_patch_vertices(state->pctx, state->patch_vertices);
2059 state->pctx->draw_vbo(state->pctx, &state->info, 0, NULL, &draw, 1);
2060 }
2061
handle_draw_multi(struct vk_cmd_queue_entry * cmd,struct rendering_state * state)2062 static void handle_draw_multi(struct vk_cmd_queue_entry *cmd,
2063 struct rendering_state *state)
2064 {
2065 struct pipe_draw_start_count_bias *draws = calloc(cmd->u.draw_multi_ext.draw_count,
2066 sizeof(*draws));
2067
2068 state->info.index_size = 0;
2069 state->info.index.resource = NULL;
2070 state->info.start_instance = cmd->u.draw_multi_ext.first_instance;
2071 state->info.instance_count = cmd->u.draw_multi_ext.instance_count;
2072 if (cmd->u.draw_multi_ext.draw_count > 1)
2073 state->info.increment_draw_id = true;
2074
2075 for(unsigned i = 0; i < cmd->u.draw_multi_ext.draw_count; i++) {
2076 draws[i].start = cmd->u.draw_multi_ext.vertex_info[i].firstVertex;
2077 draws[i].count = cmd->u.draw_multi_ext.vertex_info[i].vertexCount;
2078 draws[i].index_bias = 0;
2079 }
2080
2081 state->pctx->set_patch_vertices(state->pctx, state->patch_vertices);
2082
2083 if (cmd->u.draw_multi_indexed_ext.draw_count)
2084 state->pctx->draw_vbo(state->pctx, &state->info, 0, NULL, draws, cmd->u.draw_multi_ext.draw_count);
2085
2086 free(draws);
2087 }
2088
set_viewport(unsigned first_viewport,unsigned viewport_count,const VkViewport * viewports,struct rendering_state * state)2089 static void set_viewport(unsigned first_viewport, unsigned viewport_count,
2090 const VkViewport* viewports,
2091 struct rendering_state *state)
2092 {
2093 int i;
2094 unsigned base = 0;
2095 if (first_viewport == UINT32_MAX)
2096 state->num_viewports = viewport_count;
2097 else
2098 base = first_viewport;
2099
2100 for (i = 0; i < viewport_count; i++) {
2101 int idx = i + base;
2102 const VkViewport *vp = &viewports[i];
2103 get_viewport_xform(state, vp, idx);
2104 set_viewport_depth_xform(state, idx);
2105 }
2106 state->vp_dirty = true;
2107 }
2108
handle_set_viewport(struct vk_cmd_queue_entry * cmd,struct rendering_state * state)2109 static void handle_set_viewport(struct vk_cmd_queue_entry *cmd,
2110 struct rendering_state *state)
2111 {
2112 set_viewport(cmd->u.set_viewport.first_viewport,
2113 cmd->u.set_viewport.viewport_count,
2114 cmd->u.set_viewport.viewports,
2115 state);
2116 }
2117
handle_set_viewport_with_count(struct vk_cmd_queue_entry * cmd,struct rendering_state * state)2118 static void handle_set_viewport_with_count(struct vk_cmd_queue_entry *cmd,
2119 struct rendering_state *state)
2120 {
2121 set_viewport(UINT32_MAX,
2122 cmd->u.set_viewport_with_count.viewport_count,
2123 cmd->u.set_viewport_with_count.viewports,
2124 state);
2125 }
2126
set_scissor(unsigned first_scissor,unsigned scissor_count,const VkRect2D * scissors,struct rendering_state * state)2127 static void set_scissor(unsigned first_scissor,
2128 unsigned scissor_count,
2129 const VkRect2D *scissors,
2130 struct rendering_state *state)
2131 {
2132 int i;
2133 unsigned base = 0;
2134 if (first_scissor == UINT32_MAX)
2135 state->num_scissors = scissor_count;
2136 else
2137 base = first_scissor;
2138
2139 for (i = 0; i < scissor_count; i++) {
2140 int idx = i + base;
2141 const VkRect2D *ss = &scissors[i];
2142 state->scissors[idx].minx = ss->offset.x;
2143 state->scissors[idx].miny = ss->offset.y;
2144 state->scissors[idx].maxx = ss->offset.x + ss->extent.width;
2145 state->scissors[idx].maxy = ss->offset.y + ss->extent.height;
2146 }
2147 state->scissor_dirty = true;
2148 }
2149
handle_set_scissor(struct vk_cmd_queue_entry * cmd,struct rendering_state * state)2150 static void handle_set_scissor(struct vk_cmd_queue_entry *cmd,
2151 struct rendering_state *state)
2152 {
2153 set_scissor(cmd->u.set_scissor.first_scissor,
2154 cmd->u.set_scissor.scissor_count,
2155 cmd->u.set_scissor.scissors,
2156 state);
2157 }
2158
handle_set_scissor_with_count(struct vk_cmd_queue_entry * cmd,struct rendering_state * state)2159 static void handle_set_scissor_with_count(struct vk_cmd_queue_entry *cmd,
2160 struct rendering_state *state)
2161 {
2162 set_scissor(UINT32_MAX,
2163 cmd->u.set_scissor_with_count.scissor_count,
2164 cmd->u.set_scissor_with_count.scissors,
2165 state);
2166 }
2167
handle_set_line_width(struct vk_cmd_queue_entry * cmd,struct rendering_state * state)2168 static void handle_set_line_width(struct vk_cmd_queue_entry *cmd,
2169 struct rendering_state *state)
2170 {
2171 state->rs_state.line_width = cmd->u.set_line_width.line_width;
2172 state->rs_dirty = true;
2173 }
2174
handle_set_depth_bias(struct vk_cmd_queue_entry * cmd,struct rendering_state * state)2175 static void handle_set_depth_bias(struct vk_cmd_queue_entry *cmd,
2176 struct rendering_state *state)
2177 {
2178 state->depth_bias.offset_units = cmd->u.set_depth_bias.depth_bias_constant_factor;
2179 state->depth_bias.offset_scale = cmd->u.set_depth_bias.depth_bias_slope_factor;
2180 state->depth_bias.offset_clamp = cmd->u.set_depth_bias.depth_bias_clamp;
2181 state->rs_dirty = true;
2182 }
2183
handle_set_blend_constants(struct vk_cmd_queue_entry * cmd,struct rendering_state * state)2184 static void handle_set_blend_constants(struct vk_cmd_queue_entry *cmd,
2185 struct rendering_state *state)
2186 {
2187 memcpy(state->blend_color.color, cmd->u.set_blend_constants.blend_constants, 4 * sizeof(float));
2188 state->blend_color_dirty = true;
2189 }
2190
handle_set_depth_bounds(struct vk_cmd_queue_entry * cmd,struct rendering_state * state)2191 static void handle_set_depth_bounds(struct vk_cmd_queue_entry *cmd,
2192 struct rendering_state *state)
2193 {
2194 state->dsa_dirty |= !DOUBLE_EQ(state->dsa_state.depth_bounds_min, cmd->u.set_depth_bounds.min_depth_bounds);
2195 state->dsa_dirty |= !DOUBLE_EQ(state->dsa_state.depth_bounds_max, cmd->u.set_depth_bounds.max_depth_bounds);
2196 state->dsa_state.depth_bounds_min = cmd->u.set_depth_bounds.min_depth_bounds;
2197 state->dsa_state.depth_bounds_max = cmd->u.set_depth_bounds.max_depth_bounds;
2198 }
2199
handle_set_stencil_compare_mask(struct vk_cmd_queue_entry * cmd,struct rendering_state * state)2200 static void handle_set_stencil_compare_mask(struct vk_cmd_queue_entry *cmd,
2201 struct rendering_state *state)
2202 {
2203 if (cmd->u.set_stencil_compare_mask.face_mask & VK_STENCIL_FACE_FRONT_BIT)
2204 state->dsa_state.stencil[0].valuemask = cmd->u.set_stencil_compare_mask.compare_mask;
2205 if (cmd->u.set_stencil_compare_mask.face_mask & VK_STENCIL_FACE_BACK_BIT)
2206 state->dsa_state.stencil[1].valuemask = cmd->u.set_stencil_compare_mask.compare_mask;
2207 state->dsa_dirty = true;
2208 }
2209
handle_set_stencil_write_mask(struct vk_cmd_queue_entry * cmd,struct rendering_state * state)2210 static void handle_set_stencil_write_mask(struct vk_cmd_queue_entry *cmd,
2211 struct rendering_state *state)
2212 {
2213 if (cmd->u.set_stencil_write_mask.face_mask & VK_STENCIL_FACE_FRONT_BIT)
2214 state->dsa_state.stencil[0].writemask = cmd->u.set_stencil_write_mask.write_mask;
2215 if (cmd->u.set_stencil_write_mask.face_mask & VK_STENCIL_FACE_BACK_BIT)
2216 state->dsa_state.stencil[1].writemask = cmd->u.set_stencil_write_mask.write_mask;
2217 state->dsa_dirty = true;
2218 }
2219
handle_set_stencil_reference(struct vk_cmd_queue_entry * cmd,struct rendering_state * state)2220 static void handle_set_stencil_reference(struct vk_cmd_queue_entry *cmd,
2221 struct rendering_state *state)
2222 {
2223 if (cmd->u.set_stencil_reference.face_mask & VK_STENCIL_FACE_FRONT_BIT)
2224 state->stencil_ref.ref_value[0] = cmd->u.set_stencil_reference.reference;
2225 if (cmd->u.set_stencil_reference.face_mask & VK_STENCIL_FACE_BACK_BIT)
2226 state->stencil_ref.ref_value[1] = cmd->u.set_stencil_reference.reference;
2227 state->stencil_ref_dirty = true;
2228 }
2229
2230 static void
copy_depth_rect(ubyte * dst,enum pipe_format dst_format,unsigned dst_stride,unsigned dst_x,unsigned dst_y,unsigned width,unsigned height,const ubyte * src,enum pipe_format src_format,int src_stride,unsigned src_x,unsigned src_y)2231 copy_depth_rect(ubyte * dst,
2232 enum pipe_format dst_format,
2233 unsigned dst_stride,
2234 unsigned dst_x,
2235 unsigned dst_y,
2236 unsigned width,
2237 unsigned height,
2238 const ubyte * src,
2239 enum pipe_format src_format,
2240 int src_stride,
2241 unsigned src_x,
2242 unsigned src_y)
2243 {
2244 int src_stride_pos = src_stride < 0 ? -src_stride : src_stride;
2245 int src_blocksize = util_format_get_blocksize(src_format);
2246 int src_blockwidth = util_format_get_blockwidth(src_format);
2247 int src_blockheight = util_format_get_blockheight(src_format);
2248 int dst_blocksize = util_format_get_blocksize(dst_format);
2249 int dst_blockwidth = util_format_get_blockwidth(dst_format);
2250 int dst_blockheight = util_format_get_blockheight(dst_format);
2251
2252 assert(src_blocksize > 0);
2253 assert(src_blockwidth > 0);
2254 assert(src_blockheight > 0);
2255
2256 dst_x /= dst_blockwidth;
2257 dst_y /= dst_blockheight;
2258 width = (width + src_blockwidth - 1)/src_blockwidth;
2259 height = (height + src_blockheight - 1)/src_blockheight;
2260 src_x /= src_blockwidth;
2261 src_y /= src_blockheight;
2262
2263 dst += dst_x * dst_blocksize;
2264 src += src_x * src_blocksize;
2265 dst += dst_y * dst_stride;
2266 src += src_y * src_stride_pos;
2267
2268 if (dst_format == PIPE_FORMAT_S8_UINT) {
2269 if (src_format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT) {
2270 util_format_z32_float_s8x24_uint_unpack_s_8uint(dst, dst_stride,
2271 src, src_stride,
2272 width, height);
2273 } else if (src_format == PIPE_FORMAT_Z24_UNORM_S8_UINT) {
2274 util_format_z24_unorm_s8_uint_unpack_s_8uint(dst, dst_stride,
2275 src, src_stride,
2276 width, height);
2277 } else {
2278 }
2279 } else if (dst_format == PIPE_FORMAT_Z24X8_UNORM) {
2280 util_format_z24_unorm_s8_uint_unpack_z24(dst, dst_stride,
2281 src, src_stride,
2282 width, height);
2283 } else if (dst_format == PIPE_FORMAT_Z32_FLOAT) {
2284 if (src_format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT) {
2285 util_format_z32_float_s8x24_uint_unpack_z_float((float *)dst, dst_stride,
2286 src, src_stride,
2287 width, height);
2288 }
2289 } else if (dst_format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT) {
2290 if (src_format == PIPE_FORMAT_Z32_FLOAT)
2291 util_format_z32_float_s8x24_uint_pack_z_float(dst, dst_stride,
2292 (float *)src, src_stride,
2293 width, height);
2294 else if (src_format == PIPE_FORMAT_S8_UINT)
2295 util_format_z32_float_s8x24_uint_pack_s_8uint(dst, dst_stride,
2296 src, src_stride,
2297 width, height);
2298 } else if (dst_format == PIPE_FORMAT_Z24_UNORM_S8_UINT) {
2299 if (src_format == PIPE_FORMAT_S8_UINT)
2300 util_format_z24_unorm_s8_uint_pack_s_8uint(dst, dst_stride,
2301 src, src_stride,
2302 width, height);
2303 if (src_format == PIPE_FORMAT_Z24X8_UNORM)
2304 util_format_z24_unorm_s8_uint_pack_z24(dst, dst_stride,
2305 src, src_stride,
2306 width, height);
2307 }
2308 }
2309
2310 static void
copy_depth_box(ubyte * dst,enum pipe_format dst_format,unsigned dst_stride,unsigned dst_slice_stride,unsigned dst_x,unsigned dst_y,unsigned dst_z,unsigned width,unsigned height,unsigned depth,const ubyte * src,enum pipe_format src_format,int src_stride,unsigned src_slice_stride,unsigned src_x,unsigned src_y,unsigned src_z)2311 copy_depth_box(ubyte *dst,
2312 enum pipe_format dst_format,
2313 unsigned dst_stride, unsigned dst_slice_stride,
2314 unsigned dst_x, unsigned dst_y, unsigned dst_z,
2315 unsigned width, unsigned height, unsigned depth,
2316 const ubyte * src,
2317 enum pipe_format src_format,
2318 int src_stride, unsigned src_slice_stride,
2319 unsigned src_x, unsigned src_y, unsigned src_z)
2320 {
2321 unsigned z;
2322 dst += dst_z * dst_slice_stride;
2323 src += src_z * src_slice_stride;
2324 for (z = 0; z < depth; ++z) {
2325 copy_depth_rect(dst,
2326 dst_format,
2327 dst_stride,
2328 dst_x, dst_y,
2329 width, height,
2330 src,
2331 src_format,
2332 src_stride,
2333 src_x, src_y);
2334
2335 dst += dst_slice_stride;
2336 src += src_slice_stride;
2337 }
2338 }
2339
handle_copy_image_to_buffer2(struct vk_cmd_queue_entry * cmd,struct rendering_state * state)2340 static void handle_copy_image_to_buffer2(struct vk_cmd_queue_entry *cmd,
2341 struct rendering_state *state)
2342 {
2343 int i;
2344 struct VkCopyImageToBufferInfo2 *copycmd = cmd->u.copy_image_to_buffer2.copy_image_to_buffer_info;
2345 LVP_FROM_HANDLE(lvp_image, src_image, copycmd->srcImage);
2346 struct pipe_box box, dbox;
2347 struct pipe_transfer *src_t, *dst_t;
2348 ubyte *src_data, *dst_data;
2349
2350 for (i = 0; i < copycmd->regionCount; i++) {
2351
2352 box.x = copycmd->pRegions[i].imageOffset.x;
2353 box.y = copycmd->pRegions[i].imageOffset.y;
2354 box.z = src_image->vk.image_type == VK_IMAGE_TYPE_3D ? copycmd->pRegions[i].imageOffset.z : copycmd->pRegions[i].imageSubresource.baseArrayLayer;
2355 box.width = copycmd->pRegions[i].imageExtent.width;
2356 box.height = copycmd->pRegions[i].imageExtent.height;
2357 box.depth = src_image->vk.image_type == VK_IMAGE_TYPE_3D ? copycmd->pRegions[i].imageExtent.depth : copycmd->pRegions[i].imageSubresource.layerCount;
2358
2359 src_data = state->pctx->texture_map(state->pctx,
2360 src_image->bo,
2361 copycmd->pRegions[i].imageSubresource.mipLevel,
2362 PIPE_MAP_READ,
2363 &box,
2364 &src_t);
2365
2366 dbox.x = copycmd->pRegions[i].bufferOffset;
2367 dbox.y = 0;
2368 dbox.z = 0;
2369 dbox.width = lvp_buffer_from_handle(copycmd->dstBuffer)->bo->width0 - copycmd->pRegions[i].bufferOffset;
2370 dbox.height = 1;
2371 dbox.depth = 1;
2372 dst_data = state->pctx->buffer_map(state->pctx,
2373 lvp_buffer_from_handle(copycmd->dstBuffer)->bo,
2374 0,
2375 PIPE_MAP_WRITE,
2376 &dbox,
2377 &dst_t);
2378
2379 enum pipe_format src_format = src_image->bo->format;
2380 enum pipe_format dst_format = src_format;
2381 if (util_format_is_depth_or_stencil(src_format)) {
2382 if (copycmd->pRegions[i].imageSubresource.aspectMask == VK_IMAGE_ASPECT_DEPTH_BIT) {
2383 dst_format = util_format_get_depth_only(src_format);
2384 } else if (copycmd->pRegions[i].imageSubresource.aspectMask == VK_IMAGE_ASPECT_STENCIL_BIT) {
2385 dst_format = PIPE_FORMAT_S8_UINT;
2386 }
2387 }
2388
2389 const struct vk_image_buffer_layout buffer_layout =
2390 vk_image_buffer_copy_layout(&src_image->vk, ©cmd->pRegions[i]);
2391 if (src_format != dst_format) {
2392 copy_depth_box(dst_data, dst_format,
2393 buffer_layout.row_stride_B,
2394 buffer_layout.image_stride_B,
2395 0, 0, 0,
2396 copycmd->pRegions[i].imageExtent.width,
2397 copycmd->pRegions[i].imageExtent.height,
2398 box.depth,
2399 src_data, src_format, src_t->stride, src_t->layer_stride, 0, 0, 0);
2400 } else {
2401 util_copy_box((ubyte *)dst_data, src_format,
2402 buffer_layout.row_stride_B,
2403 buffer_layout.image_stride_B,
2404 0, 0, 0,
2405 copycmd->pRegions[i].imageExtent.width,
2406 copycmd->pRegions[i].imageExtent.height,
2407 box.depth,
2408 src_data, src_t->stride, src_t->layer_stride, 0, 0, 0);
2409 }
2410 state->pctx->texture_unmap(state->pctx, src_t);
2411 state->pctx->buffer_unmap(state->pctx, dst_t);
2412 }
2413 }
2414
handle_copy_buffer_to_image(struct vk_cmd_queue_entry * cmd,struct rendering_state * state)2415 static void handle_copy_buffer_to_image(struct vk_cmd_queue_entry *cmd,
2416 struct rendering_state *state)
2417 {
2418 int i;
2419 struct VkCopyBufferToImageInfo2 *copycmd = cmd->u.copy_buffer_to_image2.copy_buffer_to_image_info;
2420 LVP_FROM_HANDLE(lvp_image, dst_image, copycmd->dstImage);
2421 struct pipe_box box, sbox;
2422 struct pipe_transfer *src_t, *dst_t;
2423 void *src_data, *dst_data;
2424
2425 for (i = 0; i < copycmd->regionCount; i++) {
2426
2427 sbox.x = copycmd->pRegions[i].bufferOffset;
2428 sbox.y = 0;
2429 sbox.z = 0;
2430 sbox.width = lvp_buffer_from_handle(copycmd->srcBuffer)->bo->width0;
2431 sbox.height = 1;
2432 sbox.depth = 1;
2433 src_data = state->pctx->buffer_map(state->pctx,
2434 lvp_buffer_from_handle(copycmd->srcBuffer)->bo,
2435 0,
2436 PIPE_MAP_READ,
2437 &sbox,
2438 &src_t);
2439
2440
2441 box.x = copycmd->pRegions[i].imageOffset.x;
2442 box.y = copycmd->pRegions[i].imageOffset.y;
2443 box.z = dst_image->vk.image_type == VK_IMAGE_TYPE_3D ? copycmd->pRegions[i].imageOffset.z : copycmd->pRegions[i].imageSubresource.baseArrayLayer;
2444 box.width = copycmd->pRegions[i].imageExtent.width;
2445 box.height = copycmd->pRegions[i].imageExtent.height;
2446 box.depth = dst_image->vk.image_type == VK_IMAGE_TYPE_3D ? copycmd->pRegions[i].imageExtent.depth : copycmd->pRegions[i].imageSubresource.layerCount;
2447
2448 dst_data = state->pctx->texture_map(state->pctx,
2449 dst_image->bo,
2450 copycmd->pRegions[i].imageSubresource.mipLevel,
2451 PIPE_MAP_WRITE,
2452 &box,
2453 &dst_t);
2454
2455 enum pipe_format dst_format = dst_image->bo->format;
2456 enum pipe_format src_format = dst_format;
2457 if (util_format_is_depth_or_stencil(dst_format)) {
2458 if (copycmd->pRegions[i].imageSubresource.aspectMask == VK_IMAGE_ASPECT_DEPTH_BIT) {
2459 src_format = util_format_get_depth_only(dst_image->bo->format);
2460 } else if (copycmd->pRegions[i].imageSubresource.aspectMask == VK_IMAGE_ASPECT_STENCIL_BIT) {
2461 src_format = PIPE_FORMAT_S8_UINT;
2462 }
2463 }
2464
2465 const struct vk_image_buffer_layout buffer_layout =
2466 vk_image_buffer_copy_layout(&dst_image->vk, ©cmd->pRegions[i]);
2467 if (src_format != dst_format) {
2468 copy_depth_box(dst_data, dst_format,
2469 dst_t->stride, dst_t->layer_stride,
2470 0, 0, 0,
2471 copycmd->pRegions[i].imageExtent.width,
2472 copycmd->pRegions[i].imageExtent.height,
2473 box.depth,
2474 src_data, src_format,
2475 buffer_layout.row_stride_B,
2476 buffer_layout.image_stride_B,
2477 0, 0, 0);
2478 } else {
2479 util_copy_box(dst_data, dst_format,
2480 dst_t->stride, dst_t->layer_stride,
2481 0, 0, 0,
2482 copycmd->pRegions[i].imageExtent.width,
2483 copycmd->pRegions[i].imageExtent.height,
2484 box.depth,
2485 src_data,
2486 buffer_layout.row_stride_B,
2487 buffer_layout.image_stride_B,
2488 0, 0, 0);
2489 }
2490 state->pctx->buffer_unmap(state->pctx, src_t);
2491 state->pctx->texture_unmap(state->pctx, dst_t);
2492 }
2493 }
2494
handle_copy_image(struct vk_cmd_queue_entry * cmd,struct rendering_state * state)2495 static void handle_copy_image(struct vk_cmd_queue_entry *cmd,
2496 struct rendering_state *state)
2497 {
2498 int i;
2499 struct VkCopyImageInfo2 *copycmd = cmd->u.copy_image2.copy_image_info;
2500 LVP_FROM_HANDLE(lvp_image, src_image, copycmd->srcImage);
2501 LVP_FROM_HANDLE(lvp_image, dst_image, copycmd->dstImage);
2502
2503 for (i = 0; i < copycmd->regionCount; i++) {
2504 struct pipe_box src_box;
2505 src_box.x = copycmd->pRegions[i].srcOffset.x;
2506 src_box.y = copycmd->pRegions[i].srcOffset.y;
2507 src_box.width = copycmd->pRegions[i].extent.width;
2508 src_box.height = copycmd->pRegions[i].extent.height;
2509 if (src_image->bo->target == PIPE_TEXTURE_3D) {
2510 src_box.depth = copycmd->pRegions[i].extent.depth;
2511 src_box.z = copycmd->pRegions[i].srcOffset.z;
2512 } else {
2513 src_box.depth = copycmd->pRegions[i].srcSubresource.layerCount;
2514 src_box.z = copycmd->pRegions[i].srcSubresource.baseArrayLayer;
2515 }
2516
2517 unsigned dstz = dst_image->bo->target == PIPE_TEXTURE_3D ?
2518 copycmd->pRegions[i].dstOffset.z :
2519 copycmd->pRegions[i].dstSubresource.baseArrayLayer;
2520 state->pctx->resource_copy_region(state->pctx, dst_image->bo,
2521 copycmd->pRegions[i].dstSubresource.mipLevel,
2522 copycmd->pRegions[i].dstOffset.x,
2523 copycmd->pRegions[i].dstOffset.y,
2524 dstz,
2525 src_image->bo,
2526 copycmd->pRegions[i].srcSubresource.mipLevel,
2527 &src_box);
2528 }
2529 }
2530
handle_copy_buffer(struct vk_cmd_queue_entry * cmd,struct rendering_state * state)2531 static void handle_copy_buffer(struct vk_cmd_queue_entry *cmd,
2532 struct rendering_state *state)
2533 {
2534 int i;
2535 VkCopyBufferInfo2 *copycmd = cmd->u.copy_buffer2.copy_buffer_info;
2536
2537 for (i = 0; i < copycmd->regionCount; i++) {
2538 struct pipe_box box = { 0 };
2539 u_box_1d(copycmd->pRegions[i].srcOffset, copycmd->pRegions[i].size, &box);
2540 state->pctx->resource_copy_region(state->pctx, lvp_buffer_from_handle(copycmd->dstBuffer)->bo, 0,
2541 copycmd->pRegions[i].dstOffset, 0, 0,
2542 lvp_buffer_from_handle(copycmd->srcBuffer)->bo, 0, &box);
2543 }
2544 }
2545
handle_blit_image(struct vk_cmd_queue_entry * cmd,struct rendering_state * state)2546 static void handle_blit_image(struct vk_cmd_queue_entry *cmd,
2547 struct rendering_state *state)
2548 {
2549 int i;
2550 VkBlitImageInfo2 *blitcmd = cmd->u.blit_image2.blit_image_info;
2551 LVP_FROM_HANDLE(lvp_image, src_image, blitcmd->srcImage);
2552 LVP_FROM_HANDLE(lvp_image, dst_image, blitcmd->dstImage);
2553 struct pipe_blit_info info;
2554
2555 memset(&info, 0, sizeof(info));
2556
2557 info.src.resource = src_image->bo;
2558 info.dst.resource = dst_image->bo;
2559 info.src.format = src_image->bo->format;
2560 info.dst.format = dst_image->bo->format;
2561 info.mask = util_format_is_depth_or_stencil(info.src.format) ? PIPE_MASK_ZS : PIPE_MASK_RGBA;
2562 info.filter = blitcmd->filter == VK_FILTER_NEAREST ? PIPE_TEX_FILTER_NEAREST : PIPE_TEX_FILTER_LINEAR;
2563 for (i = 0; i < blitcmd->regionCount; i++) {
2564 int srcX0, srcX1, srcY0, srcY1, srcZ0, srcZ1;
2565 unsigned dstX0, dstX1, dstY0, dstY1, dstZ0, dstZ1;
2566
2567 srcX0 = blitcmd->pRegions[i].srcOffsets[0].x;
2568 srcX1 = blitcmd->pRegions[i].srcOffsets[1].x;
2569 srcY0 = blitcmd->pRegions[i].srcOffsets[0].y;
2570 srcY1 = blitcmd->pRegions[i].srcOffsets[1].y;
2571 srcZ0 = blitcmd->pRegions[i].srcOffsets[0].z;
2572 srcZ1 = blitcmd->pRegions[i].srcOffsets[1].z;
2573
2574 dstX0 = blitcmd->pRegions[i].dstOffsets[0].x;
2575 dstX1 = blitcmd->pRegions[i].dstOffsets[1].x;
2576 dstY0 = blitcmd->pRegions[i].dstOffsets[0].y;
2577 dstY1 = blitcmd->pRegions[i].dstOffsets[1].y;
2578 dstZ0 = blitcmd->pRegions[i].dstOffsets[0].z;
2579 dstZ1 = blitcmd->pRegions[i].dstOffsets[1].z;
2580
2581 if (dstX0 < dstX1) {
2582 info.dst.box.x = dstX0;
2583 info.src.box.x = srcX0;
2584 info.dst.box.width = dstX1 - dstX0;
2585 info.src.box.width = srcX1 - srcX0;
2586 } else {
2587 info.dst.box.x = dstX1;
2588 info.src.box.x = srcX1;
2589 info.dst.box.width = dstX0 - dstX1;
2590 info.src.box.width = srcX0 - srcX1;
2591 }
2592
2593 if (dstY0 < dstY1) {
2594 info.dst.box.y = dstY0;
2595 info.src.box.y = srcY0;
2596 info.dst.box.height = dstY1 - dstY0;
2597 info.src.box.height = srcY1 - srcY0;
2598 } else {
2599 info.dst.box.y = dstY1;
2600 info.src.box.y = srcY1;
2601 info.dst.box.height = dstY0 - dstY1;
2602 info.src.box.height = srcY0 - srcY1;
2603 }
2604
2605 assert_subresource_layers(info.src.resource, &blitcmd->pRegions[i].srcSubresource, blitcmd->pRegions[i].srcOffsets);
2606 assert_subresource_layers(info.dst.resource, &blitcmd->pRegions[i].dstSubresource, blitcmd->pRegions[i].dstOffsets);
2607 if (src_image->bo->target == PIPE_TEXTURE_3D) {
2608 if (dstZ0 < dstZ1) {
2609 info.dst.box.z = dstZ0;
2610 info.src.box.z = srcZ0;
2611 info.dst.box.depth = dstZ1 - dstZ0;
2612 info.src.box.depth = srcZ1 - srcZ0;
2613 } else {
2614 info.dst.box.z = dstZ1;
2615 info.src.box.z = srcZ1;
2616 info.dst.box.depth = dstZ0 - dstZ1;
2617 info.src.box.depth = srcZ0 - srcZ1;
2618 }
2619 } else {
2620 info.src.box.z = blitcmd->pRegions[i].srcSubresource.baseArrayLayer;
2621 info.dst.box.z = blitcmd->pRegions[i].dstSubresource.baseArrayLayer;
2622 info.src.box.depth = blitcmd->pRegions[i].srcSubresource.layerCount;
2623 info.dst.box.depth = blitcmd->pRegions[i].dstSubresource.layerCount;
2624 }
2625
2626 info.src.level = blitcmd->pRegions[i].srcSubresource.mipLevel;
2627 info.dst.level = blitcmd->pRegions[i].dstSubresource.mipLevel;
2628 state->pctx->blit(state->pctx, &info);
2629 }
2630 }
2631
handle_fill_buffer(struct vk_cmd_queue_entry * cmd,struct rendering_state * state)2632 static void handle_fill_buffer(struct vk_cmd_queue_entry *cmd,
2633 struct rendering_state *state)
2634 {
2635 struct vk_cmd_fill_buffer *fillcmd = &cmd->u.fill_buffer;
2636 uint32_t size = fillcmd->size;
2637
2638 if (fillcmd->size == VK_WHOLE_SIZE) {
2639 size = lvp_buffer_from_handle(fillcmd->dst_buffer)->bo->width0 - fillcmd->dst_offset;
2640 size = ROUND_DOWN_TO(size, 4);
2641 }
2642
2643 state->pctx->clear_buffer(state->pctx,
2644 lvp_buffer_from_handle(fillcmd->dst_buffer)->bo,
2645 fillcmd->dst_offset,
2646 size,
2647 &fillcmd->data,
2648 4);
2649 }
2650
handle_update_buffer(struct vk_cmd_queue_entry * cmd,struct rendering_state * state)2651 static void handle_update_buffer(struct vk_cmd_queue_entry *cmd,
2652 struct rendering_state *state)
2653 {
2654 struct vk_cmd_update_buffer *updcmd = &cmd->u.update_buffer;
2655 uint32_t *dst;
2656 struct pipe_transfer *dst_t;
2657 struct pipe_box box;
2658
2659 u_box_1d(updcmd->dst_offset, updcmd->data_size, &box);
2660 dst = state->pctx->buffer_map(state->pctx,
2661 lvp_buffer_from_handle(updcmd->dst_buffer)->bo,
2662 0,
2663 PIPE_MAP_WRITE,
2664 &box,
2665 &dst_t);
2666
2667 memcpy(dst, updcmd->data, updcmd->data_size);
2668 state->pctx->buffer_unmap(state->pctx, dst_t);
2669 }
2670
handle_draw_indexed(struct vk_cmd_queue_entry * cmd,struct rendering_state * state)2671 static void handle_draw_indexed(struct vk_cmd_queue_entry *cmd,
2672 struct rendering_state *state)
2673 {
2674 struct pipe_draw_start_count_bias draw = {0};
2675
2676 state->info.index_bounds_valid = false;
2677 state->info.min_index = 0;
2678 state->info.max_index = ~0;
2679 state->info.index_size = state->index_size;
2680 state->info.index.resource = state->index_buffer;
2681 state->info.start_instance = cmd->u.draw_indexed.first_instance;
2682 state->info.instance_count = cmd->u.draw_indexed.instance_count;
2683
2684 if (state->info.primitive_restart)
2685 state->info.restart_index = util_prim_restart_index_from_size(state->info.index_size);
2686
2687 draw.count = cmd->u.draw_indexed.index_count;
2688 draw.index_bias = cmd->u.draw_indexed.vertex_offset;
2689 /* TODO: avoid calculating multiple times if cmdbuf is submitted again */
2690 draw.start = (state->index_offset / state->index_size) + cmd->u.draw_indexed.first_index;
2691
2692 state->info.index_bias_varies = !cmd->u.draw_indexed.vertex_offset;
2693 state->pctx->set_patch_vertices(state->pctx, state->patch_vertices);
2694 state->pctx->draw_vbo(state->pctx, &state->info, 0, NULL, &draw, 1);
2695 }
2696
handle_draw_multi_indexed(struct vk_cmd_queue_entry * cmd,struct rendering_state * state)2697 static void handle_draw_multi_indexed(struct vk_cmd_queue_entry *cmd,
2698 struct rendering_state *state)
2699 {
2700 struct pipe_draw_start_count_bias *draws = calloc(cmd->u.draw_multi_indexed_ext.draw_count,
2701 sizeof(*draws));
2702
2703 state->info.index_bounds_valid = false;
2704 state->info.min_index = 0;
2705 state->info.max_index = ~0;
2706 state->info.index_size = state->index_size;
2707 state->info.index.resource = state->index_buffer;
2708 state->info.start_instance = cmd->u.draw_multi_indexed_ext.first_instance;
2709 state->info.instance_count = cmd->u.draw_multi_indexed_ext.instance_count;
2710 if (cmd->u.draw_multi_indexed_ext.draw_count > 1)
2711 state->info.increment_draw_id = true;
2712
2713 if (state->info.primitive_restart)
2714 state->info.restart_index = util_prim_restart_index_from_size(state->info.index_size);
2715
2716 unsigned size = cmd->u.draw_multi_indexed_ext.draw_count * sizeof(struct pipe_draw_start_count_bias);
2717 memcpy(draws, cmd->u.draw_multi_indexed_ext.index_info, size);
2718
2719 /* only the first member is read if index_bias_varies is true */
2720 if (cmd->u.draw_multi_indexed_ext.draw_count &&
2721 cmd->u.draw_multi_indexed_ext.vertex_offset)
2722 draws[0].index_bias = *cmd->u.draw_multi_indexed_ext.vertex_offset;
2723
2724 /* TODO: avoid calculating multiple times if cmdbuf is submitted again */
2725 for (unsigned i = 0; i < cmd->u.draw_multi_indexed_ext.draw_count; i++)
2726 draws[i].start = (state->index_offset / state->index_size) + draws[i].start;
2727
2728 state->info.index_bias_varies = !cmd->u.draw_multi_indexed_ext.vertex_offset;
2729 state->pctx->set_patch_vertices(state->pctx, state->patch_vertices);
2730
2731 if (cmd->u.draw_multi_indexed_ext.draw_count)
2732 state->pctx->draw_vbo(state->pctx, &state->info, 0, NULL, draws, cmd->u.draw_multi_indexed_ext.draw_count);
2733
2734 free(draws);
2735 }
2736
handle_draw_indirect(struct vk_cmd_queue_entry * cmd,struct rendering_state * state,bool indexed)2737 static void handle_draw_indirect(struct vk_cmd_queue_entry *cmd,
2738 struct rendering_state *state, bool indexed)
2739 {
2740 struct pipe_draw_start_count_bias draw = {0};
2741 if (indexed) {
2742 state->info.index_bounds_valid = false;
2743 state->info.index_size = state->index_size;
2744 state->info.index.resource = state->index_buffer;
2745 state->info.max_index = ~0;
2746 if (state->info.primitive_restart)
2747 state->info.restart_index = util_prim_restart_index_from_size(state->info.index_size);
2748 } else
2749 state->info.index_size = 0;
2750 state->indirect_info.offset = cmd->u.draw_indirect.offset;
2751 state->indirect_info.stride = cmd->u.draw_indirect.stride;
2752 state->indirect_info.draw_count = cmd->u.draw_indirect.draw_count;
2753 state->indirect_info.buffer = lvp_buffer_from_handle(cmd->u.draw_indirect.buffer)->bo;
2754
2755 state->pctx->set_patch_vertices(state->pctx, state->patch_vertices);
2756 state->pctx->draw_vbo(state->pctx, &state->info, 0, &state->indirect_info, &draw, 1);
2757 }
2758
handle_index_buffer(struct vk_cmd_queue_entry * cmd,struct rendering_state * state)2759 static void handle_index_buffer(struct vk_cmd_queue_entry *cmd,
2760 struct rendering_state *state)
2761 {
2762 struct vk_cmd_bind_index_buffer *ib = &cmd->u.bind_index_buffer;
2763 switch (ib->index_type) {
2764 case VK_INDEX_TYPE_UINT8_EXT:
2765 state->index_size = 1;
2766 break;
2767 case VK_INDEX_TYPE_UINT16:
2768 state->index_size = 2;
2769 break;
2770 case VK_INDEX_TYPE_UINT32:
2771 state->index_size = 4;
2772 break;
2773 default:
2774 break;
2775 }
2776 state->index_offset = ib->offset;
2777 if (ib->buffer)
2778 state->index_buffer = lvp_buffer_from_handle(ib->buffer)->bo;
2779 else
2780 state->index_buffer = NULL;
2781
2782 state->ib_dirty = true;
2783 }
2784
handle_dispatch(struct vk_cmd_queue_entry * cmd,struct rendering_state * state)2785 static void handle_dispatch(struct vk_cmd_queue_entry *cmd,
2786 struct rendering_state *state)
2787 {
2788 state->dispatch_info.grid[0] = cmd->u.dispatch.group_count_x;
2789 state->dispatch_info.grid[1] = cmd->u.dispatch.group_count_y;
2790 state->dispatch_info.grid[2] = cmd->u.dispatch.group_count_z;
2791 state->dispatch_info.grid_base[0] = 0;
2792 state->dispatch_info.grid_base[1] = 0;
2793 state->dispatch_info.grid_base[2] = 0;
2794 state->dispatch_info.indirect = NULL;
2795 state->pctx->launch_grid(state->pctx, &state->dispatch_info);
2796 }
2797
handle_dispatch_base(struct vk_cmd_queue_entry * cmd,struct rendering_state * state)2798 static void handle_dispatch_base(struct vk_cmd_queue_entry *cmd,
2799 struct rendering_state *state)
2800 {
2801 state->dispatch_info.grid[0] = cmd->u.dispatch_base.group_count_x;
2802 state->dispatch_info.grid[1] = cmd->u.dispatch_base.group_count_y;
2803 state->dispatch_info.grid[2] = cmd->u.dispatch_base.group_count_z;
2804 state->dispatch_info.grid_base[0] = cmd->u.dispatch_base.base_group_x;
2805 state->dispatch_info.grid_base[1] = cmd->u.dispatch_base.base_group_y;
2806 state->dispatch_info.grid_base[2] = cmd->u.dispatch_base.base_group_z;
2807 state->dispatch_info.indirect = NULL;
2808 state->pctx->launch_grid(state->pctx, &state->dispatch_info);
2809 }
2810
handle_dispatch_indirect(struct vk_cmd_queue_entry * cmd,struct rendering_state * state)2811 static void handle_dispatch_indirect(struct vk_cmd_queue_entry *cmd,
2812 struct rendering_state *state)
2813 {
2814 state->dispatch_info.indirect = lvp_buffer_from_handle(cmd->u.dispatch_indirect.buffer)->bo;
2815 state->dispatch_info.indirect_offset = cmd->u.dispatch_indirect.offset;
2816 state->pctx->launch_grid(state->pctx, &state->dispatch_info);
2817 }
2818
handle_push_constants(struct vk_cmd_queue_entry * cmd,struct rendering_state * state)2819 static void handle_push_constants(struct vk_cmd_queue_entry *cmd,
2820 struct rendering_state *state)
2821 {
2822 memcpy(state->push_constants + cmd->u.push_constants.offset, cmd->u.push_constants.values, cmd->u.push_constants.size);
2823
2824 VkShaderStageFlags stage_flags = cmd->u.push_constants.stage_flags;
2825 state->pcbuf_dirty[PIPE_SHADER_VERTEX] |= (stage_flags & VK_SHADER_STAGE_VERTEX_BIT) > 0;
2826 state->pcbuf_dirty[PIPE_SHADER_FRAGMENT] |= (stage_flags & VK_SHADER_STAGE_FRAGMENT_BIT) > 0;
2827 state->pcbuf_dirty[PIPE_SHADER_GEOMETRY] |= (stage_flags & VK_SHADER_STAGE_GEOMETRY_BIT) > 0;
2828 state->pcbuf_dirty[PIPE_SHADER_TESS_CTRL] |= (stage_flags & VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT) > 0;
2829 state->pcbuf_dirty[PIPE_SHADER_TESS_EVAL] |= (stage_flags & VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT) > 0;
2830 state->pcbuf_dirty[PIPE_SHADER_COMPUTE] |= (stage_flags & VK_SHADER_STAGE_COMPUTE_BIT) > 0;
2831 state->inlines_dirty[PIPE_SHADER_VERTEX] |= (stage_flags & VK_SHADER_STAGE_VERTEX_BIT) > 0;
2832 state->inlines_dirty[PIPE_SHADER_FRAGMENT] |= (stage_flags & VK_SHADER_STAGE_FRAGMENT_BIT) > 0;
2833 state->inlines_dirty[PIPE_SHADER_GEOMETRY] |= (stage_flags & VK_SHADER_STAGE_GEOMETRY_BIT) > 0;
2834 state->inlines_dirty[PIPE_SHADER_TESS_CTRL] |= (stage_flags & VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT) > 0;
2835 state->inlines_dirty[PIPE_SHADER_TESS_EVAL] |= (stage_flags & VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT) > 0;
2836 state->inlines_dirty[PIPE_SHADER_COMPUTE] |= (stage_flags & VK_SHADER_STAGE_COMPUTE_BIT) > 0;
2837 }
2838
2839 static void lvp_execute_cmd_buffer(struct lvp_cmd_buffer *cmd_buffer,
2840 struct rendering_state *state);
2841
handle_execute_commands(struct vk_cmd_queue_entry * cmd,struct rendering_state * state)2842 static void handle_execute_commands(struct vk_cmd_queue_entry *cmd,
2843 struct rendering_state *state)
2844 {
2845 for (unsigned i = 0; i < cmd->u.execute_commands.command_buffer_count; i++) {
2846 LVP_FROM_HANDLE(lvp_cmd_buffer, secondary_buf, cmd->u.execute_commands.command_buffers[i]);
2847 lvp_execute_cmd_buffer(secondary_buf, state);
2848 }
2849 }
2850
handle_event_set2(struct vk_cmd_queue_entry * cmd,struct rendering_state * state)2851 static void handle_event_set2(struct vk_cmd_queue_entry *cmd,
2852 struct rendering_state *state)
2853 {
2854 LVP_FROM_HANDLE(lvp_event, event, cmd->u.set_event2.event);
2855
2856 VkPipelineStageFlags2 src_stage_mask = 0;
2857
2858 for (uint32_t i = 0; i < cmd->u.set_event2.dependency_info->memoryBarrierCount; i++)
2859 src_stage_mask |= cmd->u.set_event2.dependency_info->pMemoryBarriers[i].srcStageMask;
2860 for (uint32_t i = 0; i < cmd->u.set_event2.dependency_info->bufferMemoryBarrierCount; i++)
2861 src_stage_mask |= cmd->u.set_event2.dependency_info->pBufferMemoryBarriers[i].srcStageMask;
2862 for (uint32_t i = 0; i < cmd->u.set_event2.dependency_info->imageMemoryBarrierCount; i++)
2863 src_stage_mask |= cmd->u.set_event2.dependency_info->pImageMemoryBarriers[i].srcStageMask;
2864
2865 if (src_stage_mask & VK_PIPELINE_STAGE_2_TOP_OF_PIPE_BIT)
2866 state->pctx->flush(state->pctx, NULL, 0);
2867 event->event_storage = 1;
2868 }
2869
handle_event_reset2(struct vk_cmd_queue_entry * cmd,struct rendering_state * state)2870 static void handle_event_reset2(struct vk_cmd_queue_entry *cmd,
2871 struct rendering_state *state)
2872 {
2873 LVP_FROM_HANDLE(lvp_event, event, cmd->u.reset_event2.event);
2874
2875 if (cmd->u.reset_event2.stage_mask == VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT)
2876 state->pctx->flush(state->pctx, NULL, 0);
2877 event->event_storage = 0;
2878 }
2879
handle_wait_events2(struct vk_cmd_queue_entry * cmd,struct rendering_state * state)2880 static void handle_wait_events2(struct vk_cmd_queue_entry *cmd,
2881 struct rendering_state *state)
2882 {
2883 finish_fence(state);
2884 for (unsigned i = 0; i < cmd->u.wait_events2.event_count; i++) {
2885 LVP_FROM_HANDLE(lvp_event, event, cmd->u.wait_events2.events[i]);
2886
2887 while (event->event_storage != true);
2888 }
2889 }
2890
handle_pipeline_barrier(struct vk_cmd_queue_entry * cmd,struct rendering_state * state)2891 static void handle_pipeline_barrier(struct vk_cmd_queue_entry *cmd,
2892 struct rendering_state *state)
2893 {
2894 finish_fence(state);
2895 }
2896
handle_begin_query(struct vk_cmd_queue_entry * cmd,struct rendering_state * state)2897 static void handle_begin_query(struct vk_cmd_queue_entry *cmd,
2898 struct rendering_state *state)
2899 {
2900 struct vk_cmd_begin_query *qcmd = &cmd->u.begin_query;
2901 LVP_FROM_HANDLE(lvp_query_pool, pool, qcmd->query_pool);
2902
2903 if (pool->type == VK_QUERY_TYPE_PIPELINE_STATISTICS &&
2904 pool->pipeline_stats & VK_QUERY_PIPELINE_STATISTIC_COMPUTE_SHADER_INVOCATIONS_BIT)
2905 emit_compute_state(state);
2906
2907 emit_state(state);
2908
2909 if (!pool->queries[qcmd->query]) {
2910 enum pipe_query_type qtype = pool->base_type;
2911 pool->queries[qcmd->query] = state->pctx->create_query(state->pctx,
2912 qtype, 0);
2913 }
2914
2915 state->pctx->begin_query(state->pctx, pool->queries[qcmd->query]);
2916 }
2917
handle_end_query(struct vk_cmd_queue_entry * cmd,struct rendering_state * state)2918 static void handle_end_query(struct vk_cmd_queue_entry *cmd,
2919 struct rendering_state *state)
2920 {
2921 struct vk_cmd_end_query *qcmd = &cmd->u.end_query;
2922 LVP_FROM_HANDLE(lvp_query_pool, pool, qcmd->query_pool);
2923 assert(pool->queries[qcmd->query]);
2924
2925 state->pctx->end_query(state->pctx, pool->queries[qcmd->query]);
2926 }
2927
2928
handle_begin_query_indexed_ext(struct vk_cmd_queue_entry * cmd,struct rendering_state * state)2929 static void handle_begin_query_indexed_ext(struct vk_cmd_queue_entry *cmd,
2930 struct rendering_state *state)
2931 {
2932 struct vk_cmd_begin_query_indexed_ext *qcmd = &cmd->u.begin_query_indexed_ext;
2933 LVP_FROM_HANDLE(lvp_query_pool, pool, qcmd->query_pool);
2934
2935 if (pool->type == VK_QUERY_TYPE_PIPELINE_STATISTICS &&
2936 pool->pipeline_stats & VK_QUERY_PIPELINE_STATISTIC_COMPUTE_SHADER_INVOCATIONS_BIT)
2937 emit_compute_state(state);
2938
2939 emit_state(state);
2940
2941 if (!pool->queries[qcmd->query]) {
2942 enum pipe_query_type qtype = pool->base_type;
2943 pool->queries[qcmd->query] = state->pctx->create_query(state->pctx,
2944 qtype, qcmd->index);
2945 }
2946
2947 state->pctx->begin_query(state->pctx, pool->queries[qcmd->query]);
2948 }
2949
handle_end_query_indexed_ext(struct vk_cmd_queue_entry * cmd,struct rendering_state * state)2950 static void handle_end_query_indexed_ext(struct vk_cmd_queue_entry *cmd,
2951 struct rendering_state *state)
2952 {
2953 struct vk_cmd_end_query_indexed_ext *qcmd = &cmd->u.end_query_indexed_ext;
2954 LVP_FROM_HANDLE(lvp_query_pool, pool, qcmd->query_pool);
2955 assert(pool->queries[qcmd->query]);
2956
2957 state->pctx->end_query(state->pctx, pool->queries[qcmd->query]);
2958 }
2959
handle_reset_query_pool(struct vk_cmd_queue_entry * cmd,struct rendering_state * state)2960 static void handle_reset_query_pool(struct vk_cmd_queue_entry *cmd,
2961 struct rendering_state *state)
2962 {
2963 struct vk_cmd_reset_query_pool *qcmd = &cmd->u.reset_query_pool;
2964 LVP_FROM_HANDLE(lvp_query_pool, pool, qcmd->query_pool);
2965 for (unsigned i = qcmd->first_query; i < qcmd->first_query + qcmd->query_count; i++) {
2966 if (pool->queries[i]) {
2967 state->pctx->destroy_query(state->pctx, pool->queries[i]);
2968 pool->queries[i] = NULL;
2969 }
2970 }
2971 }
2972
handle_write_timestamp2(struct vk_cmd_queue_entry * cmd,struct rendering_state * state)2973 static void handle_write_timestamp2(struct vk_cmd_queue_entry *cmd,
2974 struct rendering_state *state)
2975 {
2976 struct vk_cmd_write_timestamp2 *qcmd = &cmd->u.write_timestamp2;
2977 LVP_FROM_HANDLE(lvp_query_pool, pool, qcmd->query_pool);
2978 if (!pool->queries[qcmd->query]) {
2979 pool->queries[qcmd->query] = state->pctx->create_query(state->pctx,
2980 PIPE_QUERY_TIMESTAMP, 0);
2981 }
2982
2983 if (!(qcmd->stage == VK_PIPELINE_STAGE_2_TOP_OF_PIPE_BIT))
2984 state->pctx->flush(state->pctx, NULL, 0);
2985 state->pctx->end_query(state->pctx, pool->queries[qcmd->query]);
2986
2987 }
2988
handle_copy_query_pool_results(struct vk_cmd_queue_entry * cmd,struct rendering_state * state)2989 static void handle_copy_query_pool_results(struct vk_cmd_queue_entry *cmd,
2990 struct rendering_state *state)
2991 {
2992 struct vk_cmd_copy_query_pool_results *copycmd = &cmd->u.copy_query_pool_results;
2993 LVP_FROM_HANDLE(lvp_query_pool, pool, copycmd->query_pool);
2994 enum pipe_query_flags flags = (copycmd->flags & VK_QUERY_RESULT_WAIT_BIT) ? PIPE_QUERY_WAIT : 0;
2995
2996 if (copycmd->flags & VK_QUERY_RESULT_PARTIAL_BIT)
2997 flags |= PIPE_QUERY_PARTIAL;
2998 unsigned result_size = copycmd->flags & VK_QUERY_RESULT_64_BIT ? 8 : 4;
2999 for (unsigned i = copycmd->first_query; i < copycmd->first_query + copycmd->query_count; i++) {
3000 unsigned offset = copycmd->dst_offset + lvp_buffer_from_handle(copycmd->dst_buffer)->offset + (copycmd->stride * (i - copycmd->first_query));
3001 if (pool->queries[i]) {
3002 unsigned num_results = 0;
3003 if (copycmd->flags & VK_QUERY_RESULT_WITH_AVAILABILITY_BIT) {
3004 if (pool->type == VK_QUERY_TYPE_PIPELINE_STATISTICS) {
3005 num_results = util_bitcount(pool->pipeline_stats);
3006 } else
3007 num_results = pool-> type == VK_QUERY_TYPE_TRANSFORM_FEEDBACK_STREAM_EXT ? 2 : 1;
3008 state->pctx->get_query_result_resource(state->pctx,
3009 pool->queries[i],
3010 flags,
3011 copycmd->flags & VK_QUERY_RESULT_64_BIT ? PIPE_QUERY_TYPE_U64 : PIPE_QUERY_TYPE_U32,
3012 -1,
3013 lvp_buffer_from_handle(copycmd->dst_buffer)->bo,
3014 offset + num_results * result_size);
3015 }
3016 if (pool->type == VK_QUERY_TYPE_PIPELINE_STATISTICS) {
3017 num_results = 0;
3018 u_foreach_bit(bit, pool->pipeline_stats)
3019 state->pctx->get_query_result_resource(state->pctx,
3020 pool->queries[i],
3021 flags,
3022 copycmd->flags & VK_QUERY_RESULT_64_BIT ? PIPE_QUERY_TYPE_U64 : PIPE_QUERY_TYPE_U32,
3023 bit,
3024 lvp_buffer_from_handle(copycmd->dst_buffer)->bo,
3025 offset + num_results++ * result_size);
3026 } else {
3027 state->pctx->get_query_result_resource(state->pctx,
3028 pool->queries[i],
3029 flags,
3030 copycmd->flags & VK_QUERY_RESULT_64_BIT ? PIPE_QUERY_TYPE_U64 : PIPE_QUERY_TYPE_U32,
3031 0,
3032 lvp_buffer_from_handle(copycmd->dst_buffer)->bo,
3033 offset);
3034 }
3035 } else {
3036 /* if no queries emitted yet, just reset the buffer to 0 so avail is reported correctly */
3037 if (copycmd->flags & VK_QUERY_RESULT_WITH_AVAILABILITY_BIT) {
3038 struct pipe_transfer *src_t;
3039 uint32_t *map;
3040
3041 struct pipe_box box = {0};
3042 box.x = offset;
3043 box.width = copycmd->stride;
3044 box.height = 1;
3045 box.depth = 1;
3046 map = state->pctx->buffer_map(state->pctx,
3047 lvp_buffer_from_handle(copycmd->dst_buffer)->bo, 0, PIPE_MAP_READ, &box,
3048 &src_t);
3049
3050 memset(map, 0, box.width);
3051 state->pctx->buffer_unmap(state->pctx, src_t);
3052 }
3053 }
3054 }
3055 }
3056
handle_clear_color_image(struct vk_cmd_queue_entry * cmd,struct rendering_state * state)3057 static void handle_clear_color_image(struct vk_cmd_queue_entry *cmd,
3058 struct rendering_state *state)
3059 {
3060 LVP_FROM_HANDLE(lvp_image, image, cmd->u.clear_color_image.image);
3061 union util_color uc;
3062 uint32_t *col_val = uc.ui;
3063 util_pack_color_union(image->bo->format, &uc, (void*)cmd->u.clear_color_image.color);
3064 for (unsigned i = 0; i < cmd->u.clear_color_image.range_count; i++) {
3065 VkImageSubresourceRange *range = &cmd->u.clear_color_image.ranges[i];
3066 struct pipe_box box;
3067 box.x = 0;
3068 box.y = 0;
3069 box.z = 0;
3070
3071 uint32_t level_count = vk_image_subresource_level_count(&image->vk, range);
3072 for (unsigned j = range->baseMipLevel; j < range->baseMipLevel + level_count; j++) {
3073 box.width = u_minify(image->bo->width0, j);
3074 box.height = u_minify(image->bo->height0, j);
3075 box.depth = 1;
3076 if (image->bo->target == PIPE_TEXTURE_3D)
3077 box.depth = u_minify(image->bo->depth0, j);
3078 else if (image->bo->target == PIPE_TEXTURE_1D_ARRAY) {
3079 box.y = range->baseArrayLayer;
3080 box.height = vk_image_subresource_layer_count(&image->vk, range);
3081 box.depth = 1;
3082 } else {
3083 box.z = range->baseArrayLayer;
3084 box.depth = vk_image_subresource_layer_count(&image->vk, range);
3085 }
3086
3087 state->pctx->clear_texture(state->pctx, image->bo,
3088 j, &box, (void *)col_val);
3089 }
3090 }
3091 }
3092
handle_clear_ds_image(struct vk_cmd_queue_entry * cmd,struct rendering_state * state)3093 static void handle_clear_ds_image(struct vk_cmd_queue_entry *cmd,
3094 struct rendering_state *state)
3095 {
3096 LVP_FROM_HANDLE(lvp_image, image, cmd->u.clear_depth_stencil_image.image);
3097 for (unsigned i = 0; i < cmd->u.clear_depth_stencil_image.range_count; i++) {
3098 VkImageSubresourceRange *range = &cmd->u.clear_depth_stencil_image.ranges[i];
3099 uint32_t ds_clear_flags = 0;
3100 if (range->aspectMask & VK_IMAGE_ASPECT_DEPTH_BIT)
3101 ds_clear_flags |= PIPE_CLEAR_DEPTH;
3102 if (range->aspectMask & VK_IMAGE_ASPECT_STENCIL_BIT)
3103 ds_clear_flags |= PIPE_CLEAR_STENCIL;
3104
3105 uint32_t level_count = vk_image_subresource_level_count(&image->vk, range);
3106 for (unsigned j = 0; j < level_count; j++) {
3107 struct pipe_surface *surf;
3108 unsigned width, height, depth;
3109 width = u_minify(image->bo->width0, range->baseMipLevel + j);
3110 height = u_minify(image->bo->height0, range->baseMipLevel + j);
3111
3112 if (image->bo->target == PIPE_TEXTURE_3D)
3113 depth = u_minify(image->bo->depth0, range->baseMipLevel + j);
3114 else {
3115 depth = vk_image_subresource_layer_count(&image->vk, range);
3116 }
3117
3118 surf = create_img_surface_bo(state, range,
3119 image->bo, image->bo->format,
3120 width, height,
3121 0, depth, j);
3122
3123 state->pctx->clear_depth_stencil(state->pctx,
3124 surf,
3125 ds_clear_flags,
3126 cmd->u.clear_depth_stencil_image.depth_stencil->depth,
3127 cmd->u.clear_depth_stencil_image.depth_stencil->stencil,
3128 0, 0,
3129 width, height, true);
3130 state->pctx->surface_destroy(state->pctx, surf);
3131 }
3132 }
3133 }
3134
handle_clear_attachments(struct vk_cmd_queue_entry * cmd,struct rendering_state * state)3135 static void handle_clear_attachments(struct vk_cmd_queue_entry *cmd,
3136 struct rendering_state *state)
3137 {
3138 for (uint32_t a = 0; a < cmd->u.clear_attachments.attachment_count; a++) {
3139 VkClearAttachment *att = &cmd->u.clear_attachments.attachments[a];
3140 struct lvp_image_view *imgv;
3141
3142 if (att->aspectMask == VK_IMAGE_ASPECT_COLOR_BIT) {
3143 imgv = state->color_att[att->colorAttachment].imgv;
3144 } else {
3145 imgv = state->ds_imgv;
3146 }
3147 if (!imgv)
3148 continue;
3149
3150 union pipe_color_union col_val;
3151 double dclear_val = 0;
3152 uint32_t sclear_val = 0;
3153 uint32_t ds_clear_flags = 0;
3154 if (att->aspectMask & VK_IMAGE_ASPECT_DEPTH_BIT) {
3155 ds_clear_flags |= PIPE_CLEAR_DEPTH;
3156 dclear_val = att->clearValue.depthStencil.depth;
3157 }
3158 if (att->aspectMask & VK_IMAGE_ASPECT_STENCIL_BIT) {
3159 ds_clear_flags |= PIPE_CLEAR_STENCIL;
3160 sclear_val = att->clearValue.depthStencil.stencil;
3161 }
3162 if (att->aspectMask & VK_IMAGE_ASPECT_COLOR_BIT) {
3163 for (unsigned i = 0; i < 4; i++)
3164 col_val.ui[i] = att->clearValue.color.uint32[i];
3165 }
3166
3167 for (uint32_t r = 0; r < cmd->u.clear_attachments.rect_count; r++) {
3168
3169 VkClearRect *rect = &cmd->u.clear_attachments.rects[r];
3170 /* avoid crashing on spec violations */
3171 rect->rect.offset.x = MAX2(rect->rect.offset.x, 0);
3172 rect->rect.offset.y = MAX2(rect->rect.offset.y, 0);
3173 rect->rect.extent.width = MIN2(rect->rect.extent.width, state->framebuffer.width - rect->rect.offset.x);
3174 rect->rect.extent.height = MIN2(rect->rect.extent.height, state->framebuffer.height - rect->rect.offset.y);
3175 if (state->info.view_mask) {
3176 u_foreach_bit(i, state->info.view_mask)
3177 clear_attachment_layers(state, imgv, &rect->rect,
3178 i, 1,
3179 ds_clear_flags, dclear_val, sclear_val,
3180 &col_val);
3181 } else
3182 clear_attachment_layers(state, imgv, &rect->rect,
3183 rect->baseArrayLayer, rect->layerCount,
3184 ds_clear_flags, dclear_val, sclear_val,
3185 &col_val);
3186 }
3187 }
3188 }
3189
handle_resolve_image(struct vk_cmd_queue_entry * cmd,struct rendering_state * state)3190 static void handle_resolve_image(struct vk_cmd_queue_entry *cmd,
3191 struct rendering_state *state)
3192 {
3193 int i;
3194 VkResolveImageInfo2 *resolvecmd = cmd->u.resolve_image2.resolve_image_info;
3195 LVP_FROM_HANDLE(lvp_image, src_image, resolvecmd->srcImage);
3196 LVP_FROM_HANDLE(lvp_image, dst_image, resolvecmd->dstImage);
3197 struct pipe_blit_info info;
3198
3199 memset(&info, 0, sizeof(info));
3200
3201 info.src.resource = src_image->bo;
3202 info.dst.resource = dst_image->bo;
3203 info.src.format = src_image->bo->format;
3204 info.dst.format = dst_image->bo->format;
3205 info.mask = util_format_is_depth_or_stencil(info.src.format) ? PIPE_MASK_ZS : PIPE_MASK_RGBA;
3206 info.filter = PIPE_TEX_FILTER_NEAREST;
3207 for (i = 0; i < resolvecmd->regionCount; i++) {
3208 int srcX0, srcY0;
3209 unsigned dstX0, dstY0;
3210
3211 srcX0 = resolvecmd->pRegions[i].srcOffset.x;
3212 srcY0 = resolvecmd->pRegions[i].srcOffset.y;
3213
3214 dstX0 = resolvecmd->pRegions[i].dstOffset.x;
3215 dstY0 = resolvecmd->pRegions[i].dstOffset.y;
3216
3217 info.dst.box.x = dstX0;
3218 info.dst.box.y = dstY0;
3219 info.src.box.x = srcX0;
3220 info.src.box.y = srcY0;
3221
3222 info.dst.box.width = resolvecmd->pRegions[i].extent.width;
3223 info.src.box.width = resolvecmd->pRegions[i].extent.width;
3224 info.dst.box.height = resolvecmd->pRegions[i].extent.height;
3225 info.src.box.height = resolvecmd->pRegions[i].extent.height;
3226
3227 info.dst.box.depth = resolvecmd->pRegions[i].dstSubresource.layerCount;
3228 info.src.box.depth = resolvecmd->pRegions[i].srcSubresource.layerCount;
3229
3230 info.src.level = resolvecmd->pRegions[i].srcSubresource.mipLevel;
3231 info.src.box.z = resolvecmd->pRegions[i].srcOffset.z + resolvecmd->pRegions[i].srcSubresource.baseArrayLayer;
3232
3233 info.dst.level = resolvecmd->pRegions[i].dstSubresource.mipLevel;
3234 info.dst.box.z = resolvecmd->pRegions[i].dstOffset.z + resolvecmd->pRegions[i].dstSubresource.baseArrayLayer;
3235
3236 state->pctx->blit(state->pctx, &info);
3237 }
3238 }
3239
handle_draw_indirect_count(struct vk_cmd_queue_entry * cmd,struct rendering_state * state,bool indexed)3240 static void handle_draw_indirect_count(struct vk_cmd_queue_entry *cmd,
3241 struct rendering_state *state, bool indexed)
3242 {
3243 struct pipe_draw_start_count_bias draw = {0};
3244 if (indexed) {
3245 state->info.index_bounds_valid = false;
3246 state->info.index_size = state->index_size;
3247 state->info.index.resource = state->index_buffer;
3248 state->info.max_index = ~0;
3249 } else
3250 state->info.index_size = 0;
3251 state->indirect_info.offset = cmd->u.draw_indirect_count.offset;
3252 state->indirect_info.stride = cmd->u.draw_indirect_count.stride;
3253 state->indirect_info.draw_count = cmd->u.draw_indirect_count.max_draw_count;
3254 state->indirect_info.buffer = lvp_buffer_from_handle(cmd->u.draw_indirect_count.buffer)->bo;
3255 state->indirect_info.indirect_draw_count_offset = cmd->u.draw_indirect_count.count_buffer_offset;
3256 state->indirect_info.indirect_draw_count = lvp_buffer_from_handle(cmd->u.draw_indirect_count.count_buffer)->bo;
3257
3258 state->pctx->set_patch_vertices(state->pctx, state->patch_vertices);
3259 state->pctx->draw_vbo(state->pctx, &state->info, 0, &state->indirect_info, &draw, 1);
3260 }
3261
handle_compute_push_descriptor_set(struct lvp_cmd_push_descriptor_set * pds,struct dyn_info * dyn_info,struct rendering_state * state)3262 static void handle_compute_push_descriptor_set(struct lvp_cmd_push_descriptor_set *pds,
3263 struct dyn_info *dyn_info,
3264 struct rendering_state *state)
3265 {
3266 const struct lvp_descriptor_set_layout *layout =
3267 vk_to_lvp_descriptor_set_layout(pds->layout->vk.set_layouts[pds->set]);
3268
3269 if (!(layout->shader_stages & VK_SHADER_STAGE_COMPUTE_BIT))
3270 return;
3271 for (unsigned i = 0; i < pds->set; i++) {
3272 increment_dyn_info(dyn_info, pds->layout->vk.set_layouts[i], false);
3273 }
3274 unsigned info_idx = 0;
3275 for (unsigned i = 0; i < pds->descriptor_write_count; i++) {
3276 struct lvp_write_descriptor *desc = &pds->descriptors[i];
3277 const struct lvp_descriptor_set_binding_layout *binding =
3278 &layout->binding[desc->dst_binding];
3279
3280 if (!binding->valid)
3281 continue;
3282
3283 for (unsigned j = 0; j < desc->descriptor_count; j++) {
3284 union lvp_descriptor_info *info = &pds->infos[info_idx + j];
3285
3286 handle_descriptor(state, dyn_info, binding,
3287 MESA_SHADER_COMPUTE, PIPE_SHADER_COMPUTE,
3288 j, desc->descriptor_type,
3289 info);
3290 }
3291 info_idx += desc->descriptor_count;
3292 }
3293 }
3294
create_push_descriptor_set(struct vk_cmd_push_descriptor_set_khr * in_cmd)3295 static struct lvp_cmd_push_descriptor_set *create_push_descriptor_set(struct vk_cmd_push_descriptor_set_khr *in_cmd)
3296 {
3297 LVP_FROM_HANDLE(lvp_pipeline_layout, layout, in_cmd->layout);
3298 struct lvp_cmd_push_descriptor_set *out_cmd;
3299 int count_descriptors = 0;
3300
3301 for (unsigned i = 0; i < in_cmd->descriptor_write_count; i++) {
3302 count_descriptors += in_cmd->descriptor_writes[i].descriptorCount;
3303 }
3304
3305 void *descriptors;
3306 void *infos;
3307 void **ptrs[] = {&descriptors, &infos};
3308 size_t sizes[] = {
3309 in_cmd->descriptor_write_count * sizeof(struct lvp_write_descriptor),
3310 count_descriptors * sizeof(union lvp_descriptor_info),
3311 };
3312 out_cmd = ptrzalloc(sizeof(struct lvp_cmd_push_descriptor_set), 2, sizes, ptrs);
3313 if (!out_cmd)
3314 return NULL;
3315
3316 out_cmd->bind_point = in_cmd->pipeline_bind_point;
3317 out_cmd->layout = layout;
3318 out_cmd->set = in_cmd->set;
3319 out_cmd->descriptor_write_count = in_cmd->descriptor_write_count;
3320 out_cmd->descriptors = descriptors;
3321 out_cmd->infos = infos;
3322
3323 unsigned descriptor_index = 0;
3324
3325 for (unsigned i = 0; i < in_cmd->descriptor_write_count; i++) {
3326 struct lvp_write_descriptor *desc = &out_cmd->descriptors[i];
3327
3328 /* dstSet is ignored */
3329 desc->dst_binding = in_cmd->descriptor_writes[i].dstBinding;
3330 desc->dst_array_element = in_cmd->descriptor_writes[i].dstArrayElement;
3331 desc->descriptor_count = in_cmd->descriptor_writes[i].descriptorCount;
3332 desc->descriptor_type = in_cmd->descriptor_writes[i].descriptorType;
3333
3334 for (unsigned j = 0; j < desc->descriptor_count; j++) {
3335 union lvp_descriptor_info *info = &out_cmd->infos[descriptor_index + j];
3336 switch (desc->descriptor_type) {
3337 case VK_DESCRIPTOR_TYPE_SAMPLER:
3338 info->sampler = lvp_sampler_from_handle(in_cmd->descriptor_writes[i].pImageInfo[j].sampler);
3339 break;
3340 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER:
3341 info->sampler = lvp_sampler_from_handle(in_cmd->descriptor_writes[i].pImageInfo[j].sampler);
3342 info->iview = lvp_image_view_from_handle(in_cmd->descriptor_writes[i].pImageInfo[j].imageView);
3343 info->image_layout = in_cmd->descriptor_writes[i].pImageInfo[j].imageLayout;
3344 break;
3345 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE:
3346 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE:
3347 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT:
3348 info->iview = lvp_image_view_from_handle(in_cmd->descriptor_writes[i].pImageInfo[j].imageView);
3349 info->image_layout = in_cmd->descriptor_writes[i].pImageInfo[j].imageLayout;
3350 break;
3351 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER:
3352 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER:
3353 info->buffer_view = lvp_buffer_view_from_handle(in_cmd->descriptor_writes[i].pTexelBufferView[j]);
3354 break;
3355 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER:
3356 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER:
3357 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
3358 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC:
3359 default:
3360 info->buffer = lvp_buffer_from_handle(in_cmd->descriptor_writes[i].pBufferInfo[j].buffer);
3361 info->offset = in_cmd->descriptor_writes[i].pBufferInfo[j].offset;
3362 info->range = in_cmd->descriptor_writes[i].pBufferInfo[j].range;
3363 break;
3364 }
3365 }
3366 descriptor_index += desc->descriptor_count;
3367 }
3368
3369 return out_cmd;
3370 }
3371
handle_push_descriptor_set_generic(struct vk_cmd_push_descriptor_set_khr * _pds,struct rendering_state * state)3372 static void handle_push_descriptor_set_generic(struct vk_cmd_push_descriptor_set_khr *_pds,
3373 struct rendering_state *state)
3374 {
3375 struct lvp_cmd_push_descriptor_set *pds = create_push_descriptor_set(_pds);
3376 const struct lvp_descriptor_set_layout *layout =
3377 vk_to_lvp_descriptor_set_layout(pds->layout->vk.set_layouts[pds->set]);
3378
3379 struct dyn_info dyn_info;
3380 memset(&dyn_info.stage, 0, sizeof(dyn_info.stage));
3381 dyn_info.dyn_index = 0;
3382 if (pds->bind_point == VK_PIPELINE_BIND_POINT_COMPUTE) {
3383 handle_compute_push_descriptor_set(pds, &dyn_info, state);
3384 }
3385
3386 for (unsigned i = 0; i < pds->set; i++) {
3387 increment_dyn_info(&dyn_info, pds->layout->vk.set_layouts[i], false);
3388 }
3389
3390 unsigned info_idx = 0;
3391 for (unsigned i = 0; i < pds->descriptor_write_count; i++) {
3392 struct lvp_write_descriptor *desc = &pds->descriptors[i];
3393 const struct lvp_descriptor_set_binding_layout *binding =
3394 &layout->binding[desc->dst_binding];
3395
3396 if (!binding->valid)
3397 continue;
3398
3399 for (unsigned j = 0; j < desc->descriptor_count; j++) {
3400 union lvp_descriptor_info *info = &pds->infos[info_idx + j];
3401
3402 if (layout->shader_stages & VK_SHADER_STAGE_VERTEX_BIT)
3403 handle_descriptor(state, &dyn_info, binding,
3404 MESA_SHADER_VERTEX, PIPE_SHADER_VERTEX,
3405 j, desc->descriptor_type,
3406 info);
3407 if (layout->shader_stages & VK_SHADER_STAGE_FRAGMENT_BIT)
3408 handle_descriptor(state, &dyn_info, binding,
3409 MESA_SHADER_FRAGMENT, PIPE_SHADER_FRAGMENT,
3410 j, desc->descriptor_type,
3411 info);
3412 if (layout->shader_stages & VK_SHADER_STAGE_GEOMETRY_BIT)
3413 handle_descriptor(state, &dyn_info, binding,
3414 MESA_SHADER_GEOMETRY, PIPE_SHADER_GEOMETRY,
3415 j, desc->descriptor_type,
3416 info);
3417 if (layout->shader_stages & VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT)
3418 handle_descriptor(state, &dyn_info, binding,
3419 MESA_SHADER_TESS_CTRL, PIPE_SHADER_TESS_CTRL,
3420 j, desc->descriptor_type,
3421 info);
3422 if (layout->shader_stages & VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT)
3423 handle_descriptor(state, &dyn_info, binding,
3424 MESA_SHADER_TESS_EVAL, PIPE_SHADER_TESS_EVAL,
3425 j, desc->descriptor_type,
3426 info);
3427 }
3428 info_idx += desc->descriptor_count;
3429 }
3430 free(pds);
3431 }
3432
handle_push_descriptor_set(struct vk_cmd_queue_entry * cmd,struct rendering_state * state)3433 static void handle_push_descriptor_set(struct vk_cmd_queue_entry *cmd,
3434 struct rendering_state *state)
3435 {
3436 handle_push_descriptor_set_generic(&cmd->u.push_descriptor_set_khr, state);
3437 }
3438
handle_push_descriptor_set_with_template(struct vk_cmd_queue_entry * cmd,struct rendering_state * state)3439 static void handle_push_descriptor_set_with_template(struct vk_cmd_queue_entry *cmd,
3440 struct rendering_state *state)
3441 {
3442 LVP_FROM_HANDLE(lvp_descriptor_update_template, templ, cmd->u.push_descriptor_set_with_template_khr.descriptor_update_template);
3443 struct vk_cmd_push_descriptor_set_khr *pds;
3444 int pds_size = sizeof(*pds);
3445
3446 pds_size += templ->entry_count * sizeof(struct VkWriteDescriptorSet);
3447
3448 for (unsigned i = 0; i < templ->entry_count; i++) {
3449 VkDescriptorUpdateTemplateEntry *entry = &templ->entry[i];
3450 switch (entry->descriptorType) {
3451 case VK_DESCRIPTOR_TYPE_SAMPLER:
3452 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER:
3453 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE:
3454 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE:
3455 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT:
3456 pds_size += sizeof(VkDescriptorImageInfo) * entry->descriptorCount;
3457 break;
3458 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER:
3459 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER:
3460 pds_size += sizeof(VkBufferView) * entry->descriptorCount;
3461 break;
3462 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER:
3463 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER:
3464 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
3465 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC:
3466 default:
3467 pds_size += sizeof(VkDescriptorBufferInfo) * entry->descriptorCount;
3468 break;
3469 }
3470 }
3471
3472 pds = calloc(1, pds_size);
3473 if (!pds)
3474 return;
3475
3476 pds->pipeline_bind_point = templ->bind_point;
3477 pds->layout = lvp_pipeline_layout_to_handle(templ->pipeline_layout);
3478 pds->set = templ->set;
3479 pds->descriptor_write_count = templ->entry_count;
3480 pds->descriptor_writes = (struct VkWriteDescriptorSet *)(pds + 1);
3481 const uint8_t *next_info = (const uint8_t *) (pds->descriptor_writes + templ->entry_count);
3482
3483 const uint8_t *pSrc = cmd->u.push_descriptor_set_with_template_khr.data;
3484 for (unsigned i = 0; i < templ->entry_count; i++) {
3485 struct VkWriteDescriptorSet *desc = &pds->descriptor_writes[i];
3486 struct VkDescriptorUpdateTemplateEntry *entry = &templ->entry[i];
3487
3488 /* dstSet is ignored */
3489 desc->dstBinding = entry->dstBinding;
3490 desc->dstArrayElement = entry->dstArrayElement;
3491 desc->descriptorCount = entry->descriptorCount;
3492 desc->descriptorType = entry->descriptorType;
3493 desc->pImageInfo = (const VkDescriptorImageInfo *) next_info;
3494 desc->pTexelBufferView = (const VkBufferView *) next_info;
3495 desc->pBufferInfo = (const VkDescriptorBufferInfo *) next_info;
3496
3497 for (unsigned j = 0; j < desc->descriptorCount; j++) {
3498 switch (desc->descriptorType) {
3499 case VK_DESCRIPTOR_TYPE_SAMPLER:
3500 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER:
3501 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE:
3502 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE:
3503 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT:
3504 memcpy((VkDescriptorImageInfo*)&desc->pImageInfo[j], pSrc, sizeof(VkDescriptorImageInfo));
3505 next_info += sizeof(VkDescriptorImageInfo);
3506 pSrc += sizeof(VkDescriptorImageInfo);
3507 break;
3508 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER:
3509 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER:
3510 memcpy((VkBufferView*)&desc->pTexelBufferView[j], pSrc, sizeof(VkBufferView));
3511 next_info += sizeof(VkBufferView);
3512 pSrc += sizeof(VkBufferView);
3513 break;
3514 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER:
3515 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER:
3516 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
3517 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC:
3518 default:
3519 memcpy((VkDescriptorBufferInfo*)&desc->pBufferInfo[j], pSrc, sizeof(VkDescriptorBufferInfo));
3520 next_info += sizeof(VkDescriptorBufferInfo);
3521 pSrc += sizeof(VkDescriptorBufferInfo);
3522 break;
3523 }
3524 }
3525 }
3526 handle_push_descriptor_set_generic(pds, state);
3527 free(pds);
3528 }
3529
handle_bind_transform_feedback_buffers(struct vk_cmd_queue_entry * cmd,struct rendering_state * state)3530 static void handle_bind_transform_feedback_buffers(struct vk_cmd_queue_entry *cmd,
3531 struct rendering_state *state)
3532 {
3533 struct vk_cmd_bind_transform_feedback_buffers_ext *btfb = &cmd->u.bind_transform_feedback_buffers_ext;
3534
3535 for (unsigned i = 0; i < btfb->binding_count; i++) {
3536 int idx = i + btfb->first_binding;
3537 uint32_t size;
3538 if (btfb->sizes && btfb->sizes[i] != VK_WHOLE_SIZE)
3539 size = btfb->sizes[i];
3540 else
3541 size = lvp_buffer_from_handle(btfb->buffers[i])->size - btfb->offsets[i];
3542
3543 if (state->so_targets[idx])
3544 state->pctx->stream_output_target_destroy(state->pctx, state->so_targets[idx]);
3545
3546 state->so_targets[idx] = state->pctx->create_stream_output_target(state->pctx,
3547 lvp_buffer_from_handle(btfb->buffers[i])->bo,
3548 btfb->offsets[i],
3549 size);
3550 }
3551 state->num_so_targets = btfb->first_binding + btfb->binding_count;
3552 }
3553
handle_begin_transform_feedback(struct vk_cmd_queue_entry * cmd,struct rendering_state * state)3554 static void handle_begin_transform_feedback(struct vk_cmd_queue_entry *cmd,
3555 struct rendering_state *state)
3556 {
3557 struct vk_cmd_begin_transform_feedback_ext *btf = &cmd->u.begin_transform_feedback_ext;
3558 uint32_t offsets[4];
3559
3560 memset(offsets, 0, sizeof(uint32_t)*4);
3561
3562 for (unsigned i = 0; btf->counter_buffers && i < btf->counter_buffer_count; i++) {
3563 if (!btf->counter_buffers[i])
3564 continue;
3565
3566 pipe_buffer_read(state->pctx,
3567 btf->counter_buffers ? lvp_buffer_from_handle(btf->counter_buffers[i])->bo : NULL,
3568 btf->counter_buffer_offsets ? btf->counter_buffer_offsets[i] : 0,
3569 4,
3570 &offsets[i]);
3571 }
3572 state->pctx->set_stream_output_targets(state->pctx, state->num_so_targets,
3573 state->so_targets, offsets);
3574 }
3575
handle_end_transform_feedback(struct vk_cmd_queue_entry * cmd,struct rendering_state * state)3576 static void handle_end_transform_feedback(struct vk_cmd_queue_entry *cmd,
3577 struct rendering_state *state)
3578 {
3579 struct vk_cmd_end_transform_feedback_ext *etf = &cmd->u.end_transform_feedback_ext;
3580
3581 if (etf->counter_buffer_count) {
3582 for (unsigned i = 0; etf->counter_buffers && i < etf->counter_buffer_count; i++) {
3583 if (!etf->counter_buffers[i])
3584 continue;
3585
3586 uint32_t offset;
3587 offset = state->pctx->stream_output_target_offset(state->so_targets[i]);
3588
3589 pipe_buffer_write(state->pctx,
3590 etf->counter_buffers ? lvp_buffer_from_handle(etf->counter_buffers[i])->bo : NULL,
3591 etf->counter_buffer_offsets ? etf->counter_buffer_offsets[i] : 0,
3592 4,
3593 &offset);
3594 }
3595 }
3596 state->pctx->set_stream_output_targets(state->pctx, 0, NULL, NULL);
3597 }
3598
handle_draw_indirect_byte_count(struct vk_cmd_queue_entry * cmd,struct rendering_state * state)3599 static void handle_draw_indirect_byte_count(struct vk_cmd_queue_entry *cmd,
3600 struct rendering_state *state)
3601 {
3602 struct vk_cmd_draw_indirect_byte_count_ext *dibc = &cmd->u.draw_indirect_byte_count_ext;
3603 struct pipe_draw_start_count_bias draw = {0};
3604
3605 pipe_buffer_read(state->pctx,
3606 lvp_buffer_from_handle(dibc->counter_buffer)->bo,
3607 lvp_buffer_from_handle(dibc->counter_buffer)->offset + dibc->counter_buffer_offset,
3608 4, &draw.count);
3609
3610 state->info.start_instance = cmd->u.draw_indirect_byte_count_ext.first_instance;
3611 state->info.instance_count = cmd->u.draw_indirect_byte_count_ext.instance_count;
3612 state->info.index_size = 0;
3613
3614 draw.count /= cmd->u.draw_indirect_byte_count_ext.vertex_stride;
3615 state->pctx->set_patch_vertices(state->pctx, state->patch_vertices);
3616 state->pctx->draw_vbo(state->pctx, &state->info, 0, &state->indirect_info, &draw, 1);
3617 }
3618
handle_begin_conditional_rendering(struct vk_cmd_queue_entry * cmd,struct rendering_state * state)3619 static void handle_begin_conditional_rendering(struct vk_cmd_queue_entry *cmd,
3620 struct rendering_state *state)
3621 {
3622 struct VkConditionalRenderingBeginInfoEXT *bcr = cmd->u.begin_conditional_rendering_ext.conditional_rendering_begin;
3623 state->pctx->render_condition_mem(state->pctx,
3624 lvp_buffer_from_handle(bcr->buffer)->bo,
3625 lvp_buffer_from_handle(bcr->buffer)->offset + bcr->offset,
3626 bcr->flags & VK_CONDITIONAL_RENDERING_INVERTED_BIT_EXT);
3627 }
3628
handle_end_conditional_rendering(struct rendering_state * state)3629 static void handle_end_conditional_rendering(struct rendering_state *state)
3630 {
3631 state->pctx->render_condition_mem(state->pctx, NULL, 0, false);
3632 }
3633
handle_set_vertex_input(struct vk_cmd_queue_entry * cmd,struct rendering_state * state)3634 static void handle_set_vertex_input(struct vk_cmd_queue_entry *cmd,
3635 struct rendering_state *state)
3636 {
3637 const struct vk_cmd_set_vertex_input_ext *vertex_input = &cmd->u.set_vertex_input_ext;
3638 const struct VkVertexInputBindingDescription2EXT *bindings = vertex_input->vertex_binding_descriptions;
3639 const struct VkVertexInputAttributeDescription2EXT *attrs = vertex_input->vertex_attribute_descriptions;
3640 int max_location = -1;
3641 for (unsigned i = 0; i < vertex_input->vertex_attribute_description_count; i++) {
3642 const struct VkVertexInputBindingDescription2EXT *binding = NULL;
3643 unsigned location = attrs[i].location;
3644
3645 for (unsigned j = 0; j < vertex_input->vertex_binding_description_count; j++) {
3646 const struct VkVertexInputBindingDescription2EXT *b = &bindings[j];
3647 if (b->binding == attrs[i].binding) {
3648 binding = b;
3649 break;
3650 }
3651 }
3652 assert(binding);
3653 state->velem.velems[location].src_offset = attrs[i].offset;
3654 state->velem.velems[location].vertex_buffer_index = attrs[i].binding;
3655 state->velem.velems[location].src_format = lvp_vk_format_to_pipe_format(attrs[i].format);
3656 state->vb[attrs[i].binding].stride = binding->stride;
3657 uint32_t d = binding->divisor;
3658 switch (binding->inputRate) {
3659 case VK_VERTEX_INPUT_RATE_VERTEX:
3660 state->velem.velems[location].instance_divisor = 0;
3661 break;
3662 case VK_VERTEX_INPUT_RATE_INSTANCE:
3663 state->velem.velems[location].instance_divisor = d ? d : UINT32_MAX;
3664 break;
3665 default:
3666 assert(0);
3667 break;
3668 }
3669
3670 if ((int)location > max_location)
3671 max_location = location;
3672 }
3673 state->velem.count = max_location + 1;
3674 state->vb_dirty = true;
3675 state->ve_dirty = true;
3676 }
3677
handle_set_cull_mode(struct vk_cmd_queue_entry * cmd,struct rendering_state * state)3678 static void handle_set_cull_mode(struct vk_cmd_queue_entry *cmd,
3679 struct rendering_state *state)
3680 {
3681 state->rs_state.cull_face = vk_cull_to_pipe(cmd->u.set_cull_mode.cull_mode);
3682 state->rs_dirty = true;
3683 }
3684
handle_set_front_face(struct vk_cmd_queue_entry * cmd,struct rendering_state * state)3685 static void handle_set_front_face(struct vk_cmd_queue_entry *cmd,
3686 struct rendering_state *state)
3687 {
3688 state->rs_state.front_ccw = (cmd->u.set_front_face.front_face == VK_FRONT_FACE_COUNTER_CLOCKWISE);
3689 state->rs_dirty = true;
3690 }
3691
handle_set_primitive_topology(struct vk_cmd_queue_entry * cmd,struct rendering_state * state)3692 static void handle_set_primitive_topology(struct vk_cmd_queue_entry *cmd,
3693 struct rendering_state *state)
3694 {
3695 state->info.mode = vk_conv_topology(cmd->u.set_primitive_topology.primitive_topology);
3696 state->rs_dirty = true;
3697 }
3698
3699
handle_set_depth_test_enable(struct vk_cmd_queue_entry * cmd,struct rendering_state * state)3700 static void handle_set_depth_test_enable(struct vk_cmd_queue_entry *cmd,
3701 struct rendering_state *state)
3702 {
3703 state->dsa_dirty |= state->dsa_state.depth_enabled != cmd->u.set_depth_test_enable.depth_test_enable;
3704 state->dsa_state.depth_enabled = cmd->u.set_depth_test_enable.depth_test_enable;
3705 }
3706
handle_set_depth_write_enable(struct vk_cmd_queue_entry * cmd,struct rendering_state * state)3707 static void handle_set_depth_write_enable(struct vk_cmd_queue_entry *cmd,
3708 struct rendering_state *state)
3709 {
3710 state->dsa_dirty |= state->dsa_state.depth_writemask != cmd->u.set_depth_write_enable.depth_write_enable;
3711 state->dsa_state.depth_writemask = cmd->u.set_depth_write_enable.depth_write_enable;
3712 }
3713
handle_set_depth_compare_op(struct vk_cmd_queue_entry * cmd,struct rendering_state * state)3714 static void handle_set_depth_compare_op(struct vk_cmd_queue_entry *cmd,
3715 struct rendering_state *state)
3716 {
3717 state->dsa_dirty |= state->dsa_state.depth_func != cmd->u.set_depth_compare_op.depth_compare_op;
3718 state->dsa_state.depth_func = cmd->u.set_depth_compare_op.depth_compare_op;
3719 }
3720
handle_set_depth_bounds_test_enable(struct vk_cmd_queue_entry * cmd,struct rendering_state * state)3721 static void handle_set_depth_bounds_test_enable(struct vk_cmd_queue_entry *cmd,
3722 struct rendering_state *state)
3723 {
3724 state->dsa_dirty |= state->dsa_state.depth_bounds_test != cmd->u.set_depth_bounds_test_enable.depth_bounds_test_enable;
3725 state->dsa_state.depth_bounds_test = cmd->u.set_depth_bounds_test_enable.depth_bounds_test_enable;
3726 }
3727
handle_set_stencil_test_enable(struct vk_cmd_queue_entry * cmd,struct rendering_state * state)3728 static void handle_set_stencil_test_enable(struct vk_cmd_queue_entry *cmd,
3729 struct rendering_state *state)
3730 {
3731 state->dsa_dirty |= state->dsa_state.stencil[0].enabled != cmd->u.set_stencil_test_enable.stencil_test_enable ||
3732 state->dsa_state.stencil[1].enabled != cmd->u.set_stencil_test_enable.stencil_test_enable;
3733 state->dsa_state.stencil[0].enabled = cmd->u.set_stencil_test_enable.stencil_test_enable;
3734 state->dsa_state.stencil[1].enabled = cmd->u.set_stencil_test_enable.stencil_test_enable;
3735 }
3736
handle_set_stencil_op(struct vk_cmd_queue_entry * cmd,struct rendering_state * state)3737 static void handle_set_stencil_op(struct vk_cmd_queue_entry *cmd,
3738 struct rendering_state *state)
3739 {
3740 if (cmd->u.set_stencil_op.face_mask & VK_STENCIL_FACE_FRONT_BIT) {
3741 state->dsa_state.stencil[0].func = cmd->u.set_stencil_op.compare_op;
3742 state->dsa_state.stencil[0].fail_op = vk_conv_stencil_op(cmd->u.set_stencil_op.fail_op);
3743 state->dsa_state.stencil[0].zpass_op = vk_conv_stencil_op(cmd->u.set_stencil_op.pass_op);
3744 state->dsa_state.stencil[0].zfail_op = vk_conv_stencil_op(cmd->u.set_stencil_op.depth_fail_op);
3745 }
3746
3747 if (cmd->u.set_stencil_op.face_mask & VK_STENCIL_FACE_BACK_BIT) {
3748 state->dsa_state.stencil[1].func = cmd->u.set_stencil_op.compare_op;
3749 state->dsa_state.stencil[1].fail_op = vk_conv_stencil_op(cmd->u.set_stencil_op.fail_op);
3750 state->dsa_state.stencil[1].zpass_op = vk_conv_stencil_op(cmd->u.set_stencil_op.pass_op);
3751 state->dsa_state.stencil[1].zfail_op = vk_conv_stencil_op(cmd->u.set_stencil_op.depth_fail_op);
3752 }
3753 state->dsa_dirty = true;
3754 }
3755
handle_set_line_stipple(struct vk_cmd_queue_entry * cmd,struct rendering_state * state)3756 static void handle_set_line_stipple(struct vk_cmd_queue_entry *cmd,
3757 struct rendering_state *state)
3758 {
3759 state->rs_state.line_stipple_factor = cmd->u.set_line_stipple_ext.line_stipple_factor - 1;
3760 state->rs_state.line_stipple_pattern = cmd->u.set_line_stipple_ext.line_stipple_pattern;
3761 state->rs_dirty = true;
3762 }
3763
handle_set_depth_bias_enable(struct vk_cmd_queue_entry * cmd,struct rendering_state * state)3764 static void handle_set_depth_bias_enable(struct vk_cmd_queue_entry *cmd,
3765 struct rendering_state *state)
3766 {
3767 state->rs_dirty |= state->depth_bias.enabled != cmd->u.set_depth_bias_enable.depth_bias_enable;
3768 state->depth_bias.enabled = cmd->u.set_depth_bias_enable.depth_bias_enable;
3769 }
3770
handle_set_logic_op(struct vk_cmd_queue_entry * cmd,struct rendering_state * state)3771 static void handle_set_logic_op(struct vk_cmd_queue_entry *cmd,
3772 struct rendering_state *state)
3773 {
3774 unsigned op = vk_conv_logic_op(cmd->u.set_logic_op_ext.logic_op);
3775 state->rs_dirty |= state->blend_state.logicop_func != op;
3776 state->blend_state.logicop_func = op;
3777 }
3778
handle_set_patch_control_points(struct vk_cmd_queue_entry * cmd,struct rendering_state * state)3779 static void handle_set_patch_control_points(struct vk_cmd_queue_entry *cmd,
3780 struct rendering_state *state)
3781 {
3782 state->patch_vertices = cmd->u.set_patch_control_points_ext.patch_control_points;
3783 }
3784
handle_set_primitive_restart_enable(struct vk_cmd_queue_entry * cmd,struct rendering_state * state)3785 static void handle_set_primitive_restart_enable(struct vk_cmd_queue_entry *cmd,
3786 struct rendering_state *state)
3787 {
3788 state->info.primitive_restart = cmd->u.set_primitive_restart_enable.primitive_restart_enable;
3789 }
3790
handle_set_rasterizer_discard_enable(struct vk_cmd_queue_entry * cmd,struct rendering_state * state)3791 static void handle_set_rasterizer_discard_enable(struct vk_cmd_queue_entry *cmd,
3792 struct rendering_state *state)
3793 {
3794 state->rs_dirty |= state->rs_state.rasterizer_discard != cmd->u.set_rasterizer_discard_enable.rasterizer_discard_enable;
3795 state->rs_state.rasterizer_discard = cmd->u.set_rasterizer_discard_enable.rasterizer_discard_enable;
3796 }
3797
handle_set_color_write_enable(struct vk_cmd_queue_entry * cmd,struct rendering_state * state)3798 static void handle_set_color_write_enable(struct vk_cmd_queue_entry *cmd,
3799 struct rendering_state *state)
3800 {
3801 uint8_t disable_mask = 0; //PIPE_MAX_COLOR_BUFS is max attachment count
3802
3803 for (unsigned i = 0; i < cmd->u.set_color_write_enable_ext.attachment_count; i++) {
3804 /* this is inverted because cmdbufs are zero-initialized, meaning only 'true'
3805 * can be detected with a bool, and the default is to enable color writes
3806 */
3807 if (cmd->u.set_color_write_enable_ext.color_write_enables[i] != VK_TRUE)
3808 disable_mask |= BITFIELD_BIT(i);
3809 }
3810
3811 state->blend_dirty |= state->color_write_disables != disable_mask;
3812 state->color_write_disables = disable_mask;
3813 }
3814
lvp_add_enqueue_cmd_entrypoints(struct vk_device_dispatch_table * disp)3815 void lvp_add_enqueue_cmd_entrypoints(struct vk_device_dispatch_table *disp)
3816 {
3817 struct vk_device_dispatch_table cmd_enqueue_dispatch;
3818 vk_device_dispatch_table_from_entrypoints(&cmd_enqueue_dispatch,
3819 &vk_cmd_enqueue_device_entrypoints, true);
3820
3821 #define ENQUEUE_CMD(CmdName) \
3822 assert(cmd_enqueue_dispatch.CmdName != NULL); \
3823 disp->CmdName = cmd_enqueue_dispatch.CmdName;
3824
3825 /* This list needs to match what's in lvp_execute_cmd_buffer exactly */
3826 ENQUEUE_CMD(CmdBindPipeline)
3827 ENQUEUE_CMD(CmdSetViewport)
3828 ENQUEUE_CMD(CmdSetViewportWithCount)
3829 ENQUEUE_CMD(CmdSetScissor)
3830 ENQUEUE_CMD(CmdSetScissorWithCount)
3831 ENQUEUE_CMD(CmdSetLineWidth)
3832 ENQUEUE_CMD(CmdSetDepthBias)
3833 ENQUEUE_CMD(CmdSetBlendConstants)
3834 ENQUEUE_CMD(CmdSetDepthBounds)
3835 ENQUEUE_CMD(CmdSetStencilCompareMask)
3836 ENQUEUE_CMD(CmdSetStencilWriteMask)
3837 ENQUEUE_CMD(CmdSetStencilReference)
3838 ENQUEUE_CMD(CmdBindDescriptorSets)
3839 ENQUEUE_CMD(CmdBindIndexBuffer)
3840 ENQUEUE_CMD(CmdBindVertexBuffers2)
3841 ENQUEUE_CMD(CmdDraw)
3842 ENQUEUE_CMD(CmdDrawMultiEXT)
3843 ENQUEUE_CMD(CmdDrawIndexed)
3844 ENQUEUE_CMD(CmdDrawIndirect)
3845 ENQUEUE_CMD(CmdDrawIndexedIndirect)
3846 ENQUEUE_CMD(CmdDrawMultiIndexedEXT)
3847 ENQUEUE_CMD(CmdDispatch)
3848 ENQUEUE_CMD(CmdDispatchBase)
3849 ENQUEUE_CMD(CmdDispatchIndirect)
3850 ENQUEUE_CMD(CmdCopyBuffer2)
3851 ENQUEUE_CMD(CmdCopyImage2)
3852 ENQUEUE_CMD(CmdBlitImage2)
3853 ENQUEUE_CMD(CmdCopyBufferToImage2)
3854 ENQUEUE_CMD(CmdCopyImageToBuffer2)
3855 ENQUEUE_CMD(CmdUpdateBuffer)
3856 ENQUEUE_CMD(CmdFillBuffer)
3857 ENQUEUE_CMD(CmdClearColorImage)
3858 ENQUEUE_CMD(CmdClearDepthStencilImage)
3859 ENQUEUE_CMD(CmdClearAttachments)
3860 ENQUEUE_CMD(CmdResolveImage2)
3861 ENQUEUE_CMD(CmdBeginQueryIndexedEXT)
3862 ENQUEUE_CMD(CmdEndQueryIndexedEXT)
3863 ENQUEUE_CMD(CmdBeginQuery)
3864 ENQUEUE_CMD(CmdEndQuery)
3865 ENQUEUE_CMD(CmdResetQueryPool)
3866 ENQUEUE_CMD(CmdCopyQueryPoolResults)
3867 ENQUEUE_CMD(CmdPushConstants)
3868 ENQUEUE_CMD(CmdExecuteCommands)
3869 ENQUEUE_CMD(CmdDrawIndirectCount)
3870 ENQUEUE_CMD(CmdDrawIndexedIndirectCount)
3871 ENQUEUE_CMD(CmdPushDescriptorSetKHR)
3872 // ENQUEUE_CMD(CmdPushDescriptorSetWithTemplateKHR)
3873 ENQUEUE_CMD(CmdBindTransformFeedbackBuffersEXT)
3874 ENQUEUE_CMD(CmdBeginTransformFeedbackEXT)
3875 ENQUEUE_CMD(CmdEndTransformFeedbackEXT)
3876 ENQUEUE_CMD(CmdDrawIndirectByteCountEXT)
3877 ENQUEUE_CMD(CmdBeginConditionalRenderingEXT)
3878 ENQUEUE_CMD(CmdEndConditionalRenderingEXT)
3879 ENQUEUE_CMD(CmdSetVertexInputEXT)
3880 ENQUEUE_CMD(CmdSetCullMode)
3881 ENQUEUE_CMD(CmdSetFrontFace)
3882 ENQUEUE_CMD(CmdSetPrimitiveTopology)
3883 ENQUEUE_CMD(CmdSetDepthTestEnable)
3884 ENQUEUE_CMD(CmdSetDepthWriteEnable)
3885 ENQUEUE_CMD(CmdSetDepthCompareOp)
3886 ENQUEUE_CMD(CmdSetDepthBoundsTestEnable)
3887 ENQUEUE_CMD(CmdSetStencilTestEnable)
3888 ENQUEUE_CMD(CmdSetStencilOp)
3889 ENQUEUE_CMD(CmdSetLineStippleEXT)
3890 ENQUEUE_CMD(CmdSetDepthBiasEnable)
3891 ENQUEUE_CMD(CmdSetLogicOpEXT)
3892 ENQUEUE_CMD(CmdSetPatchControlPointsEXT)
3893 ENQUEUE_CMD(CmdSetPrimitiveRestartEnable)
3894 ENQUEUE_CMD(CmdSetRasterizerDiscardEnable)
3895 ENQUEUE_CMD(CmdSetColorWriteEnableEXT)
3896 ENQUEUE_CMD(CmdBeginRendering)
3897 ENQUEUE_CMD(CmdEndRendering)
3898 ENQUEUE_CMD(CmdSetDeviceMask)
3899 ENQUEUE_CMD(CmdPipelineBarrier2)
3900 ENQUEUE_CMD(CmdResetEvent2)
3901 ENQUEUE_CMD(CmdSetEvent2)
3902 ENQUEUE_CMD(CmdWaitEvents2)
3903 ENQUEUE_CMD(CmdWriteTimestamp2)
3904
3905 #undef ENQUEUE_CMD
3906 }
3907
lvp_execute_cmd_buffer(struct lvp_cmd_buffer * cmd_buffer,struct rendering_state * state)3908 static void lvp_execute_cmd_buffer(struct lvp_cmd_buffer *cmd_buffer,
3909 struct rendering_state *state)
3910 {
3911 struct vk_cmd_queue_entry *cmd;
3912 bool first = true;
3913 bool did_flush = false;
3914
3915 LIST_FOR_EACH_ENTRY(cmd, &cmd_buffer->vk.cmd_queue.cmds, cmd_link) {
3916 switch (cmd->type) {
3917 case VK_CMD_BIND_PIPELINE:
3918 handle_pipeline(cmd, state);
3919 break;
3920 case VK_CMD_SET_VIEWPORT:
3921 handle_set_viewport(cmd, state);
3922 break;
3923 case VK_CMD_SET_VIEWPORT_WITH_COUNT:
3924 handle_set_viewport_with_count(cmd, state);
3925 break;
3926 case VK_CMD_SET_SCISSOR:
3927 handle_set_scissor(cmd, state);
3928 break;
3929 case VK_CMD_SET_SCISSOR_WITH_COUNT:
3930 handle_set_scissor_with_count(cmd, state);
3931 break;
3932 case VK_CMD_SET_LINE_WIDTH:
3933 handle_set_line_width(cmd, state);
3934 break;
3935 case VK_CMD_SET_DEPTH_BIAS:
3936 handle_set_depth_bias(cmd, state);
3937 break;
3938 case VK_CMD_SET_BLEND_CONSTANTS:
3939 handle_set_blend_constants(cmd, state);
3940 break;
3941 case VK_CMD_SET_DEPTH_BOUNDS:
3942 handle_set_depth_bounds(cmd, state);
3943 break;
3944 case VK_CMD_SET_STENCIL_COMPARE_MASK:
3945 handle_set_stencil_compare_mask(cmd, state);
3946 break;
3947 case VK_CMD_SET_STENCIL_WRITE_MASK:
3948 handle_set_stencil_write_mask(cmd, state);
3949 break;
3950 case VK_CMD_SET_STENCIL_REFERENCE:
3951 handle_set_stencil_reference(cmd, state);
3952 break;
3953 case VK_CMD_BIND_DESCRIPTOR_SETS:
3954 handle_descriptor_sets(cmd, state);
3955 break;
3956 case VK_CMD_BIND_INDEX_BUFFER:
3957 handle_index_buffer(cmd, state);
3958 break;
3959 case VK_CMD_BIND_VERTEX_BUFFERS2:
3960 handle_vertex_buffers2(cmd, state);
3961 break;
3962 case VK_CMD_DRAW:
3963 emit_state(state);
3964 handle_draw(cmd, state);
3965 break;
3966 case VK_CMD_DRAW_MULTI_EXT:
3967 emit_state(state);
3968 handle_draw_multi(cmd, state);
3969 break;
3970 case VK_CMD_DRAW_INDEXED:
3971 emit_state(state);
3972 handle_draw_indexed(cmd, state);
3973 break;
3974 case VK_CMD_DRAW_INDIRECT:
3975 emit_state(state);
3976 handle_draw_indirect(cmd, state, false);
3977 break;
3978 case VK_CMD_DRAW_INDEXED_INDIRECT:
3979 emit_state(state);
3980 handle_draw_indirect(cmd, state, true);
3981 break;
3982 case VK_CMD_DRAW_MULTI_INDEXED_EXT:
3983 emit_state(state);
3984 handle_draw_multi_indexed(cmd, state);
3985 break;
3986 case VK_CMD_DISPATCH:
3987 emit_compute_state(state);
3988 handle_dispatch(cmd, state);
3989 break;
3990 case VK_CMD_DISPATCH_BASE:
3991 emit_compute_state(state);
3992 handle_dispatch_base(cmd, state);
3993 break;
3994 case VK_CMD_DISPATCH_INDIRECT:
3995 emit_compute_state(state);
3996 handle_dispatch_indirect(cmd, state);
3997 break;
3998 case VK_CMD_COPY_BUFFER2:
3999 handle_copy_buffer(cmd, state);
4000 break;
4001 case VK_CMD_COPY_IMAGE2:
4002 handle_copy_image(cmd, state);
4003 break;
4004 case VK_CMD_BLIT_IMAGE2:
4005 handle_blit_image(cmd, state);
4006 break;
4007 case VK_CMD_COPY_BUFFER_TO_IMAGE2:
4008 handle_copy_buffer_to_image(cmd, state);
4009 break;
4010 case VK_CMD_COPY_IMAGE_TO_BUFFER2:
4011 handle_copy_image_to_buffer2(cmd, state);
4012 break;
4013 case VK_CMD_UPDATE_BUFFER:
4014 handle_update_buffer(cmd, state);
4015 break;
4016 case VK_CMD_FILL_BUFFER:
4017 handle_fill_buffer(cmd, state);
4018 break;
4019 case VK_CMD_CLEAR_COLOR_IMAGE:
4020 handle_clear_color_image(cmd, state);
4021 break;
4022 case VK_CMD_CLEAR_DEPTH_STENCIL_IMAGE:
4023 handle_clear_ds_image(cmd, state);
4024 break;
4025 case VK_CMD_CLEAR_ATTACHMENTS:
4026 handle_clear_attachments(cmd, state);
4027 break;
4028 case VK_CMD_RESOLVE_IMAGE2:
4029 handle_resolve_image(cmd, state);
4030 break;
4031 case VK_CMD_PIPELINE_BARRIER2:
4032 /* skip flushes since every cmdbuf does a flush
4033 after iterating its cmds and so this is redundant
4034 */
4035 if (first || did_flush || cmd->cmd_link.next == &cmd_buffer->vk.cmd_queue.cmds)
4036 continue;
4037 handle_pipeline_barrier(cmd, state);
4038 did_flush = true;
4039 continue;
4040 case VK_CMD_BEGIN_QUERY_INDEXED_EXT:
4041 handle_begin_query_indexed_ext(cmd, state);
4042 break;
4043 case VK_CMD_END_QUERY_INDEXED_EXT:
4044 handle_end_query_indexed_ext(cmd, state);
4045 break;
4046 case VK_CMD_BEGIN_QUERY:
4047 handle_begin_query(cmd, state);
4048 break;
4049 case VK_CMD_END_QUERY:
4050 handle_end_query(cmd, state);
4051 break;
4052 case VK_CMD_RESET_QUERY_POOL:
4053 handle_reset_query_pool(cmd, state);
4054 break;
4055 case VK_CMD_COPY_QUERY_POOL_RESULTS:
4056 handle_copy_query_pool_results(cmd, state);
4057 break;
4058 case VK_CMD_PUSH_CONSTANTS:
4059 handle_push_constants(cmd, state);
4060 break;
4061 case VK_CMD_EXECUTE_COMMANDS:
4062 handle_execute_commands(cmd, state);
4063 break;
4064 case VK_CMD_DRAW_INDIRECT_COUNT:
4065 emit_state(state);
4066 handle_draw_indirect_count(cmd, state, false);
4067 break;
4068 case VK_CMD_DRAW_INDEXED_INDIRECT_COUNT:
4069 emit_state(state);
4070 handle_draw_indirect_count(cmd, state, true);
4071 break;
4072 case VK_CMD_PUSH_DESCRIPTOR_SET_KHR:
4073 handle_push_descriptor_set(cmd, state);
4074 break;
4075 case VK_CMD_PUSH_DESCRIPTOR_SET_WITH_TEMPLATE_KHR:
4076 handle_push_descriptor_set_with_template(cmd, state);
4077 break;
4078 case VK_CMD_BIND_TRANSFORM_FEEDBACK_BUFFERS_EXT:
4079 handle_bind_transform_feedback_buffers(cmd, state);
4080 break;
4081 case VK_CMD_BEGIN_TRANSFORM_FEEDBACK_EXT:
4082 handle_begin_transform_feedback(cmd, state);
4083 break;
4084 case VK_CMD_END_TRANSFORM_FEEDBACK_EXT:
4085 handle_end_transform_feedback(cmd, state);
4086 break;
4087 case VK_CMD_DRAW_INDIRECT_BYTE_COUNT_EXT:
4088 emit_state(state);
4089 handle_draw_indirect_byte_count(cmd, state);
4090 break;
4091 case VK_CMD_BEGIN_CONDITIONAL_RENDERING_EXT:
4092 handle_begin_conditional_rendering(cmd, state);
4093 break;
4094 case VK_CMD_END_CONDITIONAL_RENDERING_EXT:
4095 handle_end_conditional_rendering(state);
4096 break;
4097 case VK_CMD_SET_VERTEX_INPUT_EXT:
4098 handle_set_vertex_input(cmd, state);
4099 break;
4100 case VK_CMD_SET_CULL_MODE:
4101 handle_set_cull_mode(cmd, state);
4102 break;
4103 case VK_CMD_SET_FRONT_FACE:
4104 handle_set_front_face(cmd, state);
4105 break;
4106 case VK_CMD_SET_PRIMITIVE_TOPOLOGY:
4107 handle_set_primitive_topology(cmd, state);
4108 break;
4109 case VK_CMD_SET_DEPTH_TEST_ENABLE:
4110 handle_set_depth_test_enable(cmd, state);
4111 break;
4112 case VK_CMD_SET_DEPTH_WRITE_ENABLE:
4113 handle_set_depth_write_enable(cmd, state);
4114 break;
4115 case VK_CMD_SET_DEPTH_COMPARE_OP:
4116 handle_set_depth_compare_op(cmd, state);
4117 break;
4118 case VK_CMD_SET_DEPTH_BOUNDS_TEST_ENABLE:
4119 handle_set_depth_bounds_test_enable(cmd, state);
4120 break;
4121 case VK_CMD_SET_STENCIL_TEST_ENABLE:
4122 handle_set_stencil_test_enable(cmd, state);
4123 break;
4124 case VK_CMD_SET_STENCIL_OP:
4125 handle_set_stencil_op(cmd, state);
4126 break;
4127 case VK_CMD_SET_LINE_STIPPLE_EXT:
4128 handle_set_line_stipple(cmd, state);
4129 break;
4130 case VK_CMD_SET_DEPTH_BIAS_ENABLE:
4131 handle_set_depth_bias_enable(cmd, state);
4132 break;
4133 case VK_CMD_SET_LOGIC_OP_EXT:
4134 handle_set_logic_op(cmd, state);
4135 break;
4136 case VK_CMD_SET_PATCH_CONTROL_POINTS_EXT:
4137 handle_set_patch_control_points(cmd, state);
4138 break;
4139 case VK_CMD_SET_PRIMITIVE_RESTART_ENABLE:
4140 handle_set_primitive_restart_enable(cmd, state);
4141 break;
4142 case VK_CMD_SET_RASTERIZER_DISCARD_ENABLE:
4143 handle_set_rasterizer_discard_enable(cmd, state);
4144 break;
4145 case VK_CMD_SET_COLOR_WRITE_ENABLE_EXT:
4146 handle_set_color_write_enable(cmd, state);
4147 break;
4148 case VK_CMD_BEGIN_RENDERING:
4149 handle_begin_rendering(cmd, state);
4150 break;
4151 case VK_CMD_END_RENDERING:
4152 handle_end_rendering(cmd, state);
4153 break;
4154 case VK_CMD_SET_DEVICE_MASK:
4155 /* no-op */
4156 break;
4157 case VK_CMD_RESET_EVENT2:
4158 handle_event_reset2(cmd, state);
4159 break;
4160 case VK_CMD_SET_EVENT2:
4161 handle_event_set2(cmd, state);
4162 break;
4163 case VK_CMD_WAIT_EVENTS2:
4164 handle_wait_events2(cmd, state);
4165 break;
4166 case VK_CMD_WRITE_TIMESTAMP2:
4167 handle_write_timestamp2(cmd, state);
4168 break;
4169 default:
4170 fprintf(stderr, "Unsupported command %s\n", vk_cmd_queue_type_names[cmd->type]);
4171 unreachable("Unsupported command");
4172 break;
4173 }
4174 first = false;
4175 did_flush = false;
4176 }
4177 }
4178
lvp_execute_cmds(struct lvp_device * device,struct lvp_queue * queue,struct lvp_cmd_buffer * cmd_buffer)4179 VkResult lvp_execute_cmds(struct lvp_device *device,
4180 struct lvp_queue *queue,
4181 struct lvp_cmd_buffer *cmd_buffer)
4182 {
4183 struct rendering_state *state = queue->state;
4184 memset(state, 0, sizeof(*state));
4185 state->pctx = queue->ctx;
4186 state->uploader = queue->uploader;
4187 state->cso = queue->cso;
4188 state->blend_dirty = true;
4189 state->dsa_dirty = true;
4190 state->rs_dirty = true;
4191 state->vp_dirty = true;
4192 state->rs_state.point_tri_clip = true;
4193 state->rs_state.unclamped_fragment_depth_values = device->vk.enabled_extensions.EXT_depth_range_unrestricted;
4194 for (enum pipe_shader_type s = PIPE_SHADER_VERTEX; s < PIPE_SHADER_TYPES; s++) {
4195 for (unsigned i = 0; i < ARRAY_SIZE(state->cso_ss_ptr[s]); i++)
4196 state->cso_ss_ptr[s][i] = &state->ss[s][i];
4197 }
4198 /* create a gallium context */
4199 lvp_execute_cmd_buffer(cmd_buffer, state);
4200
4201 state->start_vb = -1;
4202 state->num_vb = 0;
4203 cso_unbind_context(queue->cso);
4204 for (unsigned i = 0; i < ARRAY_SIZE(state->so_targets); i++) {
4205 if (state->so_targets[i]) {
4206 state->pctx->stream_output_target_destroy(state->pctx, state->so_targets[i]);
4207 }
4208 }
4209
4210 for (enum pipe_shader_type s = PIPE_SHADER_VERTEX; s < PIPE_SHADER_TYPES; s++) {
4211 for (unsigned i = 0; i < ARRAY_SIZE(state->sv[s]); i++) {
4212 if (state->sv[s][i])
4213 pipe_sampler_view_reference(&state->sv[s][i], NULL);
4214 }
4215 }
4216
4217 for (unsigned i = 0;
4218 i < ARRAY_SIZE(state->cso_ss_ptr[PIPE_SHADER_COMPUTE]); i++) {
4219 if (state->cso_ss_ptr[PIPE_SHADER_COMPUTE][i])
4220 state->pctx->delete_sampler_state(state->pctx, state->ss_cso[PIPE_SHADER_COMPUTE][i]);
4221 }
4222
4223 free(state->color_att);
4224 return VK_SUCCESS;
4225 }
4226
4227 size_t
lvp_get_rendering_state_size(void)4228 lvp_get_rendering_state_size(void)
4229 {
4230 return sizeof(struct rendering_state);
4231 }
4232