1 /*
2 * Copyright © 2009 Corbin Simpson
3 * Copyright © 2011 Marek Olšák <maraeo@gmail.com>
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining
7 * a copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
15 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
16 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
17 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
18 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * The above copyright notice and this permission notice (including the
24 * next paragraph) shall be included in all copies or substantial portions
25 * of the Software.
26 */
27
28 #include "radeon_drm_bo.h"
29 #include "radeon_drm_cs.h"
30
31 #include "util/os_file.h"
32 #include "util/u_cpu_detect.h"
33 #include "util/u_memory.h"
34 #include "util/u_hash_table.h"
35 #include "util/u_pointer.h"
36
37 #include <xf86drm.h>
38 #include <stdio.h>
39 #include <sys/types.h>
40 #include <sys/stat.h>
41 #include <unistd.h>
42 #include <fcntl.h>
43 #include <radeon_surface.h>
44
45 static struct hash_table *fd_tab = NULL;
46 static mtx_t fd_tab_mutex = _MTX_INITIALIZER_NP;
47
48 /* Enable/disable feature access for one command stream.
49 * If enable == true, return true on success.
50 * Otherwise, return false.
51 *
52 * We basically do the same thing kernel does, because we have to deal
53 * with multiple contexts (here command streams) backed by one winsys. */
radeon_set_fd_access(struct radeon_drm_cs * applier,struct radeon_drm_cs ** owner,mtx_t * mutex,unsigned request,const char * request_name,bool enable)54 static bool radeon_set_fd_access(struct radeon_drm_cs *applier,
55 struct radeon_drm_cs **owner,
56 mtx_t *mutex,
57 unsigned request, const char *request_name,
58 bool enable)
59 {
60 struct drm_radeon_info info;
61 unsigned value = enable ? 1 : 0;
62
63 memset(&info, 0, sizeof(info));
64
65 mtx_lock(&*mutex);
66
67 /* Early exit if we are sure the request will fail. */
68 if (enable) {
69 if (*owner) {
70 mtx_unlock(&*mutex);
71 return false;
72 }
73 } else {
74 if (*owner != applier) {
75 mtx_unlock(&*mutex);
76 return false;
77 }
78 }
79
80 /* Pass through the request to the kernel. */
81 info.value = (unsigned long)&value;
82 info.request = request;
83 if (drmCommandWriteRead(applier->ws->fd, DRM_RADEON_INFO,
84 &info, sizeof(info)) != 0) {
85 mtx_unlock(&*mutex);
86 return false;
87 }
88
89 /* Update the rights in the winsys. */
90 if (enable) {
91 if (value) {
92 *owner = applier;
93 mtx_unlock(&*mutex);
94 return true;
95 }
96 } else {
97 *owner = NULL;
98 }
99
100 mtx_unlock(&*mutex);
101 return false;
102 }
103
radeon_get_drm_value(int fd,unsigned request,const char * errname,uint32_t * out)104 static bool radeon_get_drm_value(int fd, unsigned request,
105 const char *errname, uint32_t *out)
106 {
107 struct drm_radeon_info info;
108 int retval;
109
110 memset(&info, 0, sizeof(info));
111
112 info.value = (unsigned long)out;
113 info.request = request;
114
115 retval = drmCommandWriteRead(fd, DRM_RADEON_INFO, &info, sizeof(info));
116 if (retval) {
117 if (errname) {
118 fprintf(stderr, "radeon: Failed to get %s, error number %d\n",
119 errname, retval);
120 }
121 return false;
122 }
123 return true;
124 }
125
126 /* Helper function to do the ioctls needed for setup and init. */
do_winsys_init(struct radeon_drm_winsys * ws)127 static bool do_winsys_init(struct radeon_drm_winsys *ws)
128 {
129 struct drm_radeon_gem_info gem_info;
130 int retval;
131 drmVersionPtr version;
132
133 memset(&gem_info, 0, sizeof(gem_info));
134
135 /* We do things in a specific order here.
136 *
137 * DRM version first. We need to be sure we're running on a KMS chipset.
138 * This is also for some features.
139 *
140 * Then, the PCI ID. This is essential and should return usable numbers
141 * for all Radeons. If this fails, we probably got handed an FD for some
142 * non-Radeon card.
143 *
144 * The GEM info is actually bogus on the kernel side, as well as our side
145 * (see radeon_gem_info_ioctl in radeon_gem.c) but that's alright because
146 * we don't actually use the info for anything yet.
147 *
148 * The GB and Z pipe requests should always succeed, but they might not
149 * return sensical values for all chipsets, but that's alright because
150 * the pipe drivers already know that.
151 */
152
153 /* Get DRM version. */
154 version = drmGetVersion(ws->fd);
155 if (version->version_major != 2 ||
156 version->version_minor < 50) {
157 fprintf(stderr, "%s: DRM version is %d.%d.%d but this driver is "
158 "only compatible with 2.50.0 (kernel 4.12) or later.\n",
159 __FUNCTION__,
160 version->version_major,
161 version->version_minor,
162 version->version_patchlevel);
163 drmFreeVersion(version);
164 return false;
165 }
166
167 ws->info.drm_major = version->version_major;
168 ws->info.drm_minor = version->version_minor;
169 ws->info.drm_patchlevel = version->version_patchlevel;
170 ws->info.is_amdgpu = false;
171 drmFreeVersion(version);
172
173 /* Get PCI ID. */
174 if (!radeon_get_drm_value(ws->fd, RADEON_INFO_DEVICE_ID, "PCI ID",
175 &ws->info.pci_id))
176 return false;
177
178 /* Check PCI ID. */
179 switch (ws->info.pci_id) {
180 #define CHIPSET(pci_id, name, cfamily) case pci_id: ws->info.family = CHIP_##cfamily; ws->gen = DRV_R300; break;
181 #include "pci_ids/r300_pci_ids.h"
182 #undef CHIPSET
183
184 #define CHIPSET(pci_id, name, cfamily) case pci_id: ws->info.family = CHIP_##cfamily; ws->gen = DRV_R600; break;
185 #include "pci_ids/r600_pci_ids.h"
186 #undef CHIPSET
187
188 #define CHIPSET(pci_id, cfamily) \
189 case pci_id: \
190 ws->info.family = CHIP_##cfamily; \
191 ws->info.name = #cfamily; \
192 ws->gen = DRV_SI; \
193 break;
194 #include "pci_ids/radeonsi_pci_ids.h"
195 #undef CHIPSET
196
197 default:
198 fprintf(stderr, "radeon: Invalid PCI ID.\n");
199 return false;
200 }
201
202 switch (ws->info.family) {
203 default:
204 case CHIP_UNKNOWN:
205 fprintf(stderr, "radeon: Unknown family.\n");
206 return false;
207 case CHIP_R300:
208 case CHIP_R350:
209 case CHIP_RV350:
210 case CHIP_RV370:
211 case CHIP_RV380:
212 case CHIP_RS400:
213 case CHIP_RC410:
214 case CHIP_RS480:
215 ws->info.gfx_level = R300;
216 break;
217 case CHIP_R420: /* R4xx-based cores. */
218 case CHIP_R423:
219 case CHIP_R430:
220 case CHIP_R480:
221 case CHIP_R481:
222 case CHIP_RV410:
223 case CHIP_RS600:
224 case CHIP_RS690:
225 case CHIP_RS740:
226 ws->info.gfx_level = R400;
227 break;
228 case CHIP_RV515: /* R5xx-based cores. */
229 case CHIP_R520:
230 case CHIP_RV530:
231 case CHIP_R580:
232 case CHIP_RV560:
233 case CHIP_RV570:
234 ws->info.gfx_level = R500;
235 break;
236 case CHIP_R600:
237 case CHIP_RV610:
238 case CHIP_RV630:
239 case CHIP_RV670:
240 case CHIP_RV620:
241 case CHIP_RV635:
242 case CHIP_RS780:
243 case CHIP_RS880:
244 ws->info.gfx_level = R600;
245 break;
246 case CHIP_RV770:
247 case CHIP_RV730:
248 case CHIP_RV710:
249 case CHIP_RV740:
250 ws->info.gfx_level = R700;
251 break;
252 case CHIP_CEDAR:
253 case CHIP_REDWOOD:
254 case CHIP_JUNIPER:
255 case CHIP_CYPRESS:
256 case CHIP_HEMLOCK:
257 case CHIP_PALM:
258 case CHIP_SUMO:
259 case CHIP_SUMO2:
260 case CHIP_BARTS:
261 case CHIP_TURKS:
262 case CHIP_CAICOS:
263 ws->info.gfx_level = EVERGREEN;
264 break;
265 case CHIP_CAYMAN:
266 case CHIP_ARUBA:
267 ws->info.gfx_level = CAYMAN;
268 break;
269 case CHIP_TAHITI:
270 case CHIP_PITCAIRN:
271 case CHIP_VERDE:
272 case CHIP_OLAND:
273 case CHIP_HAINAN:
274 ws->info.gfx_level = GFX6;
275 break;
276 case CHIP_BONAIRE:
277 case CHIP_KAVERI:
278 case CHIP_KABINI:
279 case CHIP_HAWAII:
280 ws->info.gfx_level = GFX7;
281 break;
282 }
283
284 /* Set which chips don't have dedicated VRAM. */
285 switch (ws->info.family) {
286 case CHIP_RS400:
287 case CHIP_RC410:
288 case CHIP_RS480:
289 case CHIP_RS600:
290 case CHIP_RS690:
291 case CHIP_RS740:
292 case CHIP_RS780:
293 case CHIP_RS880:
294 case CHIP_PALM:
295 case CHIP_SUMO:
296 case CHIP_SUMO2:
297 case CHIP_ARUBA:
298 case CHIP_KAVERI:
299 case CHIP_KABINI:
300 ws->info.has_dedicated_vram = false;
301 break;
302
303 default:
304 ws->info.has_dedicated_vram = true;
305 }
306
307 ws->info.ip[AMD_IP_GFX].num_queues = 1;
308 /* Check for dma */
309 ws->info.ip[AMD_IP_SDMA].num_queues = 0;
310 /* DMA is disabled on R700. There is IB corruption and hangs. */
311 if (ws->info.gfx_level >= EVERGREEN) {
312 ws->info.ip[AMD_IP_SDMA].num_queues = 1;
313 }
314
315 /* Check for UVD and VCE */
316 ws->info.vce_fw_version = 0x00000000;
317
318 uint32_t value = RADEON_CS_RING_UVD;
319 if (radeon_get_drm_value(ws->fd, RADEON_INFO_RING_WORKING,
320 "UVD Ring working", &value)) {
321 ws->info.ip[AMD_IP_UVD].num_queues = 1;
322 }
323
324 value = RADEON_CS_RING_VCE;
325 if (radeon_get_drm_value(ws->fd, RADEON_INFO_RING_WORKING,
326 NULL, &value) && value) {
327
328 if (radeon_get_drm_value(ws->fd, RADEON_INFO_VCE_FW_VERSION,
329 "VCE FW version", &value)) {
330 ws->info.vce_fw_version = value;
331 ws->info.ip[AMD_IP_VCE].num_queues = 1;
332 }
333 }
334
335 /* Check for userptr support. */
336 {
337 struct drm_radeon_gem_userptr args = {0};
338
339 /* If the ioctl doesn't exist, -EINVAL is returned.
340 *
341 * If the ioctl exists, it should return -EACCES
342 * if RADEON_GEM_USERPTR_READONLY or RADEON_GEM_USERPTR_REGISTER
343 * aren't set.
344 */
345 ws->info.has_userptr =
346 drmCommandWriteRead(ws->fd, DRM_RADEON_GEM_USERPTR,
347 &args, sizeof(args)) == -EACCES;
348 }
349
350 /* Get GEM info. */
351 retval = drmCommandWriteRead(ws->fd, DRM_RADEON_GEM_INFO,
352 &gem_info, sizeof(gem_info));
353 if (retval) {
354 fprintf(stderr, "radeon: Failed to get MM info, error number %d\n",
355 retval);
356 return false;
357 }
358 ws->info.gart_size_kb = DIV_ROUND_UP(gem_info.gart_size, 1024);
359 ws->info.vram_size_kb = DIV_ROUND_UP(gem_info.vram_size, 1024);
360 ws->info.vram_vis_size_kb = DIV_ROUND_UP(gem_info.vram_visible, 1024);
361
362 /* Radeon allocates all buffers contiguously, which makes large allocations
363 * unlikely to succeed. */
364 if (ws->info.has_dedicated_vram)
365 ws->info.max_heap_size_kb = ws->info.vram_size_kb;
366 else
367 ws->info.max_heap_size_kb = ws->info.gart_size_kb;
368
369 /* Both 32-bit and 64-bit address spaces only have 4GB.
370 * This is a limitation of the VM allocator in the winsys.
371 */
372 ws->info.max_heap_size_kb = MIN2(ws->info.max_heap_size_kb, 4 * 1024 * 1024); /* 4 GB */
373
374 /* Get max clock frequency info and convert it to MHz */
375 radeon_get_drm_value(ws->fd, RADEON_INFO_MAX_SCLK, NULL,
376 &ws->info.max_gpu_freq_mhz);
377 ws->info.max_gpu_freq_mhz /= 1000;
378
379 ws->num_cpus = sysconf(_SC_NPROCESSORS_ONLN);
380
381 /* Generation-specific queries. */
382 if (ws->gen == DRV_R300) {
383 if (!radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_GB_PIPES,
384 "GB pipe count",
385 &ws->info.r300_num_gb_pipes))
386 return false;
387
388 if (!radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_Z_PIPES,
389 "Z pipe count",
390 &ws->info.r300_num_z_pipes))
391 return false;
392 }
393 else if (ws->gen >= DRV_R600) {
394 uint32_t tiling_config = 0;
395
396 if (!radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_BACKENDS,
397 "num backends",
398 &ws->info.max_render_backends))
399 return false;
400
401 /* get the GPU counter frequency, failure is not fatal */
402 radeon_get_drm_value(ws->fd, RADEON_INFO_CLOCK_CRYSTAL_FREQ, NULL,
403 &ws->info.clock_crystal_freq);
404
405 radeon_get_drm_value(ws->fd, RADEON_INFO_TILING_CONFIG, NULL,
406 &tiling_config);
407
408 ws->info.r600_num_banks =
409 ws->info.gfx_level >= EVERGREEN ?
410 4 << ((tiling_config & 0xf0) >> 4) :
411 4 << ((tiling_config & 0x30) >> 4);
412
413 ws->info.pipe_interleave_bytes =
414 ws->info.gfx_level >= EVERGREEN ?
415 256 << ((tiling_config & 0xf00) >> 8) :
416 256 << ((tiling_config & 0xc0) >> 6);
417
418 if (!ws->info.pipe_interleave_bytes)
419 ws->info.pipe_interleave_bytes =
420 ws->info.gfx_level >= EVERGREEN ? 512 : 256;
421
422 radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_TILE_PIPES, NULL,
423 &ws->info.num_tile_pipes);
424
425 /* "num_tiles_pipes" must be equal to the number of pipes (Px) in the
426 * pipe config field of the GB_TILE_MODE array. Only one card (Tahiti)
427 * reports a different value (12). Fix it by setting what's in the
428 * GB_TILE_MODE array (8).
429 */
430 if (ws->gen == DRV_SI && ws->info.num_tile_pipes == 12)
431 ws->info.num_tile_pipes = 8;
432
433 if (radeon_get_drm_value(ws->fd, RADEON_INFO_BACKEND_MAP, NULL,
434 &ws->info.r600_gb_backend_map))
435 ws->info.r600_gb_backend_map_valid = true;
436
437 /* Default value. */
438 ws->info.enabled_rb_mask = u_bit_consecutive(0, ws->info.max_render_backends);
439 /*
440 * This fails (silently) on non-GCN or older kernels, overwriting the
441 * default enabled_rb_mask with the result of the last query.
442 */
443 if (ws->gen >= DRV_SI)
444 radeon_get_drm_value(ws->fd, RADEON_INFO_SI_BACKEND_ENABLED_MASK, NULL,
445 &ws->info.enabled_rb_mask);
446
447 ws->info.r600_has_virtual_memory = false;
448
449 uint32_t ib_vm_max_size;
450
451 ws->info.r600_has_virtual_memory = true;
452 if (!radeon_get_drm_value(ws->fd, RADEON_INFO_VA_START, NULL,
453 &ws->va_start))
454 ws->info.r600_has_virtual_memory = false;
455 if (!radeon_get_drm_value(ws->fd, RADEON_INFO_IB_VM_MAX_SIZE, NULL,
456 &ib_vm_max_size))
457 ws->info.r600_has_virtual_memory = false;
458 radeon_get_drm_value(ws->fd, RADEON_INFO_VA_UNMAP_WORKING, NULL,
459 &ws->va_unmap_working);
460
461 if (ws->gen == DRV_R600 && !debug_get_bool_option("RADEON_VA", false))
462 ws->info.r600_has_virtual_memory = false;
463 }
464
465 /* Get max pipes, this is only needed for compute shaders. All evergreen+
466 * chips have at least 2 pipes, so we use 2 as a default. */
467 ws->info.r600_max_quad_pipes = 2;
468 radeon_get_drm_value(ws->fd, RADEON_INFO_MAX_PIPES, NULL,
469 &ws->info.r600_max_quad_pipes);
470
471 /* All GPUs have at least one compute unit */
472 ws->info.num_cu = 1;
473 radeon_get_drm_value(ws->fd, RADEON_INFO_ACTIVE_CU_COUNT, NULL,
474 &ws->info.num_cu);
475
476 radeon_get_drm_value(ws->fd, RADEON_INFO_MAX_SE, NULL,
477 &ws->info.max_se);
478
479 switch (ws->info.family) {
480 case CHIP_HAINAN:
481 case CHIP_KABINI:
482 ws->info.max_tcc_blocks = 2;
483 break;
484 case CHIP_VERDE:
485 case CHIP_OLAND:
486 case CHIP_BONAIRE:
487 case CHIP_KAVERI:
488 ws->info.max_tcc_blocks = 4;
489 break;
490 case CHIP_PITCAIRN:
491 ws->info.max_tcc_blocks = 8;
492 break;
493 case CHIP_TAHITI:
494 ws->info.max_tcc_blocks = 12;
495 break;
496 case CHIP_HAWAII:
497 ws->info.max_tcc_blocks = 16;
498 break;
499 default:
500 ws->info.max_tcc_blocks = 0;
501 break;
502 }
503
504 if (!ws->info.max_se) {
505 switch (ws->info.family) {
506 default:
507 ws->info.max_se = 1;
508 break;
509 case CHIP_CYPRESS:
510 case CHIP_HEMLOCK:
511 case CHIP_BARTS:
512 case CHIP_CAYMAN:
513 case CHIP_TAHITI:
514 case CHIP_PITCAIRN:
515 case CHIP_BONAIRE:
516 ws->info.max_se = 2;
517 break;
518 case CHIP_HAWAII:
519 ws->info.max_se = 4;
520 break;
521 }
522 }
523
524 ws->info.num_se = ws->info.max_se;
525
526 radeon_get_drm_value(ws->fd, RADEON_INFO_MAX_SH_PER_SE, NULL,
527 &ws->info.max_sa_per_se);
528 if (ws->gen == DRV_SI) {
529 ws->info.max_good_cu_per_sa =
530 ws->info.min_good_cu_per_sa = ws->info.num_cu /
531 (ws->info.max_se * ws->info.max_sa_per_se);
532 }
533
534 radeon_get_drm_value(ws->fd, RADEON_INFO_ACCEL_WORKING2, NULL,
535 &ws->accel_working2);
536 if (ws->info.family == CHIP_HAWAII && ws->accel_working2 < 2) {
537 fprintf(stderr, "radeon: GPU acceleration for Hawaii disabled, "
538 "returned accel_working2 value %u is smaller than 2. "
539 "Please install a newer kernel.\n",
540 ws->accel_working2);
541 return false;
542 }
543
544 if (ws->info.gfx_level == GFX7) {
545 if (!radeon_get_drm_value(ws->fd, RADEON_INFO_CIK_MACROTILE_MODE_ARRAY, NULL,
546 ws->info.cik_macrotile_mode_array)) {
547 fprintf(stderr, "radeon: Kernel 3.13 is required for Sea Islands support.\n");
548 return false;
549 }
550 }
551
552 if (ws->info.gfx_level >= GFX6) {
553 if (!radeon_get_drm_value(ws->fd, RADEON_INFO_SI_TILE_MODE_ARRAY, NULL,
554 ws->info.si_tile_mode_array)) {
555 fprintf(stderr, "radeon: Kernel 3.10 is required for Southern Islands support.\n");
556 return false;
557 }
558 }
559
560 /* Hawaii with old firmware needs type2 nop packet.
561 * accel_working2 with value 3 indicates the new firmware.
562 */
563 ws->info.gfx_ib_pad_with_type2 = ws->info.gfx_level <= GFX6 ||
564 (ws->info.family == CHIP_HAWAII &&
565 ws->accel_working2 < 3);
566 ws->info.tcc_cache_line_size = 64; /* TC L2 line size on GCN */
567 ws->info.ib_alignment = 4096;
568 ws->info.has_bo_metadata = false;
569 ws->info.has_eqaa_surface_allocator = false;
570 ws->info.has_sparse_vm_mappings = false;
571 ws->info.max_alignment = 1024*1024;
572 ws->info.has_graphics = true;
573 ws->info.cpdma_prefetch_writes_memory = true;
574 ws->info.max_wave64_per_simd = 10;
575 ws->info.num_physical_sgprs_per_simd = 512;
576 ws->info.num_physical_wave64_vgprs_per_simd = 256;
577 ws->info.has_3d_cube_border_color_mipmap = true;
578 ws->info.spi_cu_en_has_effect = false;
579 ws->info.spi_cu_en = 0xffff;
580 ws->info.never_stop_sq_perf_counters = false;
581
582 ws->check_vm = strstr(debug_get_option("R600_DEBUG", ""), "check_vm") != NULL ||
583 strstr(debug_get_option("AMD_DEBUG", ""), "check_vm") != NULL;
584 ws->noop_cs = debug_get_bool_option("RADEON_NOOP", false);
585
586 return true;
587 }
588
radeon_winsys_destroy(struct radeon_winsys * rws)589 static void radeon_winsys_destroy(struct radeon_winsys *rws)
590 {
591 struct radeon_drm_winsys *ws = (struct radeon_drm_winsys*)rws;
592
593 if (util_queue_is_initialized(&ws->cs_queue))
594 util_queue_destroy(&ws->cs_queue);
595
596 mtx_destroy(&ws->hyperz_owner_mutex);
597 mtx_destroy(&ws->cmask_owner_mutex);
598
599 if (ws->info.r600_has_virtual_memory)
600 pb_slabs_deinit(&ws->bo_slabs);
601 pb_cache_deinit(&ws->bo_cache);
602
603 if (ws->gen >= DRV_R600) {
604 radeon_surface_manager_free(ws->surf_man);
605 }
606
607 _mesa_hash_table_destroy(ws->bo_names, NULL);
608 _mesa_hash_table_destroy(ws->bo_handles, NULL);
609 _mesa_hash_table_u64_destroy(ws->bo_vas);
610 mtx_destroy(&ws->bo_handles_mutex);
611 mtx_destroy(&ws->vm32.mutex);
612 mtx_destroy(&ws->vm64.mutex);
613 mtx_destroy(&ws->bo_fence_lock);
614
615 if (ws->fd >= 0)
616 close(ws->fd);
617
618 FREE(rws);
619 }
620
radeon_query_info(struct radeon_winsys * rws,struct radeon_info * info,bool enable_smart_access_memory,bool disable_smart_access_memory)621 static void radeon_query_info(struct radeon_winsys *rws,
622 struct radeon_info *info,
623 bool enable_smart_access_memory,
624 bool disable_smart_access_memory)
625 {
626 *info = ((struct radeon_drm_winsys *)rws)->info;
627 }
628
radeon_cs_request_feature(struct radeon_cmdbuf * rcs,enum radeon_feature_id fid,bool enable)629 static bool radeon_cs_request_feature(struct radeon_cmdbuf *rcs,
630 enum radeon_feature_id fid,
631 bool enable)
632 {
633 struct radeon_drm_cs *cs = radeon_drm_cs(rcs);
634
635 switch (fid) {
636 case RADEON_FID_R300_HYPERZ_ACCESS:
637 return radeon_set_fd_access(cs, &cs->ws->hyperz_owner,
638 &cs->ws->hyperz_owner_mutex,
639 RADEON_INFO_WANT_HYPERZ, "Hyper-Z",
640 enable);
641
642 case RADEON_FID_R300_CMASK_ACCESS:
643 return radeon_set_fd_access(cs, &cs->ws->cmask_owner,
644 &cs->ws->cmask_owner_mutex,
645 RADEON_INFO_WANT_CMASK, "AA optimizations",
646 enable);
647 }
648 return false;
649 }
650
radeon_drm_get_gpu_reset_counter(struct radeon_drm_winsys * ws)651 uint32_t radeon_drm_get_gpu_reset_counter(struct radeon_drm_winsys *ws)
652 {
653 uint64_t retval = 0;
654
655 radeon_get_drm_value(ws->fd, RADEON_INFO_GPU_RESET_COUNTER,
656 "gpu-reset-counter", (uint32_t*)&retval);
657 return retval;
658 }
659
radeon_query_value(struct radeon_winsys * rws,enum radeon_value_id value)660 static uint64_t radeon_query_value(struct radeon_winsys *rws,
661 enum radeon_value_id value)
662 {
663 struct radeon_drm_winsys *ws = (struct radeon_drm_winsys*)rws;
664 uint64_t retval = 0;
665
666 switch (value) {
667 case RADEON_REQUESTED_VRAM_MEMORY:
668 return ws->allocated_vram;
669 case RADEON_REQUESTED_GTT_MEMORY:
670 return ws->allocated_gtt;
671 case RADEON_MAPPED_VRAM:
672 return ws->mapped_vram;
673 case RADEON_MAPPED_GTT:
674 return ws->mapped_gtt;
675 case RADEON_BUFFER_WAIT_TIME_NS:
676 return ws->buffer_wait_time;
677 case RADEON_NUM_MAPPED_BUFFERS:
678 return ws->num_mapped_buffers;
679 case RADEON_TIMESTAMP:
680 if (ws->gen < DRV_R600) {
681 assert(0);
682 return 0;
683 }
684
685 radeon_get_drm_value(ws->fd, RADEON_INFO_TIMESTAMP, "timestamp",
686 (uint32_t*)&retval);
687 return retval;
688 case RADEON_NUM_GFX_IBS:
689 return ws->num_gfx_IBs;
690 case RADEON_NUM_SDMA_IBS:
691 return ws->num_sdma_IBs;
692 case RADEON_NUM_BYTES_MOVED:
693 radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_BYTES_MOVED,
694 "num-bytes-moved", (uint32_t*)&retval);
695 return retval;
696 case RADEON_NUM_EVICTIONS:
697 case RADEON_NUM_VRAM_CPU_PAGE_FAULTS:
698 case RADEON_VRAM_VIS_USAGE:
699 case RADEON_GFX_BO_LIST_COUNTER:
700 case RADEON_GFX_IB_SIZE_COUNTER:
701 case RADEON_SLAB_WASTED_VRAM:
702 case RADEON_SLAB_WASTED_GTT:
703 return 0; /* unimplemented */
704 case RADEON_VRAM_USAGE:
705 radeon_get_drm_value(ws->fd, RADEON_INFO_VRAM_USAGE,
706 "vram-usage", (uint32_t*)&retval);
707 return retval;
708 case RADEON_GTT_USAGE:
709 radeon_get_drm_value(ws->fd, RADEON_INFO_GTT_USAGE,
710 "gtt-usage", (uint32_t*)&retval);
711 return retval;
712 case RADEON_GPU_TEMPERATURE:
713 radeon_get_drm_value(ws->fd, RADEON_INFO_CURRENT_GPU_TEMP,
714 "gpu-temp", (uint32_t*)&retval);
715 return retval;
716 case RADEON_CURRENT_SCLK:
717 radeon_get_drm_value(ws->fd, RADEON_INFO_CURRENT_GPU_SCLK,
718 "current-gpu-sclk", (uint32_t*)&retval);
719 return retval;
720 case RADEON_CURRENT_MCLK:
721 radeon_get_drm_value(ws->fd, RADEON_INFO_CURRENT_GPU_MCLK,
722 "current-gpu-mclk", (uint32_t*)&retval);
723 return retval;
724 case RADEON_CS_THREAD_TIME:
725 return util_queue_get_thread_time_nano(&ws->cs_queue, 0);
726 }
727 return 0;
728 }
729
radeon_read_registers(struct radeon_winsys * rws,unsigned reg_offset,unsigned num_registers,uint32_t * out)730 static bool radeon_read_registers(struct radeon_winsys *rws,
731 unsigned reg_offset,
732 unsigned num_registers, uint32_t *out)
733 {
734 struct radeon_drm_winsys *ws = (struct radeon_drm_winsys*)rws;
735 unsigned i;
736
737 for (i = 0; i < num_registers; i++) {
738 uint32_t reg = reg_offset + i*4;
739
740 if (!radeon_get_drm_value(ws->fd, RADEON_INFO_READ_REG, NULL, ®))
741 return false;
742 out[i] = reg;
743 }
744 return true;
745 }
746
747 DEBUG_GET_ONCE_BOOL_OPTION(thread, "RADEON_THREAD", true)
748
radeon_winsys_unref(struct radeon_winsys * ws)749 static bool radeon_winsys_unref(struct radeon_winsys *ws)
750 {
751 struct radeon_drm_winsys *rws = (struct radeon_drm_winsys*)ws;
752 bool destroy;
753
754 /* When the reference counter drops to zero, remove the fd from the table.
755 * This must happen while the mutex is locked, so that
756 * radeon_drm_winsys_create in another thread doesn't get the winsys
757 * from the table when the counter drops to 0. */
758 mtx_lock(&fd_tab_mutex);
759
760 destroy = pipe_reference(&rws->reference, NULL);
761 if (destroy && fd_tab) {
762 _mesa_hash_table_remove_key(fd_tab, intptr_to_pointer(rws->fd));
763 if (_mesa_hash_table_num_entries(fd_tab) == 0) {
764 _mesa_hash_table_destroy(fd_tab, NULL);
765 fd_tab = NULL;
766 }
767 }
768
769 mtx_unlock(&fd_tab_mutex);
770 return destroy;
771 }
772
radeon_pin_threads_to_L3_cache(struct radeon_winsys * ws,unsigned cache)773 static void radeon_pin_threads_to_L3_cache(struct radeon_winsys *ws,
774 unsigned cache)
775 {
776 struct radeon_drm_winsys *rws = (struct radeon_drm_winsys*)ws;
777
778 if (util_queue_is_initialized(&rws->cs_queue)) {
779 util_set_thread_affinity(rws->cs_queue.threads[0],
780 util_get_cpu_caps()->L3_affinity_mask[cache],
781 NULL, util_get_cpu_caps()->num_cpu_mask_bits);
782 }
783 }
784
radeon_cs_is_secure(struct radeon_cmdbuf * cs)785 static bool radeon_cs_is_secure(struct radeon_cmdbuf* cs)
786 {
787 return false;
788 }
789
790 PUBLIC struct radeon_winsys *
radeon_drm_winsys_create(int fd,const struct pipe_screen_config * config,radeon_screen_create_t screen_create)791 radeon_drm_winsys_create(int fd, const struct pipe_screen_config *config,
792 radeon_screen_create_t screen_create)
793 {
794 struct radeon_drm_winsys *ws;
795
796 mtx_lock(&fd_tab_mutex);
797 if (!fd_tab) {
798 fd_tab = util_hash_table_create_fd_keys();
799 }
800
801 ws = util_hash_table_get(fd_tab, intptr_to_pointer(fd));
802 if (ws) {
803 pipe_reference(NULL, &ws->reference);
804 mtx_unlock(&fd_tab_mutex);
805 return &ws->base;
806 }
807
808 ws = CALLOC_STRUCT(radeon_drm_winsys);
809 if (!ws) {
810 mtx_unlock(&fd_tab_mutex);
811 return NULL;
812 }
813
814 ws->fd = os_dupfd_cloexec(fd);
815
816 if (!do_winsys_init(ws))
817 goto fail1;
818
819 pb_cache_init(&ws->bo_cache, RADEON_NUM_HEAPS,
820 500000, ws->check_vm ? 1.0f : 2.0f, 0,
821 (uint64_t)MIN2(ws->info.vram_size_kb, ws->info.gart_size_kb) * 1024, NULL,
822 radeon_bo_destroy,
823 radeon_bo_can_reclaim);
824
825 if (ws->info.r600_has_virtual_memory) {
826 /* There is no fundamental obstacle to using slab buffer allocation
827 * without GPUVM, but enabling it requires making sure that the drivers
828 * honor the address offset.
829 */
830 if (!pb_slabs_init(&ws->bo_slabs,
831 RADEON_SLAB_MIN_SIZE_LOG2, RADEON_SLAB_MAX_SIZE_LOG2,
832 RADEON_NUM_HEAPS, false,
833 ws,
834 radeon_bo_can_reclaim_slab,
835 radeon_bo_slab_alloc,
836 radeon_bo_slab_free))
837 goto fail_cache;
838
839 ws->info.min_alloc_size = 1 << RADEON_SLAB_MIN_SIZE_LOG2;
840 } else {
841 ws->info.min_alloc_size = ws->info.gart_page_size;
842 }
843
844 if (ws->gen >= DRV_R600) {
845 ws->surf_man = radeon_surface_manager_new(ws->fd);
846 if (!ws->surf_man)
847 goto fail_slab;
848 }
849
850 /* init reference */
851 pipe_reference_init(&ws->reference, 1);
852
853 /* Set functions. */
854 ws->base.unref = radeon_winsys_unref;
855 ws->base.destroy = radeon_winsys_destroy;
856 ws->base.query_info = radeon_query_info;
857 ws->base.pin_threads_to_L3_cache = radeon_pin_threads_to_L3_cache;
858 ws->base.cs_request_feature = radeon_cs_request_feature;
859 ws->base.query_value = radeon_query_value;
860 ws->base.read_registers = radeon_read_registers;
861 ws->base.cs_is_secure = radeon_cs_is_secure;
862
863 radeon_drm_bo_init_functions(ws);
864 radeon_drm_cs_init_functions(ws);
865 radeon_surface_init_functions(ws);
866
867 (void) mtx_init(&ws->hyperz_owner_mutex, mtx_plain);
868 (void) mtx_init(&ws->cmask_owner_mutex, mtx_plain);
869
870 ws->bo_names = util_hash_table_create_ptr_keys();
871 ws->bo_handles = util_hash_table_create_ptr_keys();
872 ws->bo_vas = _mesa_hash_table_u64_create(NULL);
873 (void) mtx_init(&ws->bo_handles_mutex, mtx_plain);
874 (void) mtx_init(&ws->vm32.mutex, mtx_plain);
875 (void) mtx_init(&ws->vm64.mutex, mtx_plain);
876 (void) mtx_init(&ws->bo_fence_lock, mtx_plain);
877 list_inithead(&ws->vm32.holes);
878 list_inithead(&ws->vm64.holes);
879
880 /* The kernel currently returns 8MB. Make sure this doesn't change. */
881 if (ws->va_start > 8 * 1024 * 1024) {
882 /* Not enough 32-bit address space. */
883 radeon_winsys_destroy(&ws->base);
884 mtx_unlock(&fd_tab_mutex);
885 return NULL;
886 }
887
888 ws->vm32.start = ws->va_start;
889 ws->vm32.end = 1ull << 32;
890
891 ws->vm64.start = 1ull << 32;
892 ws->vm64.end = 1ull << 33;
893
894 /* TTM aligns the BO size to the CPU page size */
895 ws->info.gart_page_size = sysconf(_SC_PAGESIZE);
896 ws->info.pte_fragment_size = 64 * 1024; /* GPUVM page size */
897
898 if (ws->num_cpus > 1 && debug_get_option_thread())
899 util_queue_init(&ws->cs_queue, "rcs", 8, 1, 0, NULL);
900
901 /* Create the screen at the end. The winsys must be initialized
902 * completely.
903 *
904 * Alternatively, we could create the screen based on "ws->gen"
905 * and link all drivers into one binary blob. */
906 ws->base.screen = screen_create(&ws->base, config);
907 if (!ws->base.screen) {
908 radeon_winsys_destroy(&ws->base);
909 mtx_unlock(&fd_tab_mutex);
910 return NULL;
911 }
912
913 _mesa_hash_table_insert(fd_tab, intptr_to_pointer(ws->fd), ws);
914
915 /* We must unlock the mutex once the winsys is fully initialized, so that
916 * other threads attempting to create the winsys from the same fd will
917 * get a fully initialized winsys and not just half-way initialized. */
918 mtx_unlock(&fd_tab_mutex);
919
920 return &ws->base;
921
922 fail_slab:
923 if (ws->info.r600_has_virtual_memory)
924 pb_slabs_deinit(&ws->bo_slabs);
925 fail_cache:
926 pb_cache_deinit(&ws->bo_cache);
927 fail1:
928 mtx_unlock(&fd_tab_mutex);
929 if (ws->surf_man)
930 radeon_surface_manager_free(ws->surf_man);
931 if (ws->fd >= 0)
932 close(ws->fd);
933
934 FREE(ws);
935 return NULL;
936 }
937