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1 /*
2  * Copyright © 2017 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21  * IN THE SOFTWARE.
22  */
23 
24 #include "compiler/nir/nir_builder.h"
25 
26 static inline void
blorp_nir_init_shader(nir_builder * b,void * mem_ctx,gl_shader_stage stage,const char * name)27 blorp_nir_init_shader(nir_builder *b,
28                       void *mem_ctx,
29                       gl_shader_stage stage,
30                       const char *name)
31 {
32    *b = nir_builder_init_simple_shader(stage, NULL, "%s", name ? name : "");
33    ralloc_steal(mem_ctx, b->shader);
34    if (stage == MESA_SHADER_FRAGMENT)
35       b->shader->info.fs.origin_upper_left = true;
36 }
37 
38 static inline nir_ssa_def *
blorp_nir_txf_ms_mcs(nir_builder * b,nir_ssa_def * xy_pos,nir_ssa_def * layer)39 blorp_nir_txf_ms_mcs(nir_builder *b, nir_ssa_def *xy_pos, nir_ssa_def *layer)
40 {
41    nir_tex_instr *tex = nir_tex_instr_create(b->shader, 1);
42    tex->op = nir_texop_txf_ms_mcs_intel;
43    tex->sampler_dim = GLSL_SAMPLER_DIM_MS;
44    tex->dest_type = nir_type_int32;
45 
46    nir_ssa_def *coord;
47    if (layer) {
48       tex->is_array = true;
49       tex->coord_components = 3;
50       coord = nir_vec3(b, nir_channel(b, xy_pos, 0),
51                           nir_channel(b, xy_pos, 1),
52                           layer);
53    } else {
54       tex->is_array = false;
55       tex->coord_components = 2;
56       coord = nir_channels(b, xy_pos, 0x3);
57    }
58    tex->src[0].src_type = nir_tex_src_coord;
59    tex->src[0].src = nir_src_for_ssa(coord);
60 
61    /* Blorp only has one texture and it's bound at unit 0 */
62    tex->texture_index = 0;
63    tex->sampler_index = 0;
64 
65    nir_ssa_dest_init(&tex->instr, &tex->dest, 4, 32, NULL);
66    nir_builder_instr_insert(b, &tex->instr);
67 
68    return &tex->dest.ssa;
69 }
70 
71 static inline nir_ssa_def *
blorp_nir_mcs_is_clear_color(nir_builder * b,nir_ssa_def * mcs,uint32_t samples)72 blorp_nir_mcs_is_clear_color(nir_builder *b,
73                              nir_ssa_def *mcs,
74                              uint32_t samples)
75 {
76    switch (samples) {
77    case 2:
78       /* Empirical evidence suggests that the value returned from the
79        * sampler is not always 0x3 for clear color so we need to mask it.
80        */
81       return nir_ieq_imm(b, nir_iand(b, nir_channel(b, mcs, 0),
82                                         nir_imm_int(b, 0x3)),
83                             0x3);
84 
85    case 4:
86       return nir_ieq_imm(b, nir_channel(b, mcs, 0), 0xff);
87 
88    case 8:
89       return nir_ieq_imm(b, nir_channel(b, mcs, 0), ~0);
90 
91    case 16:
92       /* For 16x MSAA, the MCS is actually an ivec2 */
93       return nir_iand(b, nir_ieq_imm(b, nir_channel(b, mcs, 0), ~0),
94                          nir_ieq_imm(b, nir_channel(b, mcs, 1), ~0));
95 
96    default:
97       unreachable("Invalid sample count");
98    }
99 }
100 
101 static inline nir_ssa_def *
blorp_check_in_bounds(nir_builder * b,nir_ssa_def * bounds_rect,nir_ssa_def * pos)102 blorp_check_in_bounds(nir_builder *b,
103                       nir_ssa_def *bounds_rect,
104                       nir_ssa_def *pos)
105 {
106    nir_ssa_def *x0 = nir_channel(b, bounds_rect, 0);
107    nir_ssa_def *x1 = nir_channel(b, bounds_rect, 1);
108    nir_ssa_def *y0 = nir_channel(b, bounds_rect, 2);
109    nir_ssa_def *y1 = nir_channel(b, bounds_rect, 3);
110 
111    nir_ssa_def *c0 = nir_uge(b, nir_channel(b, pos, 0), x0);
112    nir_ssa_def *c1 = nir_ult(b, nir_channel(b, pos, 0), x1);
113    nir_ssa_def *c2 = nir_uge(b, nir_channel(b, pos, 1), y0);
114    nir_ssa_def *c3 = nir_ult(b, nir_channel(b, pos, 1), y1);
115 
116    nir_ssa_def *in_bounds =
117       nir_iand(b, nir_iand(b, c0, c1), nir_iand(b, c2, c3));
118 
119    return in_bounds;
120 }
121