1 /*
2 * Copyright (C) 2021 Collabora Ltd.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 */
23
24 #include "va_compiler.h"
25 #include "valhall.h"
26 #include "bi_builder.h"
27
28 void
va_lower_isel(bi_instr * I)29 va_lower_isel(bi_instr *I)
30 {
31 switch (I->op) {
32
33 /* Integer addition has swizzles and addition with 0 is canonical swizzle */
34 case BI_OPCODE_SWZ_V2I16:
35 I->op = BI_OPCODE_IADD_V2U16;
36 I->src[1] = bi_zero();
37 break;
38
39 case BI_OPCODE_SWZ_V4I8:
40 I->op = BI_OPCODE_IADD_V4U8;
41 I->src[1] = bi_zero();
42 break;
43
44 /* Extra source in Valhall not yet modeled in the Bifrost IR */
45 case BI_OPCODE_ICMP_I32:
46 I->op = BI_OPCODE_ICMP_U32;
47 I->src[2] = bi_zero();
48 break;
49
50 case BI_OPCODE_ICMP_V2I16:
51 I->op = BI_OPCODE_ICMP_V2U16;
52 I->src[2] = bi_zero();
53 break;
54
55 case BI_OPCODE_ICMP_V4I8:
56 I->op = BI_OPCODE_ICMP_V4U8;
57 I->src[2] = bi_zero();
58 break;
59
60 case BI_OPCODE_ICMP_U32:
61 case BI_OPCODE_ICMP_V2U16:
62 case BI_OPCODE_ICMP_V4U8:
63 case BI_OPCODE_ICMP_S32:
64 case BI_OPCODE_ICMP_V2S16:
65 case BI_OPCODE_ICMP_V4S8:
66 case BI_OPCODE_FCMP_F32:
67 case BI_OPCODE_FCMP_V2F16:
68 I->src[2] = bi_zero();
69 break;
70
71 /* Integer CSEL must have a signedness */
72 case BI_OPCODE_CSEL_I32:
73 case BI_OPCODE_CSEL_V2I16:
74 assert(I->cmpf == BI_CMPF_EQ || I->cmpf == BI_CMPF_NE);
75
76 I->op = (I->op == BI_OPCODE_CSEL_I32) ? BI_OPCODE_CSEL_U32 :
77 BI_OPCODE_CSEL_V2U16;
78 break;
79
80 /* Jump -> conditional branch with condition tied to true. */
81 case BI_OPCODE_JUMP:
82 I->op = I->branch_target ? BI_OPCODE_BRANCHZ_I16 : BI_OPCODE_BRANCHZI;
83 I->src[1] = I->src[0];
84 I->src[0] = bi_zero();
85 I->cmpf = BI_CMPF_EQ;
86 break;
87
88 case BI_OPCODE_AXCHG_I32:
89 I->op = BI_OPCODE_ATOM_RETURN_I32;
90 I->atom_opc = BI_ATOM_OPC_AXCHG;
91 I->sr_count = 1;
92 break;
93
94 case BI_OPCODE_ACMPXCHG_I32:
95 I->op = BI_OPCODE_ATOM_RETURN_I32;
96 I->atom_opc = BI_ATOM_OPC_ACMPXCHG;
97 /* Reads 2, this is special cased in bir.c */
98 I->sr_count = 1;
99 break;
100
101 case BI_OPCODE_ATOM_RETURN_I32:
102 if (bi_is_null(I->dest[0]))
103 I->op = BI_OPCODE_ATOM_I32;
104
105 break;
106
107 case BI_OPCODE_MUX_I32:
108 case BI_OPCODE_MUX_V2I16:
109 if (bi_can_replace_with_csel(I))
110 bi_replace_mux_with_csel(I, true);
111
112 break;
113
114 /* FADD_RSCALE.f32(x, y, z) -> FMA_RSCALE.f32(x, 1.0, y, z) */
115 case BI_OPCODE_FADD_RSCALE_F32:
116 I->op = BI_OPCODE_FMA_RSCALE_F32;
117 I->src[3] = I->src[2];
118 I->src[2] = I->src[1];
119 I->src[1] = bi_imm_f32(1.0);
120 break;
121
122 default:
123 break;
124 }
125 }
126