1 // bindgen-flags: --with-derive-hash --with-derive-partialeq --with-derive-eq --rustified-enum ".*" --rust-target 1.40 2 typedef unsigned char uint8_t; 3 typedef unsigned short uint16_t; 4 typedef unsigned int uint32_t; 5 typedef unsigned long long uint64_t; 6 7 /** 8 * Simple flags are used for rte_eth_conf.rxmode.mq_mode. 9 */ 10 #define ETH_MQ_RX_RSS_FLAG 0x1 11 #define ETH_MQ_RX_DCB_FLAG 0x2 12 #define ETH_MQ_RX_VMDQ_FLAG 0x4 13 14 /* Definitions used for VMDQ and DCB functionality */ 15 #define ETH_VMDQ_MAX_VLAN_FILTERS 64 /**< Maximum nb. of VMDQ vlan filters. */ 16 #define ETH_DCB_NUM_USER_PRIORITIES 8 /**< Maximum nb. of DCB priorities. */ 17 #define ETH_VMDQ_DCB_NUM_QUEUES 128 /**< Maximum nb. of VMDQ DCB queues. */ 18 #define ETH_DCB_NUM_QUEUES 128 /**< Maximum nb. of DCB queues. */ 19 20 /** 21 * A set of values to identify what method is to be used to route 22 * packets to multiple queues. 23 */ 24 enum rte_eth_rx_mq_mode { 25 /** None of DCB,RSS or VMDQ mode */ 26 ETH_MQ_RX_NONE = 0, 27 28 /** For RX side, only RSS is on */ 29 ETH_MQ_RX_RSS = ETH_MQ_RX_RSS_FLAG, 30 /** For RX side,only DCB is on. */ 31 ETH_MQ_RX_DCB = ETH_MQ_RX_DCB_FLAG, 32 /** Both DCB and RSS enable */ 33 ETH_MQ_RX_DCB_RSS = ETH_MQ_RX_RSS_FLAG | ETH_MQ_RX_DCB_FLAG, 34 35 /** Only VMDQ, no RSS nor DCB */ 36 ETH_MQ_RX_VMDQ_ONLY = ETH_MQ_RX_VMDQ_FLAG, 37 /** RSS mode with VMDQ */ 38 ETH_MQ_RX_VMDQ_RSS = ETH_MQ_RX_RSS_FLAG | ETH_MQ_RX_VMDQ_FLAG, 39 /** Use VMDQ+DCB to route traffic to queues */ 40 ETH_MQ_RX_VMDQ_DCB = ETH_MQ_RX_VMDQ_FLAG | ETH_MQ_RX_DCB_FLAG, 41 /** Enable both VMDQ and DCB in VMDq */ 42 ETH_MQ_RX_VMDQ_DCB_RSS = ETH_MQ_RX_RSS_FLAG | ETH_MQ_RX_DCB_FLAG | 43 ETH_MQ_RX_VMDQ_FLAG, 44 }; 45 46 /** 47 * A structure used to configure the RX features of an Ethernet port. 48 */ 49 struct rte_eth_rxmode { 50 /** The multi-queue packet distribution mode to be used, e.g. RSS. */ 51 enum rte_eth_rx_mq_mode mq_mode; 52 uint32_t max_rx_pkt_len; /**< Only used if jumbo_frame enabled. */ 53 uint16_t split_hdr_size; /**< hdr buf size (header_split enabled).*/ 54 __extension__ 55 uint16_t header_split : 1, /**< Header Split enable. */ 56 hw_ip_checksum : 1, /**< IP/UDP/TCP checksum offload enable. */ 57 hw_vlan_filter : 1, /**< VLAN filter enable. */ 58 hw_vlan_strip : 1, /**< VLAN strip enable. */ 59 hw_vlan_extend : 1, /**< Extended VLAN enable. */ 60 jumbo_frame : 1, /**< Jumbo Frame Receipt enable. */ 61 hw_strip_crc : 1, /**< Enable CRC stripping by hardware. */ 62 enable_scatter : 1, /**< Enable scatter packets rx handler */ 63 enable_lro : 1; /**< Enable LRO */ 64 }; 65 66 /** 67 * A set of values to identify what method is to be used to transmit 68 * packets using multi-TCs. 69 */ 70 enum rte_eth_tx_mq_mode { 71 ETH_MQ_TX_NONE = 0, /**< It is in neither DCB nor VT mode. */ 72 ETH_MQ_TX_DCB, /**< For TX side,only DCB is on. */ 73 ETH_MQ_TX_VMDQ_DCB, /**< For TX side,both DCB and VT is on. */ 74 ETH_MQ_TX_VMDQ_ONLY, /**< Only VT on, no DCB */ 75 }; 76 77 /** 78 * A structure used to configure the TX features of an Ethernet port. 79 */ 80 struct rte_eth_txmode { 81 enum rte_eth_tx_mq_mode mq_mode; /**< TX multi-queues mode. */ 82 83 /* For i40e specifically */ 84 uint16_t pvid; 85 __extension__ 86 uint8_t hw_vlan_reject_tagged : 1, 87 /**< If set, reject sending out tagged pkts */ 88 hw_vlan_reject_untagged : 1, 89 /**< If set, reject sending out untagged pkts */ 90 hw_vlan_insert_pvid : 1; 91 /**< If set, enable port based VLAN insertion */ 92 }; 93 94 /** 95 * A structure used to configure the Receive Side Scaling (RSS) feature 96 * of an Ethernet port. 97 * If not NULL, the *rss_key* pointer of the *rss_conf* structure points 98 * to an array holding the RSS key to use for hashing specific header 99 * fields of received packets. The length of this array should be indicated 100 * by *rss_key_len* below. Otherwise, a default random hash key is used by 101 * the device driver. 102 * 103 * The *rss_key_len* field of the *rss_conf* structure indicates the length 104 * in bytes of the array pointed by *rss_key*. To be compatible, this length 105 * will be checked in i40e only. Others assume 40 bytes to be used as before. 106 * 107 * The *rss_hf* field of the *rss_conf* structure indicates the different 108 * types of IPv4/IPv6 packets to which the RSS hashing must be applied. 109 * Supplying an *rss_hf* equal to zero disables the RSS feature. 110 */ 111 struct rte_eth_rss_conf { 112 uint8_t *rss_key; /**< If not NULL, 40-byte hash key. */ 113 uint8_t rss_key_len; /**< hash key length in bytes. */ 114 uint64_t rss_hf; /**< Hash functions to apply - see below. */ 115 }; 116 117 /** 118 * This enum indicates the possible number of traffic classes 119 * in DCB configratioins 120 */ 121 enum rte_eth_nb_tcs { 122 ETH_4_TCS = 4, /**< 4 TCs with DCB. */ 123 ETH_8_TCS = 8 /**< 8 TCs with DCB. */ 124 }; 125 126 /** 127 * This enum indicates the possible number of queue pools 128 * in VMDQ configurations. 129 */ 130 enum rte_eth_nb_pools { 131 ETH_8_POOLS = 8, /**< 8 VMDq pools. */ 132 ETH_16_POOLS = 16, /**< 16 VMDq pools. */ 133 ETH_32_POOLS = 32, /**< 32 VMDq pools. */ 134 ETH_64_POOLS = 64 /**< 64 VMDq pools. */ 135 }; 136 137 /** 138 * A structure used to configure the VMDQ+DCB feature 139 * of an Ethernet port. 140 * 141 * Using this feature, packets are routed to a pool of queues, based 142 * on the vlan id in the vlan tag, and then to a specific queue within 143 * that pool, using the user priority vlan tag field. 144 * 145 * A default pool may be used, if desired, to route all traffic which 146 * does not match the vlan filter rules. 147 */ 148 struct rte_eth_vmdq_dcb_conf { 149 enum rte_eth_nb_pools nb_queue_pools; /**< With DCB, 16 or 32 pools */ 150 uint8_t enable_default_pool; /**< If non-zero, use a default pool */ 151 uint8_t default_pool; /**< The default pool, if applicable */ 152 uint8_t nb_pool_maps; /**< We can have up to 64 filters/mappings */ 153 struct { 154 uint16_t vlan_id; /**< The vlan id of the received frame */ 155 uint64_t pools; /**< Bitmask of pools for packet rx */ 156 } pool_map[ETH_VMDQ_MAX_VLAN_FILTERS]; /**< VMDq vlan pool maps. */ 157 uint8_t dcb_tc[ETH_DCB_NUM_USER_PRIORITIES]; 158 /**< Selects a queue in a pool */ 159 }; 160 161 /* This structure may be extended in future. */ 162 struct rte_eth_dcb_rx_conf { 163 enum rte_eth_nb_tcs nb_tcs; /**< Possible DCB TCs, 4 or 8 TCs */ 164 /** Traffic class each UP mapped to. */ 165 uint8_t dcb_tc[ETH_DCB_NUM_USER_PRIORITIES]; 166 }; 167 168 struct rte_eth_vmdq_dcb_tx_conf { 169 enum rte_eth_nb_pools nb_queue_pools; /**< With DCB, 16 or 32 pools. */ 170 /** Traffic class each UP mapped to. */ 171 uint8_t dcb_tc[ETH_DCB_NUM_USER_PRIORITIES]; 172 }; 173 174 struct rte_eth_dcb_tx_conf { 175 enum rte_eth_nb_tcs nb_tcs; /**< Possible DCB TCs, 4 or 8 TCs. */ 176 /** Traffic class each UP mapped to. */ 177 uint8_t dcb_tc[ETH_DCB_NUM_USER_PRIORITIES]; 178 }; 179 180 struct rte_eth_vmdq_tx_conf { 181 enum rte_eth_nb_pools nb_queue_pools; /**< VMDq mode, 64 pools. */ 182 }; 183 184 struct rte_eth_vmdq_rx_conf { 185 enum rte_eth_nb_pools nb_queue_pools; /**< VMDq only mode, 8 or 64 pools */ 186 uint8_t enable_default_pool; /**< If non-zero, use a default pool */ 187 uint8_t default_pool; /**< The default pool, if applicable */ 188 uint8_t enable_loop_back; /**< Enable VT loop back */ 189 uint8_t nb_pool_maps; /**< We can have up to 64 filters/mappings */ 190 uint32_t rx_mode; /**< Flags from ETH_VMDQ_ACCEPT_* */ 191 struct { 192 uint16_t vlan_id; /**< The vlan id of the received frame */ 193 uint64_t pools; /**< Bitmask of pools for packet rx */ 194 } pool_map[ETH_VMDQ_MAX_VLAN_FILTERS]; /**< VMDq vlan pool maps. */ 195 }; 196 197 /** 198 * Flow Director setting modes: none, signature or perfect. 199 */ 200 enum rte_fdir_mode { 201 RTE_FDIR_MODE_NONE = 0, /**< Disable FDIR support. */ 202 RTE_FDIR_MODE_SIGNATURE, /**< Enable FDIR signature filter mode. */ 203 RTE_FDIR_MODE_PERFECT, /**< Enable FDIR perfect filter mode. */ 204 RTE_FDIR_MODE_PERFECT_MAC_VLAN, /**< Enable FDIR filter mode - MAC VLAN. */ 205 RTE_FDIR_MODE_PERFECT_TUNNEL, /**< Enable FDIR filter mode - tunnel. */ 206 }; 207 208 /** 209 * Memory space that can be configured to store Flow Director filters 210 * in the board memory. 211 */ 212 enum rte_fdir_pballoc_type { 213 RTE_FDIR_PBALLOC_64K = 0, /**< 64k. */ 214 RTE_FDIR_PBALLOC_128K, /**< 128k. */ 215 RTE_FDIR_PBALLOC_256K, /**< 256k. */ 216 }; 217 218 /** 219 * Select report mode of FDIR hash information in RX descriptors. 220 */ 221 enum rte_fdir_status_mode { 222 RTE_FDIR_NO_REPORT_STATUS = 0, /**< Never report FDIR hash. */ 223 RTE_FDIR_REPORT_STATUS, /**< Only report FDIR hash for matching pkts. */ 224 RTE_FDIR_REPORT_STATUS_ALWAYS, /**< Always report FDIR hash. */ 225 }; 226 227 /** 228 * A structure used to define the input for IPV4 flow 229 */ 230 struct rte_eth_ipv4_flow { 231 uint32_t src_ip; /**< IPv4 source address in big endian. */ 232 uint32_t dst_ip; /**< IPv4 destination address in big endian. */ 233 uint8_t tos; /**< Type of service to match. */ 234 uint8_t ttl; /**< Time to live to match. */ 235 uint8_t proto; /**< Protocol, next header in big endian. */ 236 }; 237 238 /** 239 * A structure used to define the input for IPV6 flow 240 */ 241 struct rte_eth_ipv6_flow { 242 uint32_t src_ip[4]; /**< IPv6 source address in big endian. */ 243 uint32_t dst_ip[4]; /**< IPv6 destination address in big endian. */ 244 uint8_t tc; /**< Traffic class to match. */ 245 uint8_t proto; /**< Protocol, next header to match. */ 246 uint8_t hop_limits; /**< Hop limits to match. */ 247 }; 248 249 /** 250 * A structure used to configure FDIR masks that are used by the device 251 * to match the various fields of RX packet headers. 252 */ 253 struct rte_eth_fdir_masks { 254 uint16_t vlan_tci_mask; /**< Bit mask for vlan_tci in big endian */ 255 /** Bit mask for ipv4 flow in big endian. */ 256 struct rte_eth_ipv4_flow ipv4_mask; 257 /** Bit maks for ipv6 flow in big endian. */ 258 struct rte_eth_ipv6_flow ipv6_mask; 259 /** Bit mask for L4 source port in big endian. */ 260 uint16_t src_port_mask; 261 /** Bit mask for L4 destination port in big endian. */ 262 uint16_t dst_port_mask; 263 /** 6 bit mask for proper 6 bytes of Mac address, bit 0 matches the 264 first byte on the wire */ 265 uint8_t mac_addr_byte_mask; 266 /** Bit mask for tunnel ID in big endian. */ 267 uint32_t tunnel_id_mask; 268 uint8_t tunnel_type_mask; /**< 1 - Match tunnel type, 269 0 - Ignore tunnel type. */ 270 }; 271 272 /** 273 * Payload type 274 */ 275 enum rte_eth_payload_type { 276 RTE_ETH_PAYLOAD_UNKNOWN = 0, 277 RTE_ETH_RAW_PAYLOAD, 278 RTE_ETH_L2_PAYLOAD, 279 RTE_ETH_L3_PAYLOAD, 280 RTE_ETH_L4_PAYLOAD, 281 RTE_ETH_PAYLOAD_MAX = 8, 282 }; 283 284 #define RTE_ETH_FDIR_MAX_FLEXLEN 16 /**< Max length of flexbytes. */ 285 #define RTE_ETH_INSET_SIZE_MAX 128 /**< Max length of input set. */ 286 287 /** 288 * A structure used to select bytes extracted from the protocol layers to 289 * flexible payload for filter 290 */ 291 struct rte_eth_flex_payload_cfg { 292 enum rte_eth_payload_type type; /**< Payload type */ 293 uint16_t src_offset[RTE_ETH_FDIR_MAX_FLEXLEN]; 294 /**< Offset in bytes from the beginning of packet's payload 295 src_offset[i] indicates the flexbyte i's offset in original 296 packet payload. This value should be less than 297 flex_payload_limit in struct rte_eth_fdir_info.*/ 298 }; 299 300 /** 301 * A structure used to define FDIR masks for flexible payload 302 * for each flow type 303 */ 304 struct rte_eth_fdir_flex_mask { 305 uint16_t flow_type; 306 uint8_t mask[RTE_ETH_FDIR_MAX_FLEXLEN]; 307 /**< Mask for the whole flexible payload */ 308 }; 309 310 311 /* 312 * A packet can be identified by hardware as different flow types. Different 313 * NIC hardwares may support different flow types. 314 * Basically, the NIC hardware identifies the flow type as deep protocol as 315 * possible, and exclusively. For example, if a packet is identified as 316 * 'RTE_ETH_FLOW_NONFRAG_IPV4_TCP', it will not be any of other flow types, 317 * though it is an actual IPV4 packet. 318 * Note that the flow types are used to define RSS offload types in 319 * rte_ethdev.h. 320 */ 321 #define RTE_ETH_FLOW_UNKNOWN 0 322 #define RTE_ETH_FLOW_RAW 1 323 #define RTE_ETH_FLOW_IPV4 2 324 #define RTE_ETH_FLOW_FRAG_IPV4 3 325 #define RTE_ETH_FLOW_NONFRAG_IPV4_TCP 4 326 #define RTE_ETH_FLOW_NONFRAG_IPV4_UDP 5 327 #define RTE_ETH_FLOW_NONFRAG_IPV4_SCTP 6 328 #define RTE_ETH_FLOW_NONFRAG_IPV4_OTHER 7 329 #define RTE_ETH_FLOW_IPV6 8 330 #define RTE_ETH_FLOW_FRAG_IPV6 9 331 #define RTE_ETH_FLOW_NONFRAG_IPV6_TCP 10 332 #define RTE_ETH_FLOW_NONFRAG_IPV6_UDP 11 333 #define RTE_ETH_FLOW_NONFRAG_IPV6_SCTP 12 334 #define RTE_ETH_FLOW_NONFRAG_IPV6_OTHER 13 335 #define RTE_ETH_FLOW_L2_PAYLOAD 14 336 #define RTE_ETH_FLOW_IPV6_EX 15 337 #define RTE_ETH_FLOW_IPV6_TCP_EX 16 338 #define RTE_ETH_FLOW_IPV6_UDP_EX 17 339 #define RTE_ETH_FLOW_PORT 18 340 /**< Consider device port number as a flow differentiator */ 341 #define RTE_ETH_FLOW_VXLAN 19 /**< VXLAN protocol based flow */ 342 #define RTE_ETH_FLOW_GENEVE 20 /**< GENEVE protocol based flow */ 343 #define RTE_ETH_FLOW_NVGRE 21 /**< NVGRE protocol based flow */ 344 #define RTE_ETH_FLOW_MAX 22 345 346 /** 347 * A structure used to define all flexible payload related setting 348 * include flex payload and flex mask 349 */ 350 struct rte_eth_fdir_flex_conf { 351 uint16_t nb_payloads; /**< The number of following payload cfg */ 352 uint16_t nb_flexmasks; /**< The number of following mask */ 353 struct rte_eth_flex_payload_cfg flex_set[RTE_ETH_PAYLOAD_MAX]; 354 /**< Flex payload configuration for each payload type */ 355 struct rte_eth_fdir_flex_mask flex_mask[RTE_ETH_FLOW_MAX]; 356 /**< Flex mask configuration for each flow type */ 357 }; 358 359 /** 360 * A structure used to configure the Flow Director (FDIR) feature 361 * of an Ethernet port. 362 * 363 * If mode is RTE_FDIR_DISABLE, the pballoc value is ignored. 364 */ 365 struct rte_fdir_conf { 366 enum rte_fdir_mode mode; /**< Flow Director mode. */ 367 enum rte_fdir_pballoc_type pballoc; /**< Space for FDIR filters. */ 368 enum rte_fdir_status_mode status; /**< How to report FDIR hash. */ 369 /** RX queue of packets matching a "drop" filter in perfect mode. */ 370 uint8_t drop_queue; 371 struct rte_eth_fdir_masks mask; 372 struct rte_eth_fdir_flex_conf flex_conf; 373 /**< Flex payload configuration. */ 374 }; 375 376 /** 377 * A structure used to enable/disable specific device interrupts. 378 */ 379 struct rte_intr_conf { 380 /** enable/disable lsc interrupt. 0 (default) - disable, 1 enable */ 381 uint16_t lsc; 382 /** enable/disable rxq interrupt. 0 (default) - disable, 1 enable */ 383 uint16_t rxq; 384 }; 385 386 /** 387 * A structure used to configure an Ethernet port. 388 * Depending upon the RX multi-queue mode, extra advanced 389 * configuration settings may be needed. 390 */ 391 struct rte_eth_conf { 392 uint32_t link_speeds; /**< bitmap of ETH_LINK_SPEED_XXX of speeds to be 393 used. ETH_LINK_SPEED_FIXED disables link 394 autonegotiation, and a unique speed shall be 395 set. Otherwise, the bitmap defines the set of 396 speeds to be advertised. If the special value 397 ETH_LINK_SPEED_AUTONEG (0) is used, all speeds 398 supported are advertised. */ 399 struct rte_eth_rxmode rxmode; /**< Port RX configuration. */ 400 struct rte_eth_txmode txmode; /**< Port TX configuration. */ 401 uint32_t lpbk_mode; /**< Loopback operation mode. By default the value 402 is 0, meaning the loopback mode is disabled. 403 Read the datasheet of given ethernet controller 404 for details. The possible values of this field 405 are defined in implementation of each driver. */ 406 struct { 407 struct rte_eth_rss_conf rss_conf; /**< Port RSS configuration */ 408 struct rte_eth_vmdq_dcb_conf vmdq_dcb_conf; 409 /**< Port vmdq+dcb configuration. */ 410 struct rte_eth_dcb_rx_conf dcb_rx_conf; 411 /**< Port dcb RX configuration. */ 412 struct rte_eth_vmdq_rx_conf vmdq_rx_conf; 413 /**< Port vmdq RX configuration. */ 414 } rx_adv_conf; /**< Port RX filtering configuration (union). */ 415 union { 416 struct rte_eth_vmdq_dcb_tx_conf vmdq_dcb_tx_conf; 417 /**< Port vmdq+dcb TX configuration. */ 418 struct rte_eth_dcb_tx_conf dcb_tx_conf; 419 /**< Port dcb TX configuration. */ 420 struct rte_eth_vmdq_tx_conf vmdq_tx_conf; 421 /**< Port vmdq TX configuration. */ 422 } tx_adv_conf; /**< Port TX DCB configuration (union). */ 423 /** Currently,Priority Flow Control(PFC) are supported,if DCB with PFC 424 is needed,and the variable must be set ETH_DCB_PFC_SUPPORT. */ 425 uint32_t dcb_capability_en; 426 struct rte_fdir_conf fdir_conf; /**< FDIR configuration. */ 427 struct rte_intr_conf intr_conf; /**< Interrupt mode configuration. */ 428 }; 429