1 /******************************************************************************
2 *
3 * Copyright (C) 2009-2012 Broadcom Corporation
4 *
5 * Licensed under the Apache License, Version 2.0 (the "License");
6 * you may not use this file except in compliance with the License.
7 * You may obtain a copy of the License at:
8 *
9 * http://www.apache.org/licenses/LICENSE-2.0
10 *
11 * Unless required by applicable law or agreed to in writing, software
12 * distributed under the License is distributed on an "AS IS" BASIS,
13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14 * See the License for the specific language governing permissions and
15 * limitations under the License.
16 *
17 ******************************************************************************/
18
19 /******************************************************************************
20 *
21 * Filename: hardware.c
22 *
23 * Description: Contains controller-specific functions, like
24 * firmware patch download
25 * low power mode operations
26 *
27 ******************************************************************************/
28
29 #define LOG_TAG "bt_hwcfg"
30
31 #include <utils/Log.h>
32 #include <sys/types.h>
33 #include <stdbool.h>
34 #include <sys/stat.h>
35 #include <signal.h>
36 #include <time.h>
37 #include <errno.h>
38 #include <fcntl.h>
39 #include <dirent.h>
40 #include <ctype.h>
41 #include <stdlib.h>
42 #include <string.h>
43 #include <stdio.h>
44 #include <unistd.h>
45 #include "bt_hci_bdroid.h"
46 #include "bt_vendor_brcm.h"
47 #include "esco_parameters.h"
48 #include "userial.h"
49 #include "userial_vendor.h"
50 #include "upio.h"
51
52 /******************************************************************************
53 ** Constants & Macros
54 ******************************************************************************/
55
56 #ifndef BTHW_DBG
57 #define BTHW_DBG FALSE
58 #endif
59
60 #if (BTHW_DBG == TRUE)
61 #define BTHWDBG(param, ...) \
62 { \
63 HILOGD(param, ##__VA_ARGS__); \
64 }
65 #else
66 #define BTHWDBG(param, ...) \
67 { \
68 HILOGD(param, ##__VA_ARGS__); \
69 }
70 #endif
71
72 #define FW_PATCHFILE_EXTENSION ".hcd"
73 #define FW_PATCHFILE_EXTENSION_LEN 4
74 #define FW_PATCHFILE_PATH_MAXLEN 248 /* Local_Name length of return of \
75 HCI_Read_Local_Name */
76
77 #define HCI_CMD_MAX_LEN 258
78
79 #define HCI_RESET 0x0C03
80 #define HCI_VSC_WRITE_UART_CLOCK_SETTING 0xFC45
81 #define HCI_VSC_UPDATE_BAUDRATE 0xFC18
82 #define HCI_READ_LOCAL_NAME 0x0C14
83 #define HCI_VSC_DOWNLOAD_MINIDRV 0xFC2E
84 #define HCI_VSC_WRITE_FIRMWARE 0xFC4C
85 #define HCI_VSC_WRITE_BD_ADDR 0xFC01
86 #define HCI_VSC_WRITE_SLEEP_MODE 0xFC27
87 #define HCI_VSC_WRITE_SCO_PCM_INT_PARAM 0xFC1C
88 #define HCI_VSC_WRITE_PCM_DATA_FORMAT_PARAM 0xFC1E
89 #define HCI_VSC_WRITE_I2SPCM_INTERFACE_PARAM 0xFC6D
90 #define HCI_VSC_ENABLE_WBS 0xFC7E
91 #define HCI_VSC_LAUNCH_RAM 0xFC4E
92 #define HCI_READ_LOCAL_BDADDR 0x1009
93
94 #define HCI_EVT_CMD_CMPL_STATUS_RET_BYTE 5
95 #define HCI_EVT_CMD_CMPL_LOCAL_NAME_STRING 6
96 #define HCI_EVT_CMD_CMPL_LOCAL_BDADDR_ARRAY 6
97 #define HCI_EVT_CMD_CMPL_OPCODE 3
98 #define LPM_CMD_PARAM_SIZE 12
99 #define UPDATE_BAUDRATE_CMD_PARAM_SIZE 6
100 #define HCI_CMD_PREAMBLE_SIZE 3
101 #define HCD_REC_PAYLOAD_LEN_BYTE 2
102 #define LOCAL_NAME_BUFFER_LEN 32
103 #define LOCAL_BDADDR_PATH_BUFFER_LEN 256
104
105 #define STREAM_TO_UINT16(u16, p) \
106 do \
107 { \
108 u16 = ((uint16_t)(*(p)) + (((uint16_t)(*((p) + 1))) << 8)); \
109 (p) += 2; \
110 } while (0)
111 #define UINT8_TO_STREAM(p, u8) \
112 do \
113 { \
114 *(p)++ = (uint8_t)(u8); \
115 } while (0)
116 #define UINT16_TO_STREAM(p, u16) \
117 do \
118 { \
119 *(p)++ = (uint8_t)(u16); \
120 *(p)++ = (uint8_t)((u16) >> 8); \
121 } while (0)
122 #define UINT32_TO_STREAM(p, u32) \
123 do \
124 { \
125 *(p)++ = (uint8_t)(u32); \
126 *(p)++ = (uint8_t)((u32) >> 8); \
127 *(p)++ = (uint8_t)((u32) >> 16); \
128 *(p)++ = (uint8_t)((u32) >> 24); \
129 } while (0)
130
131 #define SCO_INTERFACE_PCM 0
132 #define SCO_INTERFACE_I2S 1
133
134 /* one byte is for enable/disable
135 next 2 bytes are for codec type */
136 #define SCO_CODEC_PARAM_SIZE 3
137
138 #define BT_VENDOR_CFG_TIMEDELAY_ 40
139 #define BT_VENDOR_LDM_DEFAULT_IDLE 300
140 /******************************************************************************
141 ** Local type definitions
142 ******************************************************************************/
143
144 /* Hardware Configuration State */
145 enum {
146 HW_CFG_START = 1,
147 HW_CFG_SET_UART_CLOCK,
148 HW_CFG_SET_UART_BAUD_1,
149 HW_CFG_READ_LOCAL_NAME,
150 HW_CFG_DL_MINIDRIVER,
151 HW_CFG_DL_FW_PATCH,
152 HW_CFG_SET_UART_BAUD_2,
153 HW_CFG_SET_BD_ADDR,
154 HW_CFG_READ_BD_ADDR
155 };
156
157 /* h/w config control block */
158 typedef struct {
159 uint8_t state; /* Hardware configuration state */
160 int fw_fd; /* FW patch file fd */
161 uint8_t f_set_baud_2; /* Baud rate switch state */
162 char local_chip_name[LOCAL_NAME_BUFFER_LEN];
163 } bt_hw_cfg_cb_t;
164
165 /* low power mode parameters */
166 typedef struct {
167 uint8_t sleep_mode; /* 0(disable),1(UART),9(H5) */
168 uint8_t host_stack_idle_threshold; /* Unit scale 300ms/25ms */
169 uint8_t host_controller_idle_threshold; /* Unit scale 300ms/25ms */
170 uint8_t bt_wake_polarity; /* 0=Active Low, 1= Active High */
171 uint8_t host_wake_polarity; /* 0=Active Low, 1= Active High */
172 uint8_t allow_host_sleep_during_sco;
173 uint8_t combine_sleep_mode_and_lpm;
174 uint8_t enable_uart_txd_tri_state; /* UART_TXD Tri-State */
175 uint8_t sleep_guard_time; /* sleep guard time in 12.5ms */
176 uint8_t wakeup_guard_time; /* wakeup guard time in 12.5ms */
177 uint8_t txd_config; /* TXD is high in sleep state */
178 uint8_t pulsed_host_wake; /* pulsed host wake if mode = 1 */
179 } bt_lpm_param_t;
180
181 /* Firmware re-launch settlement time */
182 typedef struct {
183 const char *chipset_name;
184 const uint32_t delay_time;
185 } fw_settlement_entry_t;
186
187 #if (FW_AUTO_DETECTION == TRUE)
188 /* AMPAK FW auto detection table */
189 typedef struct {
190 char *chip_id;
191 char *updated_chip_id;
192 } fw_auto_detection_entry_t;
193 #endif
194
195 /******************************************************************************
196 ** Externs
197 ******************************************************************************/
198
199 void hw_config_cback(void *p_mem);
200
201 /******************************************************************************
202 ** Static variables
203 ******************************************************************************/
204
205 static char fw_patchfile_path[256] = FW_PATCHFILE_LOCATION;
206 static char fw_patchfile_name[128] = {0};
207 #if (VENDOR_LIB_RUNTIME_TUNING_ENABLED == TRUE)
208 static int fw_patch_settlement_delay = -1;
209 #endif
210
211 static int wbs_sample_rate = SCO_WBS_SAMPLE_RATE;
212 static bt_hw_cfg_cb_t hw_cfg_cb;
213
214 static bt_lpm_param_t lpm_param = {
215 LPM_SLEEP_MODE,
216 LPM_IDLE_THRESHOLD,
217 LPM_HC_IDLE_THRESHOLD,
218 LPM_BT_WAKE_POLARITY,
219 LPM_HOST_WAKE_POLARITY,
220 LPM_ALLOW_HOST_SLEEP_DURING_SCO,
221 LPM_COMBINE_SLEEP_MODE_AND_LPM,
222 LPM_ENABLE_UART_TXD_TRI_STATE,
223 0, /* not applicable */
224 0, /* not applicable */
225 0, /* not applicable */
226 LPM_PULSED_HOST_WAKE
227 };
228
229 /* need to update the bt_sco_i2spcm_param as well
230 bt_sco_i2spcm_param will be used for WBS setting
231 update the bt_sco_param and bt_sco_i2spcm_param */
232 static uint8_t bt_sco_param[SCO_PCM_PARAM_SIZE] = {
233 SCO_PCM_ROUTING,
234 SCO_PCM_IF_CLOCK_RATE,
235 SCO_PCM_IF_FRAME_TYPE,
236 SCO_PCM_IF_SYNC_MODE,
237 SCO_PCM_IF_CLOCK_MODE
238 };
239
240 static uint8_t bt_pcm_data_fmt_param[PCM_DATA_FORMAT_PARAM_SIZE] = {
241 PCM_DATA_FMT_SHIFT_MODE,
242 PCM_DATA_FMT_FILL_BITS,
243 PCM_DATA_FMT_FILL_METHOD,
244 PCM_DATA_FMT_FILL_NUM,
245 PCM_DATA_FMT_JUSTIFY_MODE
246 };
247
248 static uint8_t bt_sco_i2spcm_param[SCO_I2SPCM_PARAM_SIZE] = {
249 SCO_I2SPCM_IF_MODE,
250 SCO_I2SPCM_IF_ROLE,
251 SCO_I2SPCM_IF_SAMPLE_RATE,
252 SCO_I2SPCM_IF_CLOCK_RATE
253 };
254
255 /*
256 * The look-up table of recommended firmware settlement delay (milliseconds) on
257 * known chipsets.
258 */
259 static const fw_settlement_entry_t fw_settlement_table[] = {
260 {"BCM43241", 200},
261 {"BCM43341", 100},
262 {(const char *)NULL, 200} // Giving the generic fw settlement delay setting.
263 };
264
265 /*
266 * NOTICE:
267 * If the platform plans to run I2S interface bus over I2S/PCM port of the
268 * BT Controller with the Host AP, explicitly set "SCO_USE_I2S_INTERFACE = TRUE"
269 * in the correspodning include/vnd_<target>.txt file.
270 * Otherwise, leave SCO_USE_I2S_INTERFACE undefined in the vnd_<target>.txt file.
271 * And, PCM interface will be set as the default bus format running over I2S/PCM
272 * port.
273 */
274 #if (defined(SCO_USE_I2S_INTERFACE) && SCO_USE_I2S_INTERFACE == TRUE)
275 static uint8_t sco_bus_interface = SCO_INTERFACE_I2S;
276 #else
277 static uint8_t sco_bus_interface = SCO_INTERFACE_PCM;
278 #endif
279
280 #define INVALID_SCO_CLOCK_RATE 0xFF
281 static uint8_t sco_bus_clock_rate = INVALID_SCO_CLOCK_RATE;
282 static uint8_t sco_bus_wbs_clock_rate = INVALID_SCO_CLOCK_RATE;
283
284 #if (FW_AUTO_DETECTION == TRUE)
285 #define FW_TABLE_VERSION "v1.1 20161117"
286 static const fw_auto_detection_entry_t fw_auto_detection_table[] = {
287 {"4343A0", "BCM43438A0"}, // AP6212
288 {"BCM43430A1", "BCM43438A1"}, // AP6212A
289 {"BCM20702A", "BCM20710A1"}, // AP6210B
290 {"BCM4335C0", "BCM4339A0"}, // AP6335
291 {"BCM4330B1", "BCM40183B2"}, // AP6330
292 {"BCM4324B3", "BCM43241B4"}, // AP62X2
293 {"BCM4350C0", "BCM4354A1"}, // AP6354
294 {"BCM4354A2", "BCM4356A2"}, // AP6356
295 {"BCM4345C0", "BCM4345C0"}, // AP6255
296 {"BCM4345C5", "BCM4345C5"}, // AP6256
297 {"BCM43430B0", "BCM4343B0"}, // AP6236
298 {"BCM4359C0", "BCM4359C0"}, // AP6359
299 {"BCM4349B1", "BCM4359B1"}, // AP6359
300 {NULL, NULL}
301 };
302 #endif
303
304 /******************************************************************************
305 ** Static functions
306 ******************************************************************************/
307 static void hw_sco_i2spcm_config(uint16_t codec);
308 static void hw_sco_i2spcm_config_from_command(void *p_mem, uint16_t codec);
309
310 /******************************************************************************
311 ** Controller Initialization Static Functions
312 ******************************************************************************/
313
314 /*******************************************************************************
315 **
316 ** Function look_up_fw_settlement_delay
317 **
318 ** Description If FW_PATCH_SETTLEMENT_DELAY_MS has not been explicitly
319 ** re-defined in the platform specific build-time configuration
320 ** file, we will search into the look-up table for a
321 ** recommended firmware settlement delay value.
322 **
323 ** Although the settlement time might be also related to board
324 ** configurations such as the crystal clocking speed.
325 **
326 ** Returns Firmware settlement delay
327 **
328 *******************************************************************************/
look_up_fw_settlement_delay(void)329 uint32_t look_up_fw_settlement_delay(void)
330 {
331 uint32_t ret_value;
332 fw_settlement_entry_t *p_entry;
333
334 if (FW_PATCH_SETTLEMENT_DELAY_MS > 0)
335 ret_value = FW_PATCH_SETTLEMENT_DELAY_MS;
336 #if (VENDOR_LIB_RUNTIME_TUNING_ENABLED == TRUE)
337 else if (fw_patch_settlement_delay >= 0) {
338 ret_value = fw_patch_settlement_delay;
339 }
340 #endif
341 else {
342 p_entry = (fw_settlement_entry_t *)fw_settlement_table;
343
344 while (p_entry->chipset_name != NULL) {
345 if (strstr(hw_cfg_cb.local_chip_name, p_entry->chipset_name) != NULL) {
346 break;
347 }
348
349 p_entry++;
350 }
351
352 ret_value = p_entry->delay_time;
353 }
354
355 BTHWDBG("Settlement delay -- %d ms", ret_value);
356
357 return (ret_value);
358 }
359
360 /*******************************************************************************
361 **
362 ** Function ms_delay
363 **
364 ** Description sleep unconditionally for timeout milliseconds
365 **
366 ** Returns None
367 **
368 *******************************************************************************/
ms_delay(uint32_t timeout)369 void ms_delay(uint32_t timeout)
370 {
371 struct timespec delay;
372 int err;
373
374 if (timeout == 0)
375 return;
376
377 delay.tv_sec = timeout / BT_VENDOR_TIME_RAIDX;
378 delay.tv_nsec = BT_VENDOR_TIME_RAIDX * BT_VENDOR_TIME_RAIDX * (timeout % BT_VENDOR_TIME_RAIDX);
379
380 /* [u]sleep can't be used because it uses SIGALRM */
381 do {
382 err = nanosleep(&delay, &delay);
383 } while (err < 0 && errno == EINTR);
384 }
385
386 /*******************************************************************************
387 **
388 ** Function line_speed_to_userial_baud
389 **
390 ** Description helper function converts line speed number into USERIAL baud
391 ** rate symbol
392 **
393 ** Returns unit8_t (USERIAL baud symbol)
394 **
395 *******************************************************************************/
line_speed_to_userial_baud(uint32_t line_speed)396 uint8_t line_speed_to_userial_baud(uint32_t line_speed)
397 {
398 uint8_t baud;
399
400 if (line_speed == USERIAL_LINESPEED_4M)
401 baud = USERIAL_BAUD_4M;
402 else if (line_speed == USERIAL_LINESPEED_3M)
403 baud = USERIAL_BAUD_3M;
404 else if (line_speed == USERIAL_LINESPEED_2M)
405 baud = USERIAL_BAUD_2M;
406 else if (line_speed == USERIAL_LINESPEED_1_5M)
407 baud = USERIAL_BAUD_1_5M;
408 else if (line_speed == USERIAL_LINESPEED_1M)
409 baud = USERIAL_BAUD_1M;
410 else if (line_speed == USERIAL_LINESPEED_921600)
411 baud = USERIAL_BAUD_921600;
412 else if (line_speed == USERIAL_LINESPEED_460800)
413 baud = USERIAL_BAUD_460800;
414 else if (line_speed == USERIAL_LINESPEED_230400)
415 baud = USERIAL_BAUD_230400;
416 else if (line_speed == USERIAL_LINESPEED_115200)
417 baud = USERIAL_BAUD_115200;
418 else if (line_speed == USERIAL_LINESPEED_57600)
419 baud = USERIAL_BAUD_57600;
420 else if (line_speed == USERIAL_LINESPEED_19200)
421 baud = USERIAL_BAUD_19200;
422 else if (line_speed == USERIAL_LINESPEED_9600)
423 baud = USERIAL_BAUD_9600;
424 else if (line_speed == USERIAL_LINESPEED_1200)
425 baud = USERIAL_BAUD_1200;
426 else if (line_speed == USERIAL_LINESPEED_600)
427 baud = USERIAL_BAUD_600;
428 else {
429 HILOGE("userial vendor: unsupported baud speed %d", line_speed);
430 baud = USERIAL_BAUD_115200;
431 }
432
433 return baud;
434 }
435
436 /*******************************************************************************
437 **
438 ** Function hw_strncmp
439 **
440 ** Description Used to compare two strings in caseless
441 **
442 ** Returns 0: match, otherwise: not match
443 **
444 *******************************************************************************/
hw_strncmp(const char * p_str1,const char * p_str2,const int len)445 static int hw_strncmp(const char *p_str1, const char *p_str2, const int len)
446 {
447 int i;
448
449 if (!p_str1 || !p_str2) {
450 return (1);
451 }
452
453 for (i = 0; i < len; i++) {
454 if (toupper(p_str1[i]) != toupper(p_str2[i])) {
455 return (i + 1);
456 }
457 }
458
459 return 0;
460 }
461
462 /*******************************************************************************
463 **
464 ** Function hw_config_set_bdaddr
465 **
466 ** Description Program controller's Bluetooth Device Address
467 **
468 ** Returns xmit bytes
469 **
470 *******************************************************************************/
hw_config_set_bdaddr(HC_BT_HDR * p_buf)471 static ssize_t hw_config_set_bdaddr(HC_BT_HDR *p_buf)
472 {
473 uint8_t retval = FALSE;
474 uint8_t *p = (uint8_t *)(p_buf + 1);
475 int i = BD_ADDR_LEN;
476
477 UINT16_TO_STREAM(p, HCI_VSC_WRITE_BD_ADDR);
478 *p++ = BD_ADDR_LEN; /* parameter length */
479 *p++ = vnd_local_bd_addr[--i];
480 *p++ = vnd_local_bd_addr[--i];
481 *p++ = vnd_local_bd_addr[--i];
482 *p++ = vnd_local_bd_addr[--i];
483 *p++ = vnd_local_bd_addr[--i];
484 *p = vnd_local_bd_addr[--i];
485
486 p_buf->len = HCI_CMD_PREAMBLE_SIZE + BD_ADDR_LEN;
487 hw_cfg_cb.state = HW_CFG_SET_BD_ADDR;
488
489 retval = bt_vendor_cbacks->xmit_cb(HCI_VSC_WRITE_BD_ADDR, p_buf);
490
491 return (retval);
492 }
493
494 #if (USE_CONTROLLER_BDADDR == TRUE)
495 /*******************************************************************************
496 **
497 ** Function hw_config_read_bdaddr
498 **
499 ** Description Read controller's Bluetooth Device Address
500 **
501 ** Returns xmit bytes
502 **
503 *******************************************************************************/
hw_config_read_bdaddr(HC_BT_HDR * p_buf)504 static ssize_t hw_config_read_bdaddr(HC_BT_HDR *p_buf)
505 {
506 uint8_t retval = FALSE;
507 uint8_t *p = (uint8_t *)(p_buf + 1);
508
509 UINT16_TO_STREAM(p, HCI_READ_LOCAL_BDADDR);
510 *p = 0; /* parameter length */
511
512 p_buf->len = HCI_CMD_PREAMBLE_SIZE;
513 hw_cfg_cb.state = HW_CFG_READ_BD_ADDR;
514
515 retval = bt_vendor_cbacks->xmit_cb(HCI_READ_LOCAL_BDADDR, p_buf);
516
517 return (retval);
518 }
519 #endif // (USE_CONTROLLER_BDADDR == TRUE)
520
521 typedef void (*tTIMER_HANDLE_CBACK)(union sigval sigval_value);
522
OsAllocateTimer(tTIMER_HANDLE_CBACK timer_callback)523 static timer_t OsAllocateTimer(tTIMER_HANDLE_CBACK timer_callback)
524 {
525 struct sigevent sigev;
526 timer_t timerid;
527
528 (void)memset_s(&sigev, sizeof(struct sigevent), 0, sizeof(struct sigevent));
529 // Create the POSIX timer to generate signo
530 sigev.sigev_notify = SIGEV_THREAD;
531 sigev.sigev_notify_function = timer_callback;
532 sigev.sigev_value.sival_ptr = &timerid;
533
534 // Create the Timer using timer_create signal
535
536 if (timer_create(CLOCK_REALTIME, &sigev, &timerid) == 0) {
537 return timerid;
538 } else {
539 HILOGE("timer_create error!");
540 return (timer_t)-1;
541 }
542 }
543
OsFreeTimer(timer_t timerid)544 int OsFreeTimer(timer_t timerid)
545 {
546 int ret = 0;
547 ret = timer_delete(timerid);
548 if (ret != 0) {
549 HILOGE("timer_delete fail with errno(%d)", errno);
550 }
551
552 return ret;
553 }
554
OsStartTimer(timer_t timerid,int msec,int mode)555 static int OsStartTimer(timer_t timerid, int msec, int mode)
556 {
557 struct itimerspec itval;
558
559 itval.it_value.tv_sec = msec / BT_VENDOR_TIME_RAIDX;
560 itval.it_value.tv_nsec = (long)(msec % BT_VENDOR_TIME_RAIDX) * (BT_VENDOR_TIME_RAIDX * BT_VENDOR_TIME_RAIDX);
561
562 if (mode == 1) {
563 itval.it_interval.tv_sec = itval.it_value.tv_sec;
564 itval.it_interval.tv_nsec = itval.it_value.tv_nsec;
565 } else {
566 itval.it_interval.tv_sec = 0;
567 itval.it_interval.tv_nsec = 0;
568 }
569
570 // Set the Timer when to expire through timer_settime
571
572 if (timer_settime(timerid, 0, &itval, NULL) != 0) {
573 HILOGE("time_settime error!");
574 return -1;
575 }
576
577 return 0;
578 }
579
580 static timer_t localtimer = 0;
local_timer_handler(union sigval sigev_value)581 static void local_timer_handler(union sigval sigev_value)
582 {
583 bt_vendor_cbacks->init_cb(BTC_OP_RESULT_SUCCESS);
584 OsFreeTimer(localtimer);
585 }
start_fwcfg_cbtimer(void)586 static void start_fwcfg_cbtimer(void)
587 {
588 if (localtimer == 0) {
589 localtimer = OsAllocateTimer(local_timer_handler);
590 }
591 OsStartTimer(localtimer, BT_VENDOR_CFG_TIMEDELAY_, 0);
592 }
593
594 void hw_sco_config(void);
595
596 /*******************************************************************************
597 **
598 ** Function hw_config_cback
599 **
600 ** Description Callback function for controller configuration
601 **
602 ** Returns None
603 **
604 *******************************************************************************/
hw_config_cback(void * p_mem)605 void hw_config_cback(void *p_mem)
606 {
607 HC_BT_HDR *p_evt_buf = (HC_BT_HDR *)p_mem;
608 char *p_name, *p_tmp;
609 uint8_t *p, status;
610 uint16_t opcode;
611 HC_BT_HDR *p_buf = NULL;
612 ssize_t xmit_bytes = 0;
613 int i;
614 int delay = 100;
615 #if (USE_CONTROLLER_BDADDR == TRUE)
616 const uint8_t null_bdaddr[BD_ADDR_LEN] = {0, 0, 0, 0, 0, 0};
617 #endif
618
619 status = *((uint8_t *)(p_evt_buf + 1) + HCI_EVT_CMD_CMPL_STATUS_RET_BYTE);
620 p = (uint8_t *)(p_evt_buf + 1) + HCI_EVT_CMD_CMPL_OPCODE;
621 STREAM_TO_UINT16(opcode, p);
622
623 /* Ask a new buffer big enough to hold any HCI commands sent in here */
624 if ((status == 0) && bt_vendor_cbacks)
625 p_buf = (HC_BT_HDR *)bt_vendor_cbacks->alloc(BT_HC_HDR_SIZE + HCI_CMD_MAX_LEN);
626
627 if (p_buf != NULL) {
628 p_buf->event = MSG_STACK_TO_HC_HCI_CMD;
629 p_buf->offset = 0;
630 p_buf->len = 0;
631 p_buf->layer_specific = 0;
632
633 p = (uint8_t *)(p_buf + 1);
634 switch (hw_cfg_cb.state) {
635 case HW_CFG_SET_UART_BAUD_1:
636 /* update baud rate of host's UART port */
637 HILOGI("bt vendor lib: set UART baud %i", UART_TARGET_BAUD_RATE);
638 userial_vendor_set_baud(line_speed_to_userial_baud(UART_TARGET_BAUD_RATE));
639 #if 0
640
641 #endif
642 case HW_CFG_READ_LOCAL_NAME:
643 #if 0
644
645 #endif
646 {
647 // /vendor/etc/firmware
648 p_name = FW_PATCHFILE_LOCATION "BCM4362A2.hcd";
649 if ((hw_cfg_cb.fw_fd = open(p_name, O_RDONLY)) == -1) {
650 HILOGE("vendor lib preload failed to open [%s]", p_name);
651 } else {
652 /* vsc_download_minidriver */
653 UINT16_TO_STREAM(p, HCI_VSC_DOWNLOAD_MINIDRV);
654 *p = 0; /* parameter length */
655
656 p_buf->len = HCI_CMD_PREAMBLE_SIZE;
657 hw_cfg_cb.state = HW_CFG_DL_MINIDRIVER;
658
659 xmit_bytes = bt_vendor_cbacks->xmit_cb(HCI_VSC_DOWNLOAD_MINIDRV, p_buf);
660 }
661 }
662
663 if (xmit_bytes <= 0) {
664 HILOGE("vendor lib preload failed to locate firmware patch file and set bdaddr");
665 xmit_bytes = hw_config_set_bdaddr(p_buf);
666 }
667 break;
668
669 case HW_CFG_DL_MINIDRIVER:
670 /* give time for placing firmware in download mode */
671 ms_delay(50);
672 hw_cfg_cb.state = HW_CFG_DL_FW_PATCH;
673 /* fall through intentionally */
674 case HW_CFG_DL_FW_PATCH:
675 p_buf->len = read(hw_cfg_cb.fw_fd, p, HCI_CMD_PREAMBLE_SIZE);
676 if (p_buf->len > 0) {
677 if ((p_buf->len < HCI_CMD_PREAMBLE_SIZE) ||
678 (opcode == HCI_VSC_LAUNCH_RAM)) {
679 HILOGW("firmware patch file might be altered!");
680 } else {
681 p_buf->len += read(hw_cfg_cb.fw_fd,
682 p + HCI_CMD_PREAMBLE_SIZE,
683 *(p + HCD_REC_PAYLOAD_LEN_BYTE));
684 STREAM_TO_UINT16(opcode, p);
685 xmit_bytes = bt_vendor_cbacks->xmit_cb(opcode, p_buf);
686 break;
687 }
688 }
689
690 close(hw_cfg_cb.fw_fd);
691 hw_cfg_cb.fw_fd = -1;
692
693 /* Normally the firmware patch configuration file
694 * sets the new starting baud rate at 115200.
695 * So, we need update host's baud rate accordingly.
696 */
697 HILOGI("bt vendor lib: set UART baud 115200");
698 userial_vendor_set_baud(USERIAL_BAUD_115200);
699
700 /* Next, we would like to boost baud rate up again
701 * to desired working speed.
702 */
703 hw_cfg_cb.f_set_baud_2 = TRUE;
704
705 /* Check if we need to pause a few hundred milliseconds
706 * before sending down any HCI command.
707 */
708 delay = look_up_fw_settlement_delay();
709 HILOGI("Setting fw settlement delay to %d ", delay);
710 ms_delay(delay);
711
712 p_buf->len = HCI_CMD_PREAMBLE_SIZE;
713 UINT16_TO_STREAM(p, HCI_RESET);
714 *p = 0; /* parameter length */
715 hw_cfg_cb.state = HW_CFG_START;
716 xmit_bytes = bt_vendor_cbacks->xmit_cb(HCI_RESET, p_buf);
717 break;
718
719 case HW_CFG_START:
720 if (UART_TARGET_BAUD_RATE > 3000000) { /* 3000000 */
721 /* set UART clock to 48MHz */
722 UINT16_TO_STREAM(p, HCI_VSC_WRITE_UART_CLOCK_SETTING);
723 *p++ = 1; /* parameter length */
724 *p = 1; /* (1,"UART CLOCK 48 MHz")(2,"UART CLOCK 24 MHz") */
725
726 p_buf->len = HCI_CMD_PREAMBLE_SIZE + 1;
727 hw_cfg_cb.state = HW_CFG_SET_UART_CLOCK;
728
729 xmit_bytes = bt_vendor_cbacks->xmit_cb(HCI_VSC_WRITE_UART_CLOCK_SETTING, p_buf);
730 break;
731 }
732 /* fall through intentionally */
733 case HW_CFG_SET_UART_CLOCK:
734 /* set controller's UART baud rate to 3M */
735 UINT16_TO_STREAM(p, HCI_VSC_UPDATE_BAUDRATE);
736 *p++ = UPDATE_BAUDRATE_CMD_PARAM_SIZE; /* parameter length */
737 *p++ = 0; /* encoded baud rate */
738 *p++ = 0; /* use encoded form */
739 UINT32_TO_STREAM(p, UART_TARGET_BAUD_RATE);
740
741 p_buf->len = HCI_CMD_PREAMBLE_SIZE +
742 UPDATE_BAUDRATE_CMD_PARAM_SIZE;
743 hw_cfg_cb.state = (hw_cfg_cb.f_set_baud_2) ? HW_CFG_SET_UART_BAUD_2 : HW_CFG_SET_UART_BAUD_1;
744
745 xmit_bytes = bt_vendor_cbacks->xmit_cb(HCI_VSC_UPDATE_BAUDRATE, p_buf);
746 break;
747
748 case HW_CFG_SET_UART_BAUD_2:
749 /* update baud rate of host's UART port */
750 HILOGI("bt vendor lib: set UART baud %i", UART_TARGET_BAUD_RATE);
751 userial_vendor_set_baud(
752 line_speed_to_userial_baud(UART_TARGET_BAUD_RATE));
753
754 #if (USE_CONTROLLER_BDADDR == TRUE)
755 if ((xmit_bytes = hw_config_read_bdaddr(p_buf)) > 0)
756 break;
757 #else
758 if ((xmit_bytes = hw_config_set_bdaddr(p_buf)) > 0)
759 break;
760 #endif
761 /* fall through intentionally */
762 case HW_CFG_SET_BD_ADDR:
763 HILOGI("vendor lib fwcfg completed");
764 hw_sco_config();
765 start_fwcfg_cbtimer();
766
767 hw_cfg_cb.state = 0;
768
769 if (hw_cfg_cb.fw_fd != -1) {
770 close(hw_cfg_cb.fw_fd);
771 hw_cfg_cb.fw_fd = -1;
772 }
773
774 xmit_bytes = 1;
775 break;
776
777 #if (USE_CONTROLLER_BDADDR == TRUE)
778 case HW_CFG_READ_BD_ADDR:
779 p_tmp = (char *)(p_evt_buf + 1) +
780 HCI_EVT_CMD_CMPL_LOCAL_BDADDR_ARRAY;
781 HILOGI("entering HW_CFG_READ_BD_ADDR");
782 if (memcmp(p_tmp, null_bdaddr, BD_ADDR_LEN) == 0) {
783 HILOGI("entering HW_CFG_READ_BD_ADDR");
784 // Controller does not have a valid OTP BDADDR!
785 // Set the BTIF initial BDADDR instead.
786 if ((xmit_bytes = hw_config_set_bdaddr(p_buf)) > 0)
787 break;
788 } else {
789 HILOGI("Controller OTP bdaddr %02X:%02X:%02X:%02X:%02X:%02X",
790 *(p_tmp + 5), *(p_tmp + 4), *(p_tmp + 3),
791 *(p_tmp + 2), *(p_tmp + 1), *p_tmp);
792 }
793
794 HILOGI("vendor lib fwcfg completed2");
795 hw_sco_config();
796 start_fwcfg_cbtimer();
797
798 hw_cfg_cb.state = 0;
799
800 if (hw_cfg_cb.fw_fd != -1) {
801 close(hw_cfg_cb.fw_fd);
802 hw_cfg_cb.fw_fd = -1;
803 }
804
805 xmit_bytes = 1;
806 break;
807 #endif // (USE_CONTROLLER_BDADDR == TRUE)
808 }
809
810 bt_vendor_cbacks->dealloc(p_buf);
811 }
812
813 /* Free the RX event buffer */
814
815 if (xmit_bytes <= 0) {
816 HILOGE("vendor lib fwcfg aborted!!!");
817 if (bt_vendor_cbacks) {
818 bt_vendor_cbacks->init_cb(BTC_OP_RESULT_FAIL);
819 }
820
821 if (hw_cfg_cb.fw_fd != -1) {
822 close(hw_cfg_cb.fw_fd);
823 hw_cfg_cb.fw_fd = -1;
824 }
825
826 hw_cfg_cb.state = 0;
827 }
828 }
829
830 /******************************************************************************
831 ** LPM Static Functions
832 ******************************************************************************/
833
834 /*******************************************************************************
835 **
836 ** Function hw_lpm_ctrl_cback
837 **
838 ** Description Callback function for lpm enable/disable request
839 **
840 ** Returns None
841 **
842 *******************************************************************************/
hw_lpm_ctrl_cback(void * p_mem)843 void hw_lpm_ctrl_cback(void *p_mem)
844 {
845 HC_BT_HDR *p_evt_buf = (HC_BT_HDR *)p_mem;
846 bt_op_result_t status = BTC_OP_RESULT_FAIL;
847
848 if (*((uint8_t *)(p_evt_buf + 1) + HCI_EVT_CMD_CMPL_STATUS_RET_BYTE) == 0) {
849 status = BTC_OP_RESULT_SUCCESS;
850 }
851
852 if (bt_vendor_cbacks) {
853
854 }
855 }
856
857 #if (SCO_CFG_INCLUDED == TRUE)
858 /*****************************************************************************
859 ** SCO Configuration Static Functions
860 *****************************************************************************/
861
hw_sco_i2spcm_proc_interface_param(void)862 static void hw_sco_i2spcm_proc_interface_param(void)
863 {
864 bt_op_result_t status = BTC_OP_RESULT_FAIL;
865 uint8_t ret = FALSE;
866 uint8_t *p;
867 HC_BT_HDR *p_buf = NULL;
868
869 /* Ask a new buffer to hold WRITE_SCO_PCM_INT_PARAM command */
870 if (bt_vendor_cbacks) {
871 p_buf = (HC_BT_HDR *)bt_vendor_cbacks->alloc(BT_HC_HDR_SIZE
872 + HCI_CMD_PREAMBLE_SIZE + SCO_PCM_PARAM_SIZE);
873 }
874 if (p_buf) {
875 p_buf->event = MSG_STACK_TO_HC_HCI_CMD;
876 p_buf->offset = 0;
877 p_buf->layer_specific = 0;
878 p_buf->len = HCI_CMD_PREAMBLE_SIZE + SCO_PCM_PARAM_SIZE;
879 p = (uint8_t *)(p_buf + 1);
880
881 /* do we need this VSC for I2S??? */
882 UINT16_TO_STREAM(p, HCI_VSC_WRITE_SCO_PCM_INT_PARAM);
883 *p++ = SCO_PCM_PARAM_SIZE;
884 memcpy_s(p, &bt_sco_param, SCO_PCM_PARAM_SIZE);
885 ret = bt_vendor_cbacks->xmit_cb(HCI_VSC_WRITE_SCO_PCM_INT_PARAM, p_buf);
886 bt_vendor_cbacks->dealloc(p_buf);
887 if (ret) {
888 return;
889 }
890 }
891 status = BTC_OP_RESULT_FAIL;
892
893 HILOGI("sco I2S/PCM config interface result %d [0-Success, 1-Fail]", status);
894 }
895
hw_sco_i2spcm_proc_int_param(void)896 static void hw_sco_i2spcm_proc_int_param(void)
897 {
898 bt_op_result_t status = BTC_OP_RESULT_FAIL;
899 uint8_t ret = FALSE;
900 uint8_t *p;
901 HC_BT_HDR *p_buf = NULL;
902
903 /* Ask a new buffer to hold WRITE_PCM_DATA_FORMAT_PARAM command */
904 if (bt_vendor_cbacks)
905 p_buf = (HC_BT_HDR *)bt_vendor_cbacks->alloc(
906 BT_HC_HDR_SIZE + HCI_CMD_PREAMBLE_SIZE + PCM_DATA_FORMAT_PARAM_SIZE);
907 if (p_buf) {
908 p_buf->event = MSG_STACK_TO_HC_HCI_CMD;
909 p_buf->offset = 0;
910 p_buf->layer_specific = 0;
911 p_buf->len = HCI_CMD_PREAMBLE_SIZE + PCM_DATA_FORMAT_PARAM_SIZE;
912
913 p = (uint8_t *)(p_buf + 1);
914 UINT16_TO_STREAM(p, HCI_VSC_WRITE_PCM_DATA_FORMAT_PARAM);
915 *p++ = PCM_DATA_FORMAT_PARAM_SIZE;
916 memcpy_s(p, &bt_pcm_data_fmt_param, PCM_DATA_FORMAT_PARAM_SIZE);
917
918 ret = bt_vendor_cbacks->xmit_cb(HCI_VSC_WRITE_PCM_DATA_FORMAT_PARAM, p_buf);
919 bt_vendor_cbacks->dealloc(p_buf);
920 if (ret) {
921 return;
922 }
923 }
924 status = BTC_OP_RESULT_FAIL;
925
926 HILOGI("sco I2S/PCM config int result %d [0-Success, 1-Fail]", status);
927 }
928
929 /*******************************************************************************
930 **
931 ** Function hw_sco_i2spcm_cfg_cback
932 **
933 ** Description Callback function for SCO I2S/PCM configuration request
934 **
935 ** Returns None
936 **
937 *******************************************************************************/
hw_sco_i2spcm_cfg_cback(void * p_mem)938 static void hw_sco_i2spcm_cfg_cback(void *p_mem)
939 {
940 HC_BT_HDR *p_evt_buf = (HC_BT_HDR *)p_mem;
941 uint8_t *p;
942 uint16_t opcode;
943 HC_BT_HDR *p_buf = NULL;
944 bt_op_result_t status = BTC_OP_RESULT_FAIL;
945
946 p = (uint8_t *)(p_evt_buf + 1) + HCI_EVT_CMD_CMPL_OPCODE;
947 STREAM_TO_UINT16(opcode, p);
948
949 if (*((uint8_t *)(p_evt_buf + 1) + HCI_EVT_CMD_CMPL_STATUS_RET_BYTE) == 0) {
950 status = BTC_OP_RESULT_SUCCESS;
951 }
952
953 /* Free the RX event buffer */
954 if (bt_vendor_cbacks) {
955
956 }
957
958 if (status != BTC_OP_RESULT_SUCCESS) {
959 return;
960 }
961
962 if ((opcode == HCI_VSC_WRITE_I2SPCM_INTERFACE_PARAM) &&
963 (sco_bus_interface == SCO_INTERFACE_PCM)) {
964 hw_sco_i2spcm_proc_interface_param();
965 } else if ((opcode == HCI_VSC_WRITE_SCO_PCM_INT_PARAM) &&
966 (sco_bus_interface == SCO_INTERFACE_PCM)) {
967 hw_sco_i2spcm_proc_int_param();
968 }
969 }
970
971 /*******************************************************************************
972 **
973 ** Function hw_set_MSBC_codec_cback
974 **
975 ** Description Callback function for setting WBS codec
976 **
977 ** Returns None
978 **
979 *******************************************************************************/
hw_set_MSBC_codec_cback(void * p_mem)980 static void hw_set_MSBC_codec_cback(void *p_mem)
981 {
982 /* whenever update the codec enable/disable, need to update I2SPCM */
983 HILOGI("SCO I2S interface change the sample rate to 16K");
984 hw_sco_i2spcm_config_from_command(p_mem, SCO_CODEC_MSBC);
985 }
986
987 /*******************************************************************************
988 **
989 ** Function hw_set_CVSD_codec_cback
990 **
991 ** Description Callback function for setting NBS codec
992 **
993 ** Returns None
994 **
995 *******************************************************************************/
hw_set_CVSD_codec_cback(void * p_mem)996 static void hw_set_CVSD_codec_cback(void *p_mem)
997 {
998 /* whenever update the codec enable/disable, need to update I2SPCM */
999 HILOGI("SCO I2S interface change the sample rate to 8K");
1000 hw_sco_i2spcm_config_from_command(p_mem, SCO_CODEC_CVSD);
1001 }
1002
1003 #endif // SCO_CFG_INCLUDED
1004
1005 /*****************************************************************************
1006 ** Hardware Configuration Interface Functions
1007 *****************************************************************************/
1008
1009 /*******************************************************************************
1010 **
1011 ** Function hw_config_start
1012 **
1013 ** Description Kick off controller initialization process
1014 **
1015 ** Returns None
1016 **
1017 *******************************************************************************/
hw_config_start(void)1018 void hw_config_start(void)
1019 {
1020 HC_BT_HDR *p_buf = NULL;
1021 uint8_t *p;
1022
1023 hw_cfg_cb.state = 0;
1024 hw_cfg_cb.fw_fd = -1;
1025 hw_cfg_cb.f_set_baud_2 = FALSE;
1026
1027 // Start from sending HCI_RESET
1028
1029 if (bt_vendor_cbacks) {
1030 p_buf = (HC_BT_HDR *)bt_vendor_cbacks->alloc(BT_HC_HDR_SIZE +
1031 HCI_CMD_PREAMBLE_SIZE);
1032 }
1033
1034 if (p_buf) {
1035 p_buf->event = MSG_STACK_TO_HC_HCI_CMD;
1036 p_buf->offset = 0;
1037 p_buf->layer_specific = 0;
1038 p_buf->len = HCI_CMD_PREAMBLE_SIZE;
1039
1040 p = (uint8_t *)(p_buf + 1);
1041 UINT16_TO_STREAM(p, HCI_RESET);
1042 *p = 0;
1043
1044 hw_cfg_cb.state = HW_CFG_START;
1045 bt_vendor_cbacks->xmit_cb(HCI_RESET, p_buf);
1046 bt_vendor_cbacks->dealloc(p_buf);
1047 } else {
1048 if (bt_vendor_cbacks) {
1049 HILOGE("vendor lib fw conf aborted [no buffer]");
1050 bt_vendor_cbacks->init_cb(BTC_OP_RESULT_FAIL);
1051 }
1052 }
1053 }
1054
1055 /*******************************************************************************
1056 **
1057 ** Function hw_lpm_enable
1058 **
1059 ** Description Enalbe/Disable LPM
1060 **
1061 ** Returns TRUE/FALSE
1062 **
1063 *******************************************************************************/
hw_lpm_enable(uint8_t turn_on)1064 uint8_t hw_lpm_enable(uint8_t turn_on)
1065 {
1066 HILOGD("entering hw_lpm_enable11");
1067 HC_BT_HDR *p_buf = NULL;
1068 uint8_t *p;
1069 uint8_t ret = FALSE;
1070
1071 if (bt_vendor_cbacks)
1072 p_buf = (HC_BT_HDR *)bt_vendor_cbacks->alloc(BT_HC_HDR_SIZE +
1073 HCI_CMD_PREAMBLE_SIZE +
1074 LPM_CMD_PARAM_SIZE);
1075
1076 if (p_buf) {
1077 p_buf->event = MSG_STACK_TO_HC_HCI_CMD;
1078 p_buf->offset = 0;
1079 p_buf->layer_specific = 0;
1080 p_buf->len = HCI_CMD_PREAMBLE_SIZE + LPM_CMD_PARAM_SIZE;
1081
1082 p = (uint8_t *)(p_buf + 1);
1083 UINT16_TO_STREAM(p, HCI_VSC_WRITE_SLEEP_MODE);
1084 *p++ = LPM_CMD_PARAM_SIZE; /* parameter length */
1085
1086 if (turn_on) {
1087 memcpy(p, &lpm_param, LPM_CMD_PARAM_SIZE);
1088 upio_set(UPIO_LPM_MODE, UPIO_ASSERT, 0);
1089 } else {
1090 memset(p, 0, LPM_CMD_PARAM_SIZE);
1091 upio_set(UPIO_LPM_MODE, UPIO_DEASSERT, 0);
1092 }
1093
1094 ret = bt_vendor_cbacks->xmit_cb(HCI_VSC_WRITE_SLEEP_MODE, p_buf);
1095 bt_vendor_cbacks->dealloc(p_buf);
1096 }
1097
1098 if ((ret <= 0) && bt_vendor_cbacks) {
1099
1100 }
1101 HILOGD("hw_lpm_enable ret:%d", ret);
1102 return ret;
1103 }
1104
1105 /*******************************************************************************
1106 **
1107 ** Function hw_lpm_get_idle_timeout
1108 **
1109 ** Description Calculate idle time based on host stack idle threshold
1110 **
1111 ** Returns idle timeout value
1112 **
1113 *******************************************************************************/
hw_lpm_get_idle_timeout(void)1114 uint32_t hw_lpm_get_idle_timeout(void)
1115 {
1116 uint32_t timeout_ms;
1117
1118 /* set idle time to be LPM_IDLE_TIMEOUT_MULTIPLE times of
1119 * host stack idle threshold (in 300ms/25ms)
1120 */
1121 timeout_ms = (uint32_t)lpm_param.host_stack_idle_threshold * LPM_IDLE_TIMEOUT_MULTIPLE;
1122 timeout_ms *= BT_VENDOR_LDM_DEFAULT_IDLE;
1123 return timeout_ms;
1124 }
1125
1126 /*******************************************************************************
1127 **
1128 ** Function hw_lpm_set_wake_state
1129 **
1130 ** Description Assert/Deassert BT_WAKE
1131 **
1132 ** Returns None
1133 **
1134 *******************************************************************************/
hw_lpm_set_wake_state(uint8_t wake_assert)1135 void hw_lpm_set_wake_state(uint8_t wake_assert)
1136 {
1137 uint8_t state = (wake_assert) ? UPIO_ASSERT : UPIO_DEASSERT;
1138
1139 upio_set(UPIO_BT_WAKE, state, lpm_param.bt_wake_polarity);
1140 }
1141
1142 #if (SCO_CFG_INCLUDED == TRUE)
1143 /*******************************************************************************
1144 **
1145 ** Function hw_sco_config
1146 **
1147 ** Description Configure SCO related hardware settings
1148 **
1149 ** Returns None
1150 **
1151 *******************************************************************************/
hw_sco_config(void)1152 void hw_sco_config(void)
1153 {
1154 if (sco_bus_interface == SCO_INTERFACE_I2S) {
1155 /* 'Enable' I2S mode */
1156 bt_sco_i2spcm_param[SCO_I2SPCM_PARAM_IF_MODE] = 1;
1157
1158 /* set nbs clock rate as the value in SCO_I2SPCM_IF_CLOCK_RATE field */
1159 sco_bus_clock_rate = bt_sco_i2spcm_param[SCO_I2SPCM_PARAM_IF_CLOCK_RATE];
1160 } else {
1161 /* 'Disable' I2S mode */
1162 bt_sco_i2spcm_param[SCO_I2SPCM_PARAM_IF_MODE] = 0;
1163
1164 /* set nbs clock rate as the value in SCO_PCM_IF_CLOCK_RATE field */
1165 sco_bus_clock_rate = bt_sco_param[SCO_PCM_PARAM_IF_CLOCK_RATE];
1166
1167 /* sync up clock mode setting */
1168 bt_sco_i2spcm_param[SCO_I2SPCM_PARAM_IF_MODE] = bt_sco_param[SCO_PCM_PARAM_IF_CLOCK_MODE];
1169 }
1170
1171 if (sco_bus_wbs_clock_rate == INVALID_SCO_CLOCK_RATE) {
1172 /* set default wbs clock rate */
1173 sco_bus_wbs_clock_rate = SCO_I2SPCM_IF_CLOCK_RATE4WBS;
1174
1175 if (sco_bus_wbs_clock_rate < sco_bus_clock_rate)
1176 sco_bus_wbs_clock_rate = sco_bus_clock_rate;
1177 }
1178
1179 /*
1180 * To support I2S/PCM port multiplexing signals for sharing Bluetooth audio
1181 * and FM on the same PCM pins, we defer Bluetooth audio (SCO/eSCO)
1182 * configuration till SCO/eSCO is being established;
1183 * i.e. in hw_set_audio_state() call.
1184 * When configured as I2S only, Bluetooth audio configuration is executed
1185 * immediately with SCO_CODEC_CVSD by default.
1186 */
1187
1188 if (sco_bus_interface == SCO_INTERFACE_I2S) {
1189 hw_sco_i2spcm_config(SCO_CODEC_CVSD);
1190 } else {
1191 hw_sco_i2spcm_config(SCO_CODEC_NONE);
1192 }
1193
1194 if (bt_vendor_cbacks) {
1195
1196 }
1197 }
1198
hw_sco_i2spcm_config_from_command(void * p_mem,uint16_t codec)1199 static void hw_sco_i2spcm_config_from_command(void *p_mem, uint16_t codec)
1200 {
1201 HC_BT_HDR *p_evt_buf = (HC_BT_HDR *)p_mem;
1202 bool command_success = *((uint8_t *)(p_evt_buf + 1) + HCI_EVT_CMD_CMPL_STATUS_RET_BYTE) == 0;
1203
1204 /* Free the RX event buffer */
1205 if (bt_vendor_cbacks) {
1206
1207 }
1208
1209 if (command_success) {
1210 hw_sco_i2spcm_config(codec);
1211 } else if (bt_vendor_cbacks) {
1212
1213 }
1214 }
1215
1216 /*******************************************************************************
1217 **
1218 ** Function hw_sco_i2spcm_config
1219 **
1220 ** Description Configure SCO over I2S or PCM
1221 **
1222 ** Returns None
1223 **
1224 *******************************************************************************/
hw_sco_i2spcm_config(uint16_t codec)1225 static void hw_sco_i2spcm_config(uint16_t codec)
1226 {
1227 HC_BT_HDR *p_buf = NULL;
1228 uint8_t *p, ret;
1229 uint16_t cmd_u16 = HCI_CMD_PREAMBLE_SIZE + SCO_I2SPCM_PARAM_SIZE;
1230
1231 if (bt_vendor_cbacks) {
1232 p_buf = (HC_BT_HDR *)bt_vendor_cbacks->alloc(BT_HC_HDR_SIZE + cmd_u16);
1233 }
1234
1235 if (p_buf) {
1236 p_buf->event = MSG_STACK_TO_HC_HCI_CMD;
1237 p_buf->offset = 0;
1238 p_buf->layer_specific = 0;
1239 p_buf->len = cmd_u16;
1240
1241 p = (uint8_t *)(p_buf + 1);
1242
1243 UINT16_TO_STREAM(p, HCI_VSC_WRITE_I2SPCM_INTERFACE_PARAM);
1244 *p++ = SCO_I2SPCM_PARAM_SIZE;
1245 if (codec == SCO_CODEC_CVSD) {
1246 bt_sco_i2spcm_param[SCO_I2SPCM_PARAM_IF_SAMPLE_RATE] = 0; /* SCO_I2SPCM_IF_SAMPLE_RATE 8k */
1247 bt_sco_i2spcm_param[SCO_I2SPCM_PARAM_IF_CLOCK_RATE] =
1248 bt_sco_param[SCO_PCM_PARAM_IF_CLOCK_RATE] = sco_bus_clock_rate;
1249 } else if (codec == SCO_CODEC_MSBC) {
1250 bt_sco_i2spcm_param[SCO_I2SPCM_PARAM_IF_SAMPLE_RATE] = wbs_sample_rate; /* SCO_I2SPCM_IF_SAMPLE_RATE 16K */
1251 bt_sco_i2spcm_param[SCO_I2SPCM_PARAM_IF_CLOCK_RATE] =
1252 bt_sco_param[SCO_PCM_PARAM_IF_CLOCK_RATE] = sco_bus_wbs_clock_rate;
1253 } else {
1254 bt_sco_i2spcm_param[SCO_I2SPCM_PARAM_IF_SAMPLE_RATE] = 0; /* SCO_I2SPCM_IF_SAMPLE_RATE 8k */
1255 bt_sco_i2spcm_param[SCO_I2SPCM_PARAM_IF_CLOCK_RATE] =
1256 bt_sco_param[SCO_PCM_PARAM_IF_CLOCK_RATE] = sco_bus_clock_rate;
1257 HILOGE("wrong codec is use in hw_sco_i2spcm_config, goes default NBS");
1258 }
1259 memcpy_s(p, &bt_sco_i2spcm_param, SCO_I2SPCM_PARAM_SIZE);
1260 cmd_u16 = HCI_VSC_WRITE_I2SPCM_INTERFACE_PARAM;
1261 HILOGI("I2SPCM config {0x%x, 0x%x, 0x%x, 0x%x}",
1262 bt_sco_i2spcm_param[SCO_I2SPCM_PARAM_IF_MODE], bt_sco_i2spcm_param[SCO_I2SPCM_PARAM_IF_ROLE],
1263 bt_sco_i2spcm_param[SCO_I2SPCM_PARAM_IF_SAMPLE_RATE],
1264 bt_sco_i2spcm_param[SCO_I2SPCM_PARAM_IF_CLOCK_RATE]);
1265
1266 bt_vendor_cbacks->xmit_cb(cmd_u16, p_buf);
1267 bt_vendor_cbacks->dealloc(p_buf);
1268 }
1269
1270 }
1271
1272 /*******************************************************************************
1273 **
1274 ** Function hw_set_SCO_codec
1275 **
1276 ** Description This functgion sends command to the controller to setup
1277 ** WBS/NBS codec for the upcoming eSCO connection.
1278 **
1279 ** Returns -1 : Failed to send VSC
1280 ** 0 : Success
1281 **
1282 *******************************************************************************/
hw_set_SCO_codec(uint16_t codec)1283 static int hw_set_SCO_codec(uint16_t codec)
1284 {
1285 HC_BT_HDR *p_buf = NULL;
1286 uint8_t *p;
1287 uint8_t ret;
1288 int ret_val = 0;
1289 return ret_val;
1290 }
1291
1292 /*******************************************************************************
1293 **
1294 ** Function hw_set_audio_state
1295 **
1296 ** Description This function configures audio base on provided audio state
1297 **
1298 ** Paramters pointer to audio state structure
1299 **
1300 ** Returns 0: ok, -1: error
1301 **
1302 *******************************************************************************/
hw_set_audio_state(bt_vendor_op_audio_state_t * p_state)1303 int hw_set_audio_state(bt_vendor_op_audio_state_t *p_state)
1304 {
1305 int ret_val = -1;
1306
1307 if (!bt_vendor_cbacks) {
1308 return ret_val;
1309 }
1310
1311 ret_val = hw_set_SCO_codec(p_state->peer_codec);
1312 return ret_val;
1313 }
1314 #endif
1315 /*******************************************************************************
1316 **
1317 ** Function hw_set_patch_file_path
1318 **
1319 ** Description Set the location of firmware patch file
1320 **
1321 ** Returns 0 : Success
1322 ** Otherwise : Fail
1323 **
1324 *******************************************************************************/
hw_set_patch_file_path(char * p_conf_name,char * p_conf_value,int param)1325 int hw_set_patch_file_path(char *p_conf_name, char *p_conf_value, int param)
1326 {
1327 if (strcpy_s(fw_patchfile_path, sizeof(fw_patchfile_path), p_conf_value) != 0) {
1328 return -1;
1329 }
1330 return 0;
1331 }
1332
1333 /*******************************************************************************
1334 **
1335 ** Function hw_set_patch_file_name
1336 **
1337 ** Description Give the specific firmware patch filename
1338 **
1339 ** Returns 0 : Success
1340 ** Otherwise : Fail
1341 **
1342 *******************************************************************************/
hw_set_patch_file_name(char * p_conf_name,char * p_conf_value,int param)1343 int hw_set_patch_file_name(char *p_conf_name, char *p_conf_value, int param)
1344 {
1345 if (strcpy_s(fw_patchfile_name, sizeof(fw_patchfile_name), p_conf_value) != 0) {
1346 return -1;
1347 }
1348 return 0;
1349 }
1350
1351 #if (VENDOR_LIB_RUNTIME_TUNING_ENABLED == TRUE)
1352 /*******************************************************************************
1353 **
1354 ** Function hw_set_patch_settlement_delay
1355 **
1356 ** Description Give the specific firmware patch settlement time in milliseconds
1357 **
1358 ** Returns 0 : Success
1359 ** Otherwise : Fail
1360 **
1361 *******************************************************************************/
hw_set_patch_settlement_delay(char * p_conf_name,char * p_conf_value,int param)1362 int hw_set_patch_settlement_delay(char *p_conf_name, char *p_conf_value, int param)
1363 {
1364 fw_patch_settlement_delay = atoi(p_conf_value);
1365 return 0;
1366 }
1367 #endif // VENDOR_LIB_RUNTIME_TUNING_ENABLED
1368
1369 /*****************************************************************************
1370 ** Sample Codes Section
1371 *****************************************************************************/
1372
1373 #if (HW_END_WITH_HCI_RESET == TRUE)
1374 /*******************************************************************************
1375 **
1376 ** Function hw_epilog_cback
1377 **
1378 ** Description Callback function for Command Complete Events from HCI
1379 ** commands sent in epilog process.
1380 **
1381 ** Returns None
1382 **
1383 *******************************************************************************/
hw_epilog_cback(void * p_mem)1384 void hw_epilog_cback(void *p_mem)
1385 {
1386 HC_BT_HDR *p_evt_buf = (HC_BT_HDR *)p_mem;
1387 uint8_t *p, status;
1388 uint16_t opcode;
1389
1390 status = *((uint8_t *)(p_evt_buf + 1) + HCI_EVT_CMD_CMPL_STATUS_RET_BYTE);
1391 p = (uint8_t *)(p_evt_buf + 1) + HCI_EVT_CMD_CMPL_OPCODE;
1392 STREAM_TO_UINT16(opcode, p);
1393
1394 BTHWDBG("%s Opcode:0x%04X Status: %d", __FUNCTION__, opcode, status);
1395
1396 if (bt_vendor_cbacks) {
1397 /* Must free the RX event buffer */
1398 /* Once epilog process is done, must call epilog_cb callback
1399 to notify caller */
1400 }
1401 }
1402
1403 /*******************************************************************************
1404 **
1405 ** Function hw_epilog_process
1406 **
1407 ** Description Sample implementation of epilog process
1408 **
1409 ** Returns None
1410 **
1411 *******************************************************************************/
hw_epilog_process(void)1412 void hw_epilog_process(void)
1413 {
1414 HC_BT_HDR *p_buf = NULL;
1415 uint8_t *p;
1416
1417 BTHWDBG("hw_epilog_process");
1418
1419 /* Sending a HCI_RESET */
1420 if (bt_vendor_cbacks) {
1421 /* Must allocate command buffer via HC's alloc API */
1422 p_buf = (HC_BT_HDR *)bt_vendor_cbacks->alloc(BT_HC_HDR_SIZE +
1423 HCI_CMD_PREAMBLE_SIZE);
1424 }
1425
1426 if (p_buf) {
1427 p_buf->event = MSG_STACK_TO_HC_HCI_CMD;
1428 p_buf->offset = 0;
1429 p_buf->layer_specific = 0;
1430 p_buf->len = HCI_CMD_PREAMBLE_SIZE;
1431
1432 p = (uint8_t *)(p_buf + 1);
1433 UINT16_TO_STREAM(p, HCI_RESET);
1434 *p = 0; /* parameter length */
1435
1436 /* Send command via HC's xmit_cb API */
1437 bt_vendor_cbacks->xmit_cb(HCI_RESET, p_buf);
1438 bt_vendor_cbacks->dealloc(p_buf);
1439 } else {
1440 if (bt_vendor_cbacks) {
1441 HILOGE("vendor lib epilog process aborted [no buffer]");
1442 }
1443 }
1444 }
1445 #endif // (HW_END_WITH_HCI_RESET == TRUE)
1446
hw_process_event(HC_BT_HDR * p_buf)1447 void hw_process_event(HC_BT_HDR *p_buf)
1448 {
1449 uint16_t opcode;
1450 uint8_t *p = (uint8_t *)(p_buf + 1) + HCI_EVT_CMD_CMPL_OPCODE;
1451 STREAM_TO_UINT16(opcode, p);
1452
1453 HILOGI("%s, opcode:0x%04x", __FUNCTION__, opcode);
1454 switch (opcode) {
1455 case HCI_VSC_WRITE_BD_ADDR:
1456 #if (USE_CONTROLLER_BDADDR == TRUE)
1457 case HCI_READ_LOCAL_BDADDR:
1458 #endif
1459 case HCI_READ_LOCAL_NAME:
1460 case HCI_VSC_DOWNLOAD_MINIDRV:
1461 case HCI_VSC_WRITE_FIRMWARE:
1462 case HCI_VSC_LAUNCH_RAM:
1463 case HCI_RESET:
1464 case HCI_VSC_WRITE_UART_CLOCK_SETTING:
1465 case HCI_VSC_UPDATE_BAUDRATE:
1466 hw_config_cback(p_buf);
1467 break;
1468
1469 case HCI_VSC_WRITE_SCO_PCM_INT_PARAM:
1470 case HCI_VSC_WRITE_PCM_DATA_FORMAT_PARAM:
1471 case HCI_VSC_WRITE_I2SPCM_INTERFACE_PARAM:
1472 hw_sco_i2spcm_cfg_cback(p_buf);
1473 break;
1474
1475 case HCI_VSC_WRITE_SLEEP_MODE:
1476 hw_lpm_ctrl_cback(p_buf);
1477 break;
1478
1479 case HCI_VSC_ENABLE_WBS:
1480 break;
1481 }
1482
1483 HILOGI("%s, Complete", __FUNCTION__);
1484 }
1485