1root { 2 platform { 3 template codec_controller { 4 match_attr = ""; 5 serviceName = ""; 6 codecDaiName = ""; 7 } 8 controller_0x120c1030 :: codec_controller { 9 match_attr = "hdf_codec_driver_0"; 10 serviceName = "codec_service_0"; 11 codecDaiName = "codec_dai"; 12 13 hwInfo = [ 14 /* 15 Playback/Captrue, formats, rates, rate_min, rate_max, channels_min, channels_max, 16 buffer_bytes_max, period_bytes_min, period_bytes_max, periods_min, periods_max 17 */ 18 1, 0xF, 0xFF, 8000, 96000, 1, 2, 1, 2, 3, 4, 5, 19 2, 0xF, 0xFF, 8000, 96000, 1, 2, 1, 2, 3, 4, 5, 20 ]; 21 22 regConfig { 23 /* reg: register address 24 rreg: register address 25 shift: shift bits 26 rshift: rshift bits 27 min: min value 28 max: max value 29 mask: mask of value 30 invert: enum InvertVal 0-uninvert 1-invert 31 value: value 32 */ 33 34 /* reg, value */ 35 initSeqConfig = [ 36 0x13, 0xf4, 37 0x15, 0xff, 38 0x17, 0x40, 39 0x18, 0xc8, 40 0x1e, 0x00, 41 0x27, 0x3f, 42 0x29, 0x99, 43 0x2f, 0x03, 44 0x30, 0x06, 45 0x35, 0x02, 46 0x38, 0x10, 47 0x3c, 0x0F, 48 0x3d, 0x80, 49 0x3e, 0x0f, 50 0x3f, 0x11, 51 0x40, 0xa5, 52 0x41, 0x77, 53 0x42, 0x04, 54 0x43, 0x58, 55 0x44, 0x2d, 56 0x45, 0x0c, 57 0x46, 0xa5, 58 0x47, 0x00, 59 0x48, 0x00, 60 0x4b, 0x0f, 61 0x4c, 0x20, 62 0x4e, 0x0f, 63 0x4f, 0x00, 64 ]; 65 66 controlsConfig = [ 67 /*array index, iface, mixer/mux, enable,*/ 68 0, 2, 0, 1, 69 1, 2, 0, 1, 70 2, 2, 0, 1, 71 3, 2, 0, 1, 72 4, 2, 0, 1, 73 5, 2, 0, 1, 74 8, 2, 0, 1, 75 9, 2, 0, 1, 76 ]; 77 78 /* reg, rreg, shift, rshift, min, max, mask, invert, value */ 79 ctrlParamsSeqConfig = [ 80 0x31, 0x32, 0, 0, 0x00, 0xFF, 0xFF, 1, 0x00, // DACL/R Playback Volume 81 0x1a, 0x1b, 0, 0, 0x00, 0xFF, 0xFF, 1, 0x00, // ADCL/R Capture Volume 82 0x38, 0x38, 0, 0, 0x0, 0x1, 0x1, 0, 0x0, // DAC Playback Mute 83 0x27, 0x27, 6, 6, 0x0, 0x1, 0x1, 0, 0x0, // ADCL/R Capture Mute 84 0x29, 0x29, 4, 4, 0x0, 0xF, 0xF, 0, 0x9, // Mic Left Gain 85 0x29, 0x29, 0, 0, 0x0, 0xF, 0xF, 0, 0x9, // Mic Right Gain 86 0x4a, 0x4a, 2, 2, 0x0, 0x2, 0x3, 0, 0x0, // Render Channel Mode 87 0x4d, 0x4d, 2, 2, 0x0, 0x2, 0x3, 0, 0x0, // Captrue Channel Mode 88 ]; 89 90 /* reg, rreg, shift, rshift, min, max, mask, invert, value */ 91 daiParamsSeqConfig = [ 92 0x45, 0x45, 0, 0, 0x0, 0xFF, 0xFF, 0, 0x0C, // PLL_PREDIV_BIT 93 0x35, 0x35, 0, 0, 0x0, 0x7, 0x7, 0, 0x2, // DAC_Sample_rate 94 0x1e, 0x1e, 0, 0, 0x0, 0x7, 0x7, 0, 0x2, // ADC_Sample_rate 95 0x4e, 0x4e, 0, 0, 0x0, 0x17, 0x1F, 0, 0x0F, // TX_datawidth 96 0x4b, 0x4b, 0, 0, 0x0, 0x17, 0x1F, 0, 0x0F, // RX_datawidth 97 0x15, 0x15, 0x0, 0x0, 0x0, 0xf, 0xf, 0, 0x0, // rx clk enable 98 0x15, 0x15, 0x4, 0x4, 0x0, 0xf, 0xf, 0, 0x0, // tx clk enable 99 ]; 100 101 ctrlSapmParamsSeqConfig = [ 102 0x27, 0x27, 5, 5, 0x00, 0x1, 0x1, 1, 0x00, //LPGA MIC -- connect MIC1 103 0x27, 0x27, 4, 4, 0x00, 0x1, 0x1, 1, 0x00, //RPGA MIC -- connect MIC2 104 0x2F, 0x2F, 2, 2, 0x00, 0x1, 0x1, 1, 0x00, //Speaker1 Switch -- connect speaker 105 0x2F, 0x2F, 1, 1, 0x00, 0x1, 0x1, 1, 0x00, //Headphone1 Switch -- connect hpl 106 0x2F, 0x2F, 0, 0, 0x00, 0x1, 0x1, 1, 0x00, //Headphone2 Switch -- connect hpr 107 ]; 108 /* 109 reg is 0xFFFF: component has no sapm register bit 110 sapmType, compNameIndex, reg, mask, shift, invert, kcontrolNews, kcontrolsNum 111 */ 112 sapmComponent = [ 113 10, 0, 0x18, 0x1, 7, 1, 0, 0, //ADCL 114 10, 1, 0x18, 0x1, 6, 1, 0, 0, //ADCR 115 11, 32, 0xFFFF, 0xFFFF, 0, 0, 0, 0, //DAC1 116 11, 33, 0xFFFF, 0xFFFF, 0, 0, 0, 0, //DAC2 117 11, 34, 0xFFFF, 0xFFFF, 0, 0, 0, 0, //DAC3 118 6, 52, 0xFFFF, 0xFFFF, 0, 0, 3, 1, //SPKL PGA 119 6, 54, 0xFFFF, 0xFFFF, 0, 0, 4, 1, //HPL PGA 120 6, 55, 0xFFFF, 0xFFFF, 0, 0, 5, 1, //HPR PGA 121 15, 6, 0xFFFF, 0xFFFF, 0, 0, 0, 0, //SPK 122 14, 10, 0xFFFF, 0xFFFF, 0, 0, 0, 0, //HPL 123 14, 11, 0xFFFF, 0xFFFF, 0, 0, 0, 0, //HPR 124 6, 4, 0xFFFF, 0xFFFF, 6, 0, 1, 1, //LPGA 125 6, 5, 0xFFFF, 0xFFFF, 6, 0, 2, 1, //RPGA 126 13, 40, 0xFFFF, 0xFFFF, 6, 0, 0, 0, //MIC1 127 13, 41, 0x4d, 0x1, 1, 0, 0, 0 //MIC2 128 ]; 129 130 /*array index, iface, mixer/mux, enable*/ 131 sapmConfig = [ 132 0, 2, 0, 1, 133 1, 2, 0, 1, 134 24, 2, 0, 1, 135 28, 2, 0, 1, 136 29, 2, 0, 1 137 ]; 138 } 139 } 140 controller_0x120c1031 :: codec_controller { 141 match_attr = "hdf_codec_driver_1"; 142 serviceName = "codec_service_1"; 143 codecDaiName = "hdmi_codec_dai"; 144 145 hwInfo = [ 146 /* 147 Playback/Captrue, formats, rates, rate_min, rate_max, channels_min, channels_max, 148 buffer_bytes_max, period_bytes_min, period_bytes_max, periods_min, periods_max 149 */ 150 1, 0xF, 0xFF, 8000, 96000, 1, 2, 1, 2, 3, 4, 5 151 ]; 152 153 regConfig { 154 /* reg: register address 155 rreg: register address 156 shift: shift bits 157 rshift: rshift bits 158 min: min value 159 max: max value 160 mask: mask of value 161 invert: enum InvertVal 0-uninvert 1-invert 162 value: value 163 */ 164 165 initSeqConfig = [ 166 /* reg, value */ 167 0x13, 0xf4, 168 ]; 169 170 controlsConfig = [ 171 /* array index, iface, mixer/mux, enable */ 172 0, 2, 0, 1, 173 1, 2, 0, 1, 174 2, 2, 0, 1, 175 3, 2, 0, 1, 176 4, 2, 0, 1, 177 5, 2, 0, 1, 178 8, 2, 0, 1, 179 9, 2, 0, 1, 180 ]; 181 182 ctrlParamsSeqConfig = [ 183 /* reg, rreg, shift, rshift, min, max, mask, invert, value */ 184 0x31, 0x32, 0, 0, 0x00, 0xFF, 0xFF, 1, 0x00, // DACL/R Playback Volume 185 0x1a, 0x1b, 0, 0, 0x00, 0xFF, 0xFF, 1, 0x00, // ADCL/R Capture Volume 186 0x38, 0x38, 0, 0, 0x0, 0x1, 0x1, 0, 0x0, // DAC Playback Mute 187 0x27, 0x27, 6, 6, 0x0, 0x1, 0x1, 0, 0x0, // ADCL/R Capture Mute 188 0x29, 0x29, 4, 4, 0x0, 0xF, 0xF, 0, 0x9, // Mic Left Gain 189 0x29, 0x29, 0, 0, 0x0, 0xF, 0xF, 0, 0x9, // Mic Right Gain 190 0x4a, 0x4a, 2, 2, 0x0, 0x2, 0x3, 0, 0x0, // Render Channel Mode 191 0x4d, 0x4d, 2, 2, 0x0, 0x2, 0x3, 0, 0x0, // Captrue Channel Mode 192 ]; 193 194 daiParamsSeqConfig = [ 195 /* reg, rreg, shift, rshift, min, max, mask, invert, value */ 196 0x45, 0x45, 0, 0, 0x0, 0xFF, 0xFF, 0, 0x0C, // PLL_PREDIV_BIT 197 0x35, 0x35, 0, 0, 0x0, 0x7, 0x7, 0, 0x2, // DAC_Sample_rate 198 0x1e, 0x1e, 0, 0, 0x0, 0x7, 0x7, 0, 0x2, // ADC_Sample_rate 199 0x4e, 0x4e, 0, 0, 0x0, 0x17, 0x1F, 0, 0x0F, // TX_datawidth 200 0x4b, 0x4b, 0, 0, 0x0, 0x17, 0x1F, 0, 0x0F, // RX_datawidth 201 0x15, 0x15, 0x0, 0x0, 0x0, 0xf, 0xf, 0, 0x0, // rx clk enable 202 0x15, 0x15, 0x4, 0x4, 0x0, 0xf, 0xf, 0, 0x0, // tx clk enable 203 ]; 204 205 ctrlSapmParamsSeqConfig = [ 206 /* reg, rreg, shift, rshift, min, max, mask, invert, value */ 207 0x27, 0x27, 5, 5, 0x00, 0x1, 0x1, 1, 0x00, //LPGA MIC -- connect MIC1 208 0x27, 0x27, 4, 4, 0x00, 0x1, 0x1, 1, 0x00, //RPGA MIC -- connect MIC2 209 0x2F, 0x2F, 2, 2, 0x00, 0x1, 0x1, 1, 0x00, //Speaker1 Switch -- connect speaker 210 0x2F, 0x2F, 1, 1, 0x00, 0x1, 0x1, 1, 0x00, //Headphone1 Switch -- connect hpl 211 0x2F, 0x2F, 0, 0, 0x00, 0x1, 0x1, 1, 0x00, //Headphone2 Switch -- connect hpr 212 ]; 213 214 /* 215 reg is 0xFFFF: component has no sapm register bit 216 sapmType, compNameIndex, reg, mask, shift, invert, kcontrolNews, kcontrolsNum 217 */ 218 sapmComponent = [ 219 10, 0, 0x18, 0x1, 7, 1, 0, 0, //ADCL 220 10, 1, 0x18, 0x1, 6, 1, 0, 0, //ADCR 221 11, 32, 0xFFFF, 0xFFFF, 0, 0, 0, 0, //DAC1 222 11, 33, 0xFFFF, 0xFFFF, 0, 0, 0, 0, //DAC2 223 11, 34, 0xFFFF, 0xFFFF, 0, 0, 0, 0, //DAC3 224 6, 52, 0xFFFF, 0xFFFF, 0, 0, 3, 1, //SPKL PGA 225 6, 54, 0xFFFF, 0xFFFF, 0, 0, 4, 1, //HPL PGA 226 6, 55, 0xFFFF, 0xFFFF, 0, 0, 5, 1, //HPR PGA 227 15, 6, 0xFFFF, 0xFFFF, 0, 0, 0, 0, //SPK 228 14, 10, 0xFFFF, 0xFFFF, 0, 0, 0, 0, //HPL 229 14, 11, 0xFFFF, 0xFFFF, 0, 0, 0, 0, //HPR 230 6, 4, 0xFFFF, 0xFFFF, 6, 0, 1, 1, //LPGA 231 6, 5, 0xFFFF, 0xFFFF, 6, 0, 2, 1, //RPGA 232 13, 40, 0xFFFF, 0xFFFF, 6, 0, 0, 0, //MIC1 233 13, 41, 0x4d, 0x1, 1, 0, 0, 0 //MIC2 234 ]; 235 236 sapmConfig = [ 237 /* array index, iface, mixer/mux, enable */ 238 0, 2, 0, 1, 239 1, 2, 0, 1, 240 24, 2, 0, 1, 241 28, 2, 0, 1, 242 29, 2, 0, 1 243 ]; 244 } 245 } 246 } 247}