Lines Matching refs:ctx_cs
5524 radv_pipeline_emit_depth_stencil_state(struct radeon_cmdbuf *ctx_cs, in radv_pipeline_emit_depth_stencil_state() argument
5527 radeon_set_context_reg(ctx_cs, R_028000_DB_RENDER_CONTROL, ds_state->db_render_control); in radv_pipeline_emit_depth_stencil_state()
5529 radeon_set_context_reg_seq(ctx_cs, R_02800C_DB_RENDER_OVERRIDE, 2); in radv_pipeline_emit_depth_stencil_state()
5530 radeon_emit(ctx_cs, ds_state->db_render_override); in radv_pipeline_emit_depth_stencil_state()
5531 radeon_emit(ctx_cs, ds_state->db_render_override2); in radv_pipeline_emit_depth_stencil_state()
5535 radv_pipeline_emit_blend_state(struct radeon_cmdbuf *ctx_cs, in radv_pipeline_emit_blend_state() argument
5541 radeon_set_context_reg_seq(ctx_cs, R_028780_CB_BLEND0_CONTROL, 8); in radv_pipeline_emit_blend_state()
5542 radeon_emit_array(ctx_cs, blend->cb_blend_control, 8); in radv_pipeline_emit_blend_state()
5543 radeon_set_context_reg(ctx_cs, R_028B70_DB_ALPHA_TO_MASK, blend->db_alpha_to_mask); in radv_pipeline_emit_blend_state()
5547 radeon_set_context_reg_seq(ctx_cs, R_028760_SX_MRT0_BLEND_OPT, 8); in radv_pipeline_emit_blend_state()
5548 radeon_emit_array(ctx_cs, blend->sx_mrt_blend_opt, 8); in radv_pipeline_emit_blend_state()
5551 radeon_set_context_reg(ctx_cs, R_028714_SPI_SHADER_COL_FORMAT, blend->spi_shader_col_format); in radv_pipeline_emit_blend_state()
5553 radeon_set_context_reg(ctx_cs, R_02823C_CB_SHADER_MASK, blend->cb_shader_mask); in radv_pipeline_emit_blend_state()
5557 radv_pipeline_emit_raster_state(struct radeon_cmdbuf *ctx_cs, in radv_pipeline_emit_raster_state() argument
5585 radeon_set_context_reg(ctx_cs, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL, in radv_pipeline_emit_raster_state()
5591 radv_pipeline_emit_multisample_state(struct radeon_cmdbuf *ctx_cs, in radv_pipeline_emit_multisample_state() argument
5597 radeon_set_context_reg_seq(ctx_cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2); in radv_pipeline_emit_multisample_state()
5598 radeon_emit(ctx_cs, ms->pa_sc_aa_mask[0]); in radv_pipeline_emit_multisample_state()
5599 radeon_emit(ctx_cs, ms->pa_sc_aa_mask[1]); in radv_pipeline_emit_multisample_state()
5601 radeon_set_context_reg(ctx_cs, R_028804_DB_EQAA, ms->db_eqaa); in radv_pipeline_emit_multisample_state()
5602 radeon_set_context_reg(ctx_cs, R_028BE0_PA_SC_AA_CONFIG, ms->pa_sc_aa_config); in radv_pipeline_emit_multisample_state()
5604 radeon_set_context_reg_seq(ctx_cs, R_028A48_PA_SC_MODE_CNTL_0, 2); in radv_pipeline_emit_multisample_state()
5605 radeon_emit(ctx_cs, ms->pa_sc_mode_cntl_0); in radv_pipeline_emit_multisample_state()
5606 radeon_emit(ctx_cs, ms->pa_sc_mode_cntl_1); in radv_pipeline_emit_multisample_state()
5614 ctx_cs, R_02882C_PA_SU_PRIM_FILTER_CNTL, in radv_pipeline_emit_multisample_state()
5619 radv_pipeline_emit_vgt_gs_mode(struct radeon_cmdbuf *ctx_cs, in radv_pipeline_emit_vgt_gs_mode() argument
5642 radeon_set_context_reg(ctx_cs, R_028A84_VGT_PRIMITIVEID_EN, vgt_primitiveid_en); in radv_pipeline_emit_vgt_gs_mode()
5643 radeon_set_context_reg(ctx_cs, R_028A40_VGT_GS_MODE, vgt_gs_mode); in radv_pipeline_emit_vgt_gs_mode()
5647 radv_pipeline_emit_hw_vs(struct radeon_cmdbuf *ctx_cs, struct radeon_cmdbuf *cs, in radv_pipeline_emit_hw_vs() argument
5677 radeon_set_context_reg(ctx_cs, R_0286C4_SPI_VS_OUT_CONFIG, spi_vs_out_config); in radv_pipeline_emit_hw_vs()
5680 ctx_cs, R_02870C_SPI_SHADER_POS_FORMAT, in radv_pipeline_emit_hw_vs()
5689 radeon_set_context_reg(ctx_cs, R_02881C_PA_CL_VS_OUT_CNTL, in radv_pipeline_emit_hw_vs()
5701 radeon_set_context_reg(ctx_cs, R_028AB4_VGT_REUSE_OFF, outinfo->writes_viewport_index); in radv_pipeline_emit_hw_vs()
5759 radv_pipeline_emit_hw_ngg(struct radeon_cmdbuf *ctx_cs, struct radeon_cmdbuf *cs, in radv_pipeline_emit_hw_ngg() argument
5800 ctx_cs, R_0286C4_SPI_VS_OUT_CONFIG, in radv_pipeline_emit_hw_ngg()
5811 radeon_set_context_reg(ctx_cs, R_028708_SPI_SHADER_IDX_FORMAT, in radv_pipeline_emit_hw_ngg()
5814 ctx_cs, R_02870C_SPI_SHADER_POS_FORMAT, in radv_pipeline_emit_hw_ngg()
5823 radeon_set_context_reg(ctx_cs, R_02881C_PA_CL_VS_OUT_CNTL, in radv_pipeline_emit_hw_ngg()
5834 radeon_set_context_reg(ctx_cs, R_028A84_VGT_PRIMITIVEID_EN, in radv_pipeline_emit_hw_ngg()
5838 radeon_set_context_reg(ctx_cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE, in radv_pipeline_emit_hw_ngg()
5847 ctx_cs, R_028A44_VGT_GS_ONCHIP_CNTL, in radv_pipeline_emit_hw_ngg()
5853 radeon_set_context_reg(ctx_cs, R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP, in radv_pipeline_emit_hw_ngg()
5855 radeon_set_context_reg(ctx_cs, R_028B4C_GE_NGG_SUBGRP_CNTL, in radv_pipeline_emit_hw_ngg()
5859 ctx_cs, R_028B90_VGT_GS_INSTANCE_CNT, in radv_pipeline_emit_hw_ngg()
5892 radeon_set_uconfig_reg(ctx_cs, R_03096C_GE_CNTL, ge_cntl); in radv_pipeline_emit_hw_ngg()
5964 radv_pipeline_emit_vertex_shader(struct radeon_cmdbuf *ctx_cs, struct radeon_cmdbuf *cs, in radv_pipeline_emit_vertex_shader() argument
5979 radv_pipeline_emit_hw_ngg(ctx_cs, cs, pipeline, vs); in radv_pipeline_emit_vertex_shader()
5981 radv_pipeline_emit_hw_vs(ctx_cs, cs, pipeline, vs); in radv_pipeline_emit_vertex_shader()
5985 radv_pipeline_emit_tess_shaders(struct radeon_cmdbuf *ctx_cs, struct radeon_cmdbuf *cs, in radv_pipeline_emit_tess_shaders() argument
5996 radv_pipeline_emit_hw_ngg(ctx_cs, cs, pipeline, tes); in radv_pipeline_emit_tess_shaders()
6000 radv_pipeline_emit_hw_vs(ctx_cs, cs, pipeline, tes); in radv_pipeline_emit_tess_shaders()
6007 radeon_set_context_reg(ctx_cs, R_028A44_VGT_GS_ONCHIP_CNTL, in radv_pipeline_emit_tess_shaders()
6014 radv_pipeline_emit_tess_state(struct radeon_cmdbuf *ctx_cs, in radv_pipeline_emit_tess_state() argument
6033 radeon_set_context_reg_idx(ctx_cs, R_028B58_VGT_LS_HS_CONFIG, 2, ls_hs_config); in radv_pipeline_emit_tess_state()
6035 radeon_set_context_reg(ctx_cs, R_028B58_VGT_LS_HS_CONFIG, ls_hs_config); in radv_pipeline_emit_tess_state()
6087 radeon_set_context_reg(ctx_cs, R_028B6C_VGT_TF_PARAM, in radv_pipeline_emit_tess_state()
6094 radv_pipeline_emit_hw_gs(struct radeon_cmdbuf *ctx_cs, struct radeon_cmdbuf *cs, in radv_pipeline_emit_hw_gs() argument
6111 radeon_set_context_reg_seq(ctx_cs, R_028A60_VGT_GSVS_RING_OFFSET_1, 3); in radv_pipeline_emit_hw_gs()
6112 radeon_emit(ctx_cs, offset); in radv_pipeline_emit_hw_gs()
6115 radeon_emit(ctx_cs, offset); in radv_pipeline_emit_hw_gs()
6118 radeon_emit(ctx_cs, offset); in radv_pipeline_emit_hw_gs()
6121 radeon_set_context_reg(ctx_cs, R_028AB0_VGT_GSVS_RING_ITEMSIZE, offset); in radv_pipeline_emit_hw_gs()
6123 radeon_set_context_reg_seq(ctx_cs, R_028B5C_VGT_GS_VERT_ITEMSIZE, 4); in radv_pipeline_emit_hw_gs()
6124 radeon_emit(ctx_cs, num_components[0]); in radv_pipeline_emit_hw_gs()
6125 radeon_emit(ctx_cs, (max_stream >= 1) ? num_components[1] : 0); in radv_pipeline_emit_hw_gs()
6126 radeon_emit(ctx_cs, (max_stream >= 2) ? num_components[2] : 0); in radv_pipeline_emit_hw_gs()
6127 radeon_emit(ctx_cs, (max_stream >= 3) ? num_components[3] : 0); in radv_pipeline_emit_hw_gs()
6131 ctx_cs, R_028B90_VGT_GS_INSTANCE_CNT, in radv_pipeline_emit_hw_gs()
6134 radeon_set_context_reg(ctx_cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE, in radv_pipeline_emit_hw_gs()
6150 radeon_set_context_reg(ctx_cs, R_028A44_VGT_GS_ONCHIP_CNTL, gs_state->vgt_gs_onchip_cntl); in radv_pipeline_emit_hw_gs()
6151 radeon_set_context_reg(ctx_cs, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP, in radv_pipeline_emit_hw_gs()
6182 radv_pipeline_emit_hw_vs(ctx_cs, cs, pipeline, pipeline->base.gs_copy_shader); in radv_pipeline_emit_hw_gs()
6186 radv_pipeline_emit_geometry_shader(struct radeon_cmdbuf *ctx_cs, struct radeon_cmdbuf *cs, in radv_pipeline_emit_geometry_shader() argument
6196 radv_pipeline_emit_hw_ngg(ctx_cs, cs, pipeline, gs); in radv_pipeline_emit_geometry_shader()
6198 radv_pipeline_emit_hw_gs(ctx_cs, cs, pipeline, gs); in radv_pipeline_emit_geometry_shader()
6200 radeon_set_context_reg(ctx_cs, R_028B38_VGT_GS_MAX_VERT_OUT, gs->info.gs.vertices_out); in radv_pipeline_emit_geometry_shader()
6204 radv_pipeline_emit_mesh_shader(struct radeon_cmdbuf *ctx_cs, struct radeon_cmdbuf *cs, in radv_pipeline_emit_mesh_shader() argument
6212 radv_pipeline_emit_hw_ngg(ctx_cs, cs, pipeline, ms); in radv_pipeline_emit_mesh_shader()
6213 radeon_set_context_reg(ctx_cs, R_028B38_VGT_GS_MAX_VERT_OUT, ms->info.workgroup_size); in radv_pipeline_emit_mesh_shader()
6214 radeon_set_uconfig_reg_idx(pdevice, ctx_cs, in radv_pipeline_emit_mesh_shader()
6286 radv_pipeline_emit_ps_inputs(struct radeon_cmdbuf *ctx_cs, in radv_pipeline_emit_ps_inputs() argument
6341 radeon_set_context_reg_seq(ctx_cs, R_028644_SPI_PS_INPUT_CNTL_0, ps_offset); in radv_pipeline_emit_ps_inputs()
6343 radeon_emit(ctx_cs, ps_input_cntl[i]); in radv_pipeline_emit_ps_inputs()
6386 radv_pipeline_emit_fragment_shader(struct radeon_cmdbuf *ctx_cs, struct radeon_cmdbuf *cs, in radv_pipeline_emit_fragment_shader() argument
6404 radeon_set_context_reg(ctx_cs, R_02880C_DB_SHADER_CONTROL, in radv_pipeline_emit_fragment_shader()
6407 radeon_set_context_reg_seq(ctx_cs, R_0286CC_SPI_PS_INPUT_ENA, 2); in radv_pipeline_emit_fragment_shader()
6408 radeon_emit(ctx_cs, ps->config.spi_ps_input_ena); in radv_pipeline_emit_fragment_shader()
6409 radeon_emit(ctx_cs, ps->config.spi_ps_input_addr); in radv_pipeline_emit_fragment_shader()
6416 ctx_cs, R_0286D8_SPI_PS_IN_CONTROL, in radv_pipeline_emit_fragment_shader()
6422 radeon_set_context_reg(ctx_cs, R_0286E0_SPI_BARYC_CNTL, pipeline->spi_baryc_cntl); in radv_pipeline_emit_fragment_shader()
6425 ctx_cs, R_028710_SPI_SHADER_Z_FORMAT, in radv_pipeline_emit_fragment_shader()
6431 radv_pipeline_emit_vgt_vertex_reuse(struct radeon_cmdbuf *ctx_cs, in radv_pipeline_emit_vgt_vertex_reuse() argument
6445 radeon_set_context_reg(ctx_cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, in radv_pipeline_emit_vgt_vertex_reuse()
6450 radv_pipeline_emit_vgt_shader_config(struct radeon_cmdbuf *ctx_cs, in radv_pipeline_emit_vgt_shader_config() argument
6520 radeon_set_context_reg(ctx_cs, R_028B54_VGT_SHADER_STAGES_EN, stages); in radv_pipeline_emit_vgt_shader_config()
6524 radv_pipeline_emit_cliprect_rule(struct radeon_cmdbuf *ctx_cs, in radv_pipeline_emit_cliprect_rule() argument
6550 radeon_set_context_reg(ctx_cs, R_02820C_PA_SC_CLIPRECT_RULE, cliprect_rule); in radv_pipeline_emit_cliprect_rule()
6554 gfx10_pipeline_emit_ge_cntl(struct radeon_cmdbuf *ctx_cs, in gfx10_pipeline_emit_ge_cntl() argument
6578 radeon_set_uconfig_reg(ctx_cs, R_03096C_GE_CNTL, in gfx10_pipeline_emit_ge_cntl()
6586 radv_pipeline_emit_vgt_gs_out(struct radeon_cmdbuf *ctx_cs, in radv_pipeline_emit_vgt_gs_out() argument
6593 radeon_set_uconfig_reg(ctx_cs, R_030998_VGT_GS_OUT_PRIM_TYPE, vgt_gs_out_prim_type); in radv_pipeline_emit_vgt_gs_out()
6595 radeon_set_context_reg(ctx_cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, vgt_gs_out_prim_type); in radv_pipeline_emit_vgt_gs_out()
6600 gfx103_pipeline_emit_vgt_draw_payload_cntl(struct radeon_cmdbuf *ctx_cs, in gfx103_pipeline_emit_vgt_draw_payload_cntl() argument
6617 radeon_set_context_reg(ctx_cs, R_028A98_VGT_DRAW_PAYLOAD_CNTL, in gfx103_pipeline_emit_vgt_draw_payload_cntl()
6638 gfx103_pipeline_emit_vrs_state(struct radeon_cmdbuf *ctx_cs, in gfx103_pipeline_emit_vrs_state() argument
6659 radeon_set_context_reg(ctx_cs, R_028848_PA_CL_VRS_CNTL, in gfx103_pipeline_emit_vrs_state()
6672 radeon_set_context_reg(ctx_cs, R_0283D0_PA_SC_VRS_OVERRIDE_CNTL, in gfx103_pipeline_emit_vrs_state()
6676 radeon_set_context_reg(ctx_cs, R_028064_DB_VRS_OVERRIDE_CNTL, in gfx103_pipeline_emit_vrs_state()
6691 struct radeon_cmdbuf *ctx_cs = &pipeline->base.ctx_cs; in radv_pipeline_emit_pm4() local
6695 ctx_cs->max_dw = 256; in radv_pipeline_emit_pm4()
6696 cs->buf = malloc(4 * (cs->max_dw + ctx_cs->max_dw)); in radv_pipeline_emit_pm4()
6697 ctx_cs->buf = cs->buf + cs->max_dw; in radv_pipeline_emit_pm4()
6699 radv_pipeline_emit_depth_stencil_state(ctx_cs, ds_state); in radv_pipeline_emit_pm4()
6700 radv_pipeline_emit_blend_state(ctx_cs, pipeline, blend); in radv_pipeline_emit_pm4()
6701 radv_pipeline_emit_raster_state(ctx_cs, pipeline, info); in radv_pipeline_emit_pm4()
6702 radv_pipeline_emit_multisample_state(ctx_cs, pipeline); in radv_pipeline_emit_pm4()
6703 radv_pipeline_emit_vgt_gs_mode(ctx_cs, pipeline); in radv_pipeline_emit_pm4()
6704 radv_pipeline_emit_vertex_shader(ctx_cs, cs, pipeline); in radv_pipeline_emit_pm4()
6705 radv_pipeline_emit_mesh_shader(ctx_cs, cs, pipeline); in radv_pipeline_emit_pm4()
6708 radv_pipeline_emit_tess_shaders(ctx_cs, cs, pipeline); in radv_pipeline_emit_pm4()
6709 radv_pipeline_emit_tess_state(ctx_cs, pipeline, info); in radv_pipeline_emit_pm4()
6712 radv_pipeline_emit_geometry_shader(ctx_cs, cs, pipeline); in radv_pipeline_emit_pm4()
6713 radv_pipeline_emit_fragment_shader(ctx_cs, cs, pipeline); in radv_pipeline_emit_pm4()
6714 radv_pipeline_emit_ps_inputs(ctx_cs, pipeline); in radv_pipeline_emit_pm4()
6715 radv_pipeline_emit_vgt_vertex_reuse(ctx_cs, pipeline); in radv_pipeline_emit_pm4()
6716 radv_pipeline_emit_vgt_shader_config(ctx_cs, pipeline); in radv_pipeline_emit_pm4()
6717 radv_pipeline_emit_cliprect_rule(ctx_cs, info); in radv_pipeline_emit_pm4()
6718 radv_pipeline_emit_vgt_gs_out(ctx_cs, pipeline, vgt_gs_out_prim_type); in radv_pipeline_emit_pm4()
6721 gfx10_pipeline_emit_ge_cntl(ctx_cs, pipeline); in radv_pipeline_emit_pm4()
6724 gfx103_pipeline_emit_vgt_draw_payload_cntl(ctx_cs, pipeline, info); in radv_pipeline_emit_pm4()
6725 gfx103_pipeline_emit_vrs_state(ctx_cs, pipeline, info); in radv_pipeline_emit_pm4()
6728 pipeline->base.ctx_cs_hash = _mesa_hash_data(ctx_cs->buf, ctx_cs->cdw * 4); in radv_pipeline_emit_pm4()
6730 assert(ctx_cs->cdw <= ctx_cs->max_dw); in radv_pipeline_emit_pm4()