| /third_party/mesa3d/src/asahi/compiler/ |
| D | agx_pack.c | 169 (value & BITFIELD_MASK(6)) | in agx_pack_alu_src()
176 (value & BITFIELD_MASK(6)) | in agx_pack_alu_src()
180 (((value >> 6) & BITFIELD_MASK(2)) << 10); in agx_pack_alu_src()
192 (value & BITFIELD_MASK(6)) | in agx_pack_alu_src()
195 (((value >> 6) & BITFIELD_MASK(2)) << 10); in agx_pack_alu_src()
210 (value & BITFIELD_MASK(6)) | in agx_pack_cmpsel_src()
219 (value & BITFIELD_MASK(6)) | in agx_pack_cmpsel_src()
222 (((value >> 6) & BITFIELD_MASK(2)) << 10); in agx_pack_cmpsel_src()
232 (value & BITFIELD_MASK(6)) | in agx_pack_cmpsel_src()
234 (((value >> 6) & BITFIELD_MASK(2)) << 10); in agx_pack_cmpsel_src()
[all …]
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| /third_party/mesa3d/src/compiler/nir/ |
| D | nir_lower_wrmasks.c | 119 unsigned cur_mask = (BITFIELD_MASK(length) << first_component); in split_wrmask()
127 nir_intrinsic_set_write_mask(new_intr, BITFIELD_MASK(length)); in split_wrmask()
202 if (nir_intrinsic_write_mask(intr) == BITFIELD_MASK(intr->num_components)) in nir_lower_wrmasks_instr()
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| D | nir_lower_point_size_mov.c | 49 in->state_slots[0].swizzle = BITFIELD_MASK(4); in lower_impl()
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| D | nir_opt_shrink_vectors.c | 232 instr->dest.write_mask = BITFIELD_MASK(num_components); in opt_shrink_vectors_alu()
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| /third_party/mesa3d/src/panfrost/util/ |
| D | pan_lower_xfb.c | 59 nir_ssa_def *value = nir_channels(b, src, BITFIELD_MASK(num_components) << start_component); in lower_xfb_output()
60 nir_store_global(b, addr, 4, value, BITFIELD_MASK(num_components)); in lower_xfb_output()
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| /third_party/mesa3d/src/mesa/state_tracker/ |
| D | st_atom_array.cpp | 129 util_bitcount_fast<POPCNT>(inputs_read & BITFIELD_MASK(attr))); in setup_arrays()
175 util_bitcount_fast<POPCNT>(inputs_read & BITFIELD_MASK(attr))); in setup_arrays()
238 util_bitcount_fast<POPCNT>(inputs_read & BITFIELD_MASK(attr))); in st_setup_current()
290 util_bitcount(inputs_read & BITFIELD_MASK(attr))); in st_setup_current_user()
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| /third_party/mesa3d/src/broadcom/compiler/ |
| D | v3d_nir_lower_logic_ops.c | 172 const unsigned masks[4] = { BITFIELD_MASK(bits[0]), in unpack_unorm_rgb10a2()
173 BITFIELD_MASK(bits[1]), in unpack_unorm_rgb10a2()
174 BITFIELD_MASK(bits[2]), in unpack_unorm_rgb10a2()
175 BITFIELD_MASK(bits[3]) }; in unpack_unorm_rgb10a2()
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| /third_party/mesa3d/src/util/ |
| D | macros.h | 374 #define BITFIELD_MASK(b) \ macro
378 (BITFIELD_MASK((b) + (count)) & ~BITFIELD_MASK(b))
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| D | u_idalloc.c | 132 buf->data[base + num_alloc - 1] |= BITFIELD_MASK(num % 32); in util_idalloc_alloc_range()
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| /third_party/mesa3d/src/panfrost/bifrost/valhall/ |
| D | va_lower_constants.c | 97 return (x <= INT8_MAX) || ((x >> 7) == BITFIELD_MASK(24 + 1)); in is_extension_of_8()
106 return (x <= INT16_MAX) || ((x >> 15) == BITFIELD_MASK(16 + 1)); in is_extension_of_16()
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| D | va_insert_flow.c | 463 assert((I->flow & ~BITFIELD_MASK(VA_NUM_GENERAL_SLOTS)) == 0); in va_insert_flow_control_nops()
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| /third_party/mesa3d/src/panfrost/lib/ |
| D | pan_props.c | 150 .bin_size = (1 << (raw & BITFIELD_MASK(5))), in panfrost_query_tiler_features()
151 .max_levels = (raw >> 8) & BITFIELD_MASK(4) in panfrost_query_tiler_features()
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| /third_party/mesa3d/src/gallium/drivers/freedreno/a6xx/ |
| D | fd6_blend.h | 72 unsigned mask = BITFIELD_MASK(nr_samples); in fd6_blend_variant()
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| /third_party/mesa3d/src/panfrost/vulkan/ |
| D | panvk_varyings.h | 75 return util_bitcount(varyings->buf_mask & BITFIELD_MASK(b)); in panvk_varying_buf_index()
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| /third_party/mesa3d/src/microsoft/spirv_to_dxil/ |
| D | spirv_to_dxil.h | 93 #define DXIL_SPIRV_Y_FLIP_MASK BITFIELD_MASK(DXIL_SPIRV_MAX_VIEWPORT)
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| /third_party/mesa3d/src/panfrost/bifrost/ |
| D | bi_liveness.c | 48 unsigned rmask = BITFIELD_MASK(count); in bi_liveness_ins_update()
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| D | bir.c | 146 unsigned mask = BITFIELD_MASK(bi_count_write_registers(ins, d)); in bi_writemask()
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| D | bi_scoreboard.c | 244 clause->dependencies |= BITFIELD_MASK(BI_NUM_GENERAL_SLOTS); in bi_set_dependencies()
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| /third_party/mesa3d/src/freedreno/ir3/ |
| D | ir3_nir_lower_wide_load_store.c | 65 nir_ssa_def *v = nir_channels(b, val, BITFIELD_MASK(c) << off); in lower_wide_load_store()
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| D | ir3_nir_lower_64b.c | 312 nir_ssa_def *v = nir_channels(b, value, BITFIELD_MASK(c) << off); in lower_64b_global()
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| /third_party/mesa3d/src/gallium/auxiliary/util/ |
| D | u_screen.c | 99 return BITFIELD_MASK(PIPE_PRIM_MAX); in u_pipe_screen_get_param_defaults()
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| D | u_threaded_context.h | 262 #define TC_BUFFER_ID_MASK BITFIELD_MASK(14)
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| D | u_vbuf.c | 325 if (caps->supported_restart_modes != BITFIELD_MASK(PIPE_PRIM_MAX)) in u_vbuf_get_caps()
330 if (caps->supported_prim_modes != BITFIELD_MASK(PIPE_PRIM_MAX)) in u_vbuf_get_caps()
359 … ((caps->supported_prim_modes & caps->supported_restart_modes & BITFIELD_MASK(PIPE_PRIM_MAX))) != in u_vbuf_create()
360 BITFIELD_MASK(PIPE_PRIM_MAX)) { in u_vbuf_create()
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| /third_party/mesa3d/src/intel/compiler/ |
| D | brw_nir_lower_rt_intrinsics.c | 240 sysval = nir_iand_imm(b, geometry_index_dw, BITFIELD_MASK(29)); in lower_rt_intrinsics_impl()
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| /third_party/mesa3d/src/gallium/drivers/zink/ |
| D | zink_lower_cubemap_to_array.c | 171 … nir_ssa_def *c = nir_channels(b, psrc->ssa, BITFIELD_MASK(nir_tex_instr_src_size(array_tex, s))); in create_array_tex_from_cube_tex()
492 return nir_channels(b, size, BITFIELD_MASK(num_components)); in lower_cube_txs()
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