| /third_party/vixl/test/aarch32/config/ |
| D | cond-rd-rn-a32.json | 29 "Clz", // CLZ{<c>}{<q>} <Rd>, <Rm> ; A1
|
| D | cond-rd-rn-t32.json | 33 "Clz", // CLZ{<c>}{<q>} <Rd>, <Rm> ; T1
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| /third_party/mesa3d/src/gallium/drivers/vc4/ |
| D | vc4_qpu.h | 214 A_ALU1(CLZ)
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| /third_party/node/deps/v8/src/codegen/arm/ |
| D | constants-arm.h | 147 CLZ = 1 << 4 enumerator
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyInstrInteger.td | 85 defm CLZ : UnaryInt<ctlz, "clz ", 0x67, 0x79>;
|
| /third_party/node/deps/v8/src/codegen/mips/ |
| D | constants-mips.h | 571 CLZ = ((4U << 3) + 0), enumerator
1704 case CLZ: in InstructionType()
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| /third_party/node/deps/v8/src/codegen/mips64/ |
| D | constants-mips64.h | 595 CLZ = ((4U << 3) + 0), enumerator
1776 case CLZ: in InstructionType()
|
| /third_party/node/deps/v8/src/codegen/arm64/ |
| D | constants-arm64.h | 1054 CLZ = DataProcessing1SourceFixed | 0x00001000, enumerator
1055 CLZ_w = CLZ,
1056 CLZ_x = CLZ | SixtyFourBits,
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64SchedCyclone.td | 149 // CLS,CLZ,RBIT,REV,REV16,REV32
499 // CLS,CLZ,CNT,RBIT,REV16,REV32,REV64,XTN
|
| D | AArch64SchedFalkorDetails.td | 922 def : InstRW<[FalkorWr_1VXVY_2cyc], (instregex "^(CLS|CLZ|CNT|RBIT)(v2i32|v4i16|v8i8)$")>;
944 def : InstRW<[FalkorWr_2VXVY_2cyc], (instregex "^(CLS|CLZ|CNT|RBIT)(v4i32|v8i16|v16i8)$")>;
1207 def : InstRW<[FalkorWr_1XYZ_2cyc], (instregex "^(CLS|CLZ|RBIT|REV|REV16|REV32)(W|X)r$")>;
|
| D | AArch64SchedKryoDetails.td | 495 (instregex "(CLS|CLZ)(W|X)r")>;
501 (instregex "(CLS|CLZ|CNT)(v4i32|v8i16|v16i8)")>;
507 (instregex "(CLS|CLZ|CNT)(v2i32|v4i16|v8i8)")>;
|
| D | AArch64SchedThunderX2T99.td | 558 "^CLZ(W|X)r$")>;
1356 (instregex "(CLS|CLZ|CNT)(v4i32|v8i16|v16i8)")>;
|
| /third_party/pcre2/pcre2/src/sljit/ |
| D | sljitNativeARM_64.c | 84 #define CLZ 0xdac01000 macro
817 return push_inst(compiler, (CLZ ^ inv_bits) | RD(dst) | RN(arg2)); in emit_op_imm()
821 return push_inst(compiler, (CLZ ^ inv_bits) | RD(dst) | RN(dst)); in emit_op_imm()
|
| D | sljitNativeMIPS_common.c | 286 #define CLZ (HI(28) | LO(32)) macro
1571 return push_inst(compiler, SELECT_OP(DCLZ, CLZ) | S(src2) | D(dst), DR(dst)); in emit_single_op()
1573 return push_inst(compiler, SELECT_OP(DCLZ, CLZ) | S(src2) | T(dst) | D(dst), DR(dst)); in emit_single_op()
1580 FAIL_IF(push_inst(compiler, SELECT_OP(DCLZ, CLZ) | S(dst) | D(dst), DR(dst))); in emit_single_op()
1582 FAIL_IF(push_inst(compiler, SELECT_OP(DCLZ, CLZ) | S(dst) | T(dst) | D(dst), DR(dst))); in emit_single_op()
|
| D | sljitNativeARM_32.c | 98 #define CLZ 0xe16f0f10 macro
1490 FAIL_IF(push_inst(compiler, CLZ | RD(dst) | RM(src2))); in emit_single_op()
1499 FAIL_IF(push_inst(compiler, CLZ | RD(dst) | RM(TMP_REG2))); in emit_single_op()
1504 return push_inst(compiler, CLZ | RD(dst) | RM(dst)); in emit_single_op()
|
| D | sljitNativeARM_T2_32.c | 120 #define CLZ 0xfab0f080 macro
839 return push_inst32(compiler, CLZ | RN4(arg2) | RD4(dst) | RM4(arg2)); in emit_op_imm()
843 return push_inst32(compiler, CLZ | RN4(dst) | RD4(dst) | RM4(dst)); in emit_op_imm()
|
| /third_party/mesa3d/src/broadcom/compiler/ |
| D | v3d_compiler.h | 1388 VIR_A_ALU1(CLZ) in VIR_A_ALU2()
|
| /third_party/mesa3d/src/panfrost/bifrost/valhall/test/ |
| D | assembler-cases.txt | 192 0b 00 04 00 00 cc 91 00 CLZ.u32 r12, r11
|
| /third_party/vixl/src/aarch64/ |
| D | constants-aarch64.h | 1420 CLZ = DataProcessing1SourceFixed | 0x00001000, enumerator
1421 CLZ_w = CLZ,
1422 CLZ_x = CLZ | SixtyFourBits,
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsScheduleP5600.td | 181 def : InstRW<[P5600WriteAL2], (instrs CLO, CLZ, DI, EI, MFHI, MFLO,
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | README.txt | 708 should just be implemented with a CLZ instruction. Since there are other
|
| D | ARMScheduleR52.td | 309 "BICS?ri", "CLZ", "EORri", "MVNS?r", "ORRri", "RSBS?ri", "RSCri", "SBCri",
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| D | ARMScheduleSwift.td | 131 // CLZ,RBIT,REV,REV16,REVSH,PKH
|
| /third_party/node/deps/v8/src/diagnostics/mips/ |
| D | disasm-mips.cc | 1435 case CLZ: in DecodeTypeRegisterSPECIAL2()
|
| /third_party/node/deps/v8/src/diagnostics/arm/ |
| D | disasm-arm.cc | 921 case CLZ: in DecodeType01()
|